Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 1 | #include <string.h> |
| 2 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 3 | #include "fill_packet.h" |
| 4 | #include "encoder.h" |
| 5 | |
| 6 | #include "FreeRTOS.h" |
| 7 | #include "task.h" |
| 8 | |
| 9 | #include "digital.h" |
| 10 | #include "analog.h" |
Brian Silverman | 4987694 | 2013-10-11 17:50:26 -0700 | [diff] [blame] | 11 | #include "gyro.h" |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 12 | |
| 13 | // How long (in ms) to wait after a falling edge on the bottom indexer sensor |
| 14 | // before reading the indexer encoder. |
| 15 | static const int kBottomFallDelayTime = 32; |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 16 | static const int kWheelStopThreshold = 2.5; |
Daniel Petti | 5003b77 | 2013-11-07 02:19:50 +0000 | [diff] [blame] | 17 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 18 | #define ENC(gpio, a, b) readGPIO(gpio, a) * 2 + readGPIO(gpio, b) |
| 19 | int encoder_bits(int channel) { |
| 20 | switch (channel) { |
| 21 | case 0: |
| 22 | return ENC(GPIO1, 20, 23); |
| 23 | case 1: |
| 24 | return ENC(GPIO2, 11, 12); |
| 25 | case 2: |
| 26 | return ENC(GPIO0, 21, 22); |
| 27 | case 3: |
| 28 | return ENC(GPIO0, 19, 20); |
| 29 | default: |
| 30 | return -1; |
| 31 | } |
| 32 | return -1; |
| 33 | } |
| 34 | #undef ENC |
| 35 | |
| 36 | // Uses EINT1 and EINT2 on 2.11 and 2.12. |
| 37 | volatile int32_t encoder1_val; |
| 38 | // On GPIO pins 0.22 and 0.21. |
| 39 | volatile int32_t encoder2_val; |
| 40 | // On GPIO pins 0.20 and 0.19. |
| 41 | volatile int32_t encoder3_val; |
| 42 | // On GPIO pins 2.0 and 2.1. |
| 43 | volatile int32_t encoder4_val; |
| 44 | // On GPIO pins 2.2 and 2.3. |
| 45 | volatile int32_t encoder5_val; |
| 46 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 47 | // It is important to clear the various interrupt flags first thing in the ISRs. |
| 48 | // It doesn't seem to work otherwise, possibly because of the reason that Brian |
| 49 | // found poking around online: caches on the bus make it so that the clearing of |
| 50 | // the interrupt gets to the NVIC after the ISR returns, so it runs the ISR a |
| 51 | // second time. Also, by clearing them early, if a second interrupt arrives from |
| 52 | // the same source it will still get handled instead of getting lost. |
| 53 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 54 | // ENC1A 2.11 |
| 55 | void EINT1_IRQHandler(void) { |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 56 | // Make sure to change this BEFORE clearing the interrupt like the datasheet |
| 57 | // says you have to. |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 58 | SC->EXTPOLAR ^= 0x2; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 59 | SC->EXTINT = 0x2; |
| 60 | int fiopin = GPIO2->FIOPIN; |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 61 | // This looks like a weird way to XOR the 2 inputs, but it compiles down to |
| 62 | // just 2 instructions, which is hard to beat. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 63 | if (((fiopin >> 1) ^ fiopin) & 0x800) { |
| 64 | ++encoder1_val; |
| 65 | } else { |
| 66 | --encoder1_val; |
| 67 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 68 | } |
| 69 | // ENC1B 2.12 |
| 70 | void EINT2_IRQHandler(void) { |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 71 | SC->EXTPOLAR ^= 0x4; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 72 | SC->EXTINT = 0x4; |
| 73 | int fiopin = GPIO2->FIOPIN; |
| 74 | if (((fiopin >> 1) ^ fiopin) & 0x800) { |
| 75 | --encoder1_val; |
| 76 | } else { |
| 77 | ++encoder1_val; |
| 78 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 79 | } |
| 80 | |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 81 | static inline void reset_TC(void) { |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 82 | TIM2->TCR |= (1 << 1); // Put it into reset. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 83 | TIM2->TCR = 1; // Take it out of reset + make sure it's enabled. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 84 | } |
| 85 | |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 86 | // TIM2 |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 87 | volatile uint32_t shooter_cycle_ticks; |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 88 | void TIMER2_IRQHandler(void) { |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 89 | // Apparently, this handler runs regardless of a match or capture event. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 90 | if (TIM2->IR & (1 << 4)) { |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 91 | // Capture |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 92 | TIM2->IR = (1 << 3); // Clear the interrupt. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 93 | |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 94 | shooter_cycle_ticks = TIM2->CR0; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 95 | |
| 96 | reset_TC(); |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 97 | } else if (TIM2->IR & 1) { |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 98 | // Match |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 99 | TIM2->IR = 1; // Clear the interrupt |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 100 | |
| 101 | // Assume shooter is stopped. |
| 102 | shooter_cycle_ticks = 0; |
| 103 | |
| 104 | // Disable timer. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 105 | TIM2->TCR = 0; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | // It will only handle one interrupt per run. |
| 109 | // If there is another interrupt pending, it won't be cleared, and the ISR |
| 110 | // will be run again to handle it. |
| 111 | } |
| 112 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 113 | // TODO(brians): Have this indicate some kind of error instead of just looping |
| 114 | // infinitely in the ISR because it never clears it. |
| 115 | static void NoGPIO(void) {} |
| 116 | static void Encoder2ARise(void) { |
| 117 | GPIOINT->IO0IntClr = (1 << 22); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 118 | if (GPIO0->FIOPIN & (1 << 21)) { |
| 119 | ++encoder2_val; |
| 120 | } else { |
| 121 | --encoder2_val; |
| 122 | } |
| 123 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 124 | static void Encoder2AFall(void) { |
| 125 | GPIOINT->IO0IntClr = (1 << 22); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 126 | if (GPIO0->FIOPIN & (1 << 21)) { |
| 127 | --encoder2_val; |
| 128 | } else { |
| 129 | ++encoder2_val; |
| 130 | } |
| 131 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 132 | static void Encoder2BRise(void) { |
| 133 | GPIOINT->IO0IntClr = (1 << 21); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 134 | if (GPIO0->FIOPIN & (1 << 22)) { |
| 135 | --encoder2_val; |
| 136 | } else { |
| 137 | ++encoder2_val; |
| 138 | } |
| 139 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 140 | static void Encoder2BFall(void) { |
| 141 | GPIOINT->IO0IntClr = (1 << 21); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 142 | if (GPIO0->FIOPIN & (1 << 22)) { |
| 143 | ++encoder2_val; |
| 144 | } else { |
| 145 | --encoder2_val; |
| 146 | } |
| 147 | } |
| 148 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 149 | static void Encoder3ARise(void) { |
| 150 | GPIOINT->IO0IntClr = (1 << 20); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 151 | if (GPIO0->FIOPIN & (1 << 19)) { |
| 152 | ++encoder3_val; |
| 153 | } else { |
| 154 | --encoder3_val; |
| 155 | } |
| 156 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 157 | static void Encoder3AFall(void) { |
| 158 | GPIOINT->IO0IntClr = (1 << 20); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 159 | if (GPIO0->FIOPIN & (1 << 19)) { |
| 160 | --encoder3_val; |
| 161 | } else { |
| 162 | ++encoder3_val; |
| 163 | } |
| 164 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 165 | static void Encoder3BRise(void) { |
| 166 | GPIOINT->IO0IntClr = (1 << 19); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 167 | if (GPIO0->FIOPIN & (1 << 20)) { |
| 168 | --encoder3_val; |
| 169 | } else { |
| 170 | ++encoder3_val; |
| 171 | } |
| 172 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 173 | static void Encoder3BFall(void) { |
| 174 | GPIOINT->IO0IntClr = (1 << 19); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 175 | if (GPIO0->FIOPIN & (1 << 20)) { |
| 176 | ++encoder3_val; |
| 177 | } else { |
| 178 | --encoder3_val; |
| 179 | } |
| 180 | } |
| 181 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 182 | static void Encoder4ARise(void) { |
| 183 | GPIOINT->IO2IntClr = (1 << 0); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 184 | if (GPIO2->FIOPIN & (1 << 1)) { |
| 185 | ++encoder4_val; |
| 186 | } else { |
| 187 | --encoder4_val; |
| 188 | } |
| 189 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 190 | static void Encoder4AFall(void) { |
| 191 | GPIOINT->IO2IntClr = (1 << 0); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 192 | if (GPIO2->FIOPIN & (1 << 1)) { |
| 193 | --encoder4_val; |
| 194 | } else { |
| 195 | ++encoder4_val; |
| 196 | } |
| 197 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 198 | static void Encoder4BRise(void) { |
| 199 | GPIOINT->IO2IntClr = (1 << 1); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 200 | if (GPIO2->FIOPIN & (1 << 0)) { |
| 201 | --encoder4_val; |
| 202 | } else { |
| 203 | ++encoder4_val; |
| 204 | } |
| 205 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 206 | static void Encoder4BFall(void) { |
| 207 | GPIOINT->IO2IntClr = (1 << 1); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 208 | if (GPIO2->FIOPIN & (1 << 0)) { |
| 209 | ++encoder4_val; |
| 210 | } else { |
| 211 | --encoder4_val; |
| 212 | } |
| 213 | } |
| 214 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 215 | static void Encoder5ARise(void) { |
| 216 | GPIOINT->IO2IntClr = (1 << 2); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 217 | if (GPIO2->FIOPIN & (1 << 3)) { |
| 218 | ++encoder5_val; |
| 219 | } else { |
| 220 | --encoder5_val; |
| 221 | } |
| 222 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 223 | static void Encoder5AFall(void) { |
| 224 | GPIOINT->IO2IntClr = (1 << 2); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 225 | if (GPIO2->FIOPIN & (1 << 3)) { |
| 226 | --encoder5_val; |
| 227 | } else { |
| 228 | ++encoder5_val; |
| 229 | } |
| 230 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 231 | static void Encoder5BRise(void) { |
| 232 | GPIOINT->IO2IntClr = (1 << 3); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 233 | if (GPIO2->FIOPIN & (1 << 2)) { |
| 234 | --encoder5_val; |
| 235 | } else { |
| 236 | ++encoder5_val; |
| 237 | } |
| 238 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 239 | static void Encoder5BFall(void) { |
| 240 | GPIOINT->IO2IntClr = (1 << 3); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 241 | if (GPIO2->FIOPIN & (1 << 2)) { |
| 242 | ++encoder5_val; |
| 243 | } else { |
| 244 | --encoder5_val; |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | volatile int32_t capture_top_rise; |
| 249 | volatile int8_t top_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 250 | static void IndexerTopRise(void) { |
| 251 | GPIOINT->IO0IntClr = (1 << 5); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 252 | // edge counting encoder capture |
| 253 | ++top_rise_count; |
| 254 | capture_top_rise = encoder3_val; |
| 255 | } |
| 256 | volatile int32_t capture_top_fall; |
| 257 | volatile int8_t top_fall_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 258 | static void IndexerTopFall(void) { |
| 259 | GPIOINT->IO0IntClr = (1 << 5); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 260 | // edge counting encoder capture |
| 261 | ++top_fall_count; |
| 262 | capture_top_fall = encoder3_val; |
| 263 | } |
| 264 | volatile int8_t bottom_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 265 | static void IndexerBottomRise(void) { |
| 266 | GPIOINT->IO0IntClr = (1 << 4); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 267 | // edge counting |
| 268 | ++bottom_rise_count; |
| 269 | } |
| 270 | volatile int32_t capture_bottom_fall_delay; |
| 271 | volatile int8_t bottom_fall_delay_count; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 272 | portTickType xDelayTimeFrom; |
| 273 | static portTASK_FUNCTION(vDelayCapture, pvParameters) |
| 274 | { |
| 275 | portTickType xSleepFrom = xTaskGetTickCount(); |
| 276 | |
| 277 | for (;;) { |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 278 | // Atomically (wrt the ISR) switch xDelayTimeFrom to 0 and store its old |
| 279 | // value to use later. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 280 | NVIC_DisableIRQ(EINT3_IRQn); |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 281 | portTickType new_time = xDelayTimeFrom; |
| 282 | xDelayTimeFrom = 0; |
| 283 | NVIC_EnableIRQ(EINT3_IRQn); |
| 284 | |
| 285 | if (new_time != 0) { |
| 286 | xSleepFrom = new_time; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 287 | |
| 288 | vTaskDelayUntil(&xSleepFrom, kBottomFallDelayTime / portTICK_RATE_MS); |
| 289 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 290 | // Make sure that the USB ISR doesn't look at inconsistent values. |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 291 | NVIC_DisableIRQ(USB_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 292 | capture_bottom_fall_delay = encoder3_val; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 293 | ++bottom_fall_delay_count; |
| 294 | NVIC_EnableIRQ(USB_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 295 | } else { |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 296 | // Wait 10ms and then check again. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 297 | vTaskDelayUntil(&xSleepFrom, 10 / portTICK_RATE_MS); |
| 298 | } |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | volatile int8_t bottom_fall_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 303 | static void IndexerBottomFall(void) { |
| 304 | GPIOINT->IO0IntClr = (1 << 4); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 305 | ++bottom_fall_count; |
| 306 | // edge counting start delayed capture |
| 307 | xDelayTimeFrom = xTaskGetTickCount(); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 308 | } |
| 309 | volatile int32_t capture_wrist_rise; |
| 310 | volatile int8_t wrist_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 311 | static void WristHallRise(void) { |
| 312 | GPIOINT->IO0IntClr = (1 << 6); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 313 | // edge counting encoder capture |
| 314 | ++wrist_rise_count; |
| 315 | capture_wrist_rise = (int32_t)QEI->QEIPOS; |
| 316 | } |
| 317 | volatile int32_t capture_shooter_angle_rise; |
| 318 | volatile int8_t shooter_angle_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 319 | static void ShooterHallRise(void) { |
| 320 | GPIOINT->IO0IntClr = (1 << 7); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 321 | // edge counting encoder capture |
| 322 | ++shooter_angle_rise_count; |
| 323 | capture_shooter_angle_rise = encoder2_val; |
| 324 | } |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 325 | |
| 326 | // Third robot shooter. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 327 | static void ShooterPhotoFall(void) { |
| 328 | GPIOINT->IO0IntClr = (1 << 23); |
| 329 | // We reset TC to make sure we don't get a crap |
| 330 | // value from CR0 when the capture interrupt occurs |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 331 | // if the shooter is just starting up again, and so |
| 332 | // that the match interrupt thing works right. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 333 | reset_TC(); |
| 334 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 335 | |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 336 | typedef void (*Handler)(void); |
| 337 | // Contains default pointers for ISR functions. |
| 338 | // (These can be used without modifications on the comp/practice bots.) |
| 339 | Handler ISRTable[] = { |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 340 | Encoder5BFall, // index 0: P2.3 Fall #bit 31 //Encoder 5 B //Dio 10 |
| 341 | Encoder5AFall, // index 1: P2.2 Fall #bit 30 //Encoder 5 A //Dio 9 |
| 342 | Encoder4BFall, // index 2: P2.1 Fall #bit 29 //Encoder 4 B //Dio 8 |
| 343 | Encoder4AFall, // index 3: P2.0 Fall #bit 28 //Encoder 4 A //Dio 7 |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 344 | NoGPIO, // index 4: NO GPIO #bit 27 |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 345 | Encoder2AFall, // index 5: P0.22 Fall #bit 26 //Encoder 2 A |
| 346 | Encoder2BFall, // index 6: P0.21 Fall #bit 25 //Encoder 2 B |
| 347 | Encoder3AFall, // index 7: P0.20 Fall #bit 24 //Encoder 3 A |
| 348 | Encoder3BFall, // index 8: P0.19 Fall #bit 23 //Encoder 3 B |
| 349 | Encoder2ARise, // index 9: P0.22 Rise #bit 22 //Encoder 2 A |
| 350 | Encoder2BRise, // index 10: P0.21 Rise #bit 21 //Encoder 2 B |
| 351 | Encoder3ARise, // index 11: P0.20 Rise #bit 20 //Encoder 3 A |
| 352 | Encoder3BRise, // index 12: P0.19 Rise #bit 19 //Encoder 3 B |
| 353 | NoGPIO, // index 13: NO GPIO #bit 18 |
| 354 | NoGPIO, // index 14: NO GPIO #bit 17 |
| 355 | NoGPIO, // index 15: NO GPIO #bit 16 |
| 356 | NoGPIO, // index 16: NO GPIO #bit 15 |
| 357 | NoGPIO, // index 17: NO GPIO #bit 14 |
| 358 | NoGPIO, // index 18: NO GPIO #bit 13 |
| 359 | NoGPIO, // index 19: NO GPIO #bit 12 |
| 360 | ShooterHallRise, // index 20: P0.7 Fall #bit 11 //Shooter Hall //Dio 4 |
| 361 | WristHallRise, // index 21: P0.6 Fall #bit 10 //Wrist Hall //Dio 3 |
| 362 | IndexerTopRise, // index 22: P0.5 Fall #bit 9 //Indexer Top //Dio 2 |
| 363 | IndexerBottomRise, // index 23: P0.4 Fall #bit 8 //Indexer Bottom //Dio 1 |
| 364 | NoGPIO, // index 24: NO GPIO #bit 7 |
| 365 | NoGPIO, // index 25: NO GPIO #bit 6 |
| 366 | IndexerTopFall, // index 26: P0.5 Rise #bit 5 //Indexer Top //Dio 2 |
| 367 | IndexerBottomFall, // index 27: P0.4 Rise #bit 4 //Indexer Bottom //Dio 1 |
| 368 | Encoder5BRise, // index 28: P2.3 Rise #bit 3 //Encoder 5 B //Dio 10 |
| 369 | Encoder5ARise, // index 29: P2.2 Rise #bit 2 //Encoder 5 A //Dio 9 |
| 370 | Encoder4BRise, // index 30: P2.1 Rise #bit 1 //Encoder 4 B //Dio 8 |
| 371 | Encoder4ARise, // index 31: P2.0 Rise #bit 0 //Encoder 4 A //Dio 7 |
| 372 | NoGPIO // index 32: NO BITS SET #False Alarm |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 373 | }; |
| 374 | |
| 375 | // Count leading zeros. |
| 376 | // Returns 0 if bit 31 is set etc. |
| 377 | __attribute__((always_inline)) static __INLINE uint32_t __clz(uint32_t value) { |
| 378 | uint32_t result; |
| 379 | __asm__("clz %0, %1" : "=r" (result) : "r" (value)); |
| 380 | return result; |
| 381 | } |
| 382 | inline static void IRQ_Dispatch(void) { |
| 383 | // There is no need to add a loop here to handle multiple interrupts at the |
| 384 | // same time because the processor has tail chaining of interrupts which we |
| 385 | // can't really beat with our own loop. |
| 386 | // It would actually be bad because a loop here would block EINT1/2 for longer |
| 387 | // lengths of time. |
| 388 | |
| 389 | uint32_t index = __clz(GPIOINT->IO2IntStatR | GPIOINT->IO0IntStatR | |
| 390 | (GPIOINT->IO2IntStatF << 28) | (GPIOINT->IO0IntStatF << 4)); |
| 391 | |
| 392 | ISRTable[index](); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 393 | } |
| 394 | void EINT3_IRQHandler(void) { |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 395 | IRQ_Dispatch(); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 396 | } |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 397 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 398 | int32_t encoder_val(int chan) { |
| 399 | int32_t val; |
| 400 | switch (chan) { |
| 401 | case 0: // Wrist |
| 402 | return (int32_t)QEI->QEIPOS; |
| 403 | case 1: // Shooter Wheel |
| 404 | NVIC_DisableIRQ(EINT1_IRQn); |
| 405 | NVIC_DisableIRQ(EINT2_IRQn); |
| 406 | val = encoder1_val; |
| 407 | NVIC_EnableIRQ(EINT2_IRQn); |
| 408 | NVIC_EnableIRQ(EINT1_IRQn); |
| 409 | return val; |
| 410 | case 2: // Shooter Angle |
| 411 | NVIC_DisableIRQ(EINT3_IRQn); |
| 412 | val = encoder2_val; |
| 413 | NVIC_EnableIRQ(EINT3_IRQn); |
| 414 | return val; |
| 415 | case 3: // Indexer |
| 416 | NVIC_DisableIRQ(EINT3_IRQn); |
| 417 | val = encoder3_val; |
| 418 | NVIC_EnableIRQ(EINT3_IRQn); |
| 419 | return val; |
| 420 | case 4: // Drive R |
| 421 | NVIC_DisableIRQ(EINT3_IRQn); |
| 422 | val = encoder4_val; |
| 423 | NVIC_EnableIRQ(EINT3_IRQn); |
| 424 | return val; |
| 425 | case 5: // Drive L |
| 426 | NVIC_DisableIRQ(EINT3_IRQn); |
| 427 | val = encoder5_val; |
| 428 | NVIC_EnableIRQ(EINT3_IRQn); |
| 429 | return val; |
| 430 | default: |
| 431 | return -1; |
| 432 | } |
| 433 | } |
| 434 | |
Brian Silverman | a280ae0 | 2013-10-28 18:21:15 -0700 | [diff] [blame] | 435 | static volatile uint32_t sensor_timing_wraps = 0; |
| 436 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 437 | void encoder_init(void) { |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 438 | // Enable interrupts from the GPIO pins. |
| 439 | NVIC_EnableIRQ(EINT3_IRQn); |
| 440 | |
| 441 | if (is_bot3) { |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 442 | // Modify robot handler table for third robot. |
| 443 | ISRTable[23] = ShooterPhotoFall; |
| 444 | |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 445 | // Set up timer for bot3 photosensor. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 446 | // Make sure timer two is powered. |
| 447 | SC->PCONP |= (1 << 22); |
Daniel Petti | 5003b77 | 2013-11-07 02:19:50 +0000 | [diff] [blame] | 448 | // Rate of clock signal is just CCLK. |
| 449 | SC->PCLKSEL1 |= (1 << 12); |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 450 | // Select capture 2.0 function on pin 0.4. |
| 451 | PINCON->PINSEL0 |= (0x3 << 8); |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 452 | // Set timer to capture and interrupt on rising edge. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 453 | TIM2->CCR = 0x5; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 454 | // Set up match interrupt. |
Daniel Petti | 5003b77 | 2013-11-07 02:19:50 +0000 | [diff] [blame] | 455 | TIM2->MR0 = kWheelStopThreshold * (10 ^ 8); |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 456 | TIM2->MCR = 1; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 457 | // Enable timer IRQ, and make it lower priority than the encoders. |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 458 | NVIC_SetPriority(TIMER2_IRQn, 1); |
| 459 | NVIC_EnableIRQ(TIMER2_IRQn); |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 460 | // Set up GPIO interrupt on other edge. |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 461 | GPIOINT->IO0IntEnF |= (1 << 4); |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 462 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 463 | } else { // is main robot |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 464 | // Setup the encoder interface. |
| 465 | SC->PCONP |= PCONP_PCQEI; |
| 466 | PINCON->PINSEL3 = ((PINCON->PINSEL3 & 0xffff3dff) | 0x00004100); |
| 467 | // Reset the count and velocity. |
| 468 | QEI->QEICON = 0x00000005; |
| 469 | QEI->QEICONF = 0x00000004; |
| 470 | // Wrap back to 0 when we wrap the int and vice versa. |
| 471 | QEI->QEIMAXPOS = 0xFFFFFFFF; |
| 472 | |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 473 | // Set up encoder 1. |
| 474 | // Make GPIOs 2.11 and 2.12 trigger EINT1 and EINT2 (respectively). |
| 475 | // PINSEL4[23:22] = {0 1} |
| 476 | // PINSEL4[25:24] = {0 1} |
| 477 | PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 22)) | (0x1 << 22); |
| 478 | PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 24)) | (0x1 << 24); |
| 479 | // Clear the interrupt flags for EINT1 and EINT2 (0x6 = 0b0110). |
| 480 | SC->EXTMODE = 0x6; |
| 481 | SC->EXTINT = 0x6; |
| 482 | NVIC_EnableIRQ(EINT1_IRQn); |
| 483 | NVIC_EnableIRQ(EINT2_IRQn); |
| 484 | encoder1_val = 0; |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 485 | |
| 486 | // Set up encoder 2. |
| 487 | GPIOINT->IO0IntEnF |= (1 << 22); // Set GPIO falling interrupt. |
| 488 | GPIOINT->IO0IntEnR |= (1 << 22); // Set GPIO rising interrupt. |
| 489 | GPIOINT->IO0IntEnF |= (1 << 21); // Set GPIO falling interrupt. |
| 490 | GPIOINT->IO0IntEnR |= (1 << 21); // Set GPIO rising interrupt. |
| 491 | // Make sure they're in mode 00 (the default, aka nothing special). |
| 492 | PINCON->PINSEL1 &= ~(0x3 << 12); |
| 493 | PINCON->PINSEL1 &= ~(0x3 << 10); |
| 494 | encoder2_val = 0; |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 495 | |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 496 | // Set up encoder 3. |
| 497 | GPIOINT->IO0IntEnF |= (1 << 20); // Set GPIO falling interrupt. |
| 498 | GPIOINT->IO0IntEnR |= (1 << 20); // Set GPIO rising interrupt. |
| 499 | GPIOINT->IO0IntEnF |= (1 << 19); // Set GPIO falling interrupt. |
| 500 | GPIOINT->IO0IntEnR |= (1 << 19); // Set GPIO rising interrupt. |
| 501 | // Make sure they're in mode 00 (the default, aka nothing special). |
| 502 | PINCON->PINSEL1 &= ~(0x3 << 8); |
| 503 | PINCON->PINSEL1 &= ~(0x3 << 6); |
| 504 | encoder3_val = 0; |
| 505 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 506 | // Set up encoder 4. |
| 507 | GPIOINT->IO2IntEnF |= (1 << 0); // Set GPIO falling interrupt. |
| 508 | GPIOINT->IO2IntEnR |= (1 << 0); // Set GPIO rising interrupt. |
| 509 | GPIOINT->IO2IntEnF |= (1 << 1); // Set GPIO falling interrupt. |
| 510 | GPIOINT->IO2IntEnR |= (1 << 1); // Set GPIO rising interrupt. |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 511 | // Make sure they're in mode 00 (the default, aka nothing special). |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 512 | PINCON->PINSEL4 &= ~(0x3 << 0); |
| 513 | PINCON->PINSEL4 &= ~(0x3 << 2); |
| 514 | encoder4_val = 0; |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 515 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 516 | // Set up encoder 5. |
| 517 | GPIOINT->IO2IntEnF |= (1 << 2); // Set GPIO falling interrupt. |
| 518 | GPIOINT->IO2IntEnR |= (1 << 2); // Set GPIO rising interrupt. |
| 519 | GPIOINT->IO2IntEnF |= (1 << 3); // Set GPIO falling interrupt. |
| 520 | GPIOINT->IO2IntEnR |= (1 << 3); // Set GPIO rising interrupt. |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 521 | // Make sure they're in mode 00 (the default, aka nothing special). |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 522 | PINCON->PINSEL4 &= ~(0x3 << 4); |
| 523 | PINCON->PINSEL4 &= ~(0x3 << 6); |
| 524 | encoder5_val = 0; |
| 525 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 526 | xTaskCreate(vDelayCapture, |
| 527 | (signed char *) "SENSORs", |
| 528 | configMINIMAL_STACK_SIZE + 100, |
| 529 | NULL /*parameters*/, |
| 530 | tskIDLE_PRIORITY + 5, |
| 531 | NULL /*return task handle*/); |
| 532 | |
| 533 | GPIOINT->IO0IntEnF |= (1 << 4); // Set GPIO falling interrupt |
| 534 | GPIOINT->IO0IntEnR |= (1 << 4); // Set GPIO rising interrupt |
| 535 | PINCON->PINSEL0 &= ~(0x3 << 8); |
| 536 | |
| 537 | GPIOINT->IO0IntEnF |= (1 << 5); // Set GPIO falling interrupt |
| 538 | GPIOINT->IO0IntEnR |= (1 << 5); // Set GPIO rising interrupt |
| 539 | PINCON->PINSEL0 &= ~(0x3 << 10); |
| 540 | |
| 541 | GPIOINT->IO0IntEnF |= (1 << 6); |
| 542 | PINCON->PINSEL0 &= ~(0x3 << 12); |
| 543 | |
| 544 | GPIOINT->IO0IntEnF |= (1 << 7); |
| 545 | PINCON->PINSEL0 &= ~(0x3 << 14); |
| 546 | } |
| 547 | } |
| 548 | |
| 549 | void fillSensorPacket(struct DataStruct *packet) { |
Brian Silverman | d36b7d3 | 2013-10-24 15:56:47 -0700 | [diff] [blame] | 550 | if (gyro_output.initialized) { |
| 551 | packet->gyro_angle = gyro_output.angle; |
| 552 | packet->old_gyro_reading = gyro_output.last_reading_bad; |
| 553 | packet->bad_gyro = gyro_output.gyro_bad; |
| 554 | } else { |
| 555 | packet->gyro_angle = 0; |
| 556 | packet->old_gyro_reading = 1; |
| 557 | packet->bad_gyro = 0; |
| 558 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 559 | |
Brian Silverman | 28d9778 | 2013-10-31 17:33:52 -0700 | [diff] [blame] | 560 | packet->checksum = DATA_STRUCT_CHECKSUM; |
Brian Silverman | a280ae0 | 2013-10-28 18:21:15 -0700 | [diff] [blame] | 561 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 562 | packet->dip_switch0 = dip_switch(0); |
| 563 | packet->dip_switch1 = dip_switch(1); |
| 564 | packet->dip_switch2 = dip_switch(2); |
| 565 | packet->dip_switch3 = dip_switch(3); |
| 566 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 567 | // We disable EINT3 to avoid sending back inconsistent values. All of the |
| 568 | // aligned reads from the variables are atomic, so disabling it isn't |
| 569 | // necessary for just reading encoder values. We re-enable it periodically |
| 570 | // because disabling and enabling is cheap (2 instructions) and we really rely |
| 571 | // on low interrupt latencies. |
| 572 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 573 | if (is_bot3) { |
| 574 | packet->robot_id = 1; |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 575 | |
Daniel Petti | 03f5811 | 2013-11-09 16:35:55 +0000 | [diff] [blame^] | 576 | //packet->main.left_drive = encoder3_val; |
| 577 | //packet->main.right_drive = encoder2_val; |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 578 | |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 579 | packet->bot3.shooter_cycle_ticks = shooter_cycle_ticks; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 580 | } else { // is main robot |
Brian Silverman | 74acd62 | 2013-10-26 14:47:14 -0700 | [diff] [blame] | 581 | packet->robot_id = 2; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 582 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 583 | packet->main.left_drive = encoder5_val; |
| 584 | packet->main.right_drive = encoder4_val; |
| 585 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 586 | packet->main.shooter = encoder1_val; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 587 | packet->main.indexer = encoder3_val; |
| 588 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 589 | NVIC_DisableIRQ(EINT3_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 590 | |
| 591 | packet->main.wrist = (int32_t)QEI->QEIPOS; |
| 592 | packet->main.wrist_hall_effect = !digital(3); |
| 593 | packet->main.capture_wrist_rise = capture_wrist_rise; |
| 594 | packet->main.wrist_rise_count = wrist_rise_count; |
| 595 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 596 | NVIC_EnableIRQ(EINT3_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 597 | NVIC_DisableIRQ(EINT3_IRQn); |
| 598 | |
| 599 | packet->main.capture_top_rise = capture_top_rise; |
| 600 | packet->main.top_rise_count = top_rise_count; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 601 | packet->main.capture_top_fall = capture_top_fall; |
| 602 | packet->main.top_fall_count = top_fall_count; |
| 603 | packet->main.top_disc = !digital(2); |
| 604 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 605 | NVIC_EnableIRQ(EINT3_IRQn); |
| 606 | NVIC_DisableIRQ(EINT3_IRQn); |
| 607 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 608 | packet->main.capture_bottom_fall_delay = capture_bottom_fall_delay; |
| 609 | packet->main.bottom_fall_delay_count = bottom_fall_delay_count; |
| 610 | packet->main.bottom_fall_count = bottom_fall_count; |
Brian Silverman | 3e9464f | 2013-11-01 15:36:08 -0700 | [diff] [blame] | 611 | packet->main.bottom_rise_count = bottom_rise_count; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 612 | packet->main.bottom_disc = !digital(1); |
| 613 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 614 | NVIC_EnableIRQ(EINT3_IRQn); |
| 615 | NVIC_DisableIRQ(EINT3_IRQn); |
| 616 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 617 | packet->main.loader_top = !digital(5); |
| 618 | packet->main.loader_bottom = !digital(6); |
| 619 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 620 | NVIC_EnableIRQ(EINT3_IRQn); |
| 621 | NVIC_DisableIRQ(EINT3_IRQn); |
| 622 | |
| 623 | packet->main.shooter_angle = encoder2_val; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 624 | packet->main.capture_shooter_angle_rise = capture_shooter_angle_rise; |
| 625 | packet->main.shooter_angle_rise_count = shooter_angle_rise_count; |
| 626 | packet->main.angle_adjust_bottom_hall_effect = !digital(4); |
| 627 | |
| 628 | NVIC_EnableIRQ(EINT3_IRQn); |
| 629 | |
Brian Silverman | 3e9464f | 2013-11-01 15:36:08 -0700 | [diff] [blame] | 630 | // Do all of the analogs last because they have the potential to be slow and |
| 631 | // jittery. |
Brian Silverman | db85c9a | 2013-11-02 14:38:43 -0700 | [diff] [blame] | 632 | packet->main.battery_voltage = analog(1); |
| 633 | packet->main.left_drive_hall = analog(3); |
Brian Silverman | 3e9464f | 2013-11-01 15:36:08 -0700 | [diff] [blame] | 634 | packet->main.right_drive_hall = analog(2); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 635 | } |
| 636 | } |