blob: b4688a894fabe8f1d274273dce046b11b88b25ce [file] [log] [blame]
Daniel Pettie7cb20f2013-10-20 05:00:51 +00001#include <string.h>
2
Brian Silvermanf92396c2013-09-12 20:13:13 -07003#include "fill_packet.h"
4#include "encoder.h"
5
6#include "FreeRTOS.h"
7#include "task.h"
8
9#include "digital.h"
10#include "analog.h"
Brian Silverman49876942013-10-11 17:50:26 -070011#include "gyro.h"
Brian Silvermanf92396c2013-09-12 20:13:13 -070012
13// How long (in ms) to wait after a falling edge on the bottom indexer sensor
14// before reading the indexer encoder.
15static const int kBottomFallDelayTime = 32;
Daniel Petti5d0b34e2013-11-28 01:22:57 -080016static const uint32_t kWheelStopThreshold = 250000000;
Brian Silvermanf92396c2013-09-12 20:13:13 -070017
18#define ENC(gpio, a, b) readGPIO(gpio, a) * 2 + readGPIO(gpio, b)
19int encoder_bits(int channel) {
20 switch (channel) {
21 case 0:
22 return ENC(GPIO1, 20, 23);
23 case 1:
24 return ENC(GPIO2, 11, 12);
25 case 2:
26 return ENC(GPIO0, 21, 22);
27 case 3:
28 return ENC(GPIO0, 19, 20);
29 default:
30 return -1;
31 }
32 return -1;
33}
34#undef ENC
35
36// Uses EINT1 and EINT2 on 2.11 and 2.12.
37volatile int32_t encoder1_val;
38// On GPIO pins 0.22 and 0.21.
39volatile int32_t encoder2_val;
40// On GPIO pins 0.20 and 0.19.
41volatile int32_t encoder3_val;
42// On GPIO pins 2.0 and 2.1.
43volatile int32_t encoder4_val;
44// On GPIO pins 2.2 and 2.3.
45volatile int32_t encoder5_val;
46
Brian Silverman25aae9a2013-10-08 13:37:45 -070047// It is important to clear the various interrupt flags first thing in the ISRs.
48// It doesn't seem to work otherwise, possibly because of the reason that Brian
49// found poking around online: caches on the bus make it so that the clearing of
50// the interrupt gets to the NVIC after the ISR returns, so it runs the ISR a
51// second time. Also, by clearing them early, if a second interrupt arrives from
52// the same source it will still get handled instead of getting lost.
53
Brian Silvermanf92396c2013-09-12 20:13:13 -070054// ENC1A 2.11
55void EINT1_IRQHandler(void) {
Brian Silverman25aae9a2013-10-08 13:37:45 -070056 // Make sure to change this BEFORE clearing the interrupt like the datasheet
57 // says you have to.
Brian Silverman1623c332013-10-01 18:05:16 -070058 SC->EXTPOLAR ^= 0x2;
Brian Silvermanf92396c2013-09-12 20:13:13 -070059 SC->EXTINT = 0x2;
60 int fiopin = GPIO2->FIOPIN;
Brian Silverman25aae9a2013-10-08 13:37:45 -070061 // This looks like a weird way to XOR the 2 inputs, but it compiles down to
62 // just 2 instructions, which is hard to beat.
Brian Silvermanf92396c2013-09-12 20:13:13 -070063 if (((fiopin >> 1) ^ fiopin) & 0x800) {
64 ++encoder1_val;
65 } else {
66 --encoder1_val;
67 }
Brian Silvermanf92396c2013-09-12 20:13:13 -070068}
69// ENC1B 2.12
70void EINT2_IRQHandler(void) {
Brian Silverman1623c332013-10-01 18:05:16 -070071 SC->EXTPOLAR ^= 0x4;
Brian Silvermanf92396c2013-09-12 20:13:13 -070072 SC->EXTINT = 0x4;
73 int fiopin = GPIO2->FIOPIN;
74 if (((fiopin >> 1) ^ fiopin) & 0x800) {
75 --encoder1_val;
76 } else {
77 ++encoder1_val;
78 }
Brian Silvermanf92396c2013-09-12 20:13:13 -070079}
80
Daniel Petti6300d682013-10-14 02:12:18 +000081static inline void reset_TC(void) {
Daniel Petti00185262013-11-23 14:05:02 -080082 TIM2->TCR = (1 << 1); // Put it into reset and disabled.
83 while (TIM2->TC != 0);
Daniel Pettie7cb20f2013-10-20 05:00:51 +000084 TIM2->TCR = 1; // Take it out of reset + make sure it's enabled.
Daniel Petti6300d682013-10-14 02:12:18 +000085}
86
Daniel Pettie7cb20f2013-10-20 05:00:51 +000087// TIM2
Daniel Pettid9c84d42013-10-15 04:51:07 +000088volatile uint32_t shooter_cycle_ticks;
Daniel Pettie7cb20f2013-10-20 05:00:51 +000089void TIMER2_IRQHandler(void) {
Daniel Petti6300d682013-10-14 02:12:18 +000090 // Apparently, this handler runs regardless of a match or capture event.
Daniel Pettie7cb20f2013-10-20 05:00:51 +000091 if (TIM2->IR & (1 << 4)) {
Daniel Petti6300d682013-10-14 02:12:18 +000092 // Capture
Daniel Pettiaba9c612013-11-14 10:17:35 -080093 TIM2->IR = (1 << 4); // Clear the interrupt.
Daniel Petti6300d682013-10-14 02:12:18 +000094
Daniel Petti5d0b34e2013-11-28 01:22:57 -080095 shooter_cycle_ticks = TIM2->CR0;
Daniel Petti6300d682013-10-14 02:12:18 +000096
97 reset_TC();
Daniel Pettie7cb20f2013-10-20 05:00:51 +000098 } else if (TIM2->IR & 1) {
Daniel Petti6300d682013-10-14 02:12:18 +000099 // Match
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000100 TIM2->IR = 1; // Clear the interrupt
Daniel Petti6300d682013-10-14 02:12:18 +0000101
102 // Assume shooter is stopped.
Daniel Petti5d0b34e2013-11-28 01:22:57 -0800103 shooter_cycle_ticks = 0;
Daniel Petti6300d682013-10-14 02:12:18 +0000104
105 // Disable timer.
Daniel Petti5d0b34e2013-11-28 01:22:57 -0800106 TIM2->TCR = 0;
Daniel Petti6300d682013-10-14 02:12:18 +0000107 }
108
109 // It will only handle one interrupt per run.
110 // If there is another interrupt pending, it won't be cleared, and the ISR
111 // will be run again to handle it.
112}
113
Brian Silverman1623c332013-10-01 18:05:16 -0700114// TODO(brians): Have this indicate some kind of error instead of just looping
115// infinitely in the ISR because it never clears it.
116static void NoGPIO(void) {}
117static void Encoder2ARise(void) {
118 GPIOINT->IO0IntClr = (1 << 22);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700119 if (GPIO0->FIOPIN & (1 << 21)) {
120 ++encoder2_val;
121 } else {
122 --encoder2_val;
123 }
124}
Brian Silverman1623c332013-10-01 18:05:16 -0700125static void Encoder2AFall(void) {
126 GPIOINT->IO0IntClr = (1 << 22);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700127 if (GPIO0->FIOPIN & (1 << 21)) {
128 --encoder2_val;
129 } else {
130 ++encoder2_val;
131 }
132}
Brian Silverman1623c332013-10-01 18:05:16 -0700133static void Encoder2BRise(void) {
134 GPIOINT->IO0IntClr = (1 << 21);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700135 if (GPIO0->FIOPIN & (1 << 22)) {
136 --encoder2_val;
137 } else {
138 ++encoder2_val;
139 }
140}
Brian Silverman1623c332013-10-01 18:05:16 -0700141static void Encoder2BFall(void) {
142 GPIOINT->IO0IntClr = (1 << 21);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700143 if (GPIO0->FIOPIN & (1 << 22)) {
144 ++encoder2_val;
145 } else {
146 --encoder2_val;
147 }
148}
149
Brian Silverman1623c332013-10-01 18:05:16 -0700150static void Encoder3ARise(void) {
151 GPIOINT->IO0IntClr = (1 << 20);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700152 if (GPIO0->FIOPIN & (1 << 19)) {
153 ++encoder3_val;
154 } else {
155 --encoder3_val;
156 }
157}
Brian Silverman1623c332013-10-01 18:05:16 -0700158static void Encoder3AFall(void) {
159 GPIOINT->IO0IntClr = (1 << 20);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700160 if (GPIO0->FIOPIN & (1 << 19)) {
161 --encoder3_val;
162 } else {
163 ++encoder3_val;
164 }
165}
Brian Silverman1623c332013-10-01 18:05:16 -0700166static void Encoder3BRise(void) {
167 GPIOINT->IO0IntClr = (1 << 19);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700168 if (GPIO0->FIOPIN & (1 << 20)) {
169 --encoder3_val;
170 } else {
171 ++encoder3_val;
172 }
173}
Brian Silverman1623c332013-10-01 18:05:16 -0700174static void Encoder3BFall(void) {
175 GPIOINT->IO0IntClr = (1 << 19);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700176 if (GPIO0->FIOPIN & (1 << 20)) {
177 ++encoder3_val;
178 } else {
179 --encoder3_val;
180 }
181}
182
Brian Silverman1623c332013-10-01 18:05:16 -0700183static void Encoder4ARise(void) {
184 GPIOINT->IO2IntClr = (1 << 0);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700185 if (GPIO2->FIOPIN & (1 << 1)) {
186 ++encoder4_val;
187 } else {
188 --encoder4_val;
189 }
190}
Brian Silverman1623c332013-10-01 18:05:16 -0700191static void Encoder4AFall(void) {
192 GPIOINT->IO2IntClr = (1 << 0);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700193 if (GPIO2->FIOPIN & (1 << 1)) {
194 --encoder4_val;
195 } else {
196 ++encoder4_val;
197 }
198}
Brian Silverman1623c332013-10-01 18:05:16 -0700199static void Encoder4BRise(void) {
200 GPIOINT->IO2IntClr = (1 << 1);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700201 if (GPIO2->FIOPIN & (1 << 0)) {
202 --encoder4_val;
203 } else {
204 ++encoder4_val;
205 }
206}
Brian Silverman1623c332013-10-01 18:05:16 -0700207static void Encoder4BFall(void) {
208 GPIOINT->IO2IntClr = (1 << 1);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700209 if (GPIO2->FIOPIN & (1 << 0)) {
210 ++encoder4_val;
211 } else {
212 --encoder4_val;
213 }
214}
215
Brian Silverman1623c332013-10-01 18:05:16 -0700216static void Encoder5ARise(void) {
217 GPIOINT->IO2IntClr = (1 << 2);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700218 if (GPIO2->FIOPIN & (1 << 3)) {
219 ++encoder5_val;
220 } else {
221 --encoder5_val;
222 }
223}
Brian Silverman1623c332013-10-01 18:05:16 -0700224static void Encoder5AFall(void) {
225 GPIOINT->IO2IntClr = (1 << 2);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700226 if (GPIO2->FIOPIN & (1 << 3)) {
227 --encoder5_val;
228 } else {
229 ++encoder5_val;
230 }
231}
Brian Silverman1623c332013-10-01 18:05:16 -0700232static void Encoder5BRise(void) {
233 GPIOINT->IO2IntClr = (1 << 3);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700234 if (GPIO2->FIOPIN & (1 << 2)) {
235 --encoder5_val;
236 } else {
237 ++encoder5_val;
238 }
239}
Brian Silverman1623c332013-10-01 18:05:16 -0700240static void Encoder5BFall(void) {
241 GPIOINT->IO2IntClr = (1 << 3);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700242 if (GPIO2->FIOPIN & (1 << 2)) {
243 ++encoder5_val;
244 } else {
245 --encoder5_val;
246 }
247}
248
249volatile int32_t capture_top_rise;
250volatile int8_t top_rise_count;
Brian Silverman1623c332013-10-01 18:05:16 -0700251static void IndexerTopRise(void) {
252 GPIOINT->IO0IntClr = (1 << 5);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700253 // edge counting encoder capture
254 ++top_rise_count;
255 capture_top_rise = encoder3_val;
256}
257volatile int32_t capture_top_fall;
258volatile int8_t top_fall_count;
Brian Silverman1623c332013-10-01 18:05:16 -0700259static void IndexerTopFall(void) {
260 GPIOINT->IO0IntClr = (1 << 5);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700261 // edge counting encoder capture
262 ++top_fall_count;
263 capture_top_fall = encoder3_val;
264}
265volatile int8_t bottom_rise_count;
Brian Silverman1623c332013-10-01 18:05:16 -0700266static void IndexerBottomRise(void) {
267 GPIOINT->IO0IntClr = (1 << 4);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700268 // edge counting
269 ++bottom_rise_count;
270}
271volatile int32_t capture_bottom_fall_delay;
272volatile int8_t bottom_fall_delay_count;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700273portTickType xDelayTimeFrom;
274static portTASK_FUNCTION(vDelayCapture, pvParameters)
275{
276 portTickType xSleepFrom = xTaskGetTickCount();
277
278 for (;;) {
Brian Silverman25aae9a2013-10-08 13:37:45 -0700279 // Atomically (wrt the ISR) switch xDelayTimeFrom to 0 and store its old
280 // value to use later.
Brian Silvermanf92396c2013-09-12 20:13:13 -0700281 NVIC_DisableIRQ(EINT3_IRQn);
Brian Silverman25aae9a2013-10-08 13:37:45 -0700282 portTickType new_time = xDelayTimeFrom;
283 xDelayTimeFrom = 0;
284 NVIC_EnableIRQ(EINT3_IRQn);
285
286 if (new_time != 0) {
287 xSleepFrom = new_time;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700288
289 vTaskDelayUntil(&xSleepFrom, kBottomFallDelayTime / portTICK_RATE_MS);
290
Brian Silverman25aae9a2013-10-08 13:37:45 -0700291 // Make sure that the USB ISR doesn't look at inconsistent values.
Brian Silverman1623c332013-10-01 18:05:16 -0700292 NVIC_DisableIRQ(USB_IRQn);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700293 capture_bottom_fall_delay = encoder3_val;
Brian Silverman1623c332013-10-01 18:05:16 -0700294 ++bottom_fall_delay_count;
295 NVIC_EnableIRQ(USB_IRQn);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700296 } else {
Brian Silverman25aae9a2013-10-08 13:37:45 -0700297 // Wait 10ms and then check again.
Brian Silvermanf92396c2013-09-12 20:13:13 -0700298 vTaskDelayUntil(&xSleepFrom, 10 / portTICK_RATE_MS);
299 }
300 }
301}
302
303volatile int8_t bottom_fall_count;
Brian Silverman1623c332013-10-01 18:05:16 -0700304static void IndexerBottomFall(void) {
305 GPIOINT->IO0IntClr = (1 << 4);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700306 ++bottom_fall_count;
307 // edge counting start delayed capture
308 xDelayTimeFrom = xTaskGetTickCount();
Brian Silvermanf92396c2013-09-12 20:13:13 -0700309}
310volatile int32_t capture_wrist_rise;
311volatile int8_t wrist_rise_count;
Brian Silverman1623c332013-10-01 18:05:16 -0700312static void WristHallRise(void) {
313 GPIOINT->IO0IntClr = (1 << 6);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700314 // edge counting encoder capture
315 ++wrist_rise_count;
316 capture_wrist_rise = (int32_t)QEI->QEIPOS;
317}
318volatile int32_t capture_shooter_angle_rise;
319volatile int8_t shooter_angle_rise_count;
Brian Silverman1623c332013-10-01 18:05:16 -0700320static void ShooterHallRise(void) {
321 GPIOINT->IO0IntClr = (1 << 7);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700322 // edge counting encoder capture
323 ++shooter_angle_rise_count;
324 capture_shooter_angle_rise = encoder2_val;
325}
326
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000327// Third robot shooter.
Daniel Petti6300d682013-10-14 02:12:18 +0000328static void ShooterPhotoFall(void) {
Daniel Pettiaba9c612013-11-14 10:17:35 -0800329 GPIOINT->IO0IntClr = (1 << 4);
Daniel Petti6300d682013-10-14 02:12:18 +0000330 // We reset TC to make sure we don't get a crap
331 // value from CR0 when the capture interrupt occurs
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000332 // if the shooter is just starting up again, and so
333 // that the match interrupt thing works right.
Daniel Petti6300d682013-10-14 02:12:18 +0000334 reset_TC();
Brian Silvermanf92396c2013-09-12 20:13:13 -0700335}
Brian Silverman25aae9a2013-10-08 13:37:45 -0700336
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000337typedef void (*Handler)(void);
338// Contains default pointers for ISR functions.
339// (These can be used without modifications on the comp/practice bots.)
340Handler ISRTable[] = {
Brian Silvermanf92396c2013-09-12 20:13:13 -0700341 Encoder5BFall, // index 0: P2.3 Fall #bit 31 //Encoder 5 B //Dio 10
342 Encoder5AFall, // index 1: P2.2 Fall #bit 30 //Encoder 5 A //Dio 9
343 Encoder4BFall, // index 2: P2.1 Fall #bit 29 //Encoder 4 B //Dio 8
344 Encoder4AFall, // index 3: P2.0 Fall #bit 28 //Encoder 4 A //Dio 7
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000345 NoGPIO, // index 4: NO GPIO #bit 27
Brian Silvermanf92396c2013-09-12 20:13:13 -0700346 Encoder2AFall, // index 5: P0.22 Fall #bit 26 //Encoder 2 A
347 Encoder2BFall, // index 6: P0.21 Fall #bit 25 //Encoder 2 B
348 Encoder3AFall, // index 7: P0.20 Fall #bit 24 //Encoder 3 A
349 Encoder3BFall, // index 8: P0.19 Fall #bit 23 //Encoder 3 B
350 Encoder2ARise, // index 9: P0.22 Rise #bit 22 //Encoder 2 A
351 Encoder2BRise, // index 10: P0.21 Rise #bit 21 //Encoder 2 B
352 Encoder3ARise, // index 11: P0.20 Rise #bit 20 //Encoder 3 A
353 Encoder3BRise, // index 12: P0.19 Rise #bit 19 //Encoder 3 B
354 NoGPIO, // index 13: NO GPIO #bit 18
355 NoGPIO, // index 14: NO GPIO #bit 17
356 NoGPIO, // index 15: NO GPIO #bit 16
357 NoGPIO, // index 16: NO GPIO #bit 15
358 NoGPIO, // index 17: NO GPIO #bit 14
359 NoGPIO, // index 18: NO GPIO #bit 13
360 NoGPIO, // index 19: NO GPIO #bit 12
361 ShooterHallRise, // index 20: P0.7 Fall #bit 11 //Shooter Hall //Dio 4
362 WristHallRise, // index 21: P0.6 Fall #bit 10 //Wrist Hall //Dio 3
363 IndexerTopRise, // index 22: P0.5 Fall #bit 9 //Indexer Top //Dio 2
364 IndexerBottomRise, // index 23: P0.4 Fall #bit 8 //Indexer Bottom //Dio 1
365 NoGPIO, // index 24: NO GPIO #bit 7
366 NoGPIO, // index 25: NO GPIO #bit 6
367 IndexerTopFall, // index 26: P0.5 Rise #bit 5 //Indexer Top //Dio 2
368 IndexerBottomFall, // index 27: P0.4 Rise #bit 4 //Indexer Bottom //Dio 1
369 Encoder5BRise, // index 28: P2.3 Rise #bit 3 //Encoder 5 B //Dio 10
370 Encoder5ARise, // index 29: P2.2 Rise #bit 2 //Encoder 5 A //Dio 9
371 Encoder4BRise, // index 30: P2.1 Rise #bit 1 //Encoder 4 B //Dio 8
372 Encoder4ARise, // index 31: P2.0 Rise #bit 0 //Encoder 4 A //Dio 7
373 NoGPIO // index 32: NO BITS SET #False Alarm
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000374};
375
376// Count leading zeros.
377// Returns 0 if bit 31 is set etc.
378__attribute__((always_inline)) static __INLINE uint32_t __clz(uint32_t value) {
379 uint32_t result;
380 __asm__("clz %0, %1" : "=r" (result) : "r" (value));
381 return result;
382}
383inline static void IRQ_Dispatch(void) {
384 // There is no need to add a loop here to handle multiple interrupts at the
385 // same time because the processor has tail chaining of interrupts which we
386 // can't really beat with our own loop.
387 // It would actually be bad because a loop here would block EINT1/2 for longer
388 // lengths of time.
389
390 uint32_t index = __clz(GPIOINT->IO2IntStatR | GPIOINT->IO0IntStatR |
391 (GPIOINT->IO2IntStatF << 28) | (GPIOINT->IO0IntStatF << 4));
392
393 ISRTable[index]();
Brian Silvermanf92396c2013-09-12 20:13:13 -0700394}
395void EINT3_IRQHandler(void) {
Brian Silvermanf92396c2013-09-12 20:13:13 -0700396 IRQ_Dispatch();
Brian Silvermanf92396c2013-09-12 20:13:13 -0700397}
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000398
Brian Silvermanf92396c2013-09-12 20:13:13 -0700399int32_t encoder_val(int chan) {
400 int32_t val;
401 switch (chan) {
402 case 0: // Wrist
403 return (int32_t)QEI->QEIPOS;
404 case 1: // Shooter Wheel
405 NVIC_DisableIRQ(EINT1_IRQn);
406 NVIC_DisableIRQ(EINT2_IRQn);
407 val = encoder1_val;
408 NVIC_EnableIRQ(EINT2_IRQn);
409 NVIC_EnableIRQ(EINT1_IRQn);
410 return val;
411 case 2: // Shooter Angle
412 NVIC_DisableIRQ(EINT3_IRQn);
413 val = encoder2_val;
414 NVIC_EnableIRQ(EINT3_IRQn);
415 return val;
416 case 3: // Indexer
417 NVIC_DisableIRQ(EINT3_IRQn);
418 val = encoder3_val;
419 NVIC_EnableIRQ(EINT3_IRQn);
420 return val;
421 case 4: // Drive R
422 NVIC_DisableIRQ(EINT3_IRQn);
423 val = encoder4_val;
424 NVIC_EnableIRQ(EINT3_IRQn);
425 return val;
426 case 5: // Drive L
427 NVIC_DisableIRQ(EINT3_IRQn);
428 val = encoder5_val;
429 NVIC_EnableIRQ(EINT3_IRQn);
430 return val;
431 default:
432 return -1;
433 }
434}
435
Brian Silvermana280ae02013-10-28 18:21:15 -0700436static volatile uint32_t sensor_timing_wraps = 0;
437
Brian Silvermanf92396c2013-09-12 20:13:13 -0700438void encoder_init(void) {
Brian Silvermanf92396c2013-09-12 20:13:13 -0700439 // Enable interrupts from the GPIO pins.
440 NVIC_EnableIRQ(EINT3_IRQn);
441
442 if (is_bot3) {
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000443 // Modify robot handler table for third robot.
444 ISRTable[23] = ShooterPhotoFall;
445
Daniel Petti6300d682013-10-14 02:12:18 +0000446 // Set up timer for bot3 photosensor.
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000447 // Make sure timer two is powered.
448 SC->PCONP |= (1 << 22);
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000449 // Select capture 2.0 function on pin 0.4.
450 PINCON->PINSEL0 |= (0x3 << 8);
Daniel Petti6300d682013-10-14 02:12:18 +0000451 // Set timer to capture and interrupt on rising edge.
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000452 TIM2->CCR = 0x5;
Daniel Petti6300d682013-10-14 02:12:18 +0000453 // Set up match interrupt.
Daniel Petti5d0b34e2013-11-28 01:22:57 -0800454 TIM2->MR0 = kWheelStopThreshold;
Daniel Pettie7cb20f2013-10-20 05:00:51 +0000455 TIM2->MCR = 1;
Daniel Petti6300d682013-10-14 02:12:18 +0000456 // Enable timer IRQ, and make it lower priority than the encoders.
Daniel Petti03f58112013-11-09 16:35:55 +0000457 NVIC_SetPriority(TIMER2_IRQn, 1);
458 NVIC_EnableIRQ(TIMER2_IRQn);
Daniel Petti6300d682013-10-14 02:12:18 +0000459 // Set up GPIO interrupt on other edge.
Daniel Petti03f58112013-11-09 16:35:55 +0000460 GPIOINT->IO0IntEnF |= (1 << 4);
Daniel Pettid9c84d42013-10-15 04:51:07 +0000461
Brian Silvermanf92396c2013-09-12 20:13:13 -0700462 } else { // is main robot
Daniel Petti03f58112013-11-09 16:35:55 +0000463 // Setup the encoder interface.
464 SC->PCONP |= PCONP_PCQEI;
465 PINCON->PINSEL3 = ((PINCON->PINSEL3 & 0xffff3dff) | 0x00004100);
466 // Reset the count and velocity.
467 QEI->QEICON = 0x00000005;
468 QEI->QEICONF = 0x00000004;
469 // Wrap back to 0 when we wrap the int and vice versa.
470 QEI->QEIMAXPOS = 0xFFFFFFFF;
471
Daniel Pettid9c84d42013-10-15 04:51:07 +0000472 // Set up encoder 1.
473 // Make GPIOs 2.11 and 2.12 trigger EINT1 and EINT2 (respectively).
474 // PINSEL4[23:22] = {0 1}
475 // PINSEL4[25:24] = {0 1}
476 PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 22)) | (0x1 << 22);
477 PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 24)) | (0x1 << 24);
478 // Clear the interrupt flags for EINT1 and EINT2 (0x6 = 0b0110).
479 SC->EXTMODE = 0x6;
480 SC->EXTINT = 0x6;
481 NVIC_EnableIRQ(EINT1_IRQn);
482 NVIC_EnableIRQ(EINT2_IRQn);
483 encoder1_val = 0;
Daniel Petti03f58112013-11-09 16:35:55 +0000484
485 // Set up encoder 2.
486 GPIOINT->IO0IntEnF |= (1 << 22); // Set GPIO falling interrupt.
487 GPIOINT->IO0IntEnR |= (1 << 22); // Set GPIO rising interrupt.
488 GPIOINT->IO0IntEnF |= (1 << 21); // Set GPIO falling interrupt.
489 GPIOINT->IO0IntEnR |= (1 << 21); // Set GPIO rising interrupt.
490 // Make sure they're in mode 00 (the default, aka nothing special).
491 PINCON->PINSEL1 &= ~(0x3 << 12);
492 PINCON->PINSEL1 &= ~(0x3 << 10);
493 encoder2_val = 0;
Daniel Pettid9c84d42013-10-15 04:51:07 +0000494
Daniel Petti03f58112013-11-09 16:35:55 +0000495 // Set up encoder 3.
496 GPIOINT->IO0IntEnF |= (1 << 20); // Set GPIO falling interrupt.
497 GPIOINT->IO0IntEnR |= (1 << 20); // Set GPIO rising interrupt.
498 GPIOINT->IO0IntEnF |= (1 << 19); // Set GPIO falling interrupt.
499 GPIOINT->IO0IntEnR |= (1 << 19); // Set GPIO rising interrupt.
500 // Make sure they're in mode 00 (the default, aka nothing special).
501 PINCON->PINSEL1 &= ~(0x3 << 8);
502 PINCON->PINSEL1 &= ~(0x3 << 6);
503 encoder3_val = 0;
504
Daniel Petti433d6432013-11-01 05:10:28 +0000505 // Set up encoder 4.
506 GPIOINT->IO2IntEnF |= (1 << 0); // Set GPIO falling interrupt.
507 GPIOINT->IO2IntEnR |= (1 << 0); // Set GPIO rising interrupt.
508 GPIOINT->IO2IntEnF |= (1 << 1); // Set GPIO falling interrupt.
509 GPIOINT->IO2IntEnR |= (1 << 1); // Set GPIO rising interrupt.
Daniel Pettid9c84d42013-10-15 04:51:07 +0000510 // Make sure they're in mode 00 (the default, aka nothing special).
Daniel Petti433d6432013-11-01 05:10:28 +0000511 PINCON->PINSEL4 &= ~(0x3 << 0);
512 PINCON->PINSEL4 &= ~(0x3 << 2);
513 encoder4_val = 0;
Daniel Pettid9c84d42013-10-15 04:51:07 +0000514
Daniel Petti433d6432013-11-01 05:10:28 +0000515 // Set up encoder 5.
516 GPIOINT->IO2IntEnF |= (1 << 2); // Set GPIO falling interrupt.
517 GPIOINT->IO2IntEnR |= (1 << 2); // Set GPIO rising interrupt.
518 GPIOINT->IO2IntEnF |= (1 << 3); // Set GPIO falling interrupt.
519 GPIOINT->IO2IntEnR |= (1 << 3); // Set GPIO rising interrupt.
Daniel Pettid9c84d42013-10-15 04:51:07 +0000520 // Make sure they're in mode 00 (the default, aka nothing special).
Daniel Petti433d6432013-11-01 05:10:28 +0000521 PINCON->PINSEL4 &= ~(0x3 << 4);
522 PINCON->PINSEL4 &= ~(0x3 << 6);
523 encoder5_val = 0;
524
Brian Silvermanf92396c2013-09-12 20:13:13 -0700525 xTaskCreate(vDelayCapture,
526 (signed char *) "SENSORs",
527 configMINIMAL_STACK_SIZE + 100,
528 NULL /*parameters*/,
529 tskIDLE_PRIORITY + 5,
530 NULL /*return task handle*/);
531
532 GPIOINT->IO0IntEnF |= (1 << 4); // Set GPIO falling interrupt
533 GPIOINT->IO0IntEnR |= (1 << 4); // Set GPIO rising interrupt
534 PINCON->PINSEL0 &= ~(0x3 << 8);
535
536 GPIOINT->IO0IntEnF |= (1 << 5); // Set GPIO falling interrupt
537 GPIOINT->IO0IntEnR |= (1 << 5); // Set GPIO rising interrupt
538 PINCON->PINSEL0 &= ~(0x3 << 10);
539
540 GPIOINT->IO0IntEnF |= (1 << 6);
541 PINCON->PINSEL0 &= ~(0x3 << 12);
542
543 GPIOINT->IO0IntEnF |= (1 << 7);
544 PINCON->PINSEL0 &= ~(0x3 << 14);
545 }
546}
547
548void fillSensorPacket(struct DataStruct *packet) {
Brian Silvermand36b7d32013-10-24 15:56:47 -0700549 if (gyro_output.initialized) {
550 packet->gyro_angle = gyro_output.angle;
551 packet->old_gyro_reading = gyro_output.last_reading_bad;
552 packet->bad_gyro = gyro_output.gyro_bad;
553 } else {
554 packet->gyro_angle = 0;
555 packet->old_gyro_reading = 1;
556 packet->bad_gyro = 0;
557 }
Brian Silvermanf92396c2013-09-12 20:13:13 -0700558
Brian Silverman28d97782013-10-31 17:33:52 -0700559 packet->checksum = DATA_STRUCT_CHECKSUM;
560
Brian Silvermanf92396c2013-09-12 20:13:13 -0700561 packet->dip_switch0 = dip_switch(0);
562 packet->dip_switch1 = dip_switch(1);
563 packet->dip_switch2 = dip_switch(2);
564 packet->dip_switch3 = dip_switch(3);
565
Brian Silverman25aae9a2013-10-08 13:37:45 -0700566 // We disable EINT3 to avoid sending back inconsistent values. All of the
567 // aligned reads from the variables are atomic, so disabling it isn't
568 // necessary for just reading encoder values. We re-enable it periodically
569 // because disabling and enabling is cheap (2 instructions) and we really rely
570 // on low interrupt latencies.
571
Brian Silvermanf92396c2013-09-12 20:13:13 -0700572 if (is_bot3) {
573 packet->robot_id = 1;
Daniel Pettid9c84d42013-10-15 04:51:07 +0000574
575 packet->bot3.shooter_cycle_ticks = shooter_cycle_ticks;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700576 } else { // is main robot
Brian Silverman74acd622013-10-26 14:47:14 -0700577 packet->robot_id = 2;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700578
579 packet->main.shooter = encoder1_val;
Brian Silverman1623c332013-10-01 18:05:16 -0700580 packet->main.left_drive = encoder5_val;
581 packet->main.right_drive = encoder4_val;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700582 packet->main.indexer = encoder3_val;
583
Brian Silverman25aae9a2013-10-08 13:37:45 -0700584 NVIC_DisableIRQ(EINT3_IRQn);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700585
586 packet->main.wrist = (int32_t)QEI->QEIPOS;
587 packet->main.wrist_hall_effect = !digital(3);
588 packet->main.capture_wrist_rise = capture_wrist_rise;
589 packet->main.wrist_rise_count = wrist_rise_count;
590
Brian Silverman25aae9a2013-10-08 13:37:45 -0700591 NVIC_EnableIRQ(EINT3_IRQn);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700592 NVIC_DisableIRQ(EINT3_IRQn);
593
594 packet->main.capture_top_rise = capture_top_rise;
595 packet->main.top_rise_count = top_rise_count;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700596 packet->main.capture_top_fall = capture_top_fall;
597 packet->main.top_fall_count = top_fall_count;
598 packet->main.top_disc = !digital(2);
599
Brian Silverman25aae9a2013-10-08 13:37:45 -0700600 NVIC_EnableIRQ(EINT3_IRQn);
601 NVIC_DisableIRQ(EINT3_IRQn);
602
Brian Silvermanf92396c2013-09-12 20:13:13 -0700603 packet->main.capture_bottom_fall_delay = capture_bottom_fall_delay;
604 packet->main.bottom_fall_delay_count = bottom_fall_delay_count;
605 packet->main.bottom_fall_count = bottom_fall_count;
Brian Silverman3e9464f2013-11-01 15:36:08 -0700606 packet->main.bottom_rise_count = bottom_rise_count;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700607 packet->main.bottom_disc = !digital(1);
608
Brian Silverman25aae9a2013-10-08 13:37:45 -0700609 NVIC_EnableIRQ(EINT3_IRQn);
610 NVIC_DisableIRQ(EINT3_IRQn);
611
Brian Silverman1623c332013-10-01 18:05:16 -0700612 packet->main.loader_top = !digital(5);
613 packet->main.loader_bottom = !digital(6);
614
Brian Silverman25aae9a2013-10-08 13:37:45 -0700615 NVIC_EnableIRQ(EINT3_IRQn);
616 NVIC_DisableIRQ(EINT3_IRQn);
617
618 packet->main.shooter_angle = encoder2_val;
Brian Silvermanf92396c2013-09-12 20:13:13 -0700619 packet->main.capture_shooter_angle_rise = capture_shooter_angle_rise;
620 packet->main.shooter_angle_rise_count = shooter_angle_rise_count;
621 packet->main.angle_adjust_bottom_hall_effect = !digital(4);
622
623 NVIC_EnableIRQ(EINT3_IRQn);
624
Brian Silverman3e9464f2013-11-01 15:36:08 -0700625 // Do all of the analogs last because they have the potential to be slow and
626 // jittery.
Brian Silvermandb85c9a2013-11-02 14:38:43 -0700627 packet->main.battery_voltage = analog(1);
628 packet->main.left_drive_hall = analog(3);
Brian Silverman3e9464f2013-11-01 15:36:08 -0700629 packet->main.right_drive_hall = analog(2);
Brian Silvermanf92396c2013-09-12 20:13:13 -0700630 }
631}