Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 1 | #include <string.h> |
| 2 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 3 | #include "fill_packet.h" |
| 4 | #include "encoder.h" |
| 5 | |
| 6 | #include "FreeRTOS.h" |
| 7 | #include "task.h" |
| 8 | |
| 9 | #include "digital.h" |
| 10 | #include "analog.h" |
Brian Silverman | 4987694 | 2013-10-11 17:50:26 -0700 | [diff] [blame] | 11 | #include "gyro.h" |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 12 | |
| 13 | // How long (in ms) to wait after a falling edge on the bottom indexer sensor |
| 14 | // before reading the indexer encoder. |
| 15 | static const int kBottomFallDelayTime = 32; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 16 | // How long to wait for a revolution of the shooter wheel (on the third robot) |
| 17 | // before said wheel is deemed "stopped". (In secs) |
| 18 | static const uint8_t kWheelStopThreshold = 1; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 19 | |
Brian Silverman | a280ae0 | 2013-10-28 18:21:15 -0700 | [diff] [blame] | 20 | // The timer to use for timestamping sensor readings. |
| 21 | // This is a constant to avoid hard-coding it in a lot of places, but there ARE |
| 22 | // things (PCONP bits, IRQ numbers, etc) that have this value in them |
| 23 | // implicitly. |
| 24 | #define SENSOR_TIMING_TIMER TIM1 |
| 25 | // How many counts per second SENSOR_TIMING_TIMER should be. |
| 26 | // This will wrap the counter about every 1/3 of a second. |
| 27 | static const int kSensorTimingRate = 100000; |
| 28 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 29 | #define ENC(gpio, a, b) readGPIO(gpio, a) * 2 + readGPIO(gpio, b) |
| 30 | int encoder_bits(int channel) { |
| 31 | switch (channel) { |
| 32 | case 0: |
| 33 | return ENC(GPIO1, 20, 23); |
| 34 | case 1: |
| 35 | return ENC(GPIO2, 11, 12); |
| 36 | case 2: |
| 37 | return ENC(GPIO0, 21, 22); |
| 38 | case 3: |
| 39 | return ENC(GPIO0, 19, 20); |
| 40 | default: |
| 41 | return -1; |
| 42 | } |
| 43 | return -1; |
| 44 | } |
| 45 | #undef ENC |
| 46 | |
| 47 | // Uses EINT1 and EINT2 on 2.11 and 2.12. |
| 48 | volatile int32_t encoder1_val; |
| 49 | // On GPIO pins 0.22 and 0.21. |
| 50 | volatile int32_t encoder2_val; |
| 51 | // On GPIO pins 0.20 and 0.19. |
| 52 | volatile int32_t encoder3_val; |
| 53 | // On GPIO pins 2.0 and 2.1. |
| 54 | volatile int32_t encoder4_val; |
| 55 | // On GPIO pins 2.2 and 2.3. |
| 56 | volatile int32_t encoder5_val; |
| 57 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 58 | // It is important to clear the various interrupt flags first thing in the ISRs. |
| 59 | // It doesn't seem to work otherwise, possibly because of the reason that Brian |
| 60 | // found poking around online: caches on the bus make it so that the clearing of |
| 61 | // the interrupt gets to the NVIC after the ISR returns, so it runs the ISR a |
| 62 | // second time. Also, by clearing them early, if a second interrupt arrives from |
| 63 | // the same source it will still get handled instead of getting lost. |
| 64 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 65 | // ENC1A 2.11 |
| 66 | void EINT1_IRQHandler(void) { |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 67 | // Make sure to change this BEFORE clearing the interrupt like the datasheet |
| 68 | // says you have to. |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 69 | SC->EXTPOLAR ^= 0x2; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 70 | SC->EXTINT = 0x2; |
| 71 | int fiopin = GPIO2->FIOPIN; |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 72 | // This looks like a weird way to XOR the 2 inputs, but it compiles down to |
| 73 | // just 2 instructions, which is hard to beat. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 74 | if (((fiopin >> 1) ^ fiopin) & 0x800) { |
| 75 | ++encoder1_val; |
| 76 | } else { |
| 77 | --encoder1_val; |
| 78 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 79 | } |
| 80 | // ENC1B 2.12 |
| 81 | void EINT2_IRQHandler(void) { |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 82 | SC->EXTPOLAR ^= 0x4; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 83 | SC->EXTINT = 0x4; |
| 84 | int fiopin = GPIO2->FIOPIN; |
| 85 | if (((fiopin >> 1) ^ fiopin) & 0x800) { |
| 86 | --encoder1_val; |
| 87 | } else { |
| 88 | ++encoder1_val; |
| 89 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 92 | static inline void reset_TC(void) { |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 93 | TIM2->TCR |= (1 << 1); // Put it into reset. |
| 94 | while (TIM2->TC != 0) { // Wait for reset. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 95 | continue; |
| 96 | } |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 97 | TIM2->TCR = 1; // Take it out of reset + make sure it's enabled. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 100 | // TIM2 |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 101 | volatile uint32_t shooter_cycle_ticks; |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 102 | void TIMER2_IRQHandler(void) { |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 103 | // Apparently, this handler runs regardless of a match or capture event. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 104 | if (TIM2->IR & (1 << 4)) { |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 105 | // Capture |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 106 | TIM2->IR = (1 << 3); // Clear the interrupt. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 107 | |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 108 | shooter_cycle_ticks = TIM2->CR0; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 109 | |
| 110 | reset_TC(); |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 111 | } else if (TIM2->IR & 1) { |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 112 | // Match |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 113 | TIM2->IR = 1; // Clear the interrupt |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 114 | |
| 115 | // Assume shooter is stopped. |
| 116 | shooter_cycle_ticks = 0; |
| 117 | |
| 118 | // Disable timer. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 119 | TIM2->TCR = 0; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | // It will only handle one interrupt per run. |
| 123 | // If there is another interrupt pending, it won't be cleared, and the ISR |
| 124 | // will be run again to handle it. |
| 125 | } |
| 126 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 127 | // TODO(brians): Have this indicate some kind of error instead of just looping |
| 128 | // infinitely in the ISR because it never clears it. |
| 129 | static void NoGPIO(void) {} |
| 130 | static void Encoder2ARise(void) { |
| 131 | GPIOINT->IO0IntClr = (1 << 22); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 132 | if (GPIO0->FIOPIN & (1 << 21)) { |
| 133 | ++encoder2_val; |
| 134 | } else { |
| 135 | --encoder2_val; |
| 136 | } |
| 137 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 138 | static void Encoder2AFall(void) { |
| 139 | GPIOINT->IO0IntClr = (1 << 22); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 140 | if (GPIO0->FIOPIN & (1 << 21)) { |
| 141 | --encoder2_val; |
| 142 | } else { |
| 143 | ++encoder2_val; |
| 144 | } |
| 145 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 146 | static void Encoder2BRise(void) { |
| 147 | GPIOINT->IO0IntClr = (1 << 21); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 148 | if (GPIO0->FIOPIN & (1 << 22)) { |
| 149 | --encoder2_val; |
| 150 | } else { |
| 151 | ++encoder2_val; |
| 152 | } |
| 153 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 154 | static void Encoder2BFall(void) { |
| 155 | GPIOINT->IO0IntClr = (1 << 21); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 156 | if (GPIO0->FIOPIN & (1 << 22)) { |
| 157 | ++encoder2_val; |
| 158 | } else { |
| 159 | --encoder2_val; |
| 160 | } |
| 161 | } |
| 162 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 163 | static void Encoder3ARise(void) { |
| 164 | GPIOINT->IO0IntClr = (1 << 20); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 165 | if (GPIO0->FIOPIN & (1 << 19)) { |
| 166 | ++encoder3_val; |
| 167 | } else { |
| 168 | --encoder3_val; |
| 169 | } |
| 170 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 171 | static void Encoder3AFall(void) { |
| 172 | GPIOINT->IO0IntClr = (1 << 20); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 173 | if (GPIO0->FIOPIN & (1 << 19)) { |
| 174 | --encoder3_val; |
| 175 | } else { |
| 176 | ++encoder3_val; |
| 177 | } |
| 178 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 179 | static void Encoder3BRise(void) { |
| 180 | GPIOINT->IO0IntClr = (1 << 19); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 181 | if (GPIO0->FIOPIN & (1 << 20)) { |
| 182 | --encoder3_val; |
| 183 | } else { |
| 184 | ++encoder3_val; |
| 185 | } |
| 186 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 187 | static void Encoder3BFall(void) { |
| 188 | GPIOINT->IO0IntClr = (1 << 19); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 189 | if (GPIO0->FIOPIN & (1 << 20)) { |
| 190 | ++encoder3_val; |
| 191 | } else { |
| 192 | --encoder3_val; |
| 193 | } |
| 194 | } |
| 195 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 196 | static void Encoder4ARise(void) { |
| 197 | GPIOINT->IO2IntClr = (1 << 0); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 198 | if (GPIO2->FIOPIN & (1 << 1)) { |
| 199 | ++encoder4_val; |
| 200 | } else { |
| 201 | --encoder4_val; |
| 202 | } |
| 203 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 204 | static void Encoder4AFall(void) { |
| 205 | GPIOINT->IO2IntClr = (1 << 0); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 206 | if (GPIO2->FIOPIN & (1 << 1)) { |
| 207 | --encoder4_val; |
| 208 | } else { |
| 209 | ++encoder4_val; |
| 210 | } |
| 211 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 212 | static void Encoder4BRise(void) { |
| 213 | GPIOINT->IO2IntClr = (1 << 1); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 214 | if (GPIO2->FIOPIN & (1 << 0)) { |
| 215 | --encoder4_val; |
| 216 | } else { |
| 217 | ++encoder4_val; |
| 218 | } |
| 219 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 220 | static void Encoder4BFall(void) { |
| 221 | GPIOINT->IO2IntClr = (1 << 1); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 222 | if (GPIO2->FIOPIN & (1 << 0)) { |
| 223 | ++encoder4_val; |
| 224 | } else { |
| 225 | --encoder4_val; |
| 226 | } |
| 227 | } |
| 228 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 229 | static void Encoder5ARise(void) { |
| 230 | GPIOINT->IO2IntClr = (1 << 2); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 231 | if (GPIO2->FIOPIN & (1 << 3)) { |
| 232 | ++encoder5_val; |
| 233 | } else { |
| 234 | --encoder5_val; |
| 235 | } |
| 236 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 237 | static void Encoder5AFall(void) { |
| 238 | GPIOINT->IO2IntClr = (1 << 2); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 239 | if (GPIO2->FIOPIN & (1 << 3)) { |
| 240 | --encoder5_val; |
| 241 | } else { |
| 242 | ++encoder5_val; |
| 243 | } |
| 244 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 245 | static void Encoder5BRise(void) { |
| 246 | GPIOINT->IO2IntClr = (1 << 3); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 247 | if (GPIO2->FIOPIN & (1 << 2)) { |
| 248 | --encoder5_val; |
| 249 | } else { |
| 250 | ++encoder5_val; |
| 251 | } |
| 252 | } |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 253 | static void Encoder5BFall(void) { |
| 254 | GPIOINT->IO2IntClr = (1 << 3); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 255 | if (GPIO2->FIOPIN & (1 << 2)) { |
| 256 | ++encoder5_val; |
| 257 | } else { |
| 258 | --encoder5_val; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | volatile int32_t capture_top_rise; |
| 263 | volatile int8_t top_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 264 | static void IndexerTopRise(void) { |
| 265 | GPIOINT->IO0IntClr = (1 << 5); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 266 | // edge counting encoder capture |
| 267 | ++top_rise_count; |
| 268 | capture_top_rise = encoder3_val; |
| 269 | } |
| 270 | volatile int32_t capture_top_fall; |
| 271 | volatile int8_t top_fall_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 272 | static void IndexerTopFall(void) { |
| 273 | GPIOINT->IO0IntClr = (1 << 5); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 274 | // edge counting encoder capture |
| 275 | ++top_fall_count; |
| 276 | capture_top_fall = encoder3_val; |
| 277 | } |
| 278 | volatile int8_t bottom_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 279 | static void IndexerBottomRise(void) { |
| 280 | GPIOINT->IO0IntClr = (1 << 4); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 281 | // edge counting |
| 282 | ++bottom_rise_count; |
| 283 | } |
| 284 | volatile int32_t capture_bottom_fall_delay; |
| 285 | volatile int8_t bottom_fall_delay_count; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 286 | portTickType xDelayTimeFrom; |
| 287 | static portTASK_FUNCTION(vDelayCapture, pvParameters) |
| 288 | { |
| 289 | portTickType xSleepFrom = xTaskGetTickCount(); |
| 290 | |
| 291 | for (;;) { |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 292 | // Atomically (wrt the ISR) switch xDelayTimeFrom to 0 and store its old |
| 293 | // value to use later. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 294 | NVIC_DisableIRQ(EINT3_IRQn); |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 295 | portTickType new_time = xDelayTimeFrom; |
| 296 | xDelayTimeFrom = 0; |
| 297 | NVIC_EnableIRQ(EINT3_IRQn); |
| 298 | |
| 299 | if (new_time != 0) { |
| 300 | xSleepFrom = new_time; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 301 | |
| 302 | vTaskDelayUntil(&xSleepFrom, kBottomFallDelayTime / portTICK_RATE_MS); |
| 303 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 304 | // Make sure that the USB ISR doesn't look at inconsistent values. |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 305 | NVIC_DisableIRQ(USB_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 306 | capture_bottom_fall_delay = encoder3_val; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 307 | ++bottom_fall_delay_count; |
| 308 | NVIC_EnableIRQ(USB_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 309 | } else { |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 310 | // Wait 10ms and then check again. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 311 | vTaskDelayUntil(&xSleepFrom, 10 / portTICK_RATE_MS); |
| 312 | } |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | volatile int8_t bottom_fall_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 317 | static void IndexerBottomFall(void) { |
| 318 | GPIOINT->IO0IntClr = (1 << 4); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 319 | ++bottom_fall_count; |
| 320 | // edge counting start delayed capture |
| 321 | xDelayTimeFrom = xTaskGetTickCount(); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 322 | } |
| 323 | volatile int32_t capture_wrist_rise; |
| 324 | volatile int8_t wrist_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 325 | static void WristHallRise(void) { |
| 326 | GPIOINT->IO0IntClr = (1 << 6); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 327 | // edge counting encoder capture |
| 328 | ++wrist_rise_count; |
| 329 | capture_wrist_rise = (int32_t)QEI->QEIPOS; |
| 330 | } |
| 331 | volatile int32_t capture_shooter_angle_rise; |
| 332 | volatile int8_t shooter_angle_rise_count; |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 333 | static void ShooterHallRise(void) { |
| 334 | GPIOINT->IO0IntClr = (1 << 7); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 335 | // edge counting encoder capture |
| 336 | ++shooter_angle_rise_count; |
| 337 | capture_shooter_angle_rise = encoder2_val; |
| 338 | } |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 339 | |
| 340 | // Third robot shooter. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 341 | static void ShooterPhotoFall(void) { |
| 342 | GPIOINT->IO0IntClr = (1 << 23); |
| 343 | // We reset TC to make sure we don't get a crap |
| 344 | // value from CR0 when the capture interrupt occurs |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 345 | // if the shooter is just starting up again, and so |
| 346 | // that the match interrupt thing works right. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 347 | reset_TC(); |
| 348 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 349 | |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 350 | typedef void (*Handler)(void); |
| 351 | // Contains default pointers for ISR functions. |
| 352 | // (These can be used without modifications on the comp/practice bots.) |
| 353 | Handler ISRTable[] = { |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 354 | Encoder5BFall, // index 0: P2.3 Fall #bit 31 //Encoder 5 B //Dio 10 |
| 355 | Encoder5AFall, // index 1: P2.2 Fall #bit 30 //Encoder 5 A //Dio 9 |
| 356 | Encoder4BFall, // index 2: P2.1 Fall #bit 29 //Encoder 4 B //Dio 8 |
| 357 | Encoder4AFall, // index 3: P2.0 Fall #bit 28 //Encoder 4 A //Dio 7 |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 358 | NoGPIO, // index 4: NO GPIO #bit 27 |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 359 | Encoder2AFall, // index 5: P0.22 Fall #bit 26 //Encoder 2 A |
| 360 | Encoder2BFall, // index 6: P0.21 Fall #bit 25 //Encoder 2 B |
| 361 | Encoder3AFall, // index 7: P0.20 Fall #bit 24 //Encoder 3 A |
| 362 | Encoder3BFall, // index 8: P0.19 Fall #bit 23 //Encoder 3 B |
| 363 | Encoder2ARise, // index 9: P0.22 Rise #bit 22 //Encoder 2 A |
| 364 | Encoder2BRise, // index 10: P0.21 Rise #bit 21 //Encoder 2 B |
| 365 | Encoder3ARise, // index 11: P0.20 Rise #bit 20 //Encoder 3 A |
| 366 | Encoder3BRise, // index 12: P0.19 Rise #bit 19 //Encoder 3 B |
| 367 | NoGPIO, // index 13: NO GPIO #bit 18 |
| 368 | NoGPIO, // index 14: NO GPIO #bit 17 |
| 369 | NoGPIO, // index 15: NO GPIO #bit 16 |
| 370 | NoGPIO, // index 16: NO GPIO #bit 15 |
| 371 | NoGPIO, // index 17: NO GPIO #bit 14 |
| 372 | NoGPIO, // index 18: NO GPIO #bit 13 |
| 373 | NoGPIO, // index 19: NO GPIO #bit 12 |
| 374 | ShooterHallRise, // index 20: P0.7 Fall #bit 11 //Shooter Hall //Dio 4 |
| 375 | WristHallRise, // index 21: P0.6 Fall #bit 10 //Wrist Hall //Dio 3 |
| 376 | IndexerTopRise, // index 22: P0.5 Fall #bit 9 //Indexer Top //Dio 2 |
| 377 | IndexerBottomRise, // index 23: P0.4 Fall #bit 8 //Indexer Bottom //Dio 1 |
| 378 | NoGPIO, // index 24: NO GPIO #bit 7 |
| 379 | NoGPIO, // index 25: NO GPIO #bit 6 |
| 380 | IndexerTopFall, // index 26: P0.5 Rise #bit 5 //Indexer Top //Dio 2 |
| 381 | IndexerBottomFall, // index 27: P0.4 Rise #bit 4 //Indexer Bottom //Dio 1 |
| 382 | Encoder5BRise, // index 28: P2.3 Rise #bit 3 //Encoder 5 B //Dio 10 |
| 383 | Encoder5ARise, // index 29: P2.2 Rise #bit 2 //Encoder 5 A //Dio 9 |
| 384 | Encoder4BRise, // index 30: P2.1 Rise #bit 1 //Encoder 4 B //Dio 8 |
| 385 | Encoder4ARise, // index 31: P2.0 Rise #bit 0 //Encoder 4 A //Dio 7 |
| 386 | NoGPIO // index 32: NO BITS SET #False Alarm |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | // Count leading zeros. |
| 390 | // Returns 0 if bit 31 is set etc. |
| 391 | __attribute__((always_inline)) static __INLINE uint32_t __clz(uint32_t value) { |
| 392 | uint32_t result; |
| 393 | __asm__("clz %0, %1" : "=r" (result) : "r" (value)); |
| 394 | return result; |
| 395 | } |
| 396 | inline static void IRQ_Dispatch(void) { |
| 397 | // There is no need to add a loop here to handle multiple interrupts at the |
| 398 | // same time because the processor has tail chaining of interrupts which we |
| 399 | // can't really beat with our own loop. |
| 400 | // It would actually be bad because a loop here would block EINT1/2 for longer |
| 401 | // lengths of time. |
| 402 | |
| 403 | uint32_t index = __clz(GPIOINT->IO2IntStatR | GPIOINT->IO0IntStatR | |
| 404 | (GPIOINT->IO2IntStatF << 28) | (GPIOINT->IO0IntStatF << 4)); |
| 405 | |
| 406 | ISRTable[index](); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 407 | } |
| 408 | void EINT3_IRQHandler(void) { |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 409 | IRQ_Dispatch(); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 410 | } |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 411 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 412 | int32_t encoder_val(int chan) { |
| 413 | int32_t val; |
| 414 | switch (chan) { |
| 415 | case 0: // Wrist |
| 416 | return (int32_t)QEI->QEIPOS; |
| 417 | case 1: // Shooter Wheel |
| 418 | NVIC_DisableIRQ(EINT1_IRQn); |
| 419 | NVIC_DisableIRQ(EINT2_IRQn); |
| 420 | val = encoder1_val; |
| 421 | NVIC_EnableIRQ(EINT2_IRQn); |
| 422 | NVIC_EnableIRQ(EINT1_IRQn); |
| 423 | return val; |
| 424 | case 2: // Shooter Angle |
| 425 | NVIC_DisableIRQ(EINT3_IRQn); |
| 426 | val = encoder2_val; |
| 427 | NVIC_EnableIRQ(EINT3_IRQn); |
| 428 | return val; |
| 429 | case 3: // Indexer |
| 430 | NVIC_DisableIRQ(EINT3_IRQn); |
| 431 | val = encoder3_val; |
| 432 | NVIC_EnableIRQ(EINT3_IRQn); |
| 433 | return val; |
| 434 | case 4: // Drive R |
| 435 | NVIC_DisableIRQ(EINT3_IRQn); |
| 436 | val = encoder4_val; |
| 437 | NVIC_EnableIRQ(EINT3_IRQn); |
| 438 | return val; |
| 439 | case 5: // Drive L |
| 440 | NVIC_DisableIRQ(EINT3_IRQn); |
| 441 | val = encoder5_val; |
| 442 | NVIC_EnableIRQ(EINT3_IRQn); |
| 443 | return val; |
| 444 | default: |
| 445 | return -1; |
| 446 | } |
| 447 | } |
| 448 | |
Brian Silverman | a280ae0 | 2013-10-28 18:21:15 -0700 | [diff] [blame] | 449 | static volatile uint32_t sensor_timing_wraps = 0; |
| 450 | |
| 451 | void TIMER1_IRQHandler(void) { |
| 452 | SENSOR_TIMING_TIMER->IR = 1 << 0; // clear channel 0 match |
| 453 | ++sensor_timing_wraps; |
| 454 | } |
| 455 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 456 | void encoder_init(void) { |
Brian Silverman | a280ae0 | 2013-10-28 18:21:15 -0700 | [diff] [blame] | 457 | // Set up the timer for timestamping sensor readings. |
| 458 | SC->PCONP |= 1 << 2; |
| 459 | SENSOR_TIMING_TIMER->PR = (configCPU_CLOCK_HZ / kSensorTimingRate) - 1UL; |
| 460 | SENSOR_TIMING_TIMER->TC = 1; // don't match the first time around |
| 461 | SENSOR_TIMING_TIMER->MR0 = 0; // match every time it wraps |
| 462 | SENSOR_TIMING_TIMER->MCR = 1 << 0; // interrupt on match channel 0 |
| 463 | // Priority 4 is higher than any FreeRTOS-managed stuff (ie USB), but lower |
| 464 | // than encoders etc. |
| 465 | NVIC_SetPriority(TIMER1_IRQn, 4); |
| 466 | NVIC_EnableIRQ(TIMER1_IRQn); |
| 467 | SENSOR_TIMING_TIMER->TCR = 1; // enable it |
| 468 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 469 | // Setup the encoder interface. |
| 470 | SC->PCONP |= PCONP_PCQEI; |
| 471 | PINCON->PINSEL3 = ((PINCON->PINSEL3 & 0xffff3dff) | 0x00004100); |
| 472 | // Reset the count and velocity. |
| 473 | QEI->QEICON = 0x00000005; |
| 474 | QEI->QEICONF = 0x00000004; |
| 475 | // Wrap back to 0 when we wrap the int and vice versa. |
| 476 | QEI->QEIMAXPOS = 0xFFFFFFFF; |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 477 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 478 | // Set up encoder 2. |
| 479 | GPIOINT->IO0IntEnF |= (1 << 22); // Set GPIO falling interrupt. |
| 480 | GPIOINT->IO0IntEnR |= (1 << 22); // Set GPIO rising interrupt. |
| 481 | GPIOINT->IO0IntEnF |= (1 << 21); // Set GPIO falling interrupt. |
| 482 | GPIOINT->IO0IntEnR |= (1 << 21); // Set GPIO rising interrupt. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 483 | // Make sure they're in mode 00 (the default, aka nothing special). |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 484 | PINCON->PINSEL1 &= ~(0x3 << 12); |
| 485 | PINCON->PINSEL1 &= ~(0x3 << 10); |
| 486 | encoder2_val = 0; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 487 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 488 | // Set up encoder 3. |
| 489 | GPIOINT->IO0IntEnF |= (1 << 20); // Set GPIO falling interrupt. |
| 490 | GPIOINT->IO0IntEnR |= (1 << 20); // Set GPIO rising interrupt. |
| 491 | GPIOINT->IO0IntEnF |= (1 << 19); // Set GPIO falling interrupt. |
| 492 | GPIOINT->IO0IntEnR |= (1 << 19); // Set GPIO rising interrupt. |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 493 | // Make sure they're in mode 00 (the default, aka nothing special). |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 494 | PINCON->PINSEL1 &= ~(0x3 << 8); |
| 495 | PINCON->PINSEL1 &= ~(0x3 << 6); |
| 496 | encoder3_val = 0; |
| 497 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 498 | // Enable interrupts from the GPIO pins. |
| 499 | NVIC_EnableIRQ(EINT3_IRQn); |
| 500 | |
| 501 | if (is_bot3) { |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 502 | // Modify robot handler table for third robot. |
| 503 | ISRTable[23] = ShooterPhotoFall; |
| 504 | |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 505 | // Set up timer for bot3 photosensor. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 506 | // Make sure timer two is powered. |
| 507 | SC->PCONP |= (1 << 22); |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 508 | // We don't need all the precision the CCLK can provide. |
| 509 | // We'll use CCLK/8. (12.5 mhz). |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 510 | SC->PCLKSEL1 |= (0x3 << 12); |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 511 | // Use timer prescale to get that freq down to 500 hz. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 512 | TIM2->PR = 25000; |
| 513 | // Select capture 2.0 function on pin 0.4. |
| 514 | PINCON->PINSEL0 |= (0x3 << 8); |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 515 | // Set timer to capture and interrupt on rising edge. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 516 | TIM2->CCR = 0x5; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 517 | // Set up match interrupt. |
Daniel Petti | e7cb20f | 2013-10-20 05:00:51 +0000 | [diff] [blame] | 518 | TIM2->MR0 = kWheelStopThreshold * 500; |
| 519 | TIM2->MCR = 1; |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 520 | // Enable timer IRQ, and make it lower priority than the encoders. |
| 521 | NVIC_SetPriority(TIMER3_IRQn, 1); |
| 522 | NVIC_EnableIRQ(TIMER3_IRQn); |
| 523 | // Set up GPIO interrupt on other edge. |
Daniel Petti | 6300d68 | 2013-10-14 02:12:18 +0000 | [diff] [blame] | 524 | GPIOINT->IO0IntEnF |= (1 << 23); |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 525 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 526 | } else { // is main robot |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 527 | // Set up encoder 1. |
| 528 | // Make GPIOs 2.11 and 2.12 trigger EINT1 and EINT2 (respectively). |
| 529 | // PINSEL4[23:22] = {0 1} |
| 530 | // PINSEL4[25:24] = {0 1} |
| 531 | PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 22)) | (0x1 << 22); |
| 532 | PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 24)) | (0x1 << 24); |
| 533 | // Clear the interrupt flags for EINT1 and EINT2 (0x6 = 0b0110). |
| 534 | SC->EXTMODE = 0x6; |
| 535 | SC->EXTINT = 0x6; |
| 536 | NVIC_EnableIRQ(EINT1_IRQn); |
| 537 | NVIC_EnableIRQ(EINT2_IRQn); |
| 538 | encoder1_val = 0; |
| 539 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 540 | // Set up encoder 4. |
| 541 | GPIOINT->IO2IntEnF |= (1 << 0); // Set GPIO falling interrupt. |
| 542 | GPIOINT->IO2IntEnR |= (1 << 0); // Set GPIO rising interrupt. |
| 543 | GPIOINT->IO2IntEnF |= (1 << 1); // Set GPIO falling interrupt. |
| 544 | GPIOINT->IO2IntEnR |= (1 << 1); // Set GPIO rising interrupt. |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 545 | // Make sure they're in mode 00 (the default, aka nothing special). |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 546 | PINCON->PINSEL4 &= ~(0x3 << 0); |
| 547 | PINCON->PINSEL4 &= ~(0x3 << 2); |
| 548 | encoder4_val = 0; |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 549 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 550 | // Set up encoder 5. |
| 551 | GPIOINT->IO2IntEnF |= (1 << 2); // Set GPIO falling interrupt. |
| 552 | GPIOINT->IO2IntEnR |= (1 << 2); // Set GPIO rising interrupt. |
| 553 | GPIOINT->IO2IntEnF |= (1 << 3); // Set GPIO falling interrupt. |
| 554 | GPIOINT->IO2IntEnR |= (1 << 3); // Set GPIO rising interrupt. |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 555 | // Make sure they're in mode 00 (the default, aka nothing special). |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 556 | PINCON->PINSEL4 &= ~(0x3 << 4); |
| 557 | PINCON->PINSEL4 &= ~(0x3 << 6); |
| 558 | encoder5_val = 0; |
| 559 | |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 560 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 561 | xTaskCreate(vDelayCapture, |
| 562 | (signed char *) "SENSORs", |
| 563 | configMINIMAL_STACK_SIZE + 100, |
| 564 | NULL /*parameters*/, |
| 565 | tskIDLE_PRIORITY + 5, |
| 566 | NULL /*return task handle*/); |
| 567 | |
| 568 | GPIOINT->IO0IntEnF |= (1 << 4); // Set GPIO falling interrupt |
| 569 | GPIOINT->IO0IntEnR |= (1 << 4); // Set GPIO rising interrupt |
| 570 | PINCON->PINSEL0 &= ~(0x3 << 8); |
| 571 | |
| 572 | GPIOINT->IO0IntEnF |= (1 << 5); // Set GPIO falling interrupt |
| 573 | GPIOINT->IO0IntEnR |= (1 << 5); // Set GPIO rising interrupt |
| 574 | PINCON->PINSEL0 &= ~(0x3 << 10); |
| 575 | |
| 576 | GPIOINT->IO0IntEnF |= (1 << 6); |
| 577 | PINCON->PINSEL0 &= ~(0x3 << 12); |
| 578 | |
| 579 | GPIOINT->IO0IntEnF |= (1 << 7); |
| 580 | PINCON->PINSEL0 &= ~(0x3 << 14); |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | void fillSensorPacket(struct DataStruct *packet) { |
Brian Silverman | d36b7d3 | 2013-10-24 15:56:47 -0700 | [diff] [blame] | 585 | if (gyro_output.initialized) { |
| 586 | packet->gyro_angle = gyro_output.angle; |
| 587 | packet->old_gyro_reading = gyro_output.last_reading_bad; |
| 588 | packet->bad_gyro = gyro_output.gyro_bad; |
| 589 | } else { |
| 590 | packet->gyro_angle = 0; |
| 591 | packet->old_gyro_reading = 1; |
| 592 | packet->bad_gyro = 0; |
| 593 | } |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 594 | |
Brian Silverman | a280ae0 | 2013-10-28 18:21:15 -0700 | [diff] [blame] | 595 | NVIC_DisableIRQ(TIMER1_IRQn); |
| 596 | packet->timestamp = ((uint64_t)sensor_timing_wraps << 32) | TIM1->TC; |
| 597 | NVIC_EnableIRQ(TIMER1_IRQn); |
| 598 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 599 | packet->dip_switch0 = dip_switch(0); |
| 600 | packet->dip_switch1 = dip_switch(1); |
| 601 | packet->dip_switch2 = dip_switch(2); |
| 602 | packet->dip_switch3 = dip_switch(3); |
| 603 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 604 | // We disable EINT3 to avoid sending back inconsistent values. All of the |
| 605 | // aligned reads from the variables are atomic, so disabling it isn't |
| 606 | // necessary for just reading encoder values. We re-enable it periodically |
| 607 | // because disabling and enabling is cheap (2 instructions) and we really rely |
| 608 | // on low interrupt latencies. |
| 609 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 610 | if (is_bot3) { |
| 611 | packet->robot_id = 1; |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 612 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 613 | packet->main.left_drive = encoder3_val; |
| 614 | packet->main.right_drive = encoder2_val; |
| 615 | |
Daniel Petti | d9c84d4 | 2013-10-15 04:51:07 +0000 | [diff] [blame] | 616 | packet->bot3.shooter_cycle_ticks = shooter_cycle_ticks; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 617 | } else { // is main robot |
Brian Silverman | 74acd62 | 2013-10-26 14:47:14 -0700 | [diff] [blame] | 618 | packet->robot_id = 2; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 619 | |
Daniel Petti | 433d643 | 2013-11-01 05:10:28 +0000 | [diff] [blame] | 620 | packet->main.left_drive = encoder5_val; |
| 621 | packet->main.right_drive = encoder4_val; |
| 622 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 623 | packet->main.shooter = encoder1_val; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 624 | packet->main.indexer = encoder3_val; |
Brian Silverman | 1ba46c7 | 2013-10-31 16:05:57 -0700 | [diff] [blame] | 625 | packet->main.battery_voltage = analog(3); |
Brian Silverman | 74acd62 | 2013-10-26 14:47:14 -0700 | [diff] [blame] | 626 | packet->main.left_drive_hall = analog(1); |
Brian Silverman | 1ba46c7 | 2013-10-31 16:05:57 -0700 | [diff] [blame] | 627 | packet->main.right_drive_hall = analog(2); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 628 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 629 | NVIC_DisableIRQ(EINT3_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 630 | |
| 631 | packet->main.wrist = (int32_t)QEI->QEIPOS; |
| 632 | packet->main.wrist_hall_effect = !digital(3); |
| 633 | packet->main.capture_wrist_rise = capture_wrist_rise; |
| 634 | packet->main.wrist_rise_count = wrist_rise_count; |
| 635 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 636 | NVIC_EnableIRQ(EINT3_IRQn); |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 637 | NVIC_DisableIRQ(EINT3_IRQn); |
| 638 | |
| 639 | packet->main.capture_top_rise = capture_top_rise; |
| 640 | packet->main.top_rise_count = top_rise_count; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 641 | packet->main.capture_top_fall = capture_top_fall; |
| 642 | packet->main.top_fall_count = top_fall_count; |
| 643 | packet->main.top_disc = !digital(2); |
| 644 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 645 | NVIC_EnableIRQ(EINT3_IRQn); |
| 646 | NVIC_DisableIRQ(EINT3_IRQn); |
| 647 | |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 648 | packet->main.capture_bottom_fall_delay = capture_bottom_fall_delay; |
| 649 | packet->main.bottom_fall_delay_count = bottom_fall_delay_count; |
| 650 | packet->main.bottom_fall_count = bottom_fall_count; |
| 651 | packet->main.bottom_disc = !digital(1); |
| 652 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 653 | NVIC_EnableIRQ(EINT3_IRQn); |
| 654 | NVIC_DisableIRQ(EINT3_IRQn); |
| 655 | |
Brian Silverman | 1623c33 | 2013-10-01 18:05:16 -0700 | [diff] [blame] | 656 | packet->main.loader_top = !digital(5); |
| 657 | packet->main.loader_bottom = !digital(6); |
| 658 | |
Brian Silverman | 25aae9a | 2013-10-08 13:37:45 -0700 | [diff] [blame] | 659 | NVIC_EnableIRQ(EINT3_IRQn); |
| 660 | NVIC_DisableIRQ(EINT3_IRQn); |
| 661 | |
| 662 | packet->main.shooter_angle = encoder2_val; |
Brian Silverman | f92396c | 2013-09-12 20:13:13 -0700 | [diff] [blame] | 663 | packet->main.capture_shooter_angle_rise = capture_shooter_angle_rise; |
| 664 | packet->main.shooter_angle_rise_count = shooter_angle_rise_count; |
| 665 | packet->main.angle_adjust_bottom_hall_effect = !digital(4); |
| 666 | |
| 667 | NVIC_EnableIRQ(EINT3_IRQn); |
| 668 | |
| 669 | packet->main.bottom_rise_count = bottom_rise_count; |
| 670 | } |
| 671 | } |