Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 1 | #include "motors/peripheral/uart.h" |
| 2 | |
| 3 | #include <stdint.h> |
| 4 | |
| 5 | namespace frc971 { |
| 6 | namespace teensy { |
| 7 | |
James Kuszmaul | 0844eb2 | 2018-09-08 15:54:04 -0700 | [diff] [blame] | 8 | // Currently hard-coded for 8-bit + no parity + start bit + stop bit. |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 9 | void Uart::Initialize(int baud_rate) { |
| 10 | { |
| 11 | // UART baud rate = UART module clock / (16 * (SBR[12:0] + BRFD)) |
| 12 | // BRFD = BRFA (bitfield) / 32 |
| 13 | const int desired_receiver_clock = baud_rate * 16; |
| 14 | const int sbr_and_brfd32 = |
| 15 | ((static_cast<int64_t>(module_clock_frequency_) * UINT64_C(64) / |
| 16 | static_cast<int64_t>(desired_receiver_clock)) + |
| 17 | 1) / |
| 18 | 2; |
| 19 | const int sbr = sbr_and_brfd32 / 32; |
| 20 | const int brfa = sbr_and_brfd32 % 32; |
| 21 | |
| 22 | module_->BDH = (sbr >> 8) & 0x1F; |
| 23 | module_->BDL = sbr & 0xFF; |
James Kuszmaul | 0844eb2 | 2018-09-08 15:54:04 -0700 | [diff] [blame] | 24 | module_->C1 = M_UART_ILT /* only detect idle after stop bit */ | |
| 25 | M_UART_PT /* odd parity */; |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 26 | module_->C4 = V_UART_BRFA(brfa); |
| 27 | } |
| 28 | { |
| 29 | const uint8_t pfifo = module_->PFIFO; |
| 30 | tx_fifo_size_ = G_UART_TXFIFOSIZE(pfifo); |
| 31 | rx_fifo_size_ = G_UART_RXFIFOSIZE(pfifo); |
| 32 | } |
| 33 | |
| 34 | // When C1[M] is set and C4[M10] is cleared, the UART is configured for 9-bit |
| 35 | // data characters. If C1[PE] is enabled, the ninth bit is either C3[T8/R8] or |
| 36 | // the internally generated parity bit |
| 37 | |
| 38 | // TODO(Brian): M_UART_TIE /* Enable TX interrupt or DMA */ | |
| 39 | // M_UART_RIE /* Enable RX interrupt or DMA */ |
| 40 | // Also set in C5: M_UART_TDMAS /* Do DMA for TX */ | |
| 41 | // M_UART_RDMAS /* Do DMA for RX */ |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 42 | c2_value_ = 0; |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 43 | module_->C2 = c2_value_; |
| 44 | module_->PFIFO = |
| 45 | M_UART_TXFE /* Enable TX FIFO */ | M_UART_RXFE /* Enable RX FIFO */; |
| 46 | module_->CFIFO = |
| 47 | M_UART_TXFLUSH /* Flush TX FIFO */ | M_UART_RXFLUSH /* Flush RX FIFO */; |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 48 | c2_value_ = M_UART_TE | M_UART_RE; |
| 49 | module_->C2 = c2_value_; |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 50 | // TODO(Brian): Adjust for DMA? |
| 51 | module_->TWFIFO = tx_fifo_size_ - 1; |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 52 | module_->RWFIFO = 1; |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 53 | } |
| 54 | |
Brian Silverman | 4787a6e | 2018-10-06 16:00:54 -0700 | [diff] [blame] | 55 | void Uart::DoWrite(gsl::span<const char> data) { |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 56 | // In theory, we could be more efficient about this by writing the number of |
| 57 | // bytes we know there's space for and only calling SpaceAvailable() (or |
| 58 | // otherwise reading S1) before the final one. In practice, the FIFOs are so |
| 59 | // short on this part it probably won't help anything. |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 60 | for (int i = 0; i < data.size(); ++i) { |
| 61 | while (!SpaceAvailable()) { |
| 62 | } |
| 63 | WriteCharacter(data[i]); |
| 64 | } |
| 65 | } |
| 66 | |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 67 | aos::SizedArray<char, 4> Uart::DoRead() { |
| 68 | // In theory, we could be more efficient about this by reading the number of |
| 69 | // bytes we know to be accessible and only calling DataAvailable() (or |
| 70 | // otherwise reading S1) before the final one. In practice, the FIFOs are so |
| 71 | // short on this part it probably won't help anything. |
| 72 | aos::SizedArray<char, 4> result; |
| 73 | while (DataAvailable() && !result.full()) { |
| 74 | result.push_back(ReadCharacter()); |
| 75 | } |
| 76 | return result; |
| 77 | } |
| 78 | |
| 79 | Uart::~Uart() { |
| 80 | DoDisableTransmitInterrupt(); |
| 81 | DoDisableReceiveInterrupt(); |
| 82 | } |
| 83 | |
| 84 | InterruptBufferedUart::~InterruptBufferedUart() { |
| 85 | uart_.DisableReceiveInterrupt(DisableInterrupts()); |
| 86 | } |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 87 | |
| 88 | void InterruptBufferedUart::Initialize(int baud_rate) { |
| 89 | uart_.Initialize(baud_rate); |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 90 | { |
| 91 | DisableInterrupts disable_interrupts; |
| 92 | uart_.EnableReceiveInterrupt(disable_interrupts); |
| 93 | } |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 94 | } |
| 95 | |
Brian Silverman | 4787a6e | 2018-10-06 16:00:54 -0700 | [diff] [blame] | 96 | void InterruptBufferedUart::Write(gsl::span<const char> data) { |
Brian Silverman | 12fec3f | 2018-09-09 16:09:50 -0700 | [diff] [blame] | 97 | DisableInterrupts disable_interrupts; |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 98 | uart_.EnableTransmitInterrupt(disable_interrupts); |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 99 | while (!data.empty()) { |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 100 | const int bytes_written = transmit_buffer_.PushSpan(data); |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 101 | data = data.subspan(bytes_written); |
| 102 | WriteCharacters(data.empty(), disable_interrupts); |
Brian Silverman | 12fec3f | 2018-09-09 16:09:50 -0700 | [diff] [blame] | 103 | ReenableInterrupts{&disable_interrupts}; |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 104 | } |
| 105 | } |
| 106 | |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 107 | gsl::span<char> InterruptBufferedUart::Read(gsl::span<char> buffer) { |
| 108 | size_t bytes_read = 0; |
| 109 | { |
| 110 | DisableInterrupts disable_interrupts; |
| 111 | const gsl::span<const char> read_data = |
| 112 | receive_buffer_.PopSpan(buffer.size()); |
| 113 | std::copy(read_data.begin(), read_data.end(), buffer.begin()); |
| 114 | bytes_read += read_data.size(); |
| 115 | } |
| 116 | { |
| 117 | DisableInterrupts disable_interrupts; |
| 118 | const gsl::span<const char> read_data = |
| 119 | receive_buffer_.PopSpan(buffer.size() - bytes_read); |
| 120 | std::copy(read_data.begin(), read_data.end(), |
| 121 | buffer.subspan(bytes_read).begin()); |
| 122 | bytes_read += read_data.size(); |
| 123 | } |
| 124 | return buffer.subspan(0, bytes_read); |
| 125 | } |
| 126 | |
| 127 | void InterruptBufferedUart::WriteCharacters( |
| 128 | bool disable_empty, const DisableInterrupts &disable_interrupts) { |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 129 | while (true) { |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 130 | if (transmit_buffer_.empty()) { |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 131 | if (disable_empty) { |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 132 | uart_.DisableTransmitInterrupt(disable_interrupts); |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 133 | } |
| 134 | return; |
| 135 | } |
| 136 | if (!uart_.SpaceAvailable()) { |
| 137 | return; |
| 138 | } |
Brian Silverman | 4f95879 | 2019-02-16 18:20:04 -0800 | [diff] [blame] | 139 | uart_.WriteCharacter(transmit_buffer_.PopSingle()); |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | void InterruptBufferedUart::ReadCharacters(const DisableInterrupts &) { |
| 144 | while (true) { |
| 145 | if (receive_buffer_.full()) { |
| 146 | return; |
| 147 | } |
| 148 | if (!uart_.DataAvailable()) { |
| 149 | return; |
| 150 | } |
| 151 | receive_buffer_.PushSingle(uart_.ReadCharacter()); |
Brian Silverman | 55c6202 | 2018-09-03 19:13:44 -0700 | [diff] [blame] | 152 | } |
| 153 | } |
| 154 | |
| 155 | } // namespace teensy |
| 156 | } // namespace frc971 |