Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 1 | #include "aos/time/time.h" |
| 2 | #include "motors/core/kinetis.h" |
| 3 | #include "motors/core/time.h" |
| 4 | #include "motors/peripheral/configuration.h" |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 5 | #include "motors/peripheral/spi.h" |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 6 | #include "motors/peripheral/uart.h" |
| 7 | #include "motors/print/print.h" |
| 8 | #include "motors/util.h" |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 9 | #include "third_party/GSL/include/gsl/gsl" |
| 10 | #include "y2019/jevois/cobs.h" |
| 11 | #include "y2019/jevois/spi.h" |
| 12 | #include "y2019/jevois/uart.h" |
| 13 | |
| 14 | using frc971::teensy::InterruptBufferedUart; |
| 15 | using frc971::teensy::InterruptBufferedSpi; |
| 16 | |
| 17 | // All indices here refer to the ports as numbered on the PCB. |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 18 | |
| 19 | namespace frc971 { |
| 20 | namespace jevois { |
| 21 | namespace { |
| 22 | |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 23 | // Holds all of our hardware UARTs. There is exactly one global instance for |
| 24 | // interrupt handlers to access. |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 25 | struct Uarts { |
| 26 | Uarts() { |
| 27 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 28 | global_instance = this; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 29 | } |
| 30 | ~Uarts() { |
| 31 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 32 | global_instance = nullptr; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 33 | } |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 34 | Uarts(const Uarts &) = delete; |
| 35 | Uarts &operator=(const Uarts &) = delete; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 36 | |
| 37 | void Initialize(int baud_rate) { |
| 38 | cam0.Initialize(baud_rate); |
| 39 | cam1.Initialize(baud_rate); |
| 40 | cam2.Initialize(baud_rate); |
| 41 | cam3.Initialize(baud_rate); |
| 42 | cam4.Initialize(baud_rate); |
| 43 | } |
| 44 | |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 45 | InterruptBufferedUart cam0{&UART1, F_CPU}; |
| 46 | InterruptBufferedUart cam1{&UART0, F_CPU}; |
| 47 | InterruptBufferedUart cam2{&UART2, BUS_CLOCK_FREQUENCY}; |
| 48 | InterruptBufferedUart cam3{&UART3, BUS_CLOCK_FREQUENCY}; |
| 49 | InterruptBufferedUart cam4{&UART4, BUS_CLOCK_FREQUENCY}; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 50 | |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 51 | static Uarts *global_instance; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 52 | }; |
| 53 | |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 54 | Uarts *Uarts::global_instance = nullptr; |
| 55 | |
| 56 | // Manages the transmit buffer to a single camera. |
| 57 | // |
| 58 | // We have to add delays between sending each byte in order for the camera to |
| 59 | // successfully receive them. |
| 60 | struct TransmitBuffer { |
| 61 | TransmitBuffer(InterruptBufferedUart *camera_in) : camera(camera_in) {} |
| 62 | InterruptBufferedUart *const camera; |
| 63 | |
| 64 | frc971::teensy::UartBuffer<1024> buffer; |
| 65 | aos::monotonic_clock::time_point last_send = aos::monotonic_clock::min_time; |
| 66 | |
| 67 | // Sends a byte to the camera if it's time. |
| 68 | void Tick(aos::monotonic_clock::time_point now) { |
| 69 | if (buffer.empty()) { |
| 70 | return; |
| 71 | } |
| 72 | if (now < last_send + std::chrono::milliseconds(1)) { |
| 73 | return; |
| 74 | } |
| 75 | last_send = now; |
| 76 | camera->Write(std::array<char, 1>{{buffer.PopSingle()}}); |
| 77 | } |
| 78 | |
| 79 | // Queues up another packet to send, only if the previous one has finished. |
| 80 | void MaybeWritePacket(const CameraCalibration &calibration) { |
| 81 | if (!buffer.empty()) { |
| 82 | return; |
| 83 | } |
| 84 | const auto serialized = UartPackToCamera(calibration); |
| 85 | buffer.PushSingle(0); |
| 86 | if (buffer.PushSpan(serialized) == static_cast<int>(serialized.size())) { |
| 87 | buffer.PushSingle(0); |
| 88 | } |
| 89 | } |
| 90 | }; |
| 91 | |
| 92 | InterruptBufferedSpi *global_spi_instance = nullptr; |
| 93 | |
| 94 | // Manages queueing a transfer to send via SPI. |
| 95 | class SpiQueue { |
| 96 | public: |
| 97 | SpiQueue() { |
| 98 | DisableInterrupts disable_interrupts; |
| 99 | global_instance = this; |
| 100 | } |
| 101 | ~SpiQueue() { |
| 102 | DisableInterrupts disable_interrupts; |
| 103 | global_instance = nullptr; |
| 104 | } |
| 105 | SpiQueue(const SpiQueue &) = delete; |
| 106 | SpiQueue &operator=(const SpiQueue &) = delete; |
| 107 | |
| 108 | tl::optional<gsl::span<const char, spi_transfer_size()>> Tick() { |
| 109 | { |
| 110 | DisableInterrupts disable_interrupts; |
| 111 | if (waiting_for_enable_ || waiting_for_disable_) { |
| 112 | return tl::nullopt; |
| 113 | } |
| 114 | } |
| 115 | const auto now = aos::monotonic_clock::now(); |
| 116 | if (TransferTimedOut(now)) { |
| 117 | printf("SPI timeout with %d left\n", static_cast<int>(to_receive_.size())); |
| 118 | WaitForNextTransfer(); |
| 119 | return tl::nullopt; |
| 120 | } |
| 121 | { |
| 122 | DisableInterrupts disable_interrupts; |
| 123 | if (!PERIPHERAL_BITBAND(GPIOA_PDIR, 17) && |
| 124 | cs_deassert_time_ == aos::monotonic_clock::max_time) { |
| 125 | cs_deassert_time_ = now; |
| 126 | } |
| 127 | } |
| 128 | if (DeassertHappened(now)) { |
| 129 | printf("CS deasserted with %d left\n", static_cast<int>(to_receive_.size())); |
| 130 | WaitForNextTransfer(); |
| 131 | return tl::nullopt; |
| 132 | } |
| 133 | bool all_done; |
| 134 | { |
| 135 | DisableInterrupts disable_interrupts; |
| 136 | if (received_dummy_) { |
| 137 | to_receive_ = to_receive_.subspan( |
| 138 | global_spi_instance->Read(to_receive_, &disable_interrupts).size()); |
| 139 | all_done = to_receive_.empty(); |
| 140 | } else { |
| 141 | std::array<char, 1> dummy_data; |
| 142 | if (global_spi_instance->Read(dummy_data, &disable_interrupts).size() >= |
| 143 | 1) { |
| 144 | received_dummy_ = true; |
| 145 | } |
| 146 | all_done = false; |
| 147 | } |
| 148 | } |
| 149 | if (all_done) { |
| 150 | WaitForNextTransfer(); |
| 151 | return received_transfer_; |
| 152 | } |
| 153 | return tl::nullopt; |
| 154 | } |
| 155 | |
| 156 | void HandleInterrupt() { |
| 157 | DisableInterrupts disable_interrupts; |
| 158 | if (waiting_for_disable_) { |
| 159 | if (!PERIPHERAL_BITBAND(GPIOA_PDIR, 17)) { |
| 160 | PORTA_PCR17 = |
| 161 | PORT_PCR_MUX(1) | PORT_PCR_IRQC(0xC) /* Interrupt when logic 1 */; |
| 162 | // Clear the interrupt flag now that we've reconfigured it. |
| 163 | PORTA_ISFR = 1 << 17; |
| 164 | waiting_for_disable_ = false; |
| 165 | } else { |
| 166 | // Clear the interrupt flag. It shouldn't trigger again immediately |
| 167 | // because the pin is still asserted. |
| 168 | PORTA_ISFR = 1 << 17; |
| 169 | } |
| 170 | return; |
| 171 | } |
| 172 | if (waiting_for_enable_) { |
| 173 | if (PERIPHERAL_BITBAND(GPIOA_PDIR, 17)) { |
| 174 | global_spi_instance->ClearQueues(disable_interrupts); |
| 175 | // Tell the SPI peripheral its CS is asserted. |
| 176 | PERIPHERAL_BITBAND(GPIOB_PDOR, 17) = 0; |
| 177 | // Disable interrupts on the enable pin. We'll re-enable once we finish |
| 178 | // the transfer. |
| 179 | PORTA_PCR17 = PORT_PCR_MUX(1); |
| 180 | // Clear the interrupt flag now that we've reconfigured it. |
| 181 | PORTA_ISFR = 1 << 17; |
| 182 | if (have_transfer_) { |
| 183 | global_spi_instance->Write(transfer_, &disable_interrupts); |
| 184 | have_transfer_ = false; |
| 185 | } else { |
| 186 | printf("Writing dummy SPI frame\n"); |
| 187 | // If we don't have anything, just write 0s to avoid getting the |
| 188 | // hardware confused. |
| 189 | global_spi_instance->Write(SpiTransfer{}, &disable_interrupts); |
| 190 | } |
| 191 | // Queue up a dummy byte at the end. This won't actually be sent, |
| 192 | // because the first byte we do send will be garbage, but it will |
| 193 | // synchronize our queues so we receive all the useful data bytes. |
| 194 | global_spi_instance->Write(std::array<char, 1>(), &disable_interrupts); |
| 195 | waiting_for_enable_ = false; |
| 196 | receive_start_ = aos::monotonic_clock::now(); |
| 197 | cs_deassert_time_ = aos::monotonic_clock::max_time; |
| 198 | // To make debugging easier. |
| 199 | received_transfer_.fill(0); |
| 200 | } else { |
| 201 | // Clear the interrupt flag. It shouldn't trigger again immediately |
| 202 | // because the pin is still asserted. |
| 203 | PORTA_ISFR = 1 << 17; |
| 204 | } |
| 205 | return; |
| 206 | } |
| 207 | // We shouldn't ever get here. Clear all the flags and hope they don't get |
| 208 | // re-asserted immediately. |
| 209 | PORTA_ISFR = UINT32_C(0xFFFFFFFF); |
| 210 | } |
| 211 | |
| 212 | void UpdateTransfer(const SpiTransfer &transfer, const DisableInterrupts &) { |
| 213 | have_transfer_ = true; |
| 214 | transfer_ = transfer; |
| 215 | } |
| 216 | |
| 217 | // Returns whether a transfer is currently queued. This will be true between a |
| 218 | // call to UpdateTransfer and that transfer actually being moved out to the |
| 219 | // hardware. |
| 220 | bool HaveTransfer(const DisableInterrupts &) const { return have_transfer_; } |
| 221 | |
| 222 | static SpiQueue *global_instance; |
| 223 | |
| 224 | private: |
| 225 | void WaitForNextTransfer() { |
| 226 | to_receive_ = received_transfer_; |
| 227 | received_dummy_ = false; |
| 228 | { |
| 229 | DisableInterrupts disable_interrupts; |
| 230 | waiting_for_enable_ = true; |
| 231 | waiting_for_disable_ = true; |
| 232 | PORTA_PCR17 = |
| 233 | PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x8) /* Interrupt when logic 0 */; |
| 234 | // Clear the interrupt flag now that we've reconfigured it. |
| 235 | PORTA_ISFR = 1 << 17; |
| 236 | } |
| 237 | // Tell the SPI peripheral its CS is de-asserted. |
| 238 | PERIPHERAL_BITBAND(GPIOB_PDOR, 17) = 1; |
| 239 | } |
| 240 | |
| 241 | bool TransferTimedOut(aos::monotonic_clock::time_point now) { |
| 242 | DisableInterrupts disable_interrupts; |
| 243 | // TODO: Revise this timeout. |
| 244 | return now - std::chrono::milliseconds(50) > receive_start_; |
| 245 | } |
| 246 | |
| 247 | bool DeassertHappened(aos::monotonic_clock::time_point now) { |
| 248 | DisableInterrupts disable_interrupts; |
| 249 | return now - std::chrono::microseconds(50) > cs_deassert_time_; |
| 250 | } |
| 251 | |
| 252 | bool waiting_for_enable_ = true; |
| 253 | bool waiting_for_disable_ = false; |
| 254 | bool have_transfer_ = false; |
| 255 | SpiTransfer transfer_; |
| 256 | bool received_dummy_ = false; |
| 257 | SpiTransfer received_transfer_; |
| 258 | gsl::span<char> to_receive_ = received_transfer_; |
| 259 | aos::monotonic_clock::time_point receive_start_; |
| 260 | aos::monotonic_clock::time_point cs_deassert_time_; |
| 261 | }; |
| 262 | |
| 263 | SpiQueue *SpiQueue::global_instance = nullptr; |
| 264 | |
| 265 | // All methods here must be fully synchronized by the caller. |
| 266 | class FrameQueue { |
| 267 | public: |
| 268 | FrameQueue() = default; |
| 269 | FrameQueue(const FrameQueue &) = delete; |
| 270 | FrameQueue &operator=(const FrameQueue &) = delete; |
| 271 | |
| 272 | void UpdateFrame(int camera, const Frame &frame) { |
| 273 | frames_[camera].targets = frame.targets; |
| 274 | frames_[camera].capture_time = aos::monotonic_clock::now() - frame.age; |
| 275 | const aos::SizedArray<int, 3> old_last_frames = last_frames_; |
| 276 | last_frames_.clear(); |
| 277 | for (int index : old_last_frames) { |
| 278 | if (index != camera) { |
| 279 | last_frames_.push_back(index); |
| 280 | } |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | // Creates and returns a transfer with all the current information. |
| 285 | // |
| 286 | // This does not actually record these frames as transferred until |
| 287 | // RemoveLatestFrames() is called. |
| 288 | SpiTransfer MakeTransfer(); |
| 289 | |
| 290 | // Records the frames represented in the result of the latest MakeTransfer() |
| 291 | // call as being transferred, so they will not be represented in subsequent |
| 292 | // MakeTransfer() calls. |
| 293 | void RemoveLatestFrames() { |
| 294 | for (int index : last_frames_) { |
| 295 | frames_[index].capture_time = aos::monotonic_clock::min_time; |
| 296 | } |
| 297 | last_frames_.clear(); |
| 298 | } |
| 299 | |
| 300 | private: |
| 301 | struct FrameData { |
| 302 | aos::SizedArray<Target, 3> targets; |
| 303 | aos::monotonic_clock::time_point capture_time = |
| 304 | aos::monotonic_clock::min_time; |
| 305 | }; |
| 306 | |
| 307 | std::array<FrameData, 5> frames_; |
| 308 | // The indices into frames_ which we returned in the last MakeTransfer() call. |
| 309 | aos::SizedArray<int, 3> last_frames_; |
| 310 | }; |
| 311 | |
| 312 | SpiTransfer FrameQueue::MakeTransfer() { |
| 313 | aos::SizedArray<int, 5> oldest_indices; |
| 314 | for (size_t i = 0; i < frames_.size(); ++i) { |
| 315 | if (frames_[i].capture_time != aos::monotonic_clock::min_time) { |
| 316 | oldest_indices.push_back(i); |
| 317 | } |
| 318 | } |
| 319 | std::sort(oldest_indices.begin(), oldest_indices.end(), [this](int a, int b) { |
| 320 | return frames_[a].capture_time < frames_[b].capture_time; |
| 321 | }); |
| 322 | |
| 323 | TeensyToRoborio message; |
| 324 | last_frames_.clear(); |
| 325 | for (int i = 0; i < std::min<int>(oldest_indices.size(), 3); ++i) { |
| 326 | const int index = oldest_indices[i]; |
| 327 | const FrameData &frame = frames_[index]; |
| 328 | const auto age = aos::monotonic_clock::now() - frame.capture_time; |
| 329 | const auto rounded_age = aos::time::round<camera_duration>(age); |
| 330 | message.frames.push_back({frame.targets, rounded_age}); |
| 331 | last_frames_.push_back(index); |
| 332 | } |
| 333 | return SpiPackToRoborio(message); |
| 334 | } |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 335 | |
| 336 | extern "C" { |
| 337 | |
| 338 | void *__stack_chk_guard = (void *)0x67111971; |
| 339 | void __stack_chk_fail(void) { |
| 340 | while (true) { |
| 341 | GPIOC_PSOR = (1 << 5); |
| 342 | printf("Stack corruption detected\n"); |
| 343 | delay(1000); |
| 344 | GPIOC_PCOR = (1 << 5); |
| 345 | delay(1000); |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | extern char *__brkval; |
| 350 | extern uint32_t __bss_ram_start__[]; |
| 351 | extern uint32_t __heap_start__[]; |
| 352 | extern uint32_t __stack_end__[]; |
| 353 | |
| 354 | void uart0_status_isr(void) { |
| 355 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 356 | Uarts::global_instance->cam1.HandleInterrupt(disable_interrupts); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | void uart1_status_isr(void) { |
| 360 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 361 | Uarts::global_instance->cam0.HandleInterrupt(disable_interrupts); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 362 | } |
| 363 | |
| 364 | void uart2_status_isr(void) { |
| 365 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 366 | Uarts::global_instance->cam2.HandleInterrupt(disable_interrupts); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 367 | } |
| 368 | |
| 369 | void uart3_status_isr(void) { |
| 370 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 371 | Uarts::global_instance->cam3.HandleInterrupt(disable_interrupts); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | void uart4_status_isr(void) { |
| 375 | DisableInterrupts disable_interrupts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 376 | Uarts::global_instance->cam4.HandleInterrupt(disable_interrupts); |
| 377 | } |
| 378 | |
| 379 | void spi0_isr(void) { |
| 380 | DisableInterrupts disable_interrupts; |
| 381 | global_spi_instance->HandleInterrupt(disable_interrupts); |
| 382 | } |
| 383 | |
| 384 | void porta_isr(void) { |
| 385 | SpiQueue::global_instance->HandleInterrupt(); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | } // extern "C" |
| 389 | |
| 390 | // A test program which echos characters back after adding a per-UART offset to |
| 391 | // them (CAM0 adds 1, CAM1 adds 2, etc). |
| 392 | __attribute__((unused)) void TestUarts() { |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 393 | Uarts *const uarts = Uarts::global_instance; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 394 | while (true) { |
| 395 | { |
| 396 | std::array<char, 10> buffer; |
| 397 | const auto data = uarts->cam0.Read(buffer); |
| 398 | for (int i = 0; i < data.size(); ++i) { |
| 399 | data[i] += 1; |
| 400 | } |
| 401 | uarts->cam0.Write(data); |
| 402 | } |
| 403 | { |
| 404 | std::array<char, 10> buffer; |
| 405 | const auto data = uarts->cam1.Read(buffer); |
| 406 | for (int i = 0; i < data.size(); ++i) { |
| 407 | data[i] += 2; |
| 408 | } |
| 409 | uarts->cam1.Write(data); |
| 410 | } |
| 411 | { |
| 412 | std::array<char, 10> buffer; |
| 413 | const auto data = uarts->cam2.Read(buffer); |
| 414 | for (int i = 0; i < data.size(); ++i) { |
| 415 | data[i] += 3; |
| 416 | } |
| 417 | uarts->cam2.Write(data); |
| 418 | } |
| 419 | { |
| 420 | std::array<char, 10> buffer; |
| 421 | const auto data = uarts->cam3.Read(buffer); |
| 422 | for (int i = 0; i < data.size(); ++i) { |
| 423 | data[i] += 4; |
| 424 | } |
| 425 | uarts->cam3.Write(data); |
| 426 | } |
| 427 | { |
| 428 | std::array<char, 10> buffer; |
| 429 | const auto data = uarts->cam4.Read(buffer); |
| 430 | for (int i = 0; i < data.size(); ++i) { |
| 431 | data[i] += 5; |
| 432 | } |
| 433 | uarts->cam4.Write(data); |
| 434 | } |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | // Tests all the I/O pins. Cycles through each one for 1 second. While active, |
| 439 | // each output is turned on, and each input has its value printed. |
| 440 | __attribute__((unused)) void TestIo() { |
| 441 | // Set SPI0 pins to GPIO. |
| 442 | // SPI_OUT |
| 443 | PERIPHERAL_BITBAND(GPIOC_PDDR, 6) = 1; |
| 444 | PORTC_PCR6 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 445 | // SPI_CS |
| 446 | PERIPHERAL_BITBAND(GPIOD_PDDR, 0) = 0; |
| 447 | PORTD_PCR0 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 448 | // SPI_IN |
| 449 | PERIPHERAL_BITBAND(GPIOC_PDDR, 7) = 0; |
| 450 | PORTC_PCR7 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 451 | // SPI_SCK |
| 452 | PERIPHERAL_BITBAND(GPIOD_PDDR, 1) = 0; |
| 453 | PORTD_PCR1 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 454 | |
| 455 | // Set LED pins to GPIO. |
| 456 | PERIPHERAL_BITBAND(GPIOC_PDDR, 11) = 1; |
| 457 | PORTC_PCR11 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 458 | PERIPHERAL_BITBAND(GPIOC_PDDR, 10) = 1; |
| 459 | PORTC_PCR10 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 460 | PERIPHERAL_BITBAND(GPIOC_PDDR, 8) = 1; |
| 461 | PORTC_PCR8 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 462 | PERIPHERAL_BITBAND(GPIOC_PDDR, 9) = 1; |
| 463 | PORTC_PCR9 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 464 | PERIPHERAL_BITBAND(GPIOB_PDDR, 18) = 1; |
| 465 | PORTB_PCR18 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 466 | PERIPHERAL_BITBAND(GPIOC_PDDR, 2) = 1; |
| 467 | PORTC_PCR2 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 468 | PERIPHERAL_BITBAND(GPIOD_PDDR, 7) = 1; |
| 469 | PORTD_PCR7 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 470 | PERIPHERAL_BITBAND(GPIOC_PDDR, 1) = 1; |
| 471 | PORTC_PCR1 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 472 | PERIPHERAL_BITBAND(GPIOB_PDDR, 19) = 1; |
| 473 | PORTB_PCR19 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 474 | PERIPHERAL_BITBAND(GPIOD_PDDR, 5) = 1; |
| 475 | PORTD_PCR5 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 476 | |
| 477 | auto next = aos::monotonic_clock::now(); |
| 478 | static constexpr auto kTick = std::chrono::seconds(1); |
| 479 | while (true) { |
| 480 | printf("SPI_MISO\n"); |
| 481 | PERIPHERAL_BITBAND(GPIOC_PDOR, 6) = 1; |
| 482 | while (aos::monotonic_clock::now() < next + kTick) { |
| 483 | } |
| 484 | PERIPHERAL_BITBAND(GPIOC_PDOR, 6) = 0; |
| 485 | next += kTick; |
| 486 | |
| 487 | while (aos::monotonic_clock::now() < next + kTick) { |
| 488 | printf("SPI_CS %d\n", (int)PERIPHERAL_BITBAND(GPIOD_PDIR, 0)); |
| 489 | } |
| 490 | next += kTick; |
| 491 | |
| 492 | while (aos::monotonic_clock::now() < next + kTick) { |
| 493 | printf("SPI_MOSI %d\n", (int)PERIPHERAL_BITBAND(GPIOC_PDIR, 7)); |
| 494 | } |
| 495 | next += kTick; |
| 496 | |
| 497 | while (aos::monotonic_clock::now() < next + kTick) { |
| 498 | printf("SPI_CLK %d\n", (int)PERIPHERAL_BITBAND(GPIOD_PDIR, 1)); |
| 499 | } |
| 500 | next += kTick; |
| 501 | |
| 502 | printf("CAM0\n"); |
| 503 | PERIPHERAL_BITBAND(GPIOC_PDOR, 11) = 1; |
| 504 | while (aos::monotonic_clock::now() < next + kTick) { |
| 505 | } |
| 506 | PERIPHERAL_BITBAND(GPIOC_PDOR, 11) = 0; |
| 507 | next += kTick; |
| 508 | |
| 509 | printf("CAM1\n"); |
| 510 | PERIPHERAL_BITBAND(GPIOC_PDOR, 10) = 1; |
| 511 | while (aos::monotonic_clock::now() < next + kTick) { |
| 512 | } |
| 513 | PERIPHERAL_BITBAND(GPIOC_PDOR, 10) = 0; |
| 514 | next += kTick; |
| 515 | |
| 516 | printf("CAM2\n"); |
| 517 | PERIPHERAL_BITBAND(GPIOC_PDOR, 8) = 1; |
| 518 | while (aos::monotonic_clock::now() < next + kTick) { |
| 519 | } |
| 520 | PERIPHERAL_BITBAND(GPIOC_PDOR, 8) = 0; |
| 521 | next += kTick; |
| 522 | |
| 523 | printf("CAM3\n"); |
| 524 | PERIPHERAL_BITBAND(GPIOC_PDOR, 9) = 1; |
| 525 | while (aos::monotonic_clock::now() < next + kTick) { |
| 526 | } |
| 527 | PERIPHERAL_BITBAND(GPIOC_PDOR, 9) = 0; |
| 528 | next += kTick; |
| 529 | |
| 530 | printf("CAM4\n"); |
| 531 | PERIPHERAL_BITBAND(GPIOB_PDOR, 18) = 1; |
| 532 | while (aos::monotonic_clock::now() < next + kTick) { |
| 533 | } |
| 534 | PERIPHERAL_BITBAND(GPIOB_PDOR, 18) = 0; |
| 535 | next += kTick; |
| 536 | |
| 537 | printf("CAM5\n"); |
| 538 | PERIPHERAL_BITBAND(GPIOC_PDOR, 2) = 1; |
| 539 | while (aos::monotonic_clock::now() < next + kTick) { |
| 540 | } |
| 541 | PERIPHERAL_BITBAND(GPIOC_PDOR, 2) = 0; |
| 542 | next += kTick; |
| 543 | |
| 544 | printf("CAM6\n"); |
| 545 | PERIPHERAL_BITBAND(GPIOD_PDOR, 7) = 1; |
| 546 | while (aos::monotonic_clock::now() < next + kTick) { |
| 547 | } |
| 548 | PERIPHERAL_BITBAND(GPIOD_PDOR, 7) = 0; |
| 549 | next += kTick; |
| 550 | |
| 551 | printf("CAM7\n"); |
| 552 | PERIPHERAL_BITBAND(GPIOC_PDOR, 1) = 1; |
| 553 | while (aos::monotonic_clock::now() < next + kTick) { |
| 554 | } |
| 555 | PERIPHERAL_BITBAND(GPIOC_PDOR, 1) = 0; |
| 556 | next += kTick; |
| 557 | |
| 558 | printf("CAM8\n"); |
| 559 | PERIPHERAL_BITBAND(GPIOB_PDOR, 19) = 1; |
| 560 | while (aos::monotonic_clock::now() < next + kTick) { |
| 561 | } |
| 562 | PERIPHERAL_BITBAND(GPIOB_PDOR, 19) = 0; |
| 563 | next += kTick; |
| 564 | |
| 565 | printf("CAM9\n"); |
| 566 | PERIPHERAL_BITBAND(GPIOD_PDOR, 5) = 1; |
| 567 | while (aos::monotonic_clock::now() < next + kTick) { |
| 568 | } |
| 569 | PERIPHERAL_BITBAND(GPIOD_PDOR, 5) = 0; |
| 570 | next += kTick; |
| 571 | } |
| 572 | } |
| 573 | |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 574 | // Does the normal work of transferring data in all directions. |
| 575 | // |
| 576 | // https://community.nxp.com/thread/466937#comment-983881 is a post from NXP |
| 577 | // claiming that it's impossible to queue up the first byte for the slave end of |
| 578 | // an SPI connection properly. Instead, we just accept there will be a garbage |
| 579 | // byte and the other end ignores it. |
| 580 | __attribute__((unused)) void TransferData() { |
| 581 | Uarts *const uarts = Uarts::global_instance; |
| 582 | std::array<CobsPacketizer<uart_to_teensy_size()>, 5> packetizers; |
| 583 | std::array<TransmitBuffer, 5> transmit_buffers{ |
| 584 | {&uarts->cam0, &uarts->cam1, &uarts->cam2, &uarts->cam3, &uarts->cam4}}; |
| 585 | FrameQueue frame_queue; |
| 586 | aos::monotonic_clock::time_point last_camera_send = |
| 587 | aos::monotonic_clock::min_time; |
| 588 | bool first = true; |
| 589 | while (true) { |
| 590 | { |
| 591 | const auto received_transfer = SpiQueue::global_instance->Tick(); |
| 592 | if (received_transfer) { |
| 593 | const auto unpacked = SpiUnpackToTeensy(*received_transfer); |
| 594 | if (!unpacked) { |
| 595 | printf("UART decode error\n"); |
| 596 | } |
| 597 | } |
| 598 | } |
| 599 | |
| 600 | { |
| 601 | std::array<char, 20> buffer; |
| 602 | packetizers[0].ParseData(uarts->cam0.Read(buffer)); |
| 603 | packetizers[1].ParseData(uarts->cam1.Read(buffer)); |
| 604 | packetizers[2].ParseData(uarts->cam2.Read(buffer)); |
| 605 | packetizers[3].ParseData(uarts->cam3.Read(buffer)); |
| 606 | packetizers[4].ParseData(uarts->cam4.Read(buffer)); |
| 607 | } |
| 608 | for (size_t i = 0; i < packetizers.size(); ++i) { |
| 609 | if (!packetizers[i].received_packet().empty()) { |
| 610 | const auto decoded = |
| 611 | UartUnpackToTeensy(packetizers[i].received_packet()); |
| 612 | packetizers[i].clear_received_packet(); |
| 613 | if (decoded) { |
| 614 | printf("got one with %d\n", (int)decoded->targets.size()); |
| 615 | frame_queue.UpdateFrame(i, *decoded); |
| 616 | } |
| 617 | } |
| 618 | } |
| 619 | { |
| 620 | bool made_transfer = false; |
| 621 | if (!first) { |
| 622 | DisableInterrupts disable_interrupts; |
| 623 | made_transfer = |
| 624 | !SpiQueue::global_instance->HaveTransfer(disable_interrupts); |
| 625 | } |
| 626 | if (made_transfer) { |
| 627 | frame_queue.RemoveLatestFrames(); |
| 628 | } |
| 629 | const auto transfer = frame_queue.MakeTransfer(); |
| 630 | { |
| 631 | DisableInterrupts disable_interrupts; |
| 632 | SpiQueue::global_instance->UpdateTransfer(transfer, disable_interrupts); |
| 633 | } |
| 634 | } |
| 635 | { |
| 636 | const auto now = aos::monotonic_clock::now(); |
| 637 | if (last_camera_send + std::chrono::milliseconds(1000) < now) { |
| 638 | last_camera_send = now; |
| 639 | CameraCalibration calibration{}; |
| 640 | calibration.teensy_now = aos::monotonic_clock::now(); |
| 641 | calibration.realtime_now = aos::realtime_clock::min_time; |
| 642 | calibration.camera_command = CameraCalibration::CameraCommand::kNormal; |
| 643 | // TODO(Brian): Actually fill out the calibration field. |
| 644 | transmit_buffers[0].MaybeWritePacket(calibration); |
| 645 | transmit_buffers[1].MaybeWritePacket(calibration); |
| 646 | transmit_buffers[2].MaybeWritePacket(calibration); |
| 647 | transmit_buffers[3].MaybeWritePacket(calibration); |
| 648 | transmit_buffers[4].MaybeWritePacket(calibration); |
| 649 | } |
| 650 | for (TransmitBuffer &transmit_buffer : transmit_buffers) { |
| 651 | transmit_buffer.Tick(now); |
| 652 | } |
| 653 | } |
| 654 | |
| 655 | first = false; |
| 656 | } |
| 657 | } |
| 658 | |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 659 | int Main() { |
| 660 | // for background about this startup delay, please see these conversations |
| 661 | // https://forum.pjrc.com/threads/36606-startup-time-(400ms)?p=113980&viewfull=1#post113980 |
| 662 | // https://forum.pjrc.com/threads/31290-Teensey-3-2-Teensey-Loader-1-24-Issues?p=87273&viewfull=1#post87273 |
| 663 | delay(400); |
| 664 | |
| 665 | // Set all interrupts to the second-lowest priority to start with. |
| 666 | for (int i = 0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_SANE_PRIORITY(i, 0xD); |
| 667 | |
| 668 | // Now set priorities for all the ones we care about. They only have meaning |
| 669 | // relative to each other, which means centralizing them here makes it a lot |
| 670 | // more manageable. |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 671 | NVIC_SET_SANE_PRIORITY(IRQ_USBOTG, 0x7); |
| 672 | NVIC_SET_SANE_PRIORITY(IRQ_UART0_STATUS, 0x3); |
| 673 | NVIC_SET_SANE_PRIORITY(IRQ_UART1_STATUS, 0x3); |
| 674 | NVIC_SET_SANE_PRIORITY(IRQ_UART2_STATUS, 0x3); |
| 675 | NVIC_SET_SANE_PRIORITY(IRQ_UART3_STATUS, 0x3); |
| 676 | NVIC_SET_SANE_PRIORITY(IRQ_UART4_STATUS, 0x3); |
| 677 | // This one is relatively sensitive to latencies. The buffer is ~4800 clock |
| 678 | // cycles long. |
| 679 | NVIC_SET_SANE_PRIORITY(IRQ_SPI0, 0x2); |
| 680 | NVIC_SET_SANE_PRIORITY(IRQ_PORTA, 0x3); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 681 | |
| 682 | // Set the LED's pin to output mode. |
| 683 | PERIPHERAL_BITBAND(GPIOC_PDDR, 5) = 1; |
| 684 | PORTC_PCR5 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 685 | |
| 686 | frc971::motors::PrintingParameters printing_parameters; |
| 687 | printing_parameters.dedicated_usb = true; |
| 688 | const ::std::unique_ptr<frc971::motors::PrintingImplementation> printing = |
| 689 | CreatePrinting(printing_parameters); |
| 690 | printing->Initialize(); |
| 691 | |
| 692 | DMA.CR = M_DMA_EMLM; |
| 693 | |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 694 | SIM_SCGC1 |= SIM_SCGC1_UART4; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 695 | SIM_SCGC4 |= |
| 696 | SIM_SCGC4_UART0 | SIM_SCGC4_UART1 | SIM_SCGC4_UART2 | SIM_SCGC4_UART3; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 697 | SIM_SCGC6 |= SIM_SCGC6_SPI0; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 698 | |
| 699 | // SPI0 goes to the roboRIO. |
| 700 | // SPI0_PCS0 is SPI_CS. |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 701 | PORTD_PCR0 = PORT_PCR_MUX(2); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 702 | // SPI0_SOUT is SPI_MISO. |
| 703 | PORTC_PCR6 = PORT_PCR_DSE | PORT_PCR_MUX(2); |
| 704 | // SPI0_SIN is SPI_MOSI. |
| 705 | PORTC_PCR7 = PORT_PCR_DSE | PORT_PCR_MUX(2); |
| 706 | // SPI0_SCK is SPI_CLK. |
| 707 | PORTD_PCR1 = PORT_PCR_DSE | PORT_PCR_MUX(2); |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 708 | // SPI_CS_DRIVE |
| 709 | PERIPHERAL_BITBAND(GPIOB_PDDR, 17) = 1; |
| 710 | PERIPHERAL_BITBAND(GPIOB_PDOR, 17) = 1; |
| 711 | PORTB_PCR17 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 712 | // SPI_CS_IN |
| 713 | PERIPHERAL_BITBAND(GPIOA_PDDR, 17) = 0; |
| 714 | // Set the filter width. |
| 715 | PORTA_DFWR = 31; |
| 716 | // Enable the filter. |
| 717 | PERIPHERAL_BITBAND(PORTA_DFER, 17) = 1; |
| 718 | PORTA_PCR17 = |
| 719 | PORT_PCR_MUX(1) | PORT_PCR_IRQC(0xC) /* Interrupt when logic 1 */; |
| 720 | // Clear the interrupt flag now that we've reconfigured it. |
| 721 | PORTA_ISFR = 1 << 17; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 722 | |
| 723 | // FTM0_CH0 is LED0 (7 in silkscreen, a beacon channel). |
| 724 | PORTC_PCR1 = PORT_PCR_DSE | PORT_PCR_MUX(4); |
| 725 | // FTM0_CH1 is LED1 (5 in silkscreen, a beacon channel). |
| 726 | PORTC_PCR2 = PORT_PCR_DSE | PORT_PCR_MUX(4); |
| 727 | // FTM0_CH7 is LED2 (6 in silkscreen, a beacon channel). |
| 728 | PORTD_PCR7 = PORT_PCR_DSE | PORT_PCR_MUX(4); |
| 729 | // FTM0_CH5 is LED3 (9 in silkscreen, a vision camera). |
| 730 | PORTD_PCR5 = PORT_PCR_DSE | PORT_PCR_MUX(4); |
| 731 | |
| 732 | // FTM2_CH1 is LED4 (8 in silkscreen, a vision camera). |
| 733 | PORTB_PCR19 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 734 | // FTM2_CH0 is LED5 (for CAM4). |
| 735 | PORTB_PCR18 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 736 | |
| 737 | // FTM3_CH4 is LED6 (for CAM2). |
| 738 | PORTC_PCR8 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 739 | // FTM3_CH5 is LED7 (for CAM3). |
| 740 | PORTC_PCR9 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 741 | // FTM3_CH6 is LED8 (for CAM1). |
| 742 | PORTC_PCR10 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 743 | // FTM3_CH7 is LED9 (for CAM0). |
| 744 | PORTC_PCR11 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 745 | |
| 746 | // This hardware has been deactivated, but keep this comment for now to |
| 747 | // document which pins it is on. |
| 748 | #if 0 |
| 749 | // This is ODROID_EN. |
| 750 | PERIPHERAL_BITBAND(GPIOC_PDDR, 0) = 1; |
| 751 | PERIPHERAL_BITBAND(GPIOC_PDOR, 0) = 0; |
| 752 | PORTC_PCR0 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 753 | // This is CAM_EN. |
| 754 | PERIPHERAL_BITBAND(GPIOB_PDDR, 0) = 1; |
| 755 | PERIPHERAL_BITBAND(GPIOB_PDOR, 0) = 0; |
| 756 | PORTB_PCR0 = PORT_PCR_DSE | PORT_PCR_MUX(1); |
| 757 | #endif |
| 758 | // This is 5V_PGOOD. |
| 759 | PERIPHERAL_BITBAND(GPIOD_PDDR, 6) = 0; |
| 760 | PORTD_PCR6 = PORT_PCR_MUX(1); |
| 761 | |
| 762 | // These go to CAM1. |
| 763 | // UART0_RX (peripheral) is UART1_RX (schematic). |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 764 | PORTA_PCR15 = PORT_PCR_DSE | PORT_PCR_MUX(3) | PORT_PCR_PE /* Do a pull */ | |
| 765 | 0 /* !PS to pull down */; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 766 | // UART0_TX (peripheral) is UART1_TX (schematic). |
| 767 | PORTA_PCR14 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 768 | |
| 769 | // These go to CAM0. |
| 770 | // UART1_RX (peripheral) is UART0_RX (schematic). |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 771 | PORTC_PCR3 = PORT_PCR_DSE | PORT_PCR_MUX(3) | PORT_PCR_PE /* Do a pull */ | |
| 772 | 0 /* !PS to pull down */; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 773 | // UART1_TX (peripheral) is UART0_TX (schematic). |
| 774 | PORTC_PCR4 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 775 | |
| 776 | // These go to CAM2. |
| 777 | // UART2_RX |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 778 | PORTD_PCR2 = PORT_PCR_DSE | PORT_PCR_MUX(3) | PORT_PCR_PE /* Do a pull */ | |
| 779 | 0 /* !PS to pull down */; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 780 | // UART2_TX |
| 781 | PORTD_PCR3 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 782 | |
| 783 | // These go to CAM3. |
| 784 | // UART3_RX |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 785 | PORTB_PCR10 = PORT_PCR_DSE | PORT_PCR_MUX(3) | PORT_PCR_PE /* Do a pull */ | |
| 786 | 0 /* !PS to pull down */; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 787 | // UART3_TX |
| 788 | PORTB_PCR11 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 789 | |
| 790 | // These go to CAM4. |
| 791 | // UART4_RX |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 792 | PORTE_PCR25 = PORT_PCR_DSE | PORT_PCR_MUX(3) | PORT_PCR_PE /* Do a pull */ | |
| 793 | 0 /* !PS to pull down */; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 794 | // UART4_TX |
| 795 | PORTE_PCR24 = PORT_PCR_DSE | PORT_PCR_MUX(3); |
| 796 | |
| 797 | Uarts uarts; |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 798 | InterruptBufferedSpi spi0{&SPI0, BUS_CLOCK_FREQUENCY}; |
| 799 | global_spi_instance = &spi0; |
| 800 | SpiQueue spi_queue; |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 801 | |
| 802 | // Give everything a chance to get going. |
| 803 | delay(100); |
| 804 | |
| 805 | printf("Ram start: %p\n", __bss_ram_start__); |
| 806 | printf("Heap start: %p\n", __heap_start__); |
| 807 | printf("Heap end: %p\n", __brkval); |
| 808 | printf("Stack start: %p\n", __stack_end__); |
| 809 | |
| 810 | uarts.Initialize(115200); |
| 811 | NVIC_ENABLE_IRQ(IRQ_UART0_STATUS); |
| 812 | NVIC_ENABLE_IRQ(IRQ_UART1_STATUS); |
| 813 | NVIC_ENABLE_IRQ(IRQ_UART2_STATUS); |
| 814 | NVIC_ENABLE_IRQ(IRQ_UART3_STATUS); |
| 815 | NVIC_ENABLE_IRQ(IRQ_UART4_STATUS); |
Brian Silverman | d7d0110 | 2019-02-24 16:11:21 -0800 | [diff] [blame^] | 816 | spi0.Initialize(); |
| 817 | NVIC_ENABLE_IRQ(IRQ_SPI0); |
| 818 | NVIC_ENABLE_IRQ(IRQ_PORTA); |
| 819 | |
| 820 | TransferData(); |
Brian Silverman | 3240e10 | 2019-02-16 18:24:24 -0800 | [diff] [blame] | 821 | |
| 822 | while (true) { |
| 823 | } |
| 824 | } |
| 825 | |
| 826 | extern "C" { |
| 827 | |
| 828 | int main(void) { |
| 829 | return Main(); |
| 830 | } |
| 831 | |
| 832 | } // extern "C" |
| 833 | |
| 834 | } // namespace |
| 835 | } // namespace jevois |
| 836 | } // namespace frc971 |