| Scott Berman | ca91c2f | 2021-12-07 21:24:33 -0800 | [diff] [blame^] | 1 | update=Sat 18 Dec 2021 05:45:38 PM PST |
| 2 | version=1 |
| 3 | last_client=kicad |
| 4 | [general] |
| 5 | version=1 |
| 6 | RootSch= |
| 7 | BoardNm= |
| 8 | [cvpcb] |
| 9 | version=1 |
| 10 | NetIExt=net |
| 11 | [eeschema] |
| 12 | version=1 |
| 13 | LibDir= |
| 14 | [eeschema/libraries] |
| 15 | [pcbnew] |
| 16 | version=1 |
| 17 | PageLayoutDescrFile= |
| 18 | LastNetListRead=RspPiPicoIMU.net |
| 19 | CopperLayerCount=4 |
| 20 | BoardThickness=1.6 |
| 21 | AllowMicroVias=0 |
| 22 | AllowBlindVias=0 |
| 23 | RequireCourtyardDefinitions=0 |
| 24 | ProhibitOverlappingCourtyards=1 |
| 25 | MinTrackWidth=0.2 |
| 26 | MinViaDiameter=0.4 |
| 27 | MinViaDrill=0.3 |
| 28 | MinMicroViaDiameter=0.2 |
| 29 | MinMicroViaDrill=0.09999999999999999 |
| 30 | MinHoleToHole=0.25 |
| 31 | TrackWidth1=0.381 |
| 32 | TrackWidth2=0.2032 |
| 33 | TrackWidth3=0.254 |
| 34 | TrackWidth4=0.381 |
| 35 | TrackWidth5=0.508 |
| 36 | TrackWidth6=1.016 |
| 37 | ViaDiameter1=1.016 |
| 38 | ViaDrill1=0.508 |
| 39 | ViaDiameter2=0.7112 |
| 40 | ViaDrill2=0.3048 |
| 41 | ViaDiameter3=1.016 |
| 42 | ViaDrill3=0.508 |
| 43 | dPairWidth1=0.2 |
| 44 | dPairGap1=0.25 |
| 45 | dPairViaGap1=0.25 |
| 46 | SilkLineWidth=0.12 |
| 47 | SilkTextSizeV=1 |
| 48 | SilkTextSizeH=1 |
| 49 | SilkTextSizeThickness=0.15 |
| 50 | SilkTextItalic=0 |
| 51 | SilkTextUpright=1 |
| 52 | CopperLineWidth=0.2 |
| 53 | CopperTextSizeV=1.5 |
| 54 | CopperTextSizeH=1.5 |
| 55 | CopperTextThickness=0.3 |
| 56 | CopperTextItalic=0 |
| 57 | CopperTextUpright=1 |
| 58 | EdgeCutLineWidth=0.05 |
| 59 | CourtyardLineWidth=0.05 |
| 60 | OthersLineWidth=0.15 |
| 61 | OthersTextSizeV=1 |
| 62 | OthersTextSizeH=1 |
| 63 | OthersTextSizeThickness=0.15 |
| 64 | OthersTextItalic=0 |
| 65 | OthersTextUpright=1 |
| 66 | SolderMaskClearance=0 |
| 67 | SolderMaskMinWidth=0 |
| 68 | SolderPasteClearance=0 |
| 69 | SolderPasteRatio=-0 |
| 70 | [pcbnew/Layer.F.Cu] |
| 71 | Name=F.Cu |
| 72 | Type=0 |
| 73 | Enabled=1 |
| 74 | [pcbnew/Layer.In1.Cu] |
| 75 | Name=In1.Cu |
| 76 | Type=1 |
| 77 | Enabled=1 |
| 78 | [pcbnew/Layer.In2.Cu] |
| 79 | Name=In2.Cu |
| 80 | Type=1 |
| 81 | Enabled=1 |
| 82 | [pcbnew/Layer.In3.Cu] |
| 83 | Name=In3.Cu |
| 84 | Type=0 |
| 85 | Enabled=0 |
| 86 | [pcbnew/Layer.In4.Cu] |
| 87 | Name=In4.Cu |
| 88 | Type=0 |
| 89 | Enabled=0 |
| 90 | [pcbnew/Layer.In5.Cu] |
| 91 | Name=In5.Cu |
| 92 | Type=0 |
| 93 | Enabled=0 |
| 94 | [pcbnew/Layer.In6.Cu] |
| 95 | Name=In6.Cu |
| 96 | Type=0 |
| 97 | Enabled=0 |
| 98 | [pcbnew/Layer.In7.Cu] |
| 99 | Name=In7.Cu |
| 100 | Type=0 |
| 101 | Enabled=0 |
| 102 | [pcbnew/Layer.In8.Cu] |
| 103 | Name=In8.Cu |
| 104 | Type=0 |
| 105 | Enabled=0 |
| 106 | [pcbnew/Layer.In9.Cu] |
| 107 | Name=In9.Cu |
| 108 | Type=0 |
| 109 | Enabled=0 |
| 110 | [pcbnew/Layer.In10.Cu] |
| 111 | Name=In10.Cu |
| 112 | Type=0 |
| 113 | Enabled=0 |
| 114 | [pcbnew/Layer.In11.Cu] |
| 115 | Name=In11.Cu |
| 116 | Type=0 |
| 117 | Enabled=0 |
| 118 | [pcbnew/Layer.In12.Cu] |
| 119 | Name=In12.Cu |
| 120 | Type=0 |
| 121 | Enabled=0 |
| 122 | [pcbnew/Layer.In13.Cu] |
| 123 | Name=In13.Cu |
| 124 | Type=0 |
| 125 | Enabled=0 |
| 126 | [pcbnew/Layer.In14.Cu] |
| 127 | Name=In14.Cu |
| 128 | Type=0 |
| 129 | Enabled=0 |
| 130 | [pcbnew/Layer.In15.Cu] |
| 131 | Name=In15.Cu |
| 132 | Type=0 |
| 133 | Enabled=0 |
| 134 | [pcbnew/Layer.In16.Cu] |
| 135 | Name=In16.Cu |
| 136 | Type=0 |
| 137 | Enabled=0 |
| 138 | [pcbnew/Layer.In17.Cu] |
| 139 | Name=In17.Cu |
| 140 | Type=0 |
| 141 | Enabled=0 |
| 142 | [pcbnew/Layer.In18.Cu] |
| 143 | Name=In18.Cu |
| 144 | Type=0 |
| 145 | Enabled=0 |
| 146 | [pcbnew/Layer.In19.Cu] |
| 147 | Name=In19.Cu |
| 148 | Type=0 |
| 149 | Enabled=0 |
| 150 | [pcbnew/Layer.In20.Cu] |
| 151 | Name=In20.Cu |
| 152 | Type=0 |
| 153 | Enabled=0 |
| 154 | [pcbnew/Layer.In21.Cu] |
| 155 | Name=In21.Cu |
| 156 | Type=0 |
| 157 | Enabled=0 |
| 158 | [pcbnew/Layer.In22.Cu] |
| 159 | Name=In22.Cu |
| 160 | Type=0 |
| 161 | Enabled=0 |
| 162 | [pcbnew/Layer.In23.Cu] |
| 163 | Name=In23.Cu |
| 164 | Type=0 |
| 165 | Enabled=0 |
| 166 | [pcbnew/Layer.In24.Cu] |
| 167 | Name=In24.Cu |
| 168 | Type=0 |
| 169 | Enabled=0 |
| 170 | [pcbnew/Layer.In25.Cu] |
| 171 | Name=In25.Cu |
| 172 | Type=0 |
| 173 | Enabled=0 |
| 174 | [pcbnew/Layer.In26.Cu] |
| 175 | Name=In26.Cu |
| 176 | Type=0 |
| 177 | Enabled=0 |
| 178 | [pcbnew/Layer.In27.Cu] |
| 179 | Name=In27.Cu |
| 180 | Type=0 |
| 181 | Enabled=0 |
| 182 | [pcbnew/Layer.In28.Cu] |
| 183 | Name=In28.Cu |
| 184 | Type=0 |
| 185 | Enabled=0 |
| 186 | [pcbnew/Layer.In29.Cu] |
| 187 | Name=In29.Cu |
| 188 | Type=0 |
| 189 | Enabled=0 |
| 190 | [pcbnew/Layer.In30.Cu] |
| 191 | Name=In30.Cu |
| 192 | Type=0 |
| 193 | Enabled=0 |
| 194 | [pcbnew/Layer.B.Cu] |
| 195 | Name=B.Cu |
| 196 | Type=0 |
| 197 | Enabled=1 |
| 198 | [pcbnew/Layer.B.Adhes] |
| 199 | Enabled=1 |
| 200 | [pcbnew/Layer.F.Adhes] |
| 201 | Enabled=1 |
| 202 | [pcbnew/Layer.B.Paste] |
| 203 | Enabled=1 |
| 204 | [pcbnew/Layer.F.Paste] |
| 205 | Enabled=1 |
| 206 | [pcbnew/Layer.B.SilkS] |
| 207 | Enabled=1 |
| 208 | [pcbnew/Layer.F.SilkS] |
| 209 | Enabled=1 |
| 210 | [pcbnew/Layer.B.Mask] |
| 211 | Enabled=1 |
| 212 | [pcbnew/Layer.F.Mask] |
| 213 | Enabled=1 |
| 214 | [pcbnew/Layer.Dwgs.User] |
| 215 | Enabled=1 |
| 216 | [pcbnew/Layer.Cmts.User] |
| 217 | Enabled=1 |
| 218 | [pcbnew/Layer.Eco1.User] |
| 219 | Enabled=1 |
| 220 | [pcbnew/Layer.Eco2.User] |
| 221 | Enabled=1 |
| 222 | [pcbnew/Layer.Edge.Cuts] |
| 223 | Enabled=1 |
| 224 | [pcbnew/Layer.Margin] |
| 225 | Enabled=1 |
| 226 | [pcbnew/Layer.B.CrtYd] |
| 227 | Enabled=1 |
| 228 | [pcbnew/Layer.F.CrtYd] |
| 229 | Enabled=1 |
| 230 | [pcbnew/Layer.B.Fab] |
| 231 | Enabled=1 |
| 232 | [pcbnew/Layer.F.Fab] |
| 233 | Enabled=1 |
| 234 | [pcbnew/Layer.Rescue] |
| 235 | Enabled=0 |
| 236 | [pcbnew/Netclasses] |
| 237 | [pcbnew/Netclasses/Default] |
| 238 | Name=Default |
| 239 | Clearance=0.254 |
| 240 | TrackWidth=0.381 |
| 241 | ViaDiameter=1.016 |
| 242 | ViaDrill=0.508 |
| 243 | uViaDiameter=0.3 |
| 244 | uViaDrill=0.1 |
| 245 | dPairWidth=0.2 |
| 246 | dPairGap=0.25 |
| 247 | dPairViaGap=0.25 |
| 248 | [pcbnew/Netclasses/1] |
| 249 | Name=BGA_signals |
| 250 | Clearance=0.254 |
| 251 | TrackWidth=0.254 |
| 252 | ViaDiameter=0.7112 |
| 253 | ViaDrill=0.3048 |
| 254 | uViaDiameter=0.3 |
| 255 | uViaDrill=0.1 |
| 256 | dPairWidth=0.2 |
| 257 | dPairGap=0.25 |
| 258 | dPairViaGap=0.25 |
| 259 | [schematic_editor] |
| 260 | version=1 |
| 261 | PageLayoutDescrFile= |
| 262 | PlotDirectoryName= |
| 263 | SubpartIdSeparator=0 |
| 264 | SubpartFirstId=65 |
| 265 | NetFmtName=Pcbnew |
| 266 | SpiceAjustPassiveValues=0 |
| 267 | LabSize=50 |
| 268 | ERC_TestSimilarLabels=1 |