Austin Schuh | 745610d | 2015-09-06 18:19:50 -0700 | [diff] [blame] | 1 | // -*- Mode: C++; c-basic-offset: 2; indent-tabs-mode: nil -*- |
| 2 | /* Copyright (c) 2007, Google Inc. |
| 3 | * All rights reserved. |
Brian Silverman | 20350ac | 2021-11-17 18:19:55 -0800 | [diff] [blame] | 4 | * |
Austin Schuh | 745610d | 2015-09-06 18:19:50 -0700 | [diff] [blame] | 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are |
| 7 | * met: |
Brian Silverman | 20350ac | 2021-11-17 18:19:55 -0800 | [diff] [blame] | 8 | * |
Austin Schuh | 745610d | 2015-09-06 18:19:50 -0700 | [diff] [blame] | 9 | * * Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * * Redistributions in binary form must reproduce the above |
| 12 | * copyright notice, this list of conditions and the following disclaimer |
| 13 | * in the documentation and/or other materials provided with the |
| 14 | * distribution. |
| 15 | * * Neither the name of Google Inc. nor the names of its |
| 16 | * contributors may be used to endorse or promote products derived from |
| 17 | * this software without specific prior written permission. |
Brian Silverman | 20350ac | 2021-11-17 18:19:55 -0800 | [diff] [blame] | 18 | * |
Austin Schuh | 745610d | 2015-09-06 18:19:50 -0700 | [diff] [blame] | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 20 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 21 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 22 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 23 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 24 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 25 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 26 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 27 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 29 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | * |
| 31 | * --- |
| 32 | * This module gets enough CPU information to optimize the |
| 33 | * atomicops module on x86. |
| 34 | */ |
| 35 | |
| 36 | #include "base/atomicops.h" |
| 37 | #include "base/basictypes.h" |
| 38 | #include "base/googleinit.h" |
| 39 | #include "base/logging.h" |
| 40 | #include <string.h> |
| 41 | |
| 42 | // This file only makes sense with atomicops-internals-x86.h -- it |
| 43 | // depends on structs that are defined in that file. If atomicops.h |
| 44 | // doesn't sub-include that file, then we aren't needed, and shouldn't |
| 45 | // try to do anything. |
| 46 | #ifdef BASE_ATOMICOPS_INTERNALS_X86_H_ |
| 47 | |
| 48 | // Inline cpuid instruction. In PIC compilations, %ebx contains the address |
| 49 | // of the global offset table. To avoid breaking such executables, this code |
| 50 | // must preserve that register's value across cpuid instructions. |
| 51 | #if defined(__i386__) |
| 52 | #define cpuid(a, b, c, d, inp) \ |
| 53 | asm ("mov %%ebx, %%edi\n" \ |
| 54 | "cpuid\n" \ |
| 55 | "xchg %%edi, %%ebx\n" \ |
| 56 | : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
| 57 | #elif defined (__x86_64__) |
| 58 | #define cpuid(a, b, c, d, inp) \ |
| 59 | asm ("mov %%rbx, %%rdi\n" \ |
| 60 | "cpuid\n" \ |
| 61 | "xchg %%rdi, %%rbx\n" \ |
| 62 | : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
| 63 | #endif |
| 64 | |
| 65 | #if defined(cpuid) // initialize the struct only on x86 |
| 66 | |
| 67 | // Set the flags so that code will run correctly and conservatively |
| 68 | // until InitGoogle() is called. |
| 69 | struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { |
| 70 | false, // no SSE2 |
| 71 | false // no cmpxchg16b |
| 72 | }; |
| 73 | |
| 74 | // Initialize the AtomicOps_Internalx86CPUFeatures struct. |
| 75 | static void AtomicOps_Internalx86CPUFeaturesInit() { |
| 76 | uint32 eax; |
| 77 | uint32 ebx; |
| 78 | uint32 ecx; |
| 79 | uint32 edx; |
| 80 | |
| 81 | // Get vendor string (issue CPUID with eax = 0) |
| 82 | cpuid(eax, ebx, ecx, edx, 0); |
| 83 | char vendor[13]; |
| 84 | memcpy(vendor, &ebx, 4); |
| 85 | memcpy(vendor + 4, &edx, 4); |
| 86 | memcpy(vendor + 8, &ecx, 4); |
| 87 | vendor[12] = 0; |
| 88 | |
| 89 | // get feature flags in ecx/edx, and family/model in eax |
| 90 | cpuid(eax, ebx, ecx, edx, 1); |
| 91 | |
| 92 | int family = (eax >> 8) & 0xf; // family and model fields |
| 93 | int model = (eax >> 4) & 0xf; |
| 94 | if (family == 0xf) { // use extended family and model fields |
| 95 | family += (eax >> 20) & 0xff; |
| 96 | model += ((eax >> 16) & 0xf) << 4; |
| 97 | } |
| 98 | |
| 99 | // edx bit 26 is SSE2 which we use to tell use whether we can use mfence |
| 100 | AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); |
| 101 | |
| 102 | // ecx bit 13 indicates whether the cmpxchg16b instruction is supported |
| 103 | AtomicOps_Internalx86CPUFeatures.has_cmpxchg16b = ((ecx >> 13) & 1); |
| 104 | } |
| 105 | |
| 106 | REGISTER_MODULE_INITIALIZER(atomicops_x86, { |
| 107 | AtomicOps_Internalx86CPUFeaturesInit(); |
| 108 | }); |
| 109 | |
| 110 | #endif |
| 111 | |
| 112 | #endif /* ifdef BASE_ATOMICOPS_INTERNALS_X86_H_ */ |