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Brian Silverman2bf644d2013-12-06 16:54:59 -08001/* File: startup_ARMCM3.S
2 * Purpose: startup file for Cortex-M3 devices. Should use with
3 * GCC for ARM Embedded Processors
4 * Version: V1.4
5 * Date: 20 Dezember 2012
6 *
7 */
8/* Copyright (c) 2011 - 2012 ARM LIMITED
9
10 All rights reserved.
11 Redistribution and use in source and binary forms, with or without
12 modification, are permitted provided that the following conditions are met:
13 - Redistributions of source code must retain the above copyright
14 notice, this list of conditions and the following disclaimer.
15 - Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18 - Neither the name of ARM nor the names of its contributors may be used
19 to endorse or promote products derived from this software without
20 specific prior written permission.
21 *
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 POSSIBILITY OF SUCH DAMAGE.
33 ---------------------------------------------------------------------------*/
34
35
Brian Silverman5020be62013-12-06 19:09:07 -080036.syntax unified
37.arch armv7-m
38.code 16
Brian Silverman2bf644d2013-12-06 16:54:59 -080039
Brian Silverman5020be62013-12-06 19:09:07 -080040.section .stack
41 .align 3
42
Brian Silverman5020be62013-12-06 19:09:07 -080043 .equ Stack_Size, 0x00000400
Brian Silverman2bf644d2013-12-06 16:54:59 -080044
Brian Silverman5020be62013-12-06 19:09:07 -080045 .globl __StackLimit
46 __StackLimit:
47 .space Stack_Size
48 .size __StackLimit, . - __StackLimit
49
50 .globl __StackTop
51 __StackTop:
52 .size __StackTop, . - __StackTop
53
54.section .heap
55 .align 3
56
57 .globl __HeapBase
58 __HeapBase:
Brian Silverman5020be62013-12-06 19:09:07 -080059 .equ Heap_Size, 0x00000C00
Brian Silverman5020be62013-12-06 19:09:07 -080060 .if Heap_Size
61 .space Heap_Size
62 .endif
63 .size __HeapBase, . - __HeapBase
64
65 .globl __HeapLimit
66 __HeapLimit:
67 .size __HeapLimit, . - __HeapLimit
Brian Silverman2bf644d2013-12-06 16:54:59 -080068
Brian Silverman2bf644d2013-12-06 16:54:59 -080069.macro ISR_HANDLER name=
Brian Silverman5020be62013-12-06 19:09:07 -080070 .section .vectors, "a"
71 .word \name
Brian Silverman2bf644d2013-12-06 16:54:59 -080072 .section .init, "ax"
Brian Silverman5020be62013-12-06 19:09:07 -080073 .thumb_func
74 .weak \name
75 \name:
76 1: b 1b /* endless loop */
Brian Silverman2bf644d2013-12-06 16:54:59 -080077.endm
78
79.macro ISR_RESERVED
Brian Silverman5020be62013-12-06 19:09:07 -080080 .section .vectors, "a"
81 .word 0
Brian Silverman2bf644d2013-12-06 16:54:59 -080082.endm
83
Brian Silverman5020be62013-12-06 19:09:07 -080084.section .vectors, "a"
85 .global _vectors
86 _vectors:
87 .long __StackTop
88 .long Reset_Handler
89 ISR_HANDLER NMI_Handler
90 ISR_HANDLER HardFault_Handler
91 ISR_HANDLER MemManage_Handler
92 ISR_HANDLER BusFault_Handler
93 ISR_HANDLER UsageFault_Handler
94 ISR_RESERVED
95 ISR_RESERVED
96 ISR_RESERVED
97 ISR_RESERVED
98 ISR_HANDLER SVC_Handler
99 ISR_HANDLER DebugMon_Handler
100 ISR_RESERVED
101 ISR_HANDLER PendSV_Handler
102 ISR_HANDLER SysTick_Handler
Brian Silverman2bf644d2013-12-06 16:54:59 -0800103
Brian Silverman5020be62013-12-06 19:09:07 -0800104 /* interrupts */
105 ISR_HANDLER WWDG_IRQHandler
106 ISR_HANDLER PVD_IRQHandler
107 ISR_HANDLER TAMP_STAMP_IRQHandler
108 ISR_HANDLER RTC_WKUP_IRQHandler
109 ISR_HANDLER FLASH_IRQHandler
110 ISR_HANDLER RCC_IRQHandler
111 ISR_HANDLER EXTI0_IRQHandler
112 ISR_HANDLER EXTI1_IRQHandler
113 ISR_HANDLER EXTI2_IRQHandler
114 ISR_HANDLER EXTI3_IRQHandler
115 ISR_HANDLER EXTI4_IRQHandler
116 ISR_HANDLER DMA1_Stream0_IRQHandler
117 ISR_HANDLER DMA1_Stream1_IRQHandler
118 ISR_HANDLER DMA1_Stream2_IRQHandler
119 ISR_HANDLER DMA1_Stream3_IRQHandler
120 ISR_HANDLER DMA1_Stream4_IRQHandler
121 ISR_HANDLER DMA1_Stream5_IRQHandler
122 ISR_HANDLER DMA1_Stream6_IRQHandler
123 ISR_HANDLER ADC_IRQHandler
124 ISR_HANDLER CAN1_TX_IRQHandler
125 ISR_HANDLER CAN1_RX0_IRQHandler
126 ISR_HANDLER CAN1_RX1_IRQHandler
127 ISR_HANDLER CAN1_SCE_IRQHandler
128 ISR_HANDLER EXTI9_5_IRQHandler
129 ISR_HANDLER TIM1_BRK_TIM9_IRQHandler
130 ISR_HANDLER TIM1_UP_TIM10_IRQHandler
131 ISR_HANDLER TIM1_TRG_COM_TIM11_IRQHandler
132 ISR_HANDLER TIM1_CC_IRQHandler
133 ISR_HANDLER TIM2_IRQHandler
134 ISR_HANDLER TIM3_IRQHandler
135 ISR_HANDLER TIM4_IRQHandler
136 ISR_HANDLER I2C1_EV_IRQHandler
137 ISR_HANDLER I2C1_ER_IRQHandler
138 ISR_HANDLER I2C2_EV_IRQHandler
139 ISR_HANDLER I2C2_ER_IRQHandler
140 ISR_HANDLER SPI1_IRQHandler
141 ISR_HANDLER SPI2_IRQHandler
142 ISR_HANDLER USART1_IRQHandler
143 ISR_HANDLER USART2_IRQHandler
144 ISR_HANDLER USART3_IRQHandler
145 ISR_HANDLER EXTI15_10_IRQHandler
146 ISR_HANDLER RTC_Alarm_IRQHandler
147 ISR_HANDLER OTG_FS_WKUP_IRQHandler
148 ISR_HANDLER TIM8_BRK_TIM12_IRQHandler
149 ISR_HANDLER TIM8_UP_TIM13_IRQHandler
150 ISR_HANDLER TIM8_TRG_COM_TIM14_IRQHandler
151 ISR_HANDLER TIM8_CC_IRQHandler
152 ISR_HANDLER DMA1_Stream7_IRQHandler
153 ISR_HANDLER FSMC_IRQHandler
154 ISR_HANDLER SDIO_IRQHandler
155 ISR_HANDLER TIM5_IRQHandler
156 ISR_HANDLER SPI3_IRQHandler
157 ISR_HANDLER UART4_IRQHandler
158 ISR_HANDLER UART5_IRQHandler
159 ISR_HANDLER TIM6_DAC_IRQHandler
160 ISR_HANDLER TIM7_IRQHandler
161 ISR_HANDLER DMA2_Stream0_IRQHandler
162 ISR_HANDLER DMA2_Stream1_IRQHandler
163 ISR_HANDLER DMA2_Stream2_IRQHandler
164 ISR_HANDLER DMA2_Stream3_IRQHandler
165 ISR_HANDLER DMA2_Stream4_IRQHandler
166 ISR_HANDLER ETH_IRQHandler
167 ISR_HANDLER ETH_WKUP_IRQHandler
168 ISR_HANDLER CAN2_TX_IRQHandler
169 ISR_HANDLER CAN2_RX0_IRQHandler
170 ISR_HANDLER CAN2_RX1_IRQHandler
171 ISR_HANDLER CAN2_SCE_IRQHandler
172 ISR_HANDLER OTG_FS_IRQHandler
173 ISR_HANDLER DMA2_Stream5_IRQHandler
174 ISR_HANDLER DMA2_Stream6_IRQHandler
175 ISR_HANDLER DMA2_Stream7_IRQHandler
176 ISR_HANDLER USART6_IRQHandler
177 ISR_HANDLER I2C3_EV_IRQHandler
178 ISR_HANDLER I2C3_ER_IRQHandler
179 ISR_HANDLER OTG_HS_EP1_OUT_IRQHandler
180 ISR_HANDLER OTG_HS_EP1_IN_IRQHandler
181 ISR_HANDLER OTG_HS_WKUP_IRQHandler
182 ISR_HANDLER OTG_HS_IRQHandler
183 ISR_HANDLER DCMI_IRQHandler
184 ISR_HANDLER CRYP_IRQHandler
185 ISR_HANDLER HASH_RNG_IRQHandler
Brian Silverman2bf644d2013-12-06 16:54:59 -0800186
Brian Silverman5020be62013-12-06 19:09:07 -0800187.section .vectors, "a"
188 _vectors_end:
Brian Silverman2bf644d2013-12-06 16:54:59 -0800189
Brian Silverman5020be62013-12-06 19:09:07 -0800190.text
191 .thumb_func
192 .align 2
193 .globl Reset_Handler
194 .type Reset_Handler, %function
195 Reset_Handler:
196
Brian Silverman2bf644d2013-12-06 16:54:59 -0800197/* Loop to copy data from read only memory to RAM. The ranges
198 * of copy from/to are specified by following symbols evaluated in
199 * linker script.
200 * __etext: End of code section, i.e., begin of data sections to copy from.
201 * __data_start__/__data_end__: RAM address range that data should be
202 * copied to. Both must be aligned to 4 bytes boundary. */
Brian Silverman5020be62013-12-06 19:09:07 -0800203 ldr r1, =__etext
204 ldr r2, =__data_start__
205 ldr r3, =__data_end__
206 subs r3, r2
207 ble .LC1
208 .LC0:
209 subs r3, #4
210 ldr r0, [r1, r3]
211 str r0, [r2, r3]
212 bgt .LC0
213 .LC1:
Brian Silverman2bf644d2013-12-06 16:54:59 -0800214
215/* Loop to zero out BSS section, which uses following symbols
216 * in linker script:
217 * __bss_start__: start of BSS section. Must align to 4
218 * __bss_end__: end of BSS section. Must align to 4
219 */
Brian Silverman5020be62013-12-06 19:09:07 -0800220 ldr r1, =__bss_start__
221 ldr r2, =__bss_end__
222 movs r0, 0
223 .LC2:
224 cmp r1, r2
225 itt lt
226 strlt r0, [r1], #4
227 blt .LC2
Brian Silverman2bf644d2013-12-06 16:54:59 -0800228
Brian Silverman5020be62013-12-06 19:09:07 -0800229 bl _start
230 1: b 1b /* endless loop if it ever returns */
231
232 .pool
233 .size Reset_Handler, . - Reset_Handler