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realtimeroboticsgroup.org / RealtimeRoboticsGroup / test / 94bbd2187a3304cd1c9ba3c28ce36fd44d52e01e / . / bbb_cape / src / cape / CMSIS / STM32F2XX.h
blob: 0f676b0b7d2ed7f0c791427c73b3e27e4f9717c3 [file] [log] [blame]
Brian Silverman2bf644d2013-12-06 16:54:59 -0800[diff] [blame]1/**
2 ******************************************************************************
3 * @file stm32f2xx.h
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 18-April-2011
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32F2xx devices.
10 *
11 * The file is the unique include file that the application programmer
12 * is using in the C source code, usually in main.c. This file contains:
13 * - Configuration section that allows to select:
14 * - Data structures and the address mapping for all peripherals
15 * - Peripheral's registers declarations and bits definition
16 * - Macros to access peripheralÂ’s registers hardware
17 *
18 ******************************************************************************
19 * @attention
20 *
21 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
22 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
23 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
24 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
25 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
26 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
27 *
28 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
29 ******************************************************************************
30 */
31
32#ifndef __STM32F2xx_H
33#define __STM32F2xx_H
34
35#ifdef __cplusplus
36 extern "C" {
37#endif /* __cplusplus */
38
39/**
40 * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0
41 */
42#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
43#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
44#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
45#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
46#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\
47 |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\
48 |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\
49 |(__STM32F2XX_STDPERIPH_VERSION_RC))
50
51/**
52 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
53 */
54#define __MPU_PRESENT 1 /*!< STM32F2XX provide an MPU */
55#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */
56#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
57
58/**
59 * @brief STM32F2XX Interrupt Number Definition, according to the selected device
60 * in @ref Library_configuration_section
61 */
62typedef enum IRQn
63{
64/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/
65 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
66 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
67 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
68 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
69 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
70 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
71 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
72 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
73/****** STM32 specific Interrupt Numbers **********************************************************************/
74 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
75 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
76 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
77 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
78 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
79 RCC_IRQn = 5, /*!< RCC global Interrupt */
80 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
81 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
82 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
83 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
84 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
85 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
86 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
87 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
88 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
89 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
90 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
91 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
92 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
93 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
94 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
95 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
96 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
97 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
98 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
99 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
100 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
101 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
102 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
103 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
104 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
105 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
106 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
107 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
108 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
109 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
110 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
111 USART1_IRQn = 37, /*!< USART1 global Interrupt */
112 USART2_IRQn = 38, /*!< USART2 global Interrupt */
113 USART3_IRQn = 39, /*!< USART3 global Interrupt */
114 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
115 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
116 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
117 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
118 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
119 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
120 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
121 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
122 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
123 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
124 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
125 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
126 UART4_IRQn = 52, /*!< UART4 global Interrupt */
127 UART5_IRQn = 53, /*!< UART5 global Interrupt */
128 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
129 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
130 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
131 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
132 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
133 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
134 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
135 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
136 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
137 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
138 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
139 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
140 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
141 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
142 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
143 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
144 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
145 USART6_IRQn = 71, /*!< USART6 global interrupt */
146 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
147 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
148 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
149 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
150 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
151 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
152 DCMI_IRQn = 78, /*!< DCMI global interrupt */
153 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
154 HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */
155} IRQn_Type;
156
157#include "core_cm3.h"
158#include <stdint.h>
159
160/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
161typedef int32_t s32;
162typedef int16_t s16;
163typedef int8_t s8;
164
165typedef const int32_t sc32; /*!< Read Only */
166typedef const int16_t sc16; /*!< Read Only */
167typedef const int8_t sc8; /*!< Read Only */
168
169typedef __IO int32_t vs32;
170typedef __IO int16_t vs16;
171typedef __IO int8_t vs8;
172
173typedef __I int32_t vsc32; /*!< Read Only */
174typedef __I int16_t vsc16; /*!< Read Only */
175typedef __I int8_t vsc8; /*!< Read Only */
176
177typedef uint32_t u32;
178typedef uint16_t u16;
179typedef uint8_t u8;
180
181typedef const uint32_t uc32; /*!< Read Only */
182typedef const uint16_t uc16; /*!< Read Only */
183typedef const uint8_t uc8; /*!< Read Only */
184
185typedef __IO uint32_t vu32;
186typedef __IO uint16_t vu16;
187typedef __IO uint8_t vu8;
188
189typedef __I uint32_t vuc32; /*!< Read Only */
190typedef __I uint16_t vuc16; /*!< Read Only */
191typedef __I uint8_t vuc8; /*!< Read Only */
192
193typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
194
195typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
196#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
197
198typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
199
200/**
201 * @brief Analog to Digital Converter
202 */
203
204typedef struct
205{
206 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
207 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
208 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
209 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
210 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
211 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
212 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
213 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
214 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
215 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
216 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
217 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
218 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
219 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
220 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
221 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
222 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
223 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
224 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
225 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
226} ADC_TypeDef;
227
228typedef struct
229{
230 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
231 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
232 __IO uint32_t CDR; /*!< ADC common regular data register for dual
233 AND triple modes, Address offset: ADC1 base address + 0x308 */
234} ADC_Common_TypeDef;
235
236
237/**
238 * @brief Controller Area Network TxMailBox
239 */
240
241typedef struct
242{
243 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
244 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
245 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
246 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
247} CAN_TxMailBox_TypeDef;
248
249/**
250 * @brief Controller Area Network FIFOMailBox
251 */
252
253typedef struct
254{
255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
259} CAN_FIFOMailBox_TypeDef;
260
261/**
262 * @brief Controller Area Network FilterRegister
263 */
264
265typedef struct
266{
267 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
268 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
269} CAN_FilterRegister_TypeDef;
270
271/**
272 * @brief Controller Area Network
273 */
274
275typedef struct
276{
277 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
278 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
279 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
280 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
281 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
282 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
283 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
284 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
285 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
286 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
287 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
288 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
289 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
290 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
291 uint32_t RESERVED2; /*!< Reserved, 0x208 */
292 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
293 uint32_t RESERVED3; /*!< Reserved, 0x210 */
294 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
295 uint32_t RESERVED4; /*!< Reserved, 0x218 */
296 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
297 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
298 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
299} CAN_TypeDef;
300
301/**
302 * @brief CRC calculation unit
303 */
304
305typedef struct
306{
307 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
308 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
309 uint8_t RESERVED0; /*!< Reserved, 0x05 */
310 uint16_t RESERVED1; /*!< Reserved, 0x06 */
311 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
312} CRC_TypeDef;
313
314/**
315 * @brief Digital to Analog Converter
316 */
317
318typedef struct
319{
320 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
321 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
322 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
323 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
324 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
325 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
326 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
327 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
328 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
329 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
330 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
331 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
332 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
333 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
334} DAC_TypeDef;
335
336/**
337 * @brief Debug MCU
338 */
339
340typedef struct
341{
342 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
343 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
344 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
345 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
346}DBGMCU_TypeDef;
347
348/**
349 * @brief DCMI
350 */
351
352typedef struct
353{
354 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
355 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
356 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
357 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
358 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
359 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
360 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
361 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
362 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
363 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
364 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
365} DCMI_TypeDef;
366
367/**
368 * @brief DMA Controller
369 */
370
371typedef struct
372{
373 __IO uint32_t CR; /*!< DMA stream x configuration register */
374 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
375 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
376 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
377 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
378 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
379} DMA_Stream_TypeDef;
380
381typedef struct
382{
383 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
384 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
385 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
386 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
387} DMA_TypeDef;
388
389/**
390 * @brief Ethernet MAC
391 */
392
393typedef struct
394{
395 __IO uint32_t MACCR;
396 __IO uint32_t MACFFR;
397 __IO uint32_t MACHTHR;
398 __IO uint32_t MACHTLR;
399 __IO uint32_t MACMIIAR;
400 __IO uint32_t MACMIIDR;
401 __IO uint32_t MACFCR;
402 __IO uint32_t MACVLANTR; /* 8 */
403 uint32_t RESERVED0[2];
404 __IO uint32_t MACRWUFFR; /* 11 */
405 __IO uint32_t MACPMTCSR;
406 uint32_t RESERVED1[2];
407 __IO uint32_t MACSR; /* 15 */
408 __IO uint32_t MACIMR;
409 __IO uint32_t MACA0HR;
410 __IO uint32_t MACA0LR;
411 __IO uint32_t MACA1HR;
412 __IO uint32_t MACA1LR;
413 __IO uint32_t MACA2HR;
414 __IO uint32_t MACA2LR;
415 __IO uint32_t MACA3HR;
416 __IO uint32_t MACA3LR; /* 24 */
417 uint32_t RESERVED2[40];
418 __IO uint32_t MMCCR; /* 65 */
419 __IO uint32_t MMCRIR;
420 __IO uint32_t MMCTIR;
421 __IO uint32_t MMCRIMR;
422 __IO uint32_t MMCTIMR; /* 69 */
423 uint32_t RESERVED3[14];
424 __IO uint32_t MMCTGFSCCR; /* 84 */
425 __IO uint32_t MMCTGFMSCCR;
426 uint32_t RESERVED4[5];
427 __IO uint32_t MMCTGFCR;
428 uint32_t RESERVED5[10];
429 __IO uint32_t MMCRFCECR;
430 __IO uint32_t MMCRFAECR;
431 uint32_t RESERVED6[10];
432 __IO uint32_t MMCRGUFCR;
433 uint32_t RESERVED7[334];
434 __IO uint32_t PTPTSCR;
435 __IO uint32_t PTPSSIR;
436 __IO uint32_t PTPTSHR;
437 __IO uint32_t PTPTSLR;
438 __IO uint32_t PTPTSHUR;
439 __IO uint32_t PTPTSLUR;
440 __IO uint32_t PTPTSAR;
441 __IO uint32_t PTPTTHR;
442 __IO uint32_t PTPTTLR;
443 __IO uint32_t RESERVED8;
444 __IO uint32_t PTPTSSR; /* added for STM32F2xx */
445 uint32_t RESERVED9[565];
446 __IO uint32_t DMABMR;
447 __IO uint32_t DMATPDR;
448 __IO uint32_t DMARPDR;
449 __IO uint32_t DMARDLAR;
450 __IO uint32_t DMATDLAR;
451 __IO uint32_t DMASR;
452 __IO uint32_t DMAOMR;
453 __IO uint32_t DMAIER;
454 __IO uint32_t DMAMFBOCR;
455 __IO uint32_t DMARSWTR; /* added for STM32F2xx */
456 uint32_t RESERVED10[8];
457 __IO uint32_t DMACHTDR;
458 __IO uint32_t DMACHRDR;
459 __IO uint32_t DMACHTBAR;
460 __IO uint32_t DMACHRBAR;
461} ETH_TypeDef;
462
463/**
464 * @brief External Interrupt/Event Controller
465 */
466
467typedef struct
468{
469 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
470 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
471 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
472 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
473 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
474 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
475} EXTI_TypeDef;
476
477/**
478 * @brief FLASH Registers
479 */
480
481typedef struct
482{
483 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
484 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
485 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
486 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
487 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
488 __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
489} FLASH_TypeDef;
490
491/**
492 * @brief Flexible Static Memory Controller
493 */
494
495typedef struct
496{
497 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
498} FSMC_Bank1_TypeDef;
499
500/**
501 * @brief Flexible Static Memory Controller Bank1E
502 */
503
504typedef struct
505{
506 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
507} FSMC_Bank1E_TypeDef;
508
509/**
510 * @brief Flexible Static Memory Controller Bank2
511 */
512
513typedef struct
514{
515 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
516 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
517 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
518 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
519 uint32_t RESERVED0; /*!< Reserved, 0x70 */
520 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
521} FSMC_Bank2_TypeDef;
522
523/**
524 * @brief Flexible Static Memory Controller Bank3
525 */
526
527typedef struct
528{
529 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
530 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
531 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
532 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
533 uint32_t RESERVED0; /*!< Reserved, 0x90 */
534 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
535} FSMC_Bank3_TypeDef;
536
537/**
538 * @brief Flexible Static Memory Controller Bank4
539 */
540
541typedef struct
542{
543 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
544 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
545 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
546 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
547 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
548} FSMC_Bank4_TypeDef;
549
550/**
551 * @brief General Purpose I/O
552 */
553
554typedef struct
555{
556 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
557 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
558 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
559 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
560 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
561 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
562 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
563 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
564 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
565 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */
566} GPIO_TypeDef;
567
568/**
569 * @brief System configuration controller
570 */
571
572typedef struct
573{
574 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
575 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
576 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
577 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
578 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
579} SYSCFG_TypeDef;
580
581/**
582 * @brief Inter-integrated Circuit Interface
583 */
584
585typedef struct
586{
587 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
588 uint16_t RESERVED0; /*!< Reserved, 0x02 */
589 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
590 uint16_t RESERVED1; /*!< Reserved, 0x06 */
591 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
592 uint16_t RESERVED2; /*!< Reserved, 0x0A */
593 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
594 uint16_t RESERVED3; /*!< Reserved, 0x0E */
595 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
596 uint16_t RESERVED4; /*!< Reserved, 0x12 */
597 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
598 uint16_t RESERVED5; /*!< Reserved, 0x16 */
599 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
600 uint16_t RESERVED6; /*!< Reserved, 0x1A */
601 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
602 uint16_t RESERVED7; /*!< Reserved, 0x1E */
603 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
604 uint16_t RESERVED8; /*!< Reserved, 0x22 */
605} I2C_TypeDef;
606
607/**
608 * @brief Independent WATCHDOG
609 */
610
611typedef struct
612{
613 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
614 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
615 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
616 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
617} IWDG_TypeDef;
618
619/**
620 * @brief Power Control
621 */
622
623typedef struct
624{
625 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
626 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
627} PWR_TypeDef;
628
629/**
630 * @brief Reset and Clock Control
631 */
632
633typedef struct
634{
635 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
636 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
637 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
638 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
639 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
640 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
641 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
642 uint32_t RESERVED0; /*!< Reserved, 0x1C */
643 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
644 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
645 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
646 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
647 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
648 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
649 uint32_t RESERVED2; /*!< Reserved, 0x3C */
650 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
651 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
652 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
653 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
654 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
655 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
656 uint32_t RESERVED4; /*!< Reserved, 0x5C */
657 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
658 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
659 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
660 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
661 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
662 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
663 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
664 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
665} RCC_TypeDef;
666
667/**
668 * @brief Real-Time Clock
669 */
670
671typedef struct
672{
673 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
674 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
675 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
676 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
677 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
678 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
679 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
680 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
681 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
682 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
683 uint32_t RESERVED1; /*!< Reserved, 0x28 */
684 uint32_t RESERVED2; /*!< Reserved, 0x2C */
685 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
686 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
687 uint32_t RESERVED3; /*!< Reserved, 0x38 */
688 uint32_t RESERVED4; /*!< Reserved, 0x3C */
689 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
690 uint32_t RESERVED5; /*!< Reserved, 0x44 */
691 uint32_t RESERVED6; /*!< Reserved, 0x48 */
692 uint32_t RESERVED7; /*!< Reserved, 0x4C */
693 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
694 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
695 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
696 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
697 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
698 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
699 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
700 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
701 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
702 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
703 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
704 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
705 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
706 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
707 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
708 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
709 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
710 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
711 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
712 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
713} RTC_TypeDef;
714
715/**
716 * @brief SD host Interface
717 */
718
719typedef struct
720{
721 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
722 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
723 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
724 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
725 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
726 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
727 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
728 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
729 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
730 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
731 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
732 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
733 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
734 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
735 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
736 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
737 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
738 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
739 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
740 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
741} SDIO_TypeDef;
742
743/**
744 * @brief Serial Peripheral Interface
745 */
746
747typedef struct
748{
749 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
750 uint16_t RESERVED0; /*!< Reserved, 0x02 */
751 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
752 uint16_t RESERVED1; /*!< Reserved, 0x06 */
753 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
754 uint16_t RESERVED2; /*!< Reserved, 0x0A */
755 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
756 uint16_t RESERVED3; /*!< Reserved, 0x0E */
757 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
758 uint16_t RESERVED4; /*!< Reserved, 0x12 */
759 __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
760 uint16_t RESERVED5; /*!< Reserved, 0x16 */
761 __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
762 uint16_t RESERVED6; /*!< Reserved, 0x1A */
763 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
764 uint16_t RESERVED7; /*!< Reserved, 0x1E */
765 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
766 uint16_t RESERVED8; /*!< Reserved, 0x22 */
767} SPI_TypeDef;
768
769typedef struct
770{
771 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
772 uint16_t RESERVED0; /*!< Reserved, 0x02 */
773 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
774 uint16_t RESERVED1; /*!< Reserved, 0x06 */
775 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
776 uint16_t RESERVED2; /*!< Reserved, 0x0A */
777 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
778 uint16_t RESERVED3; /*!< Reserved, 0x0E */
779 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
780 uint16_t RESERVED4; /*!< Reserved, 0x12 */
781 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
782 uint16_t RESERVED5; /*!< Reserved, 0x16 */
783 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
784 uint16_t RESERVED6; /*!< Reserved, 0x1A */
785 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
786 uint16_t RESERVED7; /*!< Reserved, 0x1E */
787 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
788 uint16_t RESERVED8; /*!< Reserved, 0x22 */
789 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
790 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
791 uint16_t RESERVED9; /*!< Reserved, 0x2A */
792 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
793 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
794 uint16_t RESERVED10; /*!< Reserved, 0x32 */
795 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
796 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
797 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
798 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
799 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
800 uint16_t RESERVED11; /*!< Reserved, 0x46 */
801 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
802 uint16_t RESERVED12; /*!< Reserved, 0x4A */
803 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
804 uint16_t RESERVED13; /*!< Reserved, 0x4E */
805 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
806 uint16_t RESERVED14; /*!< Reserved, 0x52 */
807} TIM_TypeDef;
808
809/**
810 * @brief Universal Synchronous Asynchronous Receiver Transmitter
811 */
812
813typedef struct
814{
815 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
816 uint16_t RESERVED0; /*!< Reserved, 0x02 */
817 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
818 uint16_t RESERVED1; /*!< Reserved, 0x06 */
819 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
820 uint16_t RESERVED2; /*!< Reserved, 0x0A */
821 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
822 uint16_t RESERVED3; /*!< Reserved, 0x0E */
823 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
824 uint16_t RESERVED4; /*!< Reserved, 0x12 */
825 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
826 uint16_t RESERVED5; /*!< Reserved, 0x16 */
827 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
828 uint16_t RESERVED6; /*!< Reserved, 0x1A */
829} USART_TypeDef;
830
831/**
832 * @brief Window WATCHDOG
833 */
834
835typedef struct
836{
837 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
838 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
839 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
840} WWDG_TypeDef;
841
842/**
843 * @brief Crypto Processor
844 */
845
846typedef struct
847{
848 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
849 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
850 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
851 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
852 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
853 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
854 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
855 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
856 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
857 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
858 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
859 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
860 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
861 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
862 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
863 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
864 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
865 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
866 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
867 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
868} CRYP_TypeDef;
869
870typedef struct
871{
872 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
873 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
874 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
875 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
876 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
877 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
878 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
879 __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */
880} HASH_TypeDef;
881
882typedef struct
883{
884 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
885 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
886 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
887} RNG_TypeDef;
888
889#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
890#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
891#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
892
893#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
894#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
895
896#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
897
898/*!< Peripheral memory map */
899#define APB1PERIPH_BASE PERIPH_BASE
900#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
901#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
902#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
903
904/*!< APB1 peripherals */
905#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
906#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
907#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
908#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
909#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
910#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
911#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
912#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
913#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
914#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
915#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
916#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
917#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
918#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
919#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
920#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
921#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
922#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
923#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
924#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
925#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
926#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
927#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
928#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
929#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
930
931/*!< APB2 peripherals */
932#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
933#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
934#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
935#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
936#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
937#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
938#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
939#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
940#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
941#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
942#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
943#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
944#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
945#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
946#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
947
948/*!< AHB1 peripherals */
949#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
950#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
951#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
952#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
953#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
954#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
955#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
956#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
957#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
958#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
959#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
960#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
961#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000)
962#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
963#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
964#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
965#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
966#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
967#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
968#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
969#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
970#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
971#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
972#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
973#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
974#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
975#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
976#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
977#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
978#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
979#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
980#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
981#define ETH_MAC_BASE (ETH_BASE)
982#define ETH_MMC_BASE (ETH_BASE + 0x0100)
983#define ETH_PTP_BASE (ETH_BASE + 0x0700)
984#define ETH_DMA_BASE (ETH_BASE + 0x1000)
985
986/*!< AHB2 peripherals */
987#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
988#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
989#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
990#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
991
992/*!< FSMC Bankx registers base address */
993#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
994#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
995#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
996#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
997#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
998
999/* Debug MCU registers base address */
1000#define DBGMCU_BASE ((uint32_t )0xE0042000)
1001
1002#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1003#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1004#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1005#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1006#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1007#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1008#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1009#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1010#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1011#define RTC ((RTC_TypeDef *) RTC_BASE)
1012#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1013#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1014#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1015#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1016#define USART2 ((USART_TypeDef *) USART2_BASE)
1017#define USART3 ((USART_TypeDef *) USART3_BASE)
1018#define UART4 ((USART_TypeDef *) UART4_BASE)
1019#define UART5 ((USART_TypeDef *) UART5_BASE)
1020#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1021#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1022#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1023#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1024#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1025#define PWR ((PWR_TypeDef *) PWR_BASE)
1026#define DAC ((DAC_TypeDef *) DAC_BASE)
1027#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1028#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1029#define USART1 ((USART_TypeDef *) USART1_BASE)
1030#define USART6 ((USART_TypeDef *) USART6_BASE)
1031#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1032#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1033#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1034#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1035#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1036#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1037#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1038#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1039#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1040#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1041#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1042#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1043#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1044#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1045#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1046#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1047#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1048#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1049#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1050#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1051#define CRC ((CRC_TypeDef *) CRC_BASE)
1052#define RCC ((RCC_TypeDef *) RCC_BASE)
1053#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1054#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1055#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1056#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1057#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1058#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1059#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1060#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1061#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1062#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1063#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1064#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1065#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1066#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1067#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1068#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1069#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1070#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1071#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1072#define ETH ((ETH_TypeDef *) ETH_BASE)
1073#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1074#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1075#define HASH ((HASH_TypeDef *) HASH_BASE)
1076#define RNG ((RNG_TypeDef *) RNG_BASE)
1077#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1078#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1079#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1080#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1081#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1082#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1083
1084/******************************************************************************/
1085/* Peripheral Registers_Bits_Definition */
1086/******************************************************************************/
1087
1088/******************************************************************************/
1089/* */
1090/* Analog to Digital Converter */
1091/* */
1092/******************************************************************************/
1093/******************** Bit definition for ADC_SR register ********************/
1094#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
1095#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
1096#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
1097#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
1098#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
1099#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
1100
1101/******************* Bit definition for ADC_CR1 register ********************/
1102#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1103#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1104#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1105#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1106#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1107#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1108#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1109#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1110#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1111#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1112#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1113#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1114#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1115#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1116#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1117#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1118#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1119#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1120#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1121#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1122#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1123#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1124#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1125#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1126
1127/******************* Bit definition for ADC_CR2 register ********************/
1128#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1129#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1130#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1131#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1132#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1133#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1134#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1135#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1136#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1137#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1138#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1139#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1140#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1141#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1142#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1143#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1144#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1145#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1146#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1147#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1148#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1149#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1150#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1151#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1152
1153/****************** Bit definition for ADC_SMPR1 register *******************/
1154#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1155#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1156#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1157#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1158#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1159#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1160#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1161#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1162#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1163#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1164#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1165#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1166#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1167#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1168#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1169#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1170#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1171#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1172#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1173#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1174#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1175#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1176#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1177#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1178#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1179#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1180#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1181#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1182#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1183#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1184#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1185#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1186#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1187#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1188#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1189#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1190
1191/****************** Bit definition for ADC_SMPR2 register *******************/
1192#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1193#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1194#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1195#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1196#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1197#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1198#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1199#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1200#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1201#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1202#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1203#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1204#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1205#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1206#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1207#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1208#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1209#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1210#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1211#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1212#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1213#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1214#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1215#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1216#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1217#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1218#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1219#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1220#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1221#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1222#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1223#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1224#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1225#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1226#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1227#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1228#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1229#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1230#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1231#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1232
1233/****************** Bit definition for ADC_JOFR1 register *******************/
1234#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
1235
1236/****************** Bit definition for ADC_JOFR2 register *******************/
1237#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
1238
1239/****************** Bit definition for ADC_JOFR3 register *******************/
1240#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
1241
1242/****************** Bit definition for ADC_JOFR4 register *******************/
1243#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
1244
1245/******************* Bit definition for ADC_HTR register ********************/
1246#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
1247
1248/******************* Bit definition for ADC_LTR register ********************/
1249#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
1250
1251/******************* Bit definition for ADC_SQR1 register *******************/
1252#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1253#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1254#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1255#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1256#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1257#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1258#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1259#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1260#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1261#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1262#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1263#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1264#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1265#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1266#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1267#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1268#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1269#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1270#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1271#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1272#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1273#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1274#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1275#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1276#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1277#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1278#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1279#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1280#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1281
1282/******************* Bit definition for ADC_SQR2 register *******************/
1283#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1284#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1285#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1286#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1287#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1288#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1289#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1290#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1291#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1292#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1293#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1294#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1295#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1296#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1297#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1298#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1299#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1300#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1301#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1302#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1303#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1304#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1305#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1306#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1307#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1308#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1309#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1310#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1311#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1312#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1313#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1314#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1315#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1316#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1317#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1318#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1319
1320/******************* Bit definition for ADC_SQR3 register *******************/
1321#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1322#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1323#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1324#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1325#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1326#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1327#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1328#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1329#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1330#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1331#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1332#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1333#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1334#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1335#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1336#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1337#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1338#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1339#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1340#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1341#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1342#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1343#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1344#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1345#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1346#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1347#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1348#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1349#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1350#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1351#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1352#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1353#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1354#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1355#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1356#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1357
1358/******************* Bit definition for ADC_JSQR register *******************/
1359#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1360#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1361#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1362#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1363#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1364#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1365#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1366#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1367#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1368#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1369#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1370#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1371#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1372#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1373#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1374#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1375#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1376#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1377#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1378#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1379#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1380#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1381#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1382#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1383#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1384#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1385#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1386
1387/******************* Bit definition for ADC_JDR1 register *******************/
1388#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1389
1390/******************* Bit definition for ADC_JDR2 register *******************/
1391#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1392
1393/******************* Bit definition for ADC_JDR3 register *******************/
1394#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1395
1396/******************* Bit definition for ADC_JDR4 register *******************/
1397#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1398
1399/******************** Bit definition for ADC_DR register ********************/
1400#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1401#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1402
1403/******************* Bit definition for ADC_CSR register ********************/
1404#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1405#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1406#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1407#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1408#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1409#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1410#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1411#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1412#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1413#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1414#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1415#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1416#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1417#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1418#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1419#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1420#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1421#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1422
1423/******************* Bit definition for ADC_CCR register ********************/
1424#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1425#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1426#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1427#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1428#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1429#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1430#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1431#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1432#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1433#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1434#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1435#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1436#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1437#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1438#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1439#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1440#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1441#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1442#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1443#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1444
1445/******************* Bit definition for ADC_CDR register ********************/
1446#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1447#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1448
1449/******************************************************************************/
1450/* */
1451/* Controller Area Network */
1452/* */
1453/******************************************************************************/
1454/*!<CAN control and status registers */
1455/******************* Bit definition for CAN_MCR register ********************/
1456#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
1457#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
1458#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
1459#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
1460#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
1461#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
1462#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
1463#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
1464#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
1465
1466/******************* Bit definition for CAN_MSR register ********************/
1467#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
1468#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
1469#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
1470#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
1471#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
1472#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
1473#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
1474#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
1475#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
1476
1477/******************* Bit definition for CAN_TSR register ********************/
1478#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1479#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1480#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1481#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1482#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1483#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1484#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1485#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1486#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1487#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1488#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1489#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1490#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1491#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1492#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1493#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1494
1495#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1496#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1497#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1498#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1499
1500#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1501#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1502#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1503#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1504
1505/******************* Bit definition for CAN_RF0R register *******************/
1506#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
1507#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
1508#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
1509#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
1510
1511/******************* Bit definition for CAN_RF1R register *******************/
1512#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
1513#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
1514#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
1515#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
1516
1517/******************** Bit definition for CAN_IER register *******************/
1518#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1519#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1520#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1521#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1522#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1523#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1524#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1525#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1526#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1527#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1528#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1529#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1530#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1531#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1532
1533/******************** Bit definition for CAN_ESR register *******************/
1534#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1535#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1536#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1537
1538#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1539#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1540#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1541#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1542
1543#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1544#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1545
1546/******************* Bit definition for CAN_BTR register ********************/
1547#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1548#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1549#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1550#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1551#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1552#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1553
1554/*!<Mailbox registers */
1555/****************** Bit definition for CAN_TI0R register ********************/
1556#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1557#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1558#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1559#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1560#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1561
1562/****************** Bit definition for CAN_TDT0R register *******************/
1563#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1564#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1565#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1566
1567/****************** Bit definition for CAN_TDL0R register *******************/
1568#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1569#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1570#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1571#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1572
1573/****************** Bit definition for CAN_TDH0R register *******************/
1574#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1575#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1576#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1577#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1578
1579/******************* Bit definition for CAN_TI1R register *******************/
1580#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1581#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1582#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1583#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1584#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1585
1586/******************* Bit definition for CAN_TDT1R register ******************/
1587#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1588#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1589#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1590
1591/******************* Bit definition for CAN_TDL1R register ******************/
1592#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1593#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1594#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1595#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1596
1597/******************* Bit definition for CAN_TDH1R register ******************/
1598#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1599#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1600#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1601#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1602
1603/******************* Bit definition for CAN_TI2R register *******************/
1604#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1605#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1606#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1607#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1608#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1609
1610/******************* Bit definition for CAN_TDT2R register ******************/
1611#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1612#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1613#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1614
1615/******************* Bit definition for CAN_TDL2R register ******************/
1616#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1617#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1618#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1619#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1620
1621/******************* Bit definition for CAN_TDH2R register ******************/
1622#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1623#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1624#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1625#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1626
1627/******************* Bit definition for CAN_RI0R register *******************/
1628#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1629#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1630#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1631#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1632
1633/******************* Bit definition for CAN_RDT0R register ******************/
1634#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1635#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1636#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1637
1638/******************* Bit definition for CAN_RDL0R register ******************/
1639#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1640#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1641#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1642#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1643
1644/******************* Bit definition for CAN_RDH0R register ******************/
1645#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1646#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1647#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1648#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1649
1650/******************* Bit definition for CAN_RI1R register *******************/
1651#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1652#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1653#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1654#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1655
1656/******************* Bit definition for CAN_RDT1R register ******************/
1657#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1658#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1659#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1660
1661/******************* Bit definition for CAN_RDL1R register ******************/
1662#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1663#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1664#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1665#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1666
1667/******************* Bit definition for CAN_RDH1R register ******************/
1668#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1669#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1670#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1671#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1672
1673/*!<CAN filter registers */
1674/******************* Bit definition for CAN_FMR register ********************/
1675#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
1676
1677/******************* Bit definition for CAN_FM1R register *******************/
1678#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
1679#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
1680#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
1681#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
1682#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
1683#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
1684#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
1685#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
1686#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
1687#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
1688#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
1689#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
1690#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
1691#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
1692#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
1693
1694/******************* Bit definition for CAN_FS1R register *******************/
1695#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
1696#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
1697#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
1698#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
1699#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
1700#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
1701#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
1702#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
1703#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
1704#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
1705#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
1706#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
1707#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
1708#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
1709#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
1710
1711/****************** Bit definition for CAN_FFA1R register *******************/
1712#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
1713#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
1714#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
1715#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
1716#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
1717#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
1718#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
1719#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
1720#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
1721#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
1722#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
1723#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
1724#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
1725#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
1726#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
1727
1728/******************* Bit definition for CAN_FA1R register *******************/
1729#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
1730#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
1731#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
1732#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
1733#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
1734#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
1735#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
1736#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
1737#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
1738#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
1739#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
1740#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
1741#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
1742#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
1743#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
1744
1745/******************* Bit definition for CAN_F0R1 register *******************/
1746#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1747#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1748#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1749#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1750#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1751#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1752#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1753#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1754#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1755#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1756#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1757#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1758#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1759#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1760#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1761#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1762#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1763#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1764#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1765#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1766#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1767#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1768#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1769#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1770#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1771#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1772#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1773#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1774#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1775#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1776#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1777#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1778
1779/******************* Bit definition for CAN_F1R1 register *******************/
1780#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1781#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1782#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1783#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1784#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1785#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1786#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1787#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1788#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1789#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1790#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1791#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1792#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1793#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1794#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1795#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1796#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1797#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1798#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1799#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1800#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1801#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1802#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1803#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1804#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1805#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1806#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1807#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1808#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1809#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1810#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1811#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1812
1813/******************* Bit definition for CAN_F2R1 register *******************/
1814#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1815#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1816#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1817#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1818#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1819#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1820#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1821#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1822#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1823#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1824#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1825#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1826#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1827#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1828#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1829#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1830#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1831#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1832#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1833#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1834#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1835#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1836#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1837#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1838#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1839#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1840#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1841#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1842#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1843#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1844#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1845#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1846
1847/******************* Bit definition for CAN_F3R1 register *******************/
1848#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1849#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1850#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1851#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1852#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1853#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1854#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1855#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1856#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1857#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1858#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1859#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1860#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1861#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1862#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1863#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1864#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1865#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1866#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1867#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1868#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1869#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1870#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1871#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1872#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1873#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1874#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1875#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1876#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1877#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1878#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1879#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1880
1881/******************* Bit definition for CAN_F4R1 register *******************/
1882#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1883#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1884#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1885#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1886#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1887#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1888#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1889#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1890#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1891#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1892#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1893#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1894#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1895#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1896#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1897#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1898#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1899#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1900#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1901#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1902#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1903#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1904#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1905#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1906#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1907#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1908#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1909#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1910#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1911#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1912#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1913#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1914
1915/******************* Bit definition for CAN_F5R1 register *******************/
1916#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1917#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1918#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1919#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1920#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1921#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1922#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1923#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1924#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1925#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1926#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1927#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1928#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1929#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1930#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1931#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1932#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1933#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1934#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1935#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1936#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1937#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1938#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1939#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1940#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1941#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1942#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1943#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1944#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1945#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1946#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1947#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1948
1949/******************* Bit definition for CAN_F6R1 register *******************/
1950#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1951#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1952#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1953#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1954#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1955#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1956#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1957#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1958#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1959#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1960#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1961#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1962#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1963#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1964#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1965#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1966#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1967#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1968#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1969#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1970#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1971#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1972#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1973#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1974#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1975#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1976#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1977#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1978#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1979#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1980#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1981#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1982
1983/******************* Bit definition for CAN_F7R1 register *******************/
1984#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1985#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1986#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1987#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1988#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1989#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1990#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1991#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1992#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1993#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1994#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1995#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1996#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1997#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1998#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1999#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2000#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2001#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2002#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2003#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2004#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2005#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2006#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2007#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2008#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2009#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2010#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2011#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2012#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2013#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2014#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2015#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2016
2017/******************* Bit definition for CAN_F8R1 register *******************/
2018#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2019#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2020#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2021#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2022#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2023#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2024#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2025#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2026#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2027#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2028#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2029#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2030#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2031#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2032#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2033#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2034#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2035#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2036#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2037#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2038#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2039#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2040#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2041#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2042#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2043#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2044#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2045#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2046#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2047#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2048#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2049#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2050
2051/******************* Bit definition for CAN_F9R1 register *******************/
2052#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2053#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2054#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2055#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2056#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2057#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2058#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2059#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2060#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2061#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2062#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2063#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2064#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2065#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2066#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2067#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2068#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2069#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2070#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2071#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2072#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2073#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2074#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2075#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2076#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2077#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2078#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2079#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2080#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2081#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2082#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2083#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2084
2085/******************* Bit definition for CAN_F10R1 register ******************/
2086#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2087#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2088#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2089#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2090#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2091#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2092#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2093#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2094#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2095#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2096#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2097#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2098#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2099#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2100#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2101#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2102#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2103#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2104#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2105#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2106#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2107#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2108#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2109#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2110#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2111#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2112#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2113#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2114#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2115#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2116#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2117#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2118
2119/******************* Bit definition for CAN_F11R1 register ******************/
2120#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2121#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2122#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2123#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2124#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2125#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2126#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2127#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2128#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2129#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2130#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2131#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2132#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2133#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2134#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2135#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2136#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2137#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2138#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2139#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2140#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2141#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2142#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2143#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2144#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2145#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2146#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2147#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2148#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2149#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2150#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2151#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2152
2153/******************* Bit definition for CAN_F12R1 register ******************/
2154#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2155#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2156#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2157#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2158#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2159#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2160#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2161#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2162#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2163#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2164#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2165#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2166#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2167#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2168#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2169#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2170#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2171#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2172#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2173#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2174#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2175#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2176#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2177#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2178#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2179#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2180#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2181#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2182#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2183#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2184#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2185#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2186
2187/******************* Bit definition for CAN_F13R1 register ******************/
2188#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2189#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2190#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2191#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2192#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2193#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2194#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2195#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2196#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2197#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2198#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2199#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2200#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2201#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2202#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2203#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2204#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2205#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2206#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2207#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2208#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2209#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2210#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2211#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2212#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2213#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2214#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2215#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2216#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2217#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2218#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2219#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2220
2221/******************* Bit definition for CAN_F0R2 register *******************/
2222#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2223#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2224#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2225#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2226#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2227#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2228#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2229#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2230#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2231#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2232#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2233#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2234#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2235#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2236#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2237#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2238#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2239#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2240#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2241#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2242#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2243#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2244#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2245#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2246#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2247#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2248#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2249#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2250#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2251#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2252#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2253#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2254
2255/******************* Bit definition for CAN_F1R2 register *******************/
2256#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2257#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2258#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2259#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2260#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2261#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2262#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2263#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2264#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2265#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2266#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2267#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2268#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2269#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2270#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2271#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2272#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2273#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2274#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2275#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2276#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2277#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2278#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2279#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2280#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2281#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2282#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2283#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2284#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2285#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2286#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2287#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2288
2289/******************* Bit definition for CAN_F2R2 register *******************/
2290#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2291#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2292#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2293#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2294#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2295#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2296#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2297#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2298#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2299#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2300#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2301#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2302#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2303#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2304#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2305#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2306#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2307#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2308#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2309#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2310#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2311#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2312#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2313#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2314#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2315#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2316#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2317#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2318#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2319#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2320#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2321#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2322
2323/******************* Bit definition for CAN_F3R2 register *******************/
2324#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2325#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2326#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2327#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2328#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2329#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2330#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2331#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2332#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2333#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2334#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2335#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2336#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2337#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2338#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2339#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2340#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2341#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2342#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2343#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2344#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2345#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2346#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2347#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2348#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2349#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2350#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2351#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2352#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2353#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2354#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2355#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2356
2357/******************* Bit definition for CAN_F4R2 register *******************/
2358#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2359#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2360#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2361#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2362#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2363#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2364#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2365#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2366#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2367#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2368#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2369#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2370#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2371#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2372#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2373#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2374#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2375#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2376#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2377#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2378#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2379#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2380#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2381#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2382#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2383#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2384#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2385#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2386#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2387#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2388#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2389#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2390
2391/******************* Bit definition for CAN_F5R2 register *******************/
2392#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2393#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2394#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2395#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2396#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2397#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2398#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2399#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2400#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2401#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2402#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2403#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2404#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2405#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2406#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2407#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2408#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2409#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2410#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2411#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2412#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2413#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2414#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2415#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2416#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2417#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2418#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2419#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2420#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2421#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2422#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2423#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2424
2425/******************* Bit definition for CAN_F6R2 register *******************/
2426#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2427#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2428#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2429#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2430#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2431#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2432#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2433#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2434#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2435#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2436#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2437#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2438#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2439#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2440#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2441#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2442#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2443#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2444#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2445#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2446#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2447#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2448#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2449#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2450#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2451#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2452#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2453#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2454#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2455#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2456#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2457#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2458
2459/******************* Bit definition for CAN_F7R2 register *******************/
2460#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2461#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2462#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2463#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2464#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2465#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2466#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2467#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2468#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2469#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2470#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2471#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2472#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2473#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2474#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2475#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2476#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2477#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2478#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2479#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2480#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2481#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2482#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2483#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2484#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2485#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2486#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2487#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2488#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2489#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2490#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2491#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2492
2493/******************* Bit definition for CAN_F8R2 register *******************/
2494#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2495#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2496#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2497#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2498#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2499#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2500#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2501#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2502#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2503#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2504#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2505#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2506#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2507#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2508#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2509#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2510#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2511#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2512#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2513#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2514#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2515#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2516#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2517#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2518#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2519#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2520#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2521#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2522#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2523#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2524#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2525#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2526
2527/******************* Bit definition for CAN_F9R2 register *******************/
2528#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2529#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2530#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2531#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2532#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2533#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2534#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2535#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2536#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2537#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2538#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2539#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2540#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2541#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2542#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2543#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2544#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2545#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2546#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2547#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2548#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2549#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2550#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2551#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2552#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2553#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2554#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2555#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2556#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2557#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2558#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2559#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2560
2561/******************* Bit definition for CAN_F10R2 register ******************/
2562#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2563#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2564#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2565#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2566#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2567#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2568#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2569#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2570#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2571#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2572#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2573#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2574#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2575#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2576#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2577#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2578#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2579#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2580#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2581#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2582#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2583#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2584#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2585#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2586#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2587#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2588#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2589#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2590#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2591#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2592#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2593#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2594
2595/******************* Bit definition for CAN_F11R2 register ******************/
2596#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2597#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2598#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2599#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2600#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2601#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2602#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2603#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2604#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2605#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2606#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2607#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2608#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2609#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2610#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2611#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2612#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2613#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2614#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2615#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2616#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2617#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2618#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2619#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2620#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2621#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2622#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2623#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2624#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2625#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2626#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2627#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2628
2629/******************* Bit definition for CAN_F12R2 register ******************/
2630#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2631#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2632#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2633#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2634#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2635#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2636#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2637#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2638#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2639#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2640#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2641#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2642#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2643#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2644#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2645#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2646#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2647#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2648#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2649#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2650#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2651#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2652#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2653#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2654#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2655#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2656#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2657#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2658#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2659#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2660#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2661#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2662
2663/******************* Bit definition for CAN_F13R2 register ******************/
2664#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2665#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2666#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2667#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2668#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2669#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2670#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2671#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2672#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2673#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2674#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2675#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2676#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2677#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2678#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2679#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2680#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2681#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2682#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2683#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2684#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2685#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2686#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2687#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2688#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2689#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2690#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2691#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2692#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2693#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2694#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2695#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2696
2697/******************************************************************************/
2698/* */
2699/* CRC calculation unit */
2700/* */
2701/******************************************************************************/
2702/******************* Bit definition for CRC_DR register *********************/
2703#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
2704
2705
2706/******************* Bit definition for CRC_IDR register ********************/
2707#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
2708
2709
2710/******************** Bit definition for CRC_CR register ********************/
2711#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
2712
2713/******************************************************************************/
2714/* */
2715/* Crypto Processor */
2716/* */
2717/******************************************************************************/
2718/******************* Bits definition for CRYP_CR register ********************/
2719#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
2720
2721#define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)
2722#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
2723#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
2724#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
2725#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
2726#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
2727#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
2728#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
2729#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
2730#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
2731#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
2732#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
2733
2734#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
2735#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
2736#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
2737#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
2738#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
2739#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
2740#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
2741#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
2742/****************** Bits definition for CRYP_SR register *********************/
2743#define CRYP_SR_IFEM ((uint32_t)0x00000001)
2744#define CRYP_SR_IFNF ((uint32_t)0x00000002)
2745#define CRYP_SR_OFNE ((uint32_t)0x00000004)
2746#define CRYP_SR_OFFU ((uint32_t)0x00000008)
2747#define CRYP_SR_BUSY ((uint32_t)0x00000010)
2748/****************** Bits definition for CRYP_DMACR register ******************/
2749#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
2750#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
2751/***************** Bits definition for CRYP_IMSCR register ******************/
2752#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
2753#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
2754/****************** Bits definition for CRYP_RISR register *******************/
2755#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
2756#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
2757/****************** Bits definition for CRYP_MISR register *******************/
2758#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
2759#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
2760
2761/******************************************************************************/
2762/* */
2763/* Digital to Analog Converter */
2764/* */
2765/******************************************************************************/
2766/******************** Bit definition for DAC_CR register ********************/
2767#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
2768#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
2769#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
2770
2771#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
2772#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
2773#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
2774#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
2775
2776#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2777#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
2778#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
2779
2780#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2781#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2782#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2783#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
2784#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
2785
2786#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
2787#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
2788#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
2789#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
2790
2791#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
2792#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
2793#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
2794#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
2795
2796#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2797#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
2798#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
2799
2800#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2801#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
2802#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
2803#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
2804#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
2805
2806#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
2807
2808/***************** Bit definition for DAC_SWTRIGR register ******************/
2809#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
2810#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
2811
2812/***************** Bit definition for DAC_DHR12R1 register ******************/
2813#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
2814
2815/***************** Bit definition for DAC_DHR12L1 register ******************/
2816#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
2817
2818/****************** Bit definition for DAC_DHR8R1 register ******************/
2819#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
2820
2821/***************** Bit definition for DAC_DHR12R2 register ******************/
2822#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
2823
2824/***************** Bit definition for DAC_DHR12L2 register ******************/
2825#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
2826
2827/****************** Bit definition for DAC_DHR8R2 register ******************/
2828#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
2829
2830/***************** Bit definition for DAC_DHR12RD register ******************/
2831#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
2832#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
2833
2834/***************** Bit definition for DAC_DHR12LD register ******************/
2835#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
2836#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
2837
2838/****************** Bit definition for DAC_DHR8RD register ******************/
2839#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
2840#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
2841
2842/******************* Bit definition for DAC_DOR1 register *******************/
2843#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
2844
2845/******************* Bit definition for DAC_DOR2 register *******************/
2846#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
2847
2848/******************** Bit definition for DAC_SR register ********************/
2849#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
2850#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
2851
2852/******************************************************************************/
2853/* */
2854/* Debug MCU */
2855/* */
2856/******************************************************************************/
2857
2858/******************************************************************************/
2859/* */
2860/* DCMI */
2861/* */
2862/******************************************************************************/
2863/******************** Bits definition for DCMI_CR register ******************/
2864#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
2865#define DCMI_CR_CM ((uint32_t)0x00000002)
2866#define DCMI_CR_CROP ((uint32_t)0x00000004)
2867#define DCMI_CR_JPEG ((uint32_t)0x00000008)
2868#define DCMI_CR_ESS ((uint32_t)0x00000010)
2869#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
2870#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
2871#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
2872#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
2873#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
2874#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
2875#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
2876#define DCMI_CR_CRE ((uint32_t)0x00001000)
2877#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
2878
2879/******************** Bits definition for DCMI_SR register ******************/
2880#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
2881#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
2882#define DCMI_SR_FNE ((uint32_t)0x00000004)
2883
2884/******************** Bits definition for DCMI_RISR register ****************/
2885#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
2886#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
2887#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
2888#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
2889#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
2890
2891/******************** Bits definition for DCMI_IER register *****************/
2892#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
2893#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
2894#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
2895#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
2896#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
2897
2898/******************** Bits definition for DCMI_MISR register ****************/
2899#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
2900#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
2901#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
2902#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
2903#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
2904
2905/******************** Bits definition for DCMI_ICR register *****************/
2906#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
2907#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
2908#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
2909#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
2910#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
2911
2912/******************************************************************************/
2913/* */
2914/* DMA Controller */
2915/* */
2916/******************************************************************************/
2917/******************** Bits definition for DMA_SxCR register *****************/
2918#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
2919#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
2920#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
2921#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
2922#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
2923#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
2924#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
2925#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
2926#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
2927#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
2928#define DMA_SxCR_ACK ((uint32_t)0x00100000)
2929#define DMA_SxCR_CT ((uint32_t)0x00080000)
2930#define DMA_SxCR_DBM ((uint32_t)0x00040000)
2931#define DMA_SxCR_PL ((uint32_t)0x00030000)
2932#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
2933#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
2934#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
2935#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
2936#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
2937#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
2938#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
2939#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
2940#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
2941#define DMA_SxCR_MINC ((uint32_t)0x00000400)
2942#define DMA_SxCR_PINC ((uint32_t)0x00000200)
2943#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
2944#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
2945#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
2946#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
2947#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
2948#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
2949#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
2950#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
2951#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
2952#define DMA_SxCR_EN ((uint32_t)0x00000001)
2953
2954/******************** Bits definition for DMA_SxCNDTR register **************/
2955#define DMA_SxNDT ((uint32_t)0x0000FFFF)
2956#define DMA_SxNDT_0 ((uint32_t)0x00000001)
2957#define DMA_SxNDT_1 ((uint32_t)0x00000002)
2958#define DMA_SxNDT_2 ((uint32_t)0x00000004)
2959#define DMA_SxNDT_3 ((uint32_t)0x00000008)
2960#define DMA_SxNDT_4 ((uint32_t)0x00000010)
2961#define DMA_SxNDT_5 ((uint32_t)0x00000020)
2962#define DMA_SxNDT_6 ((uint32_t)0x00000040)
2963#define DMA_SxNDT_7 ((uint32_t)0x00000080)
2964#define DMA_SxNDT_8 ((uint32_t)0x00000100)
2965#define DMA_SxNDT_9 ((uint32_t)0x00000200)
2966#define DMA_SxNDT_10 ((uint32_t)0x00000400)
2967#define DMA_SxNDT_11 ((uint32_t)0x00000800)
2968#define DMA_SxNDT_12 ((uint32_t)0x00001000)
2969#define DMA_SxNDT_13 ((uint32_t)0x00002000)
2970#define DMA_SxNDT_14 ((uint32_t)0x00004000)
2971#define DMA_SxNDT_15 ((uint32_t)0x00008000)
2972
2973/******************** Bits definition for DMA_SxFCR register ****************/
2974#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
2975#define DMA_SxFCR_FS ((uint32_t)0x00000038)
2976#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
2977#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
2978#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
2979#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
2980#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
2981#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
2982#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
2983
2984/******************** Bits definition for DMA_LISR register *****************/
2985#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
2986#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
2987#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
2988#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
2989#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
2990#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
2991#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
2992#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
2993#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
2994#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
2995#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
2996#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
2997#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
2998#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
2999#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3000#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3001#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3002#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3003#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3004#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3005
3006/******************** Bits definition for DMA_HISR register *****************/
3007#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3008#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3009#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3010#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3011#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3012#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3013#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3014#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3015#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3016#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3017#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3018#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3019#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3020#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3021#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3022#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3023#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3024#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3025#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3026#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3027
3028/******************** Bits definition for DMA_LIFCR register ****************/
3029#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3030#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3031#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3032#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3033#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3034#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3035#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3036#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3037#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3038#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3039#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3040#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3041#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3042#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3043#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3044#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3045#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3046#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3047#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3048#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3049
3050/******************** Bits definition for DMA_HIFCR register ****************/
3051#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3052#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3053#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3054#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3055#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3056#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3057#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3058#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3059#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3060#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3061#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3062#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3063#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3064#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3065#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3066#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3067#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3068#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3069#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3070#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3071
3072/******************************************************************************/
3073/* */
3074/* External Interrupt/Event Controller */
3075/* */
3076/******************************************************************************/
3077/******************* Bit definition for EXTI_IMR register *******************/
3078#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3079#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3080#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3081#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3082#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3083#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3084#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3085#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3086#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3087#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3088#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3089#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3090#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3091#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3092#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3093#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3094#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3095#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3096#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3097#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3098
3099/******************* Bit definition for EXTI_EMR register *******************/
3100#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3101#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3102#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3103#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3104#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3105#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3106#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3107#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3108#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3109#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3110#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3111#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3112#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3113#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3114#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3115#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3116#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3117#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3118#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3119#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3120
3121/****************** Bit definition for EXTI_RTSR register *******************/
3122#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3123#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3124#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3125#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3126#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3127#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3128#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3129#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3130#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3131#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3132#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3133#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3134#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3135#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3136#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3137#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3138#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3139#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3140#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3141#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3142
3143/****************** Bit definition for EXTI_FTSR register *******************/
3144#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3145#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3146#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3147#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3148#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3149#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3150#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3151#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3152#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3153#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3154#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3155#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3156#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3157#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3158#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3159#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3160#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3161#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3162#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3163#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3164
3165/****************** Bit definition for EXTI_SWIER register ******************/
3166#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3167#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3168#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3169#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3170#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3171#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3172#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3173#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3174#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3175#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3176#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3177#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3178#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3179#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3180#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3181#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3182#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3183#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3184#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3185#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3186
3187/******************* Bit definition for EXTI_PR register ********************/
3188#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3189#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3190#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3191#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3192#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3193#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3194#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3195#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3196#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3197#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3198#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3199#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3200#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3201#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3202#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3203#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3204#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3205#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3206#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3207#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3208
3209/******************************************************************************/
3210/* */
3211/* FLASH */
3212/* */
3213/******************************************************************************/
3214/******************* Bits definition for FLASH_ACR register *****************/
3215#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
3216#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3217#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3218#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3219#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3220#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3221#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3222#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3223#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3224
3225#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3226#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
3227#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
3228#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
3229#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
3230#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
3231#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
3232
3233/******************* Bits definition for FLASH_SR register ******************/
3234#define FLASH_SR_EOP ((uint32_t)0x00000001)
3235#define FLASH_SR_SOP ((uint32_t)0x00000002)
3236#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3237#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3238#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3239#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
3240#define FLASH_SR_BSY ((uint32_t)0x00010000)
3241
3242/******************* Bits definition for FLASH_CR register ******************/
3243#define FLASH_CR_PG ((uint32_t)0x00000001)
3244#define FLASH_CR_SER ((uint32_t)0x00000002)
3245#define FLASH_CR_MER ((uint32_t)0x00000004)
3246#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3247#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3248#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3249#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3250#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3251#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3252#define FLASH_CR_STRT ((uint32_t)0x00010000)
3253#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3254#define FLASH_CR_LOCK ((uint32_t)0x80000000)
3255
3256/******************* Bits definition for FLASH_OPTCR register ***************/
3257#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3258#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3259#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3260#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3261#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3262#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
3263#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3264#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3265#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3266#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3267#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3268#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3269#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3270#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3271#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3272#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3273#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3274#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3275#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3276#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3277#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3278#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3279#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3280#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3281#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
3282#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
3283#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
3284#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
3285
3286/******************************************************************************/
3287/* */
3288/* Flexible Static Memory Controller */
3289/* */
3290/******************************************************************************/
3291/****************** Bit definition for FSMC_BCR1 register *******************/
3292#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3293#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3294
3295#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3296#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3297#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3298
3299#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3300#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3301#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3302
3303#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3304#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3305#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3306#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3307#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3308#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3309#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3310#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3311#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3312#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3313
3314/****************** Bit definition for FSMC_BCR2 register *******************/
3315#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3316#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3317
3318#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3319#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3320#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3321
3322#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3323#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3324#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3325
3326#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3327#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3328#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3329#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3330#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3331#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3332#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3333#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3334#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3335#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3336
3337/****************** Bit definition for FSMC_BCR3 register *******************/
3338#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3339#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3340
3341#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3342#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3343#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3344
3345#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3346#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3347#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3348
3349#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3350#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3351#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
3352#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3353#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3354#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3355#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3356#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3357#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3358#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3359
3360/****************** Bit definition for FSMC_BCR4 register *******************/
3361#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3362#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3363
3364#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3365#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3366#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3367
3368#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3369#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3370#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3371
3372#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3373#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3374#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3375#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3376#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3377#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3378#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3379#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3380#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3381#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3382
3383/****************** Bit definition for FSMC_BTR1 register ******************/
3384#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3385#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3386#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3387#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3388#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3389
3390#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3391#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3392#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3393#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3394#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3395
3396#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3397#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3398#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3399#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3400#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3401
3402#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3403#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3404#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3405#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3406#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3407
3408#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3409#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3410#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3411#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3412#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3413
3414#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3415#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3416#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3417#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3418#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3419
3420#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3421#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3422#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3423
3424/****************** Bit definition for FSMC_BTR2 register *******************/
3425#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3426#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3427#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3428#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3429#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3430
3431#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3432#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3433#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3434#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3435#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3436
3437#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3438#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3439#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3440#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3441#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3442
3443#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3444#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3445#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3446#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3447#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3448
3449#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3450#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3451#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3452#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3453#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3454
3455#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3456#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3457#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3458#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3459#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3460
3461#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3462#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3463#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3464
3465/******************* Bit definition for FSMC_BTR3 register *******************/
3466#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3467#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3468#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3469#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3470#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3471
3472#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3473#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3474#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3475#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3476#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3477
3478#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3479#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3480#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3481#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3482#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3483
3484#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3485#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3486#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3487#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3488#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3489
3490#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3491#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3492#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3493#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3494#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3495
3496#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3497#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3498#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3499#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3500#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3501
3502#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3503#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3504#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3505
3506/****************** Bit definition for FSMC_BTR4 register *******************/
3507#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3508#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3509#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3510#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3511#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3512
3513#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3514#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3515#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3516#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3517#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3518
3519#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3520#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3521#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3522#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3523#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3524
3525#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3526#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3527#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3528#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3529#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3530
3531#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3532#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3533#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3534#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3535#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3536
3537#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3538#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3539#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3540#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3541#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3542
3543#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3544#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3545#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3546
3547/****************** Bit definition for FSMC_BWTR1 register ******************/
3548#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3549#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3550#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3551#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3552#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3553
3554#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3555#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3556#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3557#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3558#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3559
3560#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3561#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3562#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3563#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3564#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3565
3566#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3567#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3568#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3569#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3570#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3571
3572#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3573#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3574#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3575#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3576#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3577
3578#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3579#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3580#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3581
3582/****************** Bit definition for FSMC_BWTR2 register ******************/
3583#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3584#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3585#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3586#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3587#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3588
3589#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3590#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3591#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3592#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3593#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3594
3595#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3596#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3597#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3598#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3599#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3600
3601#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3602#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3603#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
3604#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3605#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3606
3607#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3608#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3609#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3610#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3611#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3612
3613#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3614#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3615#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3616
3617/****************** Bit definition for FSMC_BWTR3 register ******************/
3618#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3619#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3620#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3621#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3622#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3623
3624#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3625#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3626#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3627#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3628#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3629
3630#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3631#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3632#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3633#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3634#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3635
3636#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3637#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3638#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3639#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3640#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3641
3642#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3643#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3644#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3645#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3646#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3647
3648#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3649#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3650#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3651
3652/****************** Bit definition for FSMC_BWTR4 register ******************/
3653#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3654#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3655#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3656#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3657#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3658
3659#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3660#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3661#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3662#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3663#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3664
3665#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3666#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3667#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3668#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3669#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3670
3671#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3672#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3673#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3674#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3675#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3676
3677#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3678#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3679#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3680#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3681#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3682
3683#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3684#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3685#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3686
3687/****************** Bit definition for FSMC_PCR2 register *******************/
3688#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3689#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3690#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3691
3692#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3693#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3694#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3695
3696#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3697
3698#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3699#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3700#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3701#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3702#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3703
3704#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3705#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3706#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3707#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3708#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3709
3710#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
3711#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3712#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3713#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3714
3715/****************** Bit definition for FSMC_PCR3 register *******************/
3716#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3717#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3718#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3719
3720#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3721#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3722#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3723
3724#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3725
3726#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3727#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3728#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3729#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3730#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3731
3732#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3733#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3734#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3735#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3736#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3737
3738#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
3739#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3740#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3741#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3742
3743/****************** Bit definition for FSMC_PCR4 register *******************/
3744#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3745#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3746#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3747
3748#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3749#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3750#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3751
3752#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3753
3754#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3755#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3756#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3757#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3758#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3759
3760#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3761#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3762#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3763#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3764#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3765
3766#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
3767#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3768#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3769#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3770
3771/******************* Bit definition for FSMC_SR2 register *******************/
3772#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3773#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3774#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3775#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3776#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3777#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3778#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3779
3780/******************* Bit definition for FSMC_SR3 register *******************/
3781#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3782#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3783#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3784#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3785#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3786#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3787#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3788
3789/******************* Bit definition for FSMC_SR4 register *******************/
3790#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3791#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3792#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3793#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3794#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3795#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3796#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3797
3798/****************** Bit definition for FSMC_PMEM2 register ******************/
3799#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
3800#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3801#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3802#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3803#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3804#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3805#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3806#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3807#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3808
3809#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
3810#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3811#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3812#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3813#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3814#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3815#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3816#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3817#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3818
3819#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
3820#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3821#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3822#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3823#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3824#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
3825#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
3826#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
3827#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
3828
3829#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
3830#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3831#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3832#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3833#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3834#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
3835#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
3836#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
3837#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
3838
3839/****************** Bit definition for FSMC_PMEM3 register ******************/
3840#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
3841#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3842#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3843#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3844#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3845#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3846#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3847#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3848#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3849
3850#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
3851#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3852#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3853#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3854#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3855#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3856#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3857#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3858#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3859
3860#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
3861#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3862#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3863#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3864#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3865#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
3866#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
3867#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
3868#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
3869
3870#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
3871#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3872#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3873#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3874#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3875#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
3876#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
3877#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
3878#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
3879
3880/****************** Bit definition for FSMC_PMEM4 register ******************/
3881#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
3882#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3883#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3884#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3885#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3886#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3887#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3888#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3889#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3890
3891#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
3892#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3893#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3894#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3895#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3896#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3897#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3898#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3899#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3900
3901#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
3902#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3903#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3904#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3905#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3906#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
3907#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
3908#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
3909#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
3910
3911#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
3912#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3913#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3914#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3915#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3916#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
3917#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
3918#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
3919#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
3920
3921/****************** Bit definition for FSMC_PATT2 register ******************/
3922#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
3923#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3924#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3925#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3926#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3927#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3928#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3929#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3930#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3931
3932#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
3933#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3934#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3935#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3936#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3937#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3938#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3939#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3940#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3941
3942#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
3943#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3944#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3945#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3946#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3947#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
3948#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
3949#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
3950#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
3951
3952#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
3953#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3954#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3955#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3956#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3957#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
3958#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
3959#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
3960#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
3961
3962/****************** Bit definition for FSMC_PATT3 register ******************/
3963#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
3964#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3965#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3966#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3967#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3968#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3969#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3970#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3971#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3972
3973#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
3974#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3975#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3976#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3977#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3978#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3979#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3980#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3981#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3982
3983#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
3984#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3985#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3986#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3987#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3988#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
3989#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
3990#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
3991#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
3992
3993#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
3994#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3995#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3996#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3997#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3998#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
3999#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4000#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4001#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4002
4003/****************** Bit definition for FSMC_PATT4 register ******************/
4004#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4005#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4006#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4007#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4008#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4009#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4010#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4011#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4012#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4013
4014#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4015#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4016#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4017#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4018#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4019#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4020#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4021#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4022#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4023
4024#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4025#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4026#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4027#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4028#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4029#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4030#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4031#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4032#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4033
4034#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4035#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4036#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4037#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4038#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4039#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4040#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4041#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4042#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4043
4044/****************** Bit definition for FSMC_PIO4 register *******************/
4045#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4046#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4047#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4048#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4049#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4050#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4051#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4052#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4053#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4054
4055#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4056#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4057#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4058#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4059#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4060#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4061#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4062#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4063#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4064
4065#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4066#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4067#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4068#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4069#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4070#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4071#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4072#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4073#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4074
4075#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4076#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4077#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4078#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4079#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4080#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4081#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4082#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4083#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4084
4085/****************** Bit definition for FSMC_ECCR2 register ******************/
4086#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4087
4088/****************** Bit definition for FSMC_ECCR3 register ******************/
4089#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4090
4091/******************************************************************************/
4092/* */
4093/* General Purpose I/O */
4094/* */
4095/******************************************************************************/
4096/****************** Bits definition for GPIO_MODER register *****************/
4097#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4098#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4099#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4100
4101#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4102#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4103#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4104
4105#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4106#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4107#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4108
4109#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4110#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4111#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4112
4113#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4114#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4115#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4116
4117#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4118#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4119#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4120
4121#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4122#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4123#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4124
4125#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4126#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4127#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4128
4129#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4130#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4131#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4132
4133#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4134#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4135#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4136
4137#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4138#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4139#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4140
4141#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4142#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4143#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4144
4145#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4146#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4147#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4148
4149#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4150#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4151#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4152
4153#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4154#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4155#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4156
4157#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4158#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4159#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4160
4161/****************** Bits definition for GPIO_OTYPER register ****************/
4162#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4163#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4164#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4165#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4166#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4167#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4168#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4169#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4170#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4171#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4172#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4173#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4174#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4175#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4176#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4177#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4178
4179/****************** Bits definition for GPIO_OSPEEDR register ***************/
4180#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4181#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4182#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4183
4184#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4185#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4186#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4187
4188#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4189#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4190#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4191
4192#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4193#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4194#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4195
4196#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4197#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4198#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4199
4200#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4201#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4202#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4203
4204#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4205#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4206#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4207
4208#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4209#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4210#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4211
4212#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4213#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4214#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4215
4216#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4217#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4218#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4219
4220#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4221#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4222#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4223
4224#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4225#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4226#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4227
4228#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4229#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4230#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4231
4232#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4233#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4234#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4235
4236#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4237#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4238#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4239
4240#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4241#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4242#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4243
4244/****************** Bits definition for GPIO_PUPDR register *****************/
4245#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4246#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4247#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4248
4249#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4250#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4251#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4252
4253#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4254#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4255#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4256
4257#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4258#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4259#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4260
4261#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4262#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4263#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4264
4265#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4266#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4267#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4268
4269#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4270#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4271#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4272
4273#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4274#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4275#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4276
4277#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4278#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4279#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4280
4281#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4282#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4283#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4284
4285#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4286#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4287#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4288
4289#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4290#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4291#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4292
4293#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4294#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4295#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4296
4297#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4298#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4299#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4300
4301#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4302#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4303#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4304
4305#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4306#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4307#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4308
4309/****************** Bits definition for GPIO_IDR register *******************/
4310#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)
4311#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)
4312#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)
4313#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)
4314#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)
4315#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)
4316#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)
4317#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)
4318#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)
4319#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)
4320#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)
4321#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)
4322#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)
4323#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)
4324#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)
4325#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)
4326
4327/****************** Bits definition for GPIO_ODR register *******************/
4328#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)
4329#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)
4330#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)
4331#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)
4332#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)
4333#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)
4334#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)
4335#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)
4336#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)
4337#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)
4338#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)
4339#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)
4340#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)
4341#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)
4342#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)
4343#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)
4344
4345/****************** Bits definition for GPIO_BSRR register ******************/
4346#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4347#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4348#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4349#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4350#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4351#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4352#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4353#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4354#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4355#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4356#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4357#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4358#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4359#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4360#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4361#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4362#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4363#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4364#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4365#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4366#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4367#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4368#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4369#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4370#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4371#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4372#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4373#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4374#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4375#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4376#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4377#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4378
4379/******************************************************************************/
4380/* */
4381/* HASH */
4382/* */
4383/******************************************************************************/
4384/****************** Bits definition for HASH_CR register ********************/
4385#define HASH_CR_INIT ((uint32_t)0x00000004)
4386#define HASH_CR_DMAE ((uint32_t)0x00000008)
4387#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
4388#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
4389#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
4390#define HASH_CR_MODE ((uint32_t)0x00000040)
4391#define HASH_CR_ALGO ((uint32_t)0x00000080)
4392#define HASH_CR_NBW ((uint32_t)0x00000F00)
4393#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
4394#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
4395#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
4396#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
4397#define HASH_CR_DINNE ((uint32_t)0x00001000)
4398#define HASH_CR_LKEY ((uint32_t)0x00010000)
4399
4400/****************** Bits definition for HASH_STR register *******************/
4401#define HASH_STR_NBW ((uint32_t)0x0000001F)
4402#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
4403#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
4404#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
4405#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
4406#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
4407#define HASH_STR_DCAL ((uint32_t)0x00000100)
4408
4409/****************** Bits definition for HASH_IMR register *******************/
4410#define HASH_IMR_DINIM ((uint32_t)0x00000001)
4411#define HASH_IMR_DCIM ((uint32_t)0x00000002)
4412
4413/****************** Bits definition for HASH_SR register ********************/
4414#define HASH_SR_DINIS ((uint32_t)0x00000001)
4415#define HASH_SR_DCIS ((uint32_t)0x00000002)
4416#define HASH_SR_DMAS ((uint32_t)0x00000004)
4417#define HASH_SR_BUSY ((uint32_t)0x00000008)
4418
4419/******************************************************************************/
4420/* */
4421/* Inter-integrated Circuit Interface */
4422/* */
4423/******************************************************************************/
4424/******************* Bit definition for I2C_CR1 register ********************/
4425#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
4426#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
4427#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
4428#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
4429#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
4430#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
4431#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
4432#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
4433#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
4434#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
4435#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
4436#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
4437#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
4438#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
4439
4440/******************* Bit definition for I2C_CR2 register ********************/
4441#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
4442#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
4443#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
4444#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
4445#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
4446#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
4447#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
4448
4449#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
4450#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
4451#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
4452#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
4453#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
4454
4455/******************* Bit definition for I2C_OAR1 register *******************/
4456#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
4457#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
4458
4459#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
4460#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
4461#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
4462#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
4463#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
4464#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
4465#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
4466#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
4467#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
4468#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
4469
4470#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
4471
4472/******************* Bit definition for I2C_OAR2 register *******************/
4473#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
4474#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
4475
4476/******************** Bit definition for I2C_DR register ********************/
4477#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
4478
4479/******************* Bit definition for I2C_SR1 register ********************/
4480#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
4481#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
4482#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
4483#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
4484#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
4485#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
4486#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
4487#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
4488#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
4489#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
4490#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
4491#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
4492#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
4493#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
4494
4495/******************* Bit definition for I2C_SR2 register ********************/
4496#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
4497#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
4498#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
4499#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
4500#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
4501#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
4502#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
4503#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
4504
4505/******************* Bit definition for I2C_CCR register ********************/
4506#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
4507#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
4508#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
4509
4510/****************** Bit definition for I2C_TRISE register *******************/
4511#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
4512
4513/******************************************************************************/
4514/* */
4515/* Independent WATCHDOG */
4516/* */
4517/******************************************************************************/
4518/******************* Bit definition for IWDG_KR register ********************/
4519#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4520
4521/******************* Bit definition for IWDG_PR register ********************/
4522#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4523#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
4524#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
4525#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
4526
4527/******************* Bit definition for IWDG_RLR register *******************/
4528#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
4529
4530/******************* Bit definition for IWDG_SR register ********************/
4531#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
4532#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
4533
4534/******************************************************************************/
4535/* */
4536/* Power Control */
4537/* */
4538/******************************************************************************/
4539/******************** Bit definition for PWR_CR register ********************/
4540#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
4541#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
4542#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
4543#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
4544#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
4545
4546#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
4547#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
4548#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
4549#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
4550
4551/*!< PVD level configuration */
4552#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
4553#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
4554#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
4555#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
4556#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
4557#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
4558#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
4559#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
4560
4561#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
4562#define PWR_CR_FPDS ((uint16_t)0x0200) /*!< Flash power down in Stop mode */
4563
4564
4565/******************* Bit definition for PWR_CSR register ********************/
4566#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
4567#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
4568#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
4569#define PWR_CSR_BRR ((uint16_t)0x0008) /*!< Backup regulator ready */
4570#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
4571#define PWR_CSR_BRE ((uint16_t)0x0200) /*!< Backup regulator enable */
4572
4573/******************************************************************************/
4574/* */
4575/* Reset and Clock Control */
4576/* */
4577/******************************************************************************/
4578/******************** Bit definition for RCC_CR register ********************/
4579#define RCC_CR_HSION ((uint32_t)0x00000001)
4580#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
4581
4582#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
4583#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
4584#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
4585#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
4586#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
4587#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
4588
4589#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
4590#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
4591#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
4592#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
4593#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
4594#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
4595#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
4596#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4597#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
4598
4599#define RCC_CR_HSEON ((uint32_t)0x00010000)
4600#define RCC_CR_HSERDY ((uint32_t)0x00020000)
4601#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
4602#define RCC_CR_CSSON ((uint32_t)0x00080000)
4603#define RCC_CR_PLLON ((uint32_t)0x01000000)
4604#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
4605#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
4606#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
4607
4608/******************** Bit definition for RCC_PLLCFGR register ***************/
4609#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
4610#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
4611#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
4612#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
4613#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
4614#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
4615#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
4616
4617#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
4618#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
4619#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
4620#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
4621#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
4622#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
4623#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
4624#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
4625#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
4626#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
4627
4628#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
4629#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
4630#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
4631
4632#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
4633#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
4634#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
4635
4636#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
4637#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
4638#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
4639#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
4640#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
4641
4642/******************** Bit definition for RCC_CFGR register ******************/
4643/*!< SW configuration */
4644#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
4645#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4646#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4647
4648#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
4649#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
4650#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
4651
4652/*!< SWS configuration */
4653#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
4654#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
4655#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
4656
4657#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
4658#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
4659#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
4660
4661/*!< HPRE configuration */
4662#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
4663#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4664#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4665#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4666#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4667
4668#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
4669#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
4670#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
4671#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
4672#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
4673#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
4674#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
4675#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
4676#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
4677
4678/*!< PPRE1 configuration */
4679#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
4680#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4681#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4682#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4683
4684#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4685#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
4686#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
4687#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
4688#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
4689
4690/*!< PPRE2 configuration */
4691#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
4692#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
4693#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
4694#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
4695
4696#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4697#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
4698#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
4699#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
4700#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E00) /*!< HCLK divided by 16 */
4701
4702/*!< RTCPRE configuration */
4703#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
4704#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
4705#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
4706#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
4707#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
4708#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
4709
4710/*!< MCO1 configuration */
4711#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
4712#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
4713#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
4714
4715#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
4716
4717#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
4718#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
4719#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
4720#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
4721
4722#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
4723#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
4724#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
4725#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
4726
4727#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
4728#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
4729#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
4730
4731/******************** Bit definition for RCC_CIR register *******************/
4732#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
4733#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
4734#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
4735#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
4736#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
4737#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
4738#define RCC_CIR_CSSF ((uint32_t)0x00000080)
4739#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
4740#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
4741#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
4742#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
4743#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
4744#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
4745#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
4746#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
4747#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
4748#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
4749#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
4750#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
4751#define RCC_CIR_CSSC ((uint32_t)0x00800000)
4752
4753/******************** Bit definition for RCC_AHB1RSTR register **************/
4754#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
4755#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
4756#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
4757#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
4758#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
4759#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
4760#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
4761#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
4762#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
4763#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
4764#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
4765#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
4766#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
4767#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
4768
4769/******************** Bit definition for RCC_AHB2RSTR register **************/
4770#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
4771#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
4772#define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)
4773#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
4774#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
4775
4776/******************** Bit definition for RCC_AHB3RSTR register **************/
4777#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
4778
4779/******************** Bit definition for RCC_APB1RSTR register **************/
4780#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
4781#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
4782#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
4783#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
4784#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
4785#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
4786#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
4787#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
4788#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
4789#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
4790#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)
4791#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)
4792#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
4793#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
4794#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
4795#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
4796#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
4797#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
4798#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
4799#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
4800#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
4801#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
4802#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
4803
4804/******************** Bit definition for RCC_APB2RSTR register **************/
4805#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
4806#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
4807#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
4808#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
4809#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
4810#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
4811#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
4812#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
4813#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
4814#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
4815#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
4816
4817/******************** Bit definition for RCC_AHB1ENR register ***************/
4818#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
4819#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
4820#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
4821#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
4822#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
4823#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
4824#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
4825#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
4826#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
4827#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
4828#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
4829#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
4830#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
4831#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
4832#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
4833#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
4834#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
4835#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
4836#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
4837
4838/******************** Bit definition for RCC_AHB2ENR register ***************/
4839#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
4840#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
4841#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
4842#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
4843#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
4844
4845/******************** Bit definition for RCC_AHB3ENR register ***************/
4846#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
4847
4848/******************** Bit definition for RCC_APB1ENR register ***************/
4849#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
4850#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
4851#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
4852#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
4853#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
4854#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
4855#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
4856#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
4857#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
4858#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
4859#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
4860#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
4861#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
4862#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
4863#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
4864#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
4865#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
4866#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
4867#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
4868#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
4869#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
4870#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
4871#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
4872
4873/******************** Bit definition for RCC_APB2ENR register ***************/
4874#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
4875#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
4876#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
4877#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
4878#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
4879#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
4880#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
4881#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
4882#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
4883#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
4884#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
4885#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
4886#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
4887
4888/******************** Bit definition for RCC_AHB1LPENR register *************/
4889#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
4890#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
4891#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
4892#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
4893#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
4894#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
4895#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
4896#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
4897#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
4898#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
4899#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
4900#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
4901#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
4902#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
4903#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
4904#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
4905#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
4906#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
4907#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
4908#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
4909#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
4910#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
4911
4912/******************** Bit definition for RCC_AHB2LPENR register *************/
4913#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
4914#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
4915#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
4916#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
4917#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
4918
4919/******************** Bit definition for RCC_AHB3LPENR register *************/
4920#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
4921
4922/******************** Bit definition for RCC_APB1LPENR register *************/
4923#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
4924#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
4925#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
4926#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
4927#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
4928#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
4929#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
4930#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
4931#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
4932#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
4933#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
4934#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
4935#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
4936#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
4937#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
4938#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
4939#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
4940#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
4941#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
4942#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
4943#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
4944#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
4945#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
4946
4947/******************** Bit definition for RCC_APB2LPENR register *************/
4948#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
4949#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
4950#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
4951#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
4952#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
4953#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
4954#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
4955#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
4956#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
4957#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
4958#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
4959#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
4960#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
4961
4962/******************** Bit definition for RCC_BDCR register ******************/
4963#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
4964#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
4965#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
4966
4967#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
4968#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
4969#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
4970
4971#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
4972#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
4973
4974/******************** Bit definition for RCC_CSR register *******************/
4975#define RCC_CSR_LSION ((uint32_t)0x00000001)
4976#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
4977#define RCC_CSR_RMVF ((uint32_t)0x01000000)
4978#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
4979#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
4980#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
4981#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
4982#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
4983#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
4984#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
4985
4986/******************** Bit definition for RCC_SSCGR register *****************/
4987#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
4988#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
4989#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
4990#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
4991
4992/******************** Bit definition for RCC_PLLI2SCFGR register ************/
4993#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
4994#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
4995
4996/******************************************************************************/
4997/* */
4998/* RNG */
4999/* */
5000/******************************************************************************/
5001/******************** Bits definition for RNG_CR register *******************/
5002#define RNG_CR_RNGEN ((uint32_t)0x00000004)
5003#define RNG_CR_IE ((uint32_t)0x00000008)
5004
5005/******************** Bits definition for RNG_SR register *******************/
5006#define RNG_SR_DRDY ((uint32_t)0x00000001)
5007#define RNG_SR_CECS ((uint32_t)0x00000002)
5008#define RNG_SR_SECS ((uint32_t)0x00000004)
5009#define RNG_SR_CEIS ((uint32_t)0x00000020)
5010#define RNG_SR_SEIS ((uint32_t)0x00000040)
5011
5012/******************************************************************************/
5013/* */
5014/* Real-Time Clock (RTC) */
5015/* */
5016/******************************************************************************/
5017/******************** Bits definition for RTC_TR register *******************/
5018#define RTC_TR_PM ((uint32_t)0x00400000)
5019#define RTC_TR_HT ((uint32_t)0x00300000)
5020#define RTC_TR_HT_0 ((uint32_t)0x00100000)
5021#define RTC_TR_HT_1 ((uint32_t)0x00200000)
5022#define RTC_TR_HU ((uint32_t)0x000F0000)
5023#define RTC_TR_HU_0 ((uint32_t)0x00010000)
5024#define RTC_TR_HU_1 ((uint32_t)0x00020000)
5025#define RTC_TR_HU_2 ((uint32_t)0x00040000)
5026#define RTC_TR_HU_3 ((uint32_t)0x00080000)
5027#define RTC_TR_MNT ((uint32_t)0x00007000)
5028#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5029#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5030#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5031#define RTC_TR_MNU ((uint32_t)0x00000F00)
5032#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5033#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5034#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5035#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5036#define RTC_TR_ST ((uint32_t)0x00000070)
5037#define RTC_TR_ST_0 ((uint32_t)0x00000010)
5038#define RTC_TR_ST_1 ((uint32_t)0x00000020)
5039#define RTC_TR_ST_2 ((uint32_t)0x00000040)
5040#define RTC_TR_SU ((uint32_t)0x0000000F)
5041#define RTC_TR_SU_0 ((uint32_t)0x00000001)
5042#define RTC_TR_SU_1 ((uint32_t)0x00000002)
5043#define RTC_TR_SU_2 ((uint32_t)0x00000004)
5044#define RTC_TR_SU_3 ((uint32_t)0x00000008)
5045
5046/******************** Bits definition for RTC_DR register *******************/
5047#define RTC_DR_YT ((uint32_t)0x00F00000)
5048#define RTC_DR_YT_0 ((uint32_t)0x00100000)
5049#define RTC_DR_YT_1 ((uint32_t)0x00200000)
5050#define RTC_DR_YT_2 ((uint32_t)0x00400000)
5051#define RTC_DR_YT_3 ((uint32_t)0x00800000)
5052#define RTC_DR_YU ((uint32_t)0x000F0000)
5053#define RTC_DR_YU_0 ((uint32_t)0x00010000)
5054#define RTC_DR_YU_1 ((uint32_t)0x00020000)
5055#define RTC_DR_YU_2 ((uint32_t)0x00040000)
5056#define RTC_DR_YU_3 ((uint32_t)0x00080000)
5057#define RTC_DR_WDU ((uint32_t)0x0000E000)
5058#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5059#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5060#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5061#define RTC_DR_MT ((uint32_t)0x00001000)
5062#define RTC_DR_MU ((uint32_t)0x00000F00)
5063#define RTC_DR_MU_0 ((uint32_t)0x00000100)
5064#define RTC_DR_MU_1 ((uint32_t)0x00000200)
5065#define RTC_DR_MU_2 ((uint32_t)0x00000400)
5066#define RTC_DR_MU_3 ((uint32_t)0x00000800)
5067#define RTC_DR_DT ((uint32_t)0x00000030)
5068#define RTC_DR_DT_0 ((uint32_t)0x00000010)
5069#define RTC_DR_DT_1 ((uint32_t)0x00000020)
5070#define RTC_DR_DU ((uint32_t)0x0000000F)
5071#define RTC_DR_DU_0 ((uint32_t)0x00000001)
5072#define RTC_DR_DU_1 ((uint32_t)0x00000002)
5073#define RTC_DR_DU_2 ((uint32_t)0x00000004)
5074#define RTC_DR_DU_3 ((uint32_t)0x00000008)
5075
5076/******************** Bits definition for RTC_CR register *******************/
5077#define RTC_CR_COE ((uint32_t)0x00800000)
5078#define RTC_CR_OSEL ((uint32_t)0x00600000)
5079#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5080#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5081#define RTC_CR_POL ((uint32_t)0x00100000)
5082#define RTC_CR_BCK ((uint32_t)0x00040000)
5083#define RTC_CR_SUB1H ((uint32_t)0x00020000)
5084#define RTC_CR_ADD1H ((uint32_t)0x00010000)
5085#define RTC_CR_TSIE ((uint32_t)0x00008000)
5086#define RTC_CR_WUTIE ((uint32_t)0x00004000)
5087#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5088#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5089#define RTC_CR_TSE ((uint32_t)0x00000800)
5090#define RTC_CR_WUTE ((uint32_t)0x00000400)
5091#define RTC_CR_ALRBE ((uint32_t)0x00000200)
5092#define RTC_CR_ALRAE ((uint32_t)0x00000100)
5093#define RTC_CR_DCE ((uint32_t)0x00000080)
5094#define RTC_CR_FMT ((uint32_t)0x00000040)
5095#define RTC_CR_REFCKON ((uint32_t)0x00000010)
5096#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5097#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5098#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5099#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5100#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5101
5102/******************** Bits definition for RTC_ISR register ******************/
5103#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5104#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5105#define RTC_ISR_TSF ((uint32_t)0x00000800)
5106#define RTC_ISR_WUTF ((uint32_t)0x00000400)
5107#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5108#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5109#define RTC_ISR_INIT ((uint32_t)0x00000080)
5110#define RTC_ISR_INITF ((uint32_t)0x00000040)
5111#define RTC_ISR_RSF ((uint32_t)0x00000020)
5112#define RTC_ISR_INITS ((uint32_t)0x00000010)
5113#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5114#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5115#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5116
5117/******************** Bits definition for RTC_PRER register *****************/
5118#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5119#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5120
5121/******************** Bits definition for RTC_WUTR register *****************/
5122#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5123
5124/******************** Bits definition for RTC_CALIBR register ***************/
5125#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5126#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5127
5128/******************** Bits definition for RTC_ALRMAR register ***************/
5129#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5130#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5131#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5132#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5133#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5134#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5135#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5136#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5137#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5138#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5139#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5140#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5141#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5142#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5143#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5144#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5145#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5146#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5147#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5148#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5149#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5150#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5151#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5152#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5153#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5154#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5155#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5156#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5157#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5158#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5159#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5160#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5161#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5162#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5163#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5164#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5165#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5166#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5167#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5168#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5169
5170/******************** Bits definition for RTC_ALRMBR register ***************/
5171#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5172#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5173#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5174#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5175#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5176#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5177#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5178#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5179#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5180#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5181#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5182#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5183#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5184#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5185#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5186#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5187#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5188#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5189#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5190#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5191#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5192#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5193#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5194#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5195#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5196#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5197#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5198#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5199#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5200#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5201#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5202#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5203#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5204#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5205#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5206#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5207#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5208#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5209#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5210#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5211
5212/******************** Bits definition for RTC_WPR register ******************/
5213#define RTC_WPR_KEY ((uint32_t)0x000000FF)
5214
5215/******************** Bits definition for RTC_TSTR register *****************/
5216#define RTC_TSTR_PM ((uint32_t)0x00400000)
5217#define RTC_TSTR_HT ((uint32_t)0x00300000)
5218#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5219#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5220#define RTC_TSTR_HU ((uint32_t)0x000F0000)
5221#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5222#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5223#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5224#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5225#define RTC_TSTR_MNT ((uint32_t)0x00007000)
5226#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5227#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5228#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5229#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5230#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5231#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5232#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5233#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5234#define RTC_TSTR_ST ((uint32_t)0x00000070)
5235#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5236#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5237#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5238#define RTC_TSTR_SU ((uint32_t)0x0000000F)
5239#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5240#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5241#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5242#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5243
5244/******************** Bits definition for RTC_TSDR register *****************/
5245#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5246#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5247#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5248#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5249#define RTC_TSDR_MT ((uint32_t)0x00001000)
5250#define RTC_TSDR_MU ((uint32_t)0x00000F00)
5251#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5252#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5253#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5254#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5255#define RTC_TSDR_DT ((uint32_t)0x00000030)
5256#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5257#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5258#define RTC_TSDR_DU ((uint32_t)0x0000000F)
5259#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5260#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5261#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5262#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5263
5264/******************** Bits definition for RTC_TAFCR register ****************/
5265#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5266#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
5267#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
5268#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5269#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5270#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5271
5272/******************** Bits definition for RTC_BKP0R register ****************/
5273#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5274
5275/******************** Bits definition for RTC_BKP1R register ****************/
5276#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5277
5278/******************** Bits definition for RTC_BKP2R register ****************/
5279#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5280
5281/******************** Bits definition for RTC_BKP3R register ****************/
5282#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5283
5284/******************** Bits definition for RTC_BKP4R register ****************/
5285#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5286
5287/******************** Bits definition for RTC_BKP5R register ****************/
5288#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5289
5290/******************** Bits definition for RTC_BKP6R register ****************/
5291#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5292
5293/******************** Bits definition for RTC_BKP7R register ****************/
5294#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5295
5296/******************** Bits definition for RTC_BKP8R register ****************/
5297#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5298
5299/******************** Bits definition for RTC_BKP9R register ****************/
5300#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5301
5302/******************** Bits definition for RTC_BKP10R register ***************/
5303#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5304
5305/******************** Bits definition for RTC_BKP11R register ***************/
5306#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5307
5308/******************** Bits definition for RTC_BKP12R register ***************/
5309#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5310
5311/******************** Bits definition for RTC_BKP13R register ***************/
5312#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5313
5314/******************** Bits definition for RTC_BKP14R register ***************/
5315#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5316
5317/******************** Bits definition for RTC_BKP15R register ***************/
5318#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5319
5320/******************** Bits definition for RTC_BKP16R register ***************/
5321#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
5322
5323/******************** Bits definition for RTC_BKP17R register ***************/
5324#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
5325
5326/******************** Bits definition for RTC_BKP18R register ***************/
5327#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
5328
5329/******************** Bits definition for RTC_BKP19R register ***************/
5330#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
5331
5332/******************************************************************************/
5333/* */
5334/* SD host Interface */
5335/* */
5336/******************************************************************************/
5337/****************** Bit definition for SDIO_POWER register ******************/
5338#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5339#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
5340#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
5341
5342/****************** Bit definition for SDIO_CLKCR register ******************/
5343#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
5344#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
5345#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
5346#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
5347
5348#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5349#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
5350#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
5351
5352#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5353#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
5354
5355/******************* Bit definition for SDIO_ARG register *******************/
5356#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5357
5358/******************* Bit definition for SDIO_CMD register *******************/
5359#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
5360
5361#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
5362#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
5363#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
5364
5365#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5366#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
5367#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
5368#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
5369#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
5370#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
5371#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
5372
5373/***************** Bit definition for SDIO_RESPCMD register *****************/
5374#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
5375
5376/****************** Bit definition for SDIO_RESP0 register ******************/
5377#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5378
5379/****************** Bit definition for SDIO_RESP1 register ******************/
5380#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5381
5382/****************** Bit definition for SDIO_RESP2 register ******************/
5383#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5384
5385/****************** Bit definition for SDIO_RESP3 register ******************/
5386#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5387
5388/****************** Bit definition for SDIO_RESP4 register ******************/
5389#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5390
5391/****************** Bit definition for SDIO_DTIMER register *****************/
5392#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
5393
5394/****************** Bit definition for SDIO_DLEN register *******************/
5395#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5396
5397/****************** Bit definition for SDIO_DCTRL register ******************/
5398#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
5399#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
5400#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
5401#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
5402
5403#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5404#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
5405#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
5406#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
5407#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
5408
5409#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
5410#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
5411#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
5412#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
5413
5414/****************** Bit definition for SDIO_DCOUNT register *****************/
5415#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5416
5417/****************** Bit definition for SDIO_STA register ********************/
5418#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
5419#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
5420#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5421#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5422#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5423#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5424#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5425#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5426#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5427#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5428#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
5429#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
5430#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
5431#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
5432#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5433#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5434#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5435#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5436#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5437#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5438#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5439#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5440#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5441#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5442
5443/******************* Bit definition for SDIO_ICR register *******************/
5444#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5445#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5446#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5447#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5448#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5449#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5450#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5451#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5452#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5453#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5454#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5455#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5456#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5457
5458/****************** Bit definition for SDIO_MASK register *******************/
5459#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5460#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5461#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5462#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5463#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
5464#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5465#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5466#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
5467#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5468#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
5469#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
5470#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
5471#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
5472#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
5473#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
5474#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
5475#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5476#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
5477#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5478#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5479#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
5480#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
5481#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
5482#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
5483
5484/***************** Bit definition for SDIO_FIFOCNT register *****************/
5485#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
5486
5487/****************** Bit definition for SDIO_FIFO register *******************/
5488#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
5489
5490/******************************************************************************/
5491/* */
5492/* Serial Peripheral Interface */
5493/* */
5494/******************************************************************************/
5495/******************* Bit definition for SPI_CR1 register ********************/
5496#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
5497#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
5498#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
5499
5500#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
5501#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
5502#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
5503#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
5504
5505#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
5506#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
5507#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
5508#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
5509#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
5510#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
5511#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
5512#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
5513#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
5514#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
5515
5516/******************* Bit definition for SPI_CR2 register ********************/
5517#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
5518#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
5519#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
5520#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
5521#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
5522#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
5523
5524/******************** Bit definition for SPI_SR register ********************/
5525#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
5526#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
5527#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
5528#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
5529#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
5530#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
5531#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
5532#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
5533
5534/******************** Bit definition for SPI_DR register ********************/
5535#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
5536
5537/******************* Bit definition for SPI_CRCPR register ******************/
5538#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
5539
5540/****************** Bit definition for SPI_RXCRCR register ******************/
5541#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
5542
5543/****************** Bit definition for SPI_TXCRCR register ******************/
5544#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
5545
5546/****************** Bit definition for SPI_I2SCFGR register *****************/
5547#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
5548
5549#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
5550#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
5551#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
5552
5553#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
5554
5555#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
5556#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
5557#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
5558
5559#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
5560
5561#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5562#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
5563#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
5564
5565#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
5566#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
5567
5568/****************** Bit definition for SPI_I2SPR register *******************/
5569#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
5570#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
5571#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
5572
5573/******************************************************************************/
5574/* */
5575/* SYSCFG */
5576/* */
5577/******************************************************************************/
5578/****************** Bit definition for SYSCFG_MEMRMP register ***************/
5579#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */
5580#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
5581#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
5582
5583/****************** Bit definition for SYSCFG_PMC register ******************/
5584#define SYSCFG_PMC_MII_RMII ((uint16_t)0x0080) /*!<Ethernet PHY interface selection */
5585
5586/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5587#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
5588#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
5589#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
5590#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
5591/**
5592 * @brief EXTI0 configuration
5593 */
5594#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
5595#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
5596#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
5597#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
5598#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
5599#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
5600#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
5601#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
5602#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
5603/**
5604 * @brief EXTI1 configuration
5605 */
5606#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
5607#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
5608#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
5609#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
5610#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
5611#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
5612#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
5613#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
5614#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
5615/**
5616 * @brief EXTI2 configuration
5617 */
5618#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
5619#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
5620#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
5621#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
5622#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
5623#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
5624#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
5625#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
5626#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
5627/**
5628 * @brief EXTI3 configuration
5629 */
5630#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
5631#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
5632#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
5633#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
5634#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
5635#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
5636#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
5637#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
5638#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
5639
5640/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5641#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
5642#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
5643#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
5644#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
5645/**
5646 * @brief EXTI4 configuration
5647 */
5648#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
5649#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
5650#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
5651#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
5652#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
5653#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
5654#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
5655#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
5656#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
5657/**
5658 * @brief EXTI5 configuration
5659 */
5660#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
5661#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
5662#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
5663#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
5664#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
5665#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
5666#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
5667#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
5668#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
5669/**
5670 * @brief EXTI6 configuration
5671 */
5672#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
5673#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
5674#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
5675#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
5676#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
5677#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
5678#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
5679#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
5680#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
5681/**
5682 * @brief EXTI7 configuration
5683 */
5684#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
5685#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
5686#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
5687#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
5688#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
5689#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
5690#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
5691#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
5692#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
5693
5694/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5695#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
5696#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
5697#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
5698#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
5699
5700/**
5701 * @brief EXTI8 configuration
5702 */
5703#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
5704#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
5705#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
5706#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
5707#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
5708#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
5709#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
5710#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
5711#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
5712/**
5713 * @brief EXTI9 configuration
5714 */
5715#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
5716#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
5717#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
5718#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
5719#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
5720#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
5721#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
5722#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
5723#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
5724/**
5725 * @brief EXTI10 configuration
5726 */
5727#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
5728#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
5729#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
5730#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
5731#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
5732#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
5733#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
5734#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
5735#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
5736/**
5737 * @brief EXTI11 configuration
5738 */
5739#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
5740#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
5741#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
5742#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
5743#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
5744#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
5745#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
5746#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
5747#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
5748
5749/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5750#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
5751#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
5752#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
5753#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
5754/**
5755 * @brief EXTI12 configuration
5756 */
5757#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
5758#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
5759#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
5760#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
5761#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
5762#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
5763#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
5764#define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
5765/**
5766 * @brief EXTI13 configuration
5767 */
5768#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
5769#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
5770#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
5771#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
5772#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
5773#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
5774#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
5775#define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
5776/**
5777 * @brief EXTI14 configuration
5778 */
5779#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
5780#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
5781#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
5782#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
5783#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
5784#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
5785#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
5786#define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
5787/**
5788 * @brief EXTI15 configuration
5789 */
5790#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
5791#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
5792#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
5793#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
5794#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
5795#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
5796#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
5797#define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
5798
5799/****************** Bit definition for SYSCFG_CMPCR register ****************/
5800#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
5801#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
5802
5803/******************************************************************************/
5804/* */
5805/* TIM */
5806/* */
5807/******************************************************************************/
5808/******************* Bit definition for TIM_CR1 register ********************/
5809#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
5810#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
5811#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
5812#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
5813#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
5814
5815#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
5816#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
5817#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
5818
5819#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
5820
5821#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
5822#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
5823#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
5824
5825/******************* Bit definition for TIM_CR2 register ********************/
5826#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
5827#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
5828#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
5829
5830#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
5831#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
5832#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
5833#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
5834
5835#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
5836#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
5837#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
5838#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
5839#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
5840#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
5841#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
5842#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
5843
5844/******************* Bit definition for TIM_SMCR register *******************/
5845#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
5846#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
5847#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
5848#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
5849
5850#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
5851#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
5852#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
5853#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
5854
5855#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
5856
5857#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
5858#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
5859#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
5860#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
5861#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
5862
5863#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
5864#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
5865#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
5866
5867#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
5868#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
5869
5870/******************* Bit definition for TIM_DIER register *******************/
5871#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
5872#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
5873#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
5874#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
5875#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
5876#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
5877#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
5878#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
5879#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
5880#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
5881#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
5882#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
5883#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
5884#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
5885#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
5886
5887/******************** Bit definition for TIM_SR register ********************/
5888#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
5889#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
5890#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
5891#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
5892#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
5893#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
5894#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
5895#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
5896#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
5897#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
5898#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
5899#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
5900
5901/******************* Bit definition for TIM_EGR register ********************/
5902#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
5903#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
5904#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
5905#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
5906#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
5907#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
5908#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
5909#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
5910
5911/****************** Bit definition for TIM_CCMR1 register *******************/
5912#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5913#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
5914#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
5915
5916#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
5917#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
5918
5919#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5920#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
5921#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
5922#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
5923
5924#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
5925
5926#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5927#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
5928#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
5929
5930#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
5931#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
5932
5933#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5934#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
5935#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
5936#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
5937
5938#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
5939
5940/*----------------------------------------------------------------------------*/
5941
5942#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
5943#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
5944#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
5945
5946#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5947#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
5948#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
5949#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
5950#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
5951
5952#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5953#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
5954#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
5955
5956#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5957#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
5958#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
5959#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
5960#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
5961
5962/****************** Bit definition for TIM_CCMR2 register *******************/
5963#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5964#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
5965#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
5966
5967#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
5968#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
5969
5970#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5971#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
5972#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
5973#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
5974
5975#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
5976
5977#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5978#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
5979#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
5980
5981#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
5982#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
5983
5984#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5985#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
5986#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
5987#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
5988
5989#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
5990
5991/*----------------------------------------------------------------------------*/
5992
5993#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5994#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
5995#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
5996
5997#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5998#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
5999#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
6000#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
6001#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
6002
6003#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6004#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
6005#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
6006
6007#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6008#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
6009#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
6010#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
6011#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
6012
6013/******************* Bit definition for TIM_CCER register *******************/
6014#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
6015#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
6016#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
6017#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
6018#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
6019#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
6020#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
6021#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
6022#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
6023#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
6024#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
6025#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
6026#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
6027#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
6028#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
6029
6030/******************* Bit definition for TIM_CNT register ********************/
6031#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
6032
6033/******************* Bit definition for TIM_PSC register ********************/
6034#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
6035
6036/******************* Bit definition for TIM_ARR register ********************/
6037#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
6038
6039/******************* Bit definition for TIM_RCR register ********************/
6040#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
6041
6042/******************* Bit definition for TIM_CCR1 register *******************/
6043#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
6044
6045/******************* Bit definition for TIM_CCR2 register *******************/
6046#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
6047
6048/******************* Bit definition for TIM_CCR3 register *******************/
6049#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
6050
6051/******************* Bit definition for TIM_CCR4 register *******************/
6052#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
6053
6054/******************* Bit definition for TIM_BDTR register *******************/
6055#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6056#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
6057#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
6058#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
6059#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
6060#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
6061#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
6062#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
6063#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
6064
6065#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
6066#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
6067#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
6068
6069#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
6070#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
6071#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
6072#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
6073#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
6074#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
6075
6076/******************* Bit definition for TIM_DCR register ********************/
6077#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
6078#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
6079#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
6080#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
6081#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
6082#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
6083
6084#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
6085#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
6086#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
6087#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
6088#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
6089#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
6090
6091/******************* Bit definition for TIM_DMAR register *******************/
6092#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
6093
6094/******************* Bit definition for TIM_OR register *********************/
6095#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
6096#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
6097#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
6098#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
6099#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
6100#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
6101
6102
6103/******************************************************************************/
6104/* */
6105/* Universal Synchronous Asynchronous Receiver Transmitter */
6106/* */
6107/******************************************************************************/
6108/******************* Bit definition for USART_SR register *******************/
6109#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
6110#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
6111#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
6112#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
6113#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
6114#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
6115#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
6116#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
6117#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
6118#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
6119
6120/******************* Bit definition for USART_DR register *******************/
6121#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
6122
6123/****************** Bit definition for USART_BRR register *******************/
6124#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
6125#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
6126
6127/****************** Bit definition for USART_CR1 register *******************/
6128#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
6129#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
6130#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
6131#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
6132#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
6133#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
6134#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
6135#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
6136#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
6137#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
6138#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
6139#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
6140#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
6141#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
6142#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
6143
6144/****************** Bit definition for USART_CR2 register *******************/
6145#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
6146#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
6147#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
6148#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
6149#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
6150#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
6151#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
6152
6153#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
6154#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
6155#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
6156
6157#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
6158
6159/****************** Bit definition for USART_CR3 register *******************/
6160#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
6161#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
6162#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
6163#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
6164#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
6165#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
6166#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
6167#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
6168#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
6169#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
6170#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
6171#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
6172
6173/****************** Bit definition for USART_GTPR register ******************/
6174#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
6175#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
6176#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
6177#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
6178#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
6179#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
6180#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
6181#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
6182#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
6183
6184#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
6185
6186/******************************************************************************/
6187/* */
6188/* Window WATCHDOG */
6189/* */
6190/******************************************************************************/
6191/******************* Bit definition for WWDG_CR register ********************/
6192#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6193#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
6194#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
6195#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
6196#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
6197#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
6198#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
6199#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
6200
6201#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
6202
6203/******************* Bit definition for WWDG_CFR register *******************/
6204#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
6205#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
6206#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
6207#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
6208#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
6209#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
6210#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
6211#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
6212
6213#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
6214#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
6215#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
6216
6217#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
6218
6219/******************* Bit definition for WWDG_SR register ********************/
6220#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
6221
6222
6223/******************************************************************************/
6224/* */
6225/* DBG */
6226/* */
6227/******************************************************************************/
6228/******************** Bit definition for DBGMCU_IDCODE register *************/
6229#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
6230#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
6231
6232/******************** Bit definition for DBGMCU_CR register *****************/
6233#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
6234#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
6235#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
6236#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
6237
6238#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
6239#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
6240#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
6241
6242/******************** Bit definition for DBGMCU_APB1_FZ register ************/
6243#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
6244#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
6245#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
6246#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
6247#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
6248#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
6249#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
6250#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
6251#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
6252#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
6253#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
6254#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
6255#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
6256#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
6257#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
6258#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
6259#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
6260
6261/******************** Bit definition for DBGMCU_APB2_FZ register ************/
6262#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
6263#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
6264#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
6265#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
6266#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
6267
6268/******************************************************************************/
6269/* */
6270/* Ethernet MAC Registers bits definitions */
6271/* */
6272/******************************************************************************/
6273/* Bit definition for Ethernet MAC Control Register register */
6274#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
6275#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
6276#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
6277#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
6278 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
6279 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
6280 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
6281 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
6282 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
6283 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
6284 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
6285#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
6286#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
6287#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
6288#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
6289#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
6290#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
6291#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
6292#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
6293#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
6294 a transmission attempt during retries after a collision: 0 =< r <2^k */
6295 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
6296 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
6297 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
6298 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
6299#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
6300#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
6301#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
6302
6303/* Bit definition for Ethernet MAC Frame Filter Register */
6304#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
6305#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
6306#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
6307#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
6308#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
6309 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
6310 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
6311 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
6312#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
6313#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
6314#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
6315#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
6316#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
6317#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
6318
6319/* Bit definition for Ethernet MAC Hash Table High Register */
6320#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
6321
6322/* Bit definition for Ethernet MAC Hash Table Low Register */
6323#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
6324
6325/* Bit definition for Ethernet MAC MII Address Register */
6326#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
6327#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
6328#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
6329 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
6330 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-120 MHz; MDC clock= HCLK/62 */
6331 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
6332 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/42 */
6333#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
6334#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
6335
6336/* Bit definition for Ethernet MAC MII Data Register */
6337#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
6338
6339/* Bit definition for Ethernet MAC Flow Control Register */
6340#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
6341#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
6342#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
6343 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
6344 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
6345 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
6346 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
6347#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
6348#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
6349#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
6350#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
6351
6352/* Bit definition for Ethernet MAC VLAN Tag Register */
6353#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
6354#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
6355
6356/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
6357#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
6358/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
6359 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
6360/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
6361 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
6362 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
6363 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
6364 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
6365 RSVD - Filter1 Command - RSVD - Filter0 Command
6366 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
6367 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
6368 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
6369
6370/* Bit definition for Ethernet MAC PMT Control and Status Register */
6371#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
6372#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
6373#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
6374#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
6375#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
6376#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
6377#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
6378
6379/* Bit definition for Ethernet MAC Status Register */
6380#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
6381#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
6382#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
6383#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
6384#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
6385
6386/* Bit definition for Ethernet MAC Interrupt Mask Register */
6387#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
6388#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
6389
6390/* Bit definition for Ethernet MAC Address0 High Register */
6391#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
6392
6393/* Bit definition for Ethernet MAC Address0 Low Register */
6394#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
6395
6396/* Bit definition for Ethernet MAC Address1 High Register */
6397#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
6398#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
6399#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6400 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6401 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6402 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6403 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6404 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6405 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
6406#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6407
6408/* Bit definition for Ethernet MAC Address1 Low Register */
6409#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
6410
6411/* Bit definition for Ethernet MAC Address2 High Register */
6412#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
6413#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
6414#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6415 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6416 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6417 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6418 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6419 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6420 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6421#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6422
6423/* Bit definition for Ethernet MAC Address2 Low Register */
6424#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
6425
6426/* Bit definition for Ethernet MAC Address3 High Register */
6427#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
6428#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
6429#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6430 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6431 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6432 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6433 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6434 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6435 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6436#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
6437
6438/* Bit definition for Ethernet MAC Address3 Low Register */
6439#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
6440
6441/******************************************************************************/
6442/* Ethernet MMC Registers bits definition */
6443/******************************************************************************/
6444
6445/* Bit definition for Ethernet MMC Contol Register */
6446#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset (Only in STM32F2xx) */
6447#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset (Only in STM32F2xx) */
6448#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
6449#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
6450#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
6451#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
6452
6453/* Bit definition for Ethernet MMC Receive Interrupt Register */
6454#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
6455#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
6456#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
6457
6458/* Bit definition for Ethernet MMC Transmit Interrupt Register */
6459#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
6460#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
6461#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
6462
6463/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
6464#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
6465#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
6466#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
6467
6468/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
6469#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
6470#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
6471#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
6472
6473/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
6474#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
6475
6476/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
6477#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
6478
6479/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
6480#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
6481
6482/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
6483#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
6484
6485/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
6486#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
6487
6488/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
6489#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
6490
6491/******************************************************************************/
6492/* Ethernet PTP Registers bits definition */
6493/******************************************************************************/
6494
6495/* Bit definition for Ethernet PTP Time Stamp Contol Register */
6496#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
6497#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
6498#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
6499#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
6500#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
6501#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
6502#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
6503#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
6504#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
6505
6506#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
6507#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
6508#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
6509#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
6510#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
6511#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
6512
6513/* Bit definition for Ethernet PTP Sub-Second Increment Register */
6514#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
6515
6516/* Bit definition for Ethernet PTP Time Stamp High Register */
6517#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
6518
6519/* Bit definition for Ethernet PTP Time Stamp Low Register */
6520#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
6521#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
6522
6523/* Bit definition for Ethernet PTP Time Stamp High Update Register */
6524#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
6525
6526/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
6527#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
6528#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
6529
6530/* Bit definition for Ethernet PTP Time Stamp Addend Register */
6531#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
6532
6533/* Bit definition for Ethernet PTP Target Time High Register */
6534#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
6535
6536/* Bit definition for Ethernet PTP Target Time Low Register */
6537#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
6538
6539/* Bit definition for Ethernet PTP Time Stamp Status Register */
6540#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
6541#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
6542
6543/******************************************************************************/
6544/* Ethernet DMA Registers bits definition */
6545/******************************************************************************/
6546
6547/* Bit definition for Ethernet DMA Bus Mode Register */
6548#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
6549#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
6550#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
6551#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
6552 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
6553 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
6554 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6555 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6556 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6557 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6558 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6559 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6560 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6561 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6562 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
6563 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
6564#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
6565#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
6566 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
6567 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
6568 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
6569 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
6570#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
6571 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
6572 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
6573 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6574 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6575 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6576 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6577 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6578 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6579 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6580 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6581 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
6582 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
6583#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
6584#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
6585#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
6586#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
6587
6588/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
6589#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
6590
6591/* Bit definition for Ethernet DMA Receive Poll Demand Register */
6592#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
6593
6594/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
6595#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
6596
6597/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
6598#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
6599
6600/* Bit definition for Ethernet DMA Status Register */
6601#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
6602#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
6603#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
6604#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
6605 /* combination with EBS[2:0] for GetFlagStatus function */
6606 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
6607 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
6608 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
6609#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
6610 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
6611 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
6612 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
6613 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
6614 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
6615 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
6616#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
6617 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
6618 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
6619 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
6620 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
6621 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
6622 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
6623#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
6624#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
6625#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
6626#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
6627#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
6628#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
6629#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
6630#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
6631#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
6632#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
6633#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
6634#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
6635#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
6636#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
6637#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
6638
6639/* Bit definition for Ethernet DMA Operation Mode Register */
6640#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
6641#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
6642#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
6643#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
6644#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
6645#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
6646 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
6647 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
6648 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
6649 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
6650 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
6651 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
6652 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
6653 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
6654#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
6655#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
6656#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
6657#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
6658 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
6659 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
6660 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
6661 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
6662#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
6663#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
6664
6665/* Bit definition for Ethernet DMA Interrupt Enable Register */
6666#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
6667#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
6668#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
6669#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
6670#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
6671#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
6672#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
6673#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
6674#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
6675#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
6676#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
6677#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
6678#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
6679#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
6680#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
6681
6682/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
6683#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
6684#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
6685#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
6686#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
6687
6688/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
6689#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
6690
6691/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
6692#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
6693
6694/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
6695#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
6696
6697/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
6698#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
6699
6700#define SET_BIT(REG, BIT) ((REG) |= (BIT))
6701
6702#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
6703
6704#define READ_BIT(REG, BIT) ((REG) & (BIT))
6705
6706#define CLEAR_REG(REG) ((REG) = (0x0))
6707
6708#define WRITE_REG(REG, VAL) ((REG) = (VAL))
6709
6710#define READ_REG(REG) ((REG))
6711
6712#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
6713
6714#ifdef __cplusplus
6715}
6716#endif /* __cplusplus */
6717
6718#endif /* __STM32F2xx_H */
6719
6720/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/