brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 1 | // **************************************************************************** |
| 2 | // CopyLeft qwerk Robotics unINC. 2010 All Rights Reserved. |
| 3 | // **************************************************************************** |
| 4 | |
| 5 | // **************************************************************************** |
| 6 | // **************** IO Pin Setup |
| 7 | // **************************************************************************** |
| 8 | |
| 9 | #include "FreeRTOS.h" |
Austin Schuh | 63d0e9b | 2013-03-27 04:43:14 +0000 | [diff] [blame^] | 10 | /* Scheduler includes. */ |
| 11 | #include "FreeRTOS.h" |
| 12 | #include "queue.h" |
| 13 | #include "task.h" |
| 14 | |
| 15 | #include "analog.h" |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 16 | |
| 17 | void analog_init (void) |
| 18 | { |
| 19 | // b[1:0] CAN RD1 p0.0 |
| 20 | // b[3:2] CAN TD1 p0.1 |
| 21 | //PINCON->PINSEL0 = 0x00000005; |
| 22 | |
| 23 | // b[29:28] USB_DMIN p0.30 |
| 24 | // b[27:26] USB_DPLUS p0.29 |
| 25 | // b[21:20] AD0.3 p0.26 |
| 26 | // b[19:18] AD0.2 p0.25 |
| 27 | // PINCON->PINSEL1 = 0x14140000; |
| 28 | |
| 29 | // PINCON->PINSEL2 = 0x0; |
| 30 | |
| 31 | // b[31:30] AD0.5 p1.31 |
| 32 | // b[29:28] V_BUS p1.30 |
| 33 | // b[21:20] MCOB1 p1.26 |
| 34 | // b[19:18] MCOA1 p1.25 |
| 35 | // b[15:14] MCI1 p1.23 |
| 36 | // b[13:12] MCOB0 p1.22 |
| 37 | // b[09:08] MCI0 p1.20 |
| 38 | // b[07:06] MCOA0 p1.19 |
| 39 | // b[05:04] USB_UP_LED p1.18 |
| 40 | //PINCON->PINSEL3 = 0xE0145150; |
| 41 | SC->PCONP |= PCONP_PCAD; |
| 42 | |
| 43 | // Enable AD0.0, AD0.1, AD0.2, AD0.3 |
| 44 | PINCON->PINSEL1 &= 0xFFC03FFF; |
| 45 | PINCON->PINSEL1 |= 0x00D54000; |
| 46 | ADC->ADCR = 0x00200500; |
| 47 | } |
| 48 | |
| 49 | // **************************************************************************** |
| 50 | // **************** ADC Functions |
| 51 | // **************************************************************************** |
| 52 | |
| 53 | |
| 54 | // **************** macros |
| 55 | // starts convertion [26:24] = 001 |
| 56 | |
| 57 | // **************** functions |
| 58 | int analog(int channel) |
| 59 | { |
| 60 | ADC->ADCR = ((ADC->ADCR & 0xF8FFFF00) | (0x01000000 | (1 << channel))); |
| 61 | |
| 62 | // Poll until it is done. |
| 63 | while(!(ADC->ADGDR & 0x80000000)); |
| 64 | |
| 65 | return ((ADC->ADGDR & 0x0000FFF0) >> 4); |
| 66 | } |
| 67 | // GPIO1 P0.4 |
| 68 | // GPIO2 P0.5 |
| 69 | // GPIO3 P0.6 |
| 70 | // GPIO4 P0.7 |
| 71 | // GPIO5 P0.8 |
| 72 | // GPIO6 P0.9 |
| 73 | // GPIO7 P2.0 |
| 74 | // GPIO8 P2.1 |
| 75 | // GPIO9 P2.2 |
| 76 | // GPIO10 P2.3 |
| 77 | // GPIO11 P2.4 |
| 78 | // GPIO12 P2.5 |
| 79 | |
| 80 | // DIP0 P1.29 |
| 81 | // DIP1 P2.13 |
| 82 | // DIP2 P0.11 |
| 83 | // DIP3 P0.10 |
| 84 | #define readGPIO(gpio,chan) ((((gpio)->FIOPIN) >> (chan)) & 1) |
| 85 | inline int readGPIO_inline(int major,int minor){ |
| 86 | switch(major){ |
| 87 | case 0: |
| 88 | return readGPIO(GPIO0,minor); |
| 89 | case 1: |
| 90 | return readGPIO(GPIO1,minor); |
| 91 | case 2: |
| 92 | return readGPIO(GPIO2,minor); |
| 93 | default: |
| 94 | return -1; |
| 95 | } |
| 96 | } |
| 97 | int digital(int channel) |
| 98 | { |
| 99 | if(channel < 1){ |
| 100 | return -1; |
| 101 | }else if(channel < 7){ |
| 102 | int chan = channel + 3; |
| 103 | return readGPIO(GPIO0,chan); |
| 104 | }else if(channel < 13){ |
| 105 | int chan = channel - 7; |
| 106 | return readGPIO(GPIO2,chan); |
| 107 | } |
| 108 | return -1; |
| 109 | } |
| 110 | int dip(int channel) |
| 111 | { |
| 112 | switch(channel){ |
| 113 | case 0: |
| 114 | return readGPIO(GPIO1,29); |
| 115 | case 1: |
| 116 | return readGPIO(GPIO2,13); |
| 117 | case 2: |
| 118 | return readGPIO(GPIO0,11); |
| 119 | case 3: |
| 120 | return readGPIO(GPIO0,10); |
| 121 | default: |
| 122 | return -1; |
| 123 | |
| 124 | } |
| 125 | } |
| 126 | //ENC0A 1.20 |
| 127 | //ENC0B 1.23 |
| 128 | //ENC1A 2.11 |
| 129 | //ENC1B 2.12 |
| 130 | //ENC2A 0.21 |
| 131 | //ENC2B 0.22 |
| 132 | //ENC3A 0.19 |
| 133 | //ENC3B 0.20 |
| 134 | |
| 135 | #define ENC(gpio,a,b) readGPIO(gpio,a) * 2 + readGPIO(gpio,b) |
| 136 | int encoder_bits(int channel) |
| 137 | { |
| 138 | switch(channel){ |
| 139 | case 0: |
| 140 | return ENC(GPIO1,20,23); |
| 141 | case 1: |
| 142 | return ENC(GPIO2,11,12); |
| 143 | case 2: |
| 144 | return ENC(GPIO0,21,22); |
| 145 | case 3: |
| 146 | return ENC(GPIO0,19,20); |
| 147 | default: |
| 148 | return -1; |
| 149 | } |
| 150 | return -1; |
| 151 | } |
| 152 | |
| 153 | volatile int32_t encoder1_val; |
Austin Schuh | 63d0e9b | 2013-03-27 04:43:14 +0000 | [diff] [blame^] | 154 | volatile int32_t encoder2_val; |
| 155 | volatile int32_t encoder3_val; |
| 156 | volatile int32_t encoder4_val; |
| 157 | volatile int32_t encoder5_val; |
| 158 | |
| 159 | // indexer encoder |
| 160 | void EINT1_IRQHandler(void){ |
| 161 | //ENC1A 2.11 |
| 162 | SC->EXTINT = 0x2; |
| 163 | int stored_val = encoder1_val; |
| 164 | int fiopin = GPIO2->FIOPIN; |
| 165 | if(((fiopin >> 1) ^ fiopin) & 0x800){ |
| 166 | stored_val ++; |
| 167 | }else{ |
| 168 | stored_val --; |
| 169 | } |
| 170 | encoder1_val = stored_val; |
| 171 | SC->EXTPOLAR ^= 0x2; |
| 172 | } |
| 173 | void EINT2_IRQHandler(void){ |
| 174 | //ENC1B 2.12 |
| 175 | SC->EXTINT = 0x4; |
| 176 | int stored_val = encoder1_val; |
| 177 | int fiopin = GPIO2->FIOPIN; |
| 178 | if(((fiopin >> 1) ^ fiopin) & 0x800){ |
| 179 | stored_val --; |
| 180 | }else{ |
| 181 | stored_val ++; |
| 182 | } |
| 183 | encoder1_val = stored_val; |
| 184 | SC->EXTPOLAR ^= 0x4; |
| 185 | } |
| 186 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __clz(uint32_t value) |
| 187 | { |
| 188 | uint8_t result; |
| 189 | |
| 190 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); |
| 191 | return(result); |
| 192 | } |
| 193 | //GPIO Interrupt handlers: |
| 194 | void NoGPIO(){ |
| 195 | } |
| 196 | void Encoder2ARise(){ |
| 197 | GPIOINT->IO0IntClr |= (1<<22); |
| 198 | if(GPIO0->FIOPIN & (1<<21)){ |
| 199 | encoder2_val ++; |
| 200 | }else{ |
| 201 | encoder2_val --; |
| 202 | } |
| 203 | } |
| 204 | void Encoder2AFall(){ |
| 205 | GPIOINT->IO0IntClr |= (1<<22); |
| 206 | if(GPIO0->FIOPIN & (1<<21)){ |
| 207 | encoder2_val --; |
| 208 | }else{ |
| 209 | encoder2_val ++; |
| 210 | } |
| 211 | } |
| 212 | void Encoder2BRise(){ |
| 213 | GPIOINT->IO0IntClr |= (1<<21); |
| 214 | if(GPIO0->FIOPIN & (1<<22)){ |
| 215 | encoder2_val --; |
| 216 | }else{ |
| 217 | encoder2_val ++; |
| 218 | } |
| 219 | } |
| 220 | void Encoder2BFall(){ |
| 221 | GPIOINT->IO0IntClr |= (1<<21); |
| 222 | if(GPIO0->FIOPIN & (1<<22)){ |
| 223 | encoder2_val ++; |
| 224 | }else{ |
| 225 | encoder2_val --; |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | void Encoder3ARise(){ |
| 230 | GPIOINT->IO0IntClr |= (1<<20); |
| 231 | if(GPIO0->FIOPIN & (1<<19)){ |
| 232 | encoder3_val ++; |
| 233 | }else{ |
| 234 | encoder3_val --; |
| 235 | } |
| 236 | } |
| 237 | void Encoder3AFall(){ |
| 238 | GPIOINT->IO0IntClr |= (1<<20); |
| 239 | if(GPIO0->FIOPIN & (1<<19)){ |
| 240 | encoder3_val --; |
| 241 | }else{ |
| 242 | encoder3_val ++; |
| 243 | } |
| 244 | } |
| 245 | void Encoder3BRise(){ |
| 246 | GPIOINT->IO0IntClr |= (1<<19); |
| 247 | if(GPIO0->FIOPIN & (1<<20)){ |
| 248 | encoder3_val --; |
| 249 | }else{ |
| 250 | encoder3_val ++; |
| 251 | } |
| 252 | } |
| 253 | void Encoder3BFall(){ |
| 254 | GPIOINT->IO0IntClr |= (1<<19); |
| 255 | if(GPIO0->FIOPIN & (1<<20)){ |
| 256 | encoder3_val ++; |
| 257 | }else{ |
| 258 | encoder3_val --; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | void Encoder4ARise(){ |
| 263 | GPIOINT->IO2IntClr |= (1<<0); |
| 264 | if(GPIO2->FIOPIN & (1<<1)){ |
| 265 | encoder4_val ++; |
| 266 | }else{ |
| 267 | encoder4_val --; |
| 268 | } |
| 269 | } |
| 270 | void Encoder4AFall(){ |
| 271 | GPIOINT->IO2IntClr |= (1<<0); |
| 272 | if(GPIO2->FIOPIN & (1<<1)){ |
| 273 | encoder4_val --; |
| 274 | }else{ |
| 275 | encoder4_val ++; |
| 276 | } |
| 277 | } |
| 278 | void Encoder4BRise(){ |
| 279 | GPIOINT->IO2IntClr |= (1<<1); |
| 280 | if(GPIO2->FIOPIN & (1<<0)){ |
| 281 | encoder4_val --; |
| 282 | }else{ |
| 283 | encoder4_val ++; |
| 284 | } |
| 285 | } |
| 286 | void Encoder4BFall(){ |
| 287 | GPIOINT->IO2IntClr |= (1<<1); |
| 288 | if(GPIO2->FIOPIN & (1<<0)){ |
| 289 | encoder4_val ++; |
| 290 | }else{ |
| 291 | encoder4_val --; |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | // |
| 296 | |
| 297 | void Encoder5ARise(){ |
| 298 | GPIOINT->IO2IntClr |= (1<<2); |
| 299 | if(GPIO2->FIOPIN & (1<<3)){ |
| 300 | encoder5_val ++; |
| 301 | }else{ |
| 302 | encoder5_val --; |
| 303 | } |
| 304 | } |
| 305 | void Encoder5AFall(){ |
| 306 | GPIOINT->IO2IntClr |= (1<<2); |
| 307 | if(GPIO2->FIOPIN & (1<<3)){ |
| 308 | encoder5_val --; |
| 309 | }else{ |
| 310 | encoder5_val ++; |
| 311 | } |
| 312 | } |
| 313 | void Encoder5BRise(){ |
| 314 | GPIOINT->IO2IntClr |= (1<<3); |
| 315 | if(GPIO2->FIOPIN & (1<<2)){ |
| 316 | encoder5_val --; |
| 317 | }else{ |
| 318 | encoder5_val ++; |
| 319 | } |
| 320 | } |
| 321 | void Encoder5BFall(){ |
| 322 | GPIOINT->IO2IntClr |= (1<<3); |
| 323 | if(GPIO2->FIOPIN & (1<<2)){ |
| 324 | encoder5_val ++; |
| 325 | }else{ |
| 326 | encoder5_val --; |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | volatile int32_t capture_top_rise; |
| 331 | volatile int8_t top_rise_count; |
| 332 | void IndexerTopRise(){ |
| 333 | GPIOINT->IO0IntClr |= (1<<5); |
| 334 | // edge counting encoder capture |
| 335 | top_rise_count ++; |
| 336 | capture_top_rise = encoder3_val; |
| 337 | } |
| 338 | volatile int32_t capture_top_fall; |
| 339 | volatile int8_t top_fall_count; |
| 340 | void IndexerTopFall(){ |
| 341 | GPIOINT->IO0IntClr |= (1<<5); |
| 342 | // edge counting encoder capture |
| 343 | top_fall_count ++; |
| 344 | capture_top_fall = encoder3_val; |
| 345 | } |
| 346 | volatile int8_t bottom_rise_count; |
| 347 | void IndexerBottomRise(){ |
| 348 | GPIOINT->IO0IntClr |= (1<<4); |
| 349 | // edge counting |
| 350 | bottom_rise_count ++; |
| 351 | } |
| 352 | volatile int32_t capture_bottom_fall_delay; |
| 353 | volatile int8_t bottom_fall_delay_count; |
| 354 | volatile int32_t dirty_delay; |
| 355 | portTickType xDelayTimeFrom; |
| 356 | static portTASK_FUNCTION(vDelayCapture, pvParameters) |
| 357 | { |
| 358 | portTickType xSleepFrom; |
| 359 | xSleepFrom = xTaskGetTickCount(); |
| 360 | |
| 361 | for(;;){ |
| 362 | NVIC_DisableIRQ(EINT3_IRQn); |
| 363 | if(dirty_delay){ |
| 364 | xSleepFrom = xDelayTimeFrom; |
| 365 | dirty_delay = 0; |
| 366 | NVIC_EnableIRQ(EINT3_IRQn); |
| 367 | |
| 368 | vTaskDelayUntil(&xSleepFrom, 32 / portTICK_RATE_MS); |
| 369 | |
| 370 | NVIC_DisableIRQ(EINT3_IRQn); |
| 371 | bottom_fall_delay_count ++; |
| 372 | capture_bottom_fall_delay = encoder3_val; |
| 373 | NVIC_EnableIRQ(EINT3_IRQn); |
| 374 | }else{ |
| 375 | NVIC_EnableIRQ(EINT3_IRQn); |
| 376 | vTaskDelayUntil(&xSleepFrom, 10 / portTICK_RATE_MS); |
| 377 | } |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | |
| 382 | volatile int8_t bottom_fall_count; |
| 383 | void IndexerBottomFall(){ |
| 384 | GPIOINT->IO0IntClr |= (1<<4); |
| 385 | bottom_fall_count ++; |
| 386 | // edge counting start delayed capture |
| 387 | xDelayTimeFrom = xTaskGetTickCount(); |
| 388 | dirty_delay = 1; |
| 389 | } |
| 390 | volatile int32_t capture_wrist_rise; |
| 391 | volatile int8_t wrist_rise_count; |
| 392 | void WristHallRise(){ |
| 393 | GPIOINT->IO0IntClr |= (1<<6); |
| 394 | // edge counting encoder capture |
| 395 | wrist_rise_count ++; |
| 396 | capture_wrist_rise = (int32_t)QEI->QEIPOS; |
| 397 | } |
| 398 | volatile int32_t capture_shooter_angle_rise; |
| 399 | volatile int8_t shooter_angle_rise_count; |
| 400 | void ShooterHallRise(){ |
| 401 | GPIOINT->IO0IntClr |= (1<<7); |
| 402 | // edge counting encoder capture |
| 403 | shooter_angle_rise_count ++; |
| 404 | capture_shooter_angle_rise = encoder2_val; |
| 405 | } |
| 406 | typedef void (*PFUNC)(void); |
| 407 | inline static void IRQ_Dispatch(void){ |
| 408 | uint8_t index = __clz(GPIOINT->IO2IntStatR | GPIOINT->IO0IntStatR | |
| 409 | (GPIOINT->IO2IntStatF << 28) | (GPIOINT->IO0IntStatF << 4)); |
| 410 | |
| 411 | |
| 412 | const static PFUNC table[] = { |
| 413 | Encoder5BFall, // index 0: P2.3 Fall #bit 31 //Encoder 5 B //Dio 10 |
| 414 | Encoder5AFall, // index 1: P2.2 Fall #bit 30 //Encoder 5 A //Dio 9 |
| 415 | Encoder4BFall, // index 2: P2.1 Fall #bit 29 //Encoder 4 B //Dio 8 |
| 416 | Encoder4AFall, // index 3: P2.0 Fall #bit 28 //Encoder 4 A //Dio 7 |
| 417 | NoGPIO, // index 4: NO GPIO #bit 27 |
| 418 | Encoder2AFall, // index 5: P0.22 Fall #bit 26 //Encoder 2 A |
| 419 | Encoder2BFall, // index 6: P0.21 Fall #bit 25 //Encoder 2 B |
| 420 | Encoder3AFall, // index 7: P0.20 Fall #bit 24 //Encoder 3 A |
| 421 | Encoder3BFall, // index 8: P0.19 Fall #bit 23 //Encoder 3 B |
| 422 | Encoder2ARise, // index 9: P0.22 Rise #bit 22 //Encoder 2 A |
| 423 | Encoder2BRise, // index 10: P0.21 Rise #bit 21 //Encoder 2 B |
| 424 | Encoder3ARise, // index 11: P0.20 Rise #bit 20 //Encoder 3 A |
| 425 | Encoder3BRise, // index 12: P0.19 Rise #bit 19 //Encoder 3 B |
| 426 | NoGPIO, // index 13: NO GPIO #bit 18 |
| 427 | NoGPIO, // index 14: NO GPIO #bit 17 |
| 428 | NoGPIO, // index 15: NO GPIO #bit 16 |
| 429 | NoGPIO, // index 16: NO GPIO #bit 15 |
| 430 | NoGPIO, // index 17: NO GPIO #bit 14 |
| 431 | NoGPIO, // index 18: NO GPIO #bit 13 |
| 432 | NoGPIO, // index 19: NO GPIO #bit 12 |
| 433 | NoGPIO, // index 20: NO GPIO #bit 11 |
| 434 | NoGPIO, // index 21: NO GPIO #bit 10 |
| 435 | IndexerTopFall, // index 22: P0.5 Fall #bit 9 //Indexer Top //Dio 2 |
| 436 | IndexerBottomFall, // index 23: P0.4 Fall #bit 8 //Indexer Bottom //Dio 1 |
| 437 | ShooterHallRise, // index 24: P0.7 Rise #bit 7 //Shooter Hall //Dio 4 |
| 438 | WristHallRise, // index 25: P0.6 Rise #bit 6 //Wrist Hall //Dio 3 |
| 439 | IndexerTopRise, // index 26: P0.5 Rise #bit 5 //Indexer Top //Dio 2 |
| 440 | IndexerBottomRise, // index 27: P0.4 Rise #bit 4 //Indexer Bottom //Dio 1 |
| 441 | Encoder5BRise, // index 28: P2.3 Rise #bit 3 //Encoder 5 B //Dio 10 |
| 442 | Encoder5ARise, // index 29: P2.2 Rise #bit 2 //Encoder 5 A //Dio 9 |
| 443 | Encoder4BRise, // index 30: P2.1 Rise #bit 1 //Encoder 4 B //Dio 8 |
| 444 | Encoder4ARise, // index 31: P2.0 Rise #bit 0 //Encoder 4 A //Dio 7 |
| 445 | NoGPIO // index 32: NO BITS SET #False Alarm |
| 446 | }; |
| 447 | table[index](); |
| 448 | |
| 449 | |
| 450 | /* |
| 451 | switch(index){ |
| 452 | case 0: //P2.3 Fall #bit 31 //Encoder 5 B //Dio 10 |
| 453 | Encoder5BFall(); |
| 454 | return; |
| 455 | |
| 456 | case 1: //P2.2 Fall #bit 30 //Encoder 5 A //Dio 9 |
| 457 | Encoder5AFall(); |
| 458 | return; |
| 459 | |
| 460 | case 2: //P2.1 Fall #bit 29 //Encoder 4 B //Dio 8 |
| 461 | Encoder4BFall(); |
| 462 | return; |
| 463 | |
| 464 | case 3: //P2.0 Fall #bit 28 //Encoder 4 A //Dio 7 |
| 465 | Encoder4AFall(); |
| 466 | return; |
| 467 | |
| 468 | case 4: //NO GPIO #bit 27 |
| 469 | NoGPIO(); |
| 470 | return; |
| 471 | |
| 472 | case 5: //P0.22 Fall #bit 26 //Encoder 2 A |
| 473 | Encoder2AFall(); |
| 474 | return; |
| 475 | |
| 476 | case 6: //P0.21 Fall #bit 25 //Encoder 2 B |
| 477 | Encoder2BFall(); |
| 478 | return; |
| 479 | |
| 480 | case 7: //P0.20 Fall #bit 24 //Encoder 3 A |
| 481 | Encoder3AFall(); |
| 482 | return; |
| 483 | |
| 484 | case 8: //P0.19 Fall #bit 23 //Encoder 3 B |
| 485 | Encoder3BFall(); |
| 486 | return; |
| 487 | |
| 488 | case 9: //P0.22 Rise #bit 22 //Encoder 2 A |
| 489 | Encoder2ARise(); |
| 490 | return; |
| 491 | |
| 492 | case 10: //P0.21 Rise #bit 21 //Encoder 2 B |
| 493 | Encoder2BRise(); |
| 494 | return; |
| 495 | |
| 496 | case 11: //P0.20 Rise #bit 20 //Encoder 3 A |
| 497 | Encoder3ARise(); |
| 498 | return; |
| 499 | |
| 500 | case 12: //P0.19 Rise #bit 19 //Encoder 3 B |
| 501 | Encoder3BRise(); |
| 502 | return; |
| 503 | |
| 504 | case 13: //NO GPIO #bit 18 |
| 505 | NoGPIO(); |
| 506 | return; |
| 507 | |
| 508 | case 14: //NO GPIO #bit 17 |
| 509 | NoGPIO(); |
| 510 | return; |
| 511 | |
| 512 | case 15: //NO GPIO #bit 16 |
| 513 | NoGPIO(); |
| 514 | return; |
| 515 | |
| 516 | case 16: //NO GPIO #bit 15 |
| 517 | NoGPIO(); |
| 518 | return; |
| 519 | |
| 520 | case 17: //NO GPIO #bit 14 |
| 521 | NoGPIO(); |
| 522 | return; |
| 523 | |
| 524 | case 18: //NO GPIO #bit 13 |
| 525 | NoGPIO(); |
| 526 | return; |
| 527 | |
| 528 | case 19: //NO GPIO #bit 12 |
| 529 | NoGPIO(); |
| 530 | return; |
| 531 | |
| 532 | case 20: //NO GPIO #bit 11 |
| 533 | NoGPIO(); |
| 534 | return; |
| 535 | |
| 536 | case 21: //NO GPIO #bit 10 |
| 537 | NoGPIO(); |
| 538 | return; |
| 539 | |
| 540 | case 22: //P0.3 Fall #bit 9 //Indexer Top //Dio 2 |
| 541 | IndexerTopFall(); |
| 542 | return; |
| 543 | |
| 544 | case 23: //P0.4 Fall #bit 8 //Indexer Bottom //Dio 1 |
| 545 | IndexerBottomFall(); |
| 546 | return; |
| 547 | |
| 548 | case 24: //P0.7 Rise #bit 7 //Shooter Hall //Dio 4 |
| 549 | ShooterHallRise(); |
| 550 | return; |
| 551 | |
| 552 | case 25: //P0.6 Rise #bit 6 //Wrist Hall //Dio 3 |
| 553 | WristHallRise(); |
| 554 | return; |
| 555 | |
| 556 | case 26: //P0.5 Rise #bit 5 //Indexer Top //Dio 2 |
| 557 | IndexerTopRise(); |
| 558 | return; |
| 559 | |
| 560 | case 27: //P0.4 Rise #bit 4 //Indexer Bottom //Dio 1 |
| 561 | IndexerBottomRise(); |
| 562 | return; |
| 563 | |
| 564 | case 28: //P2.3 Rise #bit 3 //Encoder 5 B //Dio 10 |
| 565 | Encoder5BRise(); |
| 566 | return; |
| 567 | |
| 568 | case 29: //P2.2 Rise #bit 2 //Encoder 5 A //Dio 9 |
| 569 | Encoder5ARise(); |
| 570 | return; |
| 571 | |
| 572 | case 30: //P2.1 Rise #bit 1 //Encoder 4 B //Dio 8 |
| 573 | Encoder4BRise(); |
| 574 | return; |
| 575 | |
| 576 | case 31: //P2.0 Rise #bit 0 //Encoder 4 A //Dio 7 |
| 577 | Encoder4ARise(); |
| 578 | return; |
| 579 | |
| 580 | case 32: //NO BITS SET #False Alarm |
| 581 | NoGPIO(); |
| 582 | return; |
| 583 | } |
| 584 | */ |
| 585 | } |
| 586 | void EINT3_IRQHandler(void){ |
| 587 | NVIC_DisableIRQ(EINT3_IRQn); |
| 588 | IRQ_Dispatch(); |
| 589 | NVIC_EnableIRQ(EINT3_IRQn); |
| 590 | } |
| 591 | int32_t encoder_val(int chan) |
| 592 | { |
| 593 | int32_t val; |
| 594 | switch(chan){ |
| 595 | case 0: //Wrist |
| 596 | return (int32_t)QEI->QEIPOS; |
| 597 | case 1: //Shooter Wheel |
| 598 | NVIC_DisableIRQ(EINT1_IRQn); |
| 599 | NVIC_DisableIRQ(EINT2_IRQn); |
| 600 | val = encoder1_val; |
| 601 | NVIC_EnableIRQ(EINT2_IRQn); |
| 602 | NVIC_EnableIRQ(EINT1_IRQn); |
| 603 | return val; |
| 604 | case 2: //Shooter Angle |
| 605 | NVIC_DisableIRQ(EINT3_IRQn); |
| 606 | val = encoder2_val; |
| 607 | NVIC_EnableIRQ(EINT3_IRQn); |
| 608 | return val; |
| 609 | case 3: //Indexer |
| 610 | NVIC_DisableIRQ(EINT3_IRQn); |
| 611 | val = encoder3_val; |
| 612 | NVIC_EnableIRQ(EINT3_IRQn); |
| 613 | return val; |
| 614 | case 4: //Drive R |
| 615 | NVIC_DisableIRQ(EINT3_IRQn); |
| 616 | val = encoder4_val; |
| 617 | NVIC_EnableIRQ(EINT3_IRQn); |
| 618 | return val; |
| 619 | case 5: //Drive L |
| 620 | NVIC_DisableIRQ(EINT3_IRQn); |
| 621 | val = encoder5_val; |
| 622 | NVIC_EnableIRQ(EINT3_IRQn); |
| 623 | return val; |
| 624 | default: |
| 625 | return -1; |
| 626 | } |
| 627 | } |
| 628 | void fillSensorPacket(struct DataStruct *packet){ |
| 629 | packet->gyro_angle = gyro_angle; |
| 630 | NVIC_DisableIRQ(EINT1_IRQn); |
| 631 | NVIC_DisableIRQ(EINT2_IRQn); |
| 632 | packet->shooter = encoder1_val; |
| 633 | NVIC_EnableIRQ(EINT2_IRQn); |
| 634 | NVIC_EnableIRQ(EINT1_IRQn); |
| 635 | NVIC_DisableIRQ(EINT3_IRQn); |
| 636 | packet->right_drive = encoder4_val; |
| 637 | packet->left_drive = encoder5_val; |
| 638 | packet->shooter_angle = encoder2_val; |
| 639 | packet->indexer = encoder3_val; |
| 640 | packet->wrist = (int32_t)QEI->QEIPOS; |
| 641 | |
| 642 | packet->capture_top_rise = capture_top_rise; |
| 643 | packet->top_rise_count = top_rise_count; |
| 644 | |
| 645 | packet->capture_top_fall = capture_top_fall; |
| 646 | packet->top_fall_count = top_fall_count; |
| 647 | |
| 648 | packet->bottom_rise_count = bottom_rise_count; |
| 649 | |
| 650 | packet->capture_bottom_fall_delay = capture_bottom_fall_delay; |
| 651 | packet->bottom_fall_delay_count = bottom_fall_delay_count; |
| 652 | packet->bottom_fall_count = bottom_fall_count; |
| 653 | |
| 654 | packet->capture_wrist_rise = capture_wrist_rise; |
| 655 | packet->wrist_rise_count = wrist_rise_count; |
| 656 | |
| 657 | packet->capture_shooter_angle_rise = capture_shooter_angle_rise; |
| 658 | packet->shooter_angle_rise_count = shooter_angle_rise_count; |
| 659 | |
| 660 | NVIC_EnableIRQ(EINT3_IRQn); |
| 661 | } |
| 662 | |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 663 | void encoder_init(void) |
| 664 | { |
Austin Schuh | 63d0e9b | 2013-03-27 04:43:14 +0000 | [diff] [blame^] | 665 | // port 0 |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 666 | // Setup the encoder interface. |
| 667 | SC->PCONP |= PCONP_PCQEI; |
| 668 | PINCON->PINSEL3 = ((PINCON->PINSEL3 & 0xffff3dff) | 0x00004100); |
| 669 | |
| 670 | // Reset the count and velocity |
| 671 | QEI->QEICON = 0x00000005; |
| 672 | |
| 673 | QEI->QEICONF = 0x00000004; |
| 674 | // Wrap back to 0 when we wrap the int... |
| 675 | QEI->QEIMAXPOS = 0xffffffff; |
| 676 | // port 1 |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 677 | //PINSEL4 23/22 0 1 |
| 678 | //PINSEL4 25 24 0 1 |
| 679 | PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 22)) | (0x1 << 22); |
| 680 | PINCON->PINSEL4 = (PINCON->PINSEL4 & ~(0x3 << 24)) | (0x1 << 24); |
| 681 | |
| 682 | //EXTMODE 1 2 1 1 // all others off |
| 683 | SC->EXTMODE = 0x6; |
| 684 | SC->EXTINT = 0x6; |
Austin Schuh | 63d0e9b | 2013-03-27 04:43:14 +0000 | [diff] [blame^] | 685 | NVIC_EnableIRQ(EINT1_IRQn); |
| 686 | NVIC_EnableIRQ(EINT2_IRQn); |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 687 | encoder1_val = 0; |
Austin Schuh | 63d0e9b | 2013-03-27 04:43:14 +0000 | [diff] [blame^] | 688 | |
| 689 | //port 2 |
| 690 | |
| 691 | encoder2_val = 0; |
| 692 | GPIOINT->IO0IntEnF |= (1 << 22); // Set GPIO falling interrupt |
| 693 | GPIOINT->IO0IntEnR |= (1 << 22); // Set GPIO rising interrupt |
| 694 | GPIOINT->IO0IntEnF |= (1 << 21); // Set GPIO falling interrupt |
| 695 | GPIOINT->IO0IntEnR |= (1 << 21); // Set GPIO rising interrupt |
| 696 | PINCON->PINSEL1 &= ~(0x3 << 12); |
| 697 | PINCON->PINSEL1 &= ~(0x3 << 10); |
| 698 | |
| 699 | //port 3 |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 700 | |
Austin Schuh | 63d0e9b | 2013-03-27 04:43:14 +0000 | [diff] [blame^] | 701 | encoder3_val = 0; |
| 702 | GPIOINT->IO0IntEnF |= (1 << 20); // Set GPIO falling interrupt |
| 703 | GPIOINT->IO0IntEnR |= (1 << 20); // Set GPIO rising interrupt |
| 704 | GPIOINT->IO0IntEnF |= (1 << 19); // Set GPIO falling interrupt |
| 705 | GPIOINT->IO0IntEnR |= (1 << 19); // Set GPIO rising interrupt |
| 706 | PINCON->PINSEL1 &= ~(0x3 << 8); |
| 707 | PINCON->PINSEL1 &= ~(0x3 << 6); |
| 708 | |
| 709 | //port 4 |
| 710 | encoder4_val = 0; |
| 711 | GPIOINT->IO2IntEnF |= (1 << 0); // Set GPIO falling interrupt |
| 712 | GPIOINT->IO2IntEnR |= (1 << 0); // Set GPIO rising interrupt |
| 713 | GPIOINT->IO2IntEnF |= (1 << 1); // Set GPIO falling interrupt |
| 714 | GPIOINT->IO2IntEnR |= (1 << 1); // Set GPIO rising interrupt |
| 715 | PINCON->PINSEL4 &= ~(0x3 << 0); |
| 716 | PINCON->PINSEL4 &= ~(0x3 << 2); |
| 717 | |
| 718 | //port 5 |
| 719 | encoder5_val = 0; |
| 720 | GPIOINT->IO2IntEnF |= (1 << 2); // Set GPIO falling interrupt |
| 721 | GPIOINT->IO2IntEnR |= (1 << 2); // Set GPIO rising interrupt |
| 722 | GPIOINT->IO2IntEnF |= (1 << 3); // Set GPIO falling interrupt |
| 723 | GPIOINT->IO2IntEnR |= (1 << 3); // Set GPIO rising interrupt |
| 724 | PINCON->PINSEL4 &= ~(0x3 << 4); |
| 725 | PINCON->PINSEL4 &= ~(0x3 << 6); |
| 726 | |
| 727 | |
| 728 | //gpio pins: |
| 729 | NVIC_EnableIRQ(EINT3_IRQn); |
| 730 | |
| 731 | |
| 732 | // delay capture: |
| 733 | xTaskCreate(vDelayCapture, (signed char *) "SENSORs", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 5, NULL); |
| 734 | |
| 735 | |
| 736 | // other: |
| 737 | GPIOINT->IO0IntEnF |= (1 << 4); // Set GPIO falling interrupt |
| 738 | GPIOINT->IO0IntEnR |= (1 << 4); // Set GPIO rising interrupt |
| 739 | PINCON->PINSEL0 &= ~(0x3 << 8); |
| 740 | |
| 741 | GPIOINT->IO0IntEnF |= (1 << 5); // Set GPIO falling interrupt |
| 742 | GPIOINT->IO0IntEnR |= (1 << 5); // Set GPIO rising interrupt |
| 743 | PINCON->PINSEL0 &= ~(0x3 << 10); |
| 744 | |
| 745 | GPIOINT->IO0IntEnR |= (1 << 6); // Set GPIO rising interrupt |
| 746 | PINCON->PINSEL0 &= ~(0x3 << 12); |
| 747 | |
| 748 | GPIOINT->IO0IntEnR |= (1 << 7); // Set GPIO rising interrupt |
| 749 | PINCON->PINSEL0 &= ~(0x3 << 14); |
| 750 | |
brians | 0ab60bb | 2013-01-31 02:21:51 +0000 | [diff] [blame] | 751 | |
| 752 | } |