| Austin Schuh | 41baf20 | 2022-01-01 14:33:40 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * The MIT License (MIT) |
| 3 | * |
| 4 | * Copyright (c) 2020, Ha Thach (tinyusb.org) |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | * |
| 24 | * This file is part of the TinyUSB stack. |
| 25 | */ |
| 26 | |
| 27 | #ifndef BOARD_H_ |
| 28 | #define BOARD_H_ |
| 29 | |
| 30 | #ifdef __cplusplus |
| 31 | extern "C" { |
| 32 | #endif |
| 33 | |
| 34 | #define LED_PORT GPIOB |
| 35 | #define LED_PIN GPIO_PIN_14 |
| 36 | #define LED_STATE_ON 1 |
| 37 | |
| 38 | #define BUTTON_PORT GPIOC |
| 39 | #define BUTTON_PIN GPIO_PIN_13 |
| 40 | #define BUTTON_STATE_ACTIVE 1 |
| 41 | |
| 42 | #define UART_DEV LPUART1 |
| 43 | #define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE |
| 44 | #define UART_GPIO_PORT GPIOG |
| 45 | #define UART_GPIO_AF GPIO_AF8_LPUART1 |
| 46 | #define UART_TX_PIN GPIO_PIN_7 |
| 47 | #define UART_RX_PIN GPIO_PIN_8 |
| 48 | |
| 49 | //--------------------------------------------------------------------+ |
| 50 | // RCC Clock |
| 51 | //--------------------------------------------------------------------+ |
| 52 | |
| 53 | /** |
| 54 | * @brief System Clock Configuration |
| 55 | * The system Clock is configured as follow : |
| 56 | * System Clock source = PLL (MSI) |
| 57 | * SYSCLK(Hz) = 120000000 |
| 58 | * HCLK(Hz) = 120000000 |
| 59 | * AHB Prescaler = 1 |
| 60 | * APB1 Prescaler = 1 |
| 61 | * APB2 Prescaler = 1 |
| 62 | * MSI Frequency(Hz) = 48000000 |
| 63 | * PLL_M = 12 |
| 64 | * PLL_N = 60 |
| 65 | * PLL_P = 2 |
| 66 | * PLL_Q = 2 |
| 67 | * VDD(V) = 3.3 |
| 68 | * Main regulator output voltage = Scale1 mode |
| 69 | * Flash Latency(WS) = 5 |
| 70 | * The USB clock configuration from PLLSAI: |
| 71 | * PLLSAIP = 8 FIXME |
| 72 | * PLLSAIN = 384 FIXME |
| 73 | * PLLSAIQ = 7 FIXME |
| 74 | * @param None |
| 75 | * @retval None |
| 76 | */ |
| 77 | |
| 78 | static inline void board_clock_init(void) |
| 79 | { |
| 80 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| 81 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| 82 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; |
| 83 | |
| 84 | /* Activate PLL with MSI , stabilizied via PLL by LSE */ |
| 85 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; |
| 86 | RCC_OscInitStruct.MSIState = RCC_MSI_ON; |
| 87 | RCC_OscInitStruct.LSEState = RCC_LSE_ON; |
| 88 | RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; |
| 89 | RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; |
| 90 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 91 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; |
| 92 | RCC_OscInitStruct.PLL.PLLM = 12; |
| 93 | RCC_OscInitStruct.PLL.PLLN = 60; |
| 94 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
| 95 | RCC_OscInitStruct.PLL.PLLQ = 2; |
| 96 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
| 97 | |
| 98 | /* Enable MSI Auto-calibration through LSE */ |
| 99 | HAL_RCCEx_EnableMSIPLLMode(); |
| 100 | |
| 101 | /* Select MSI output as USB clock source */ |
| 102 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; |
| 103 | PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; |
| 104 | HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
| 105 | |
| 106 | /* Select MSI output as USB clock source */ |
| 107 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
| 108 | PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; |
| 109 | HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
| 110 | |
| 111 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 |
| 112 | clocks dividers */ |
| 113 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| 114 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 115 | // Avoid overshoot and start with HCLK 60 MHz |
| 116 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; |
| 117 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; |
| 118 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
| 119 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); |
| 120 | |
| 121 | /* AHB prescaler divider at 1 as second step */ |
| 122 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; |
| 123 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| 124 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); |
| 125 | } |
| 126 | |
| 127 | static inline void board_vbus_sense_init(void) |
| 128 | { |
| 129 | // Enable VBUS sense (B device) via pin PA9 |
| 130 | USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; |
| 131 | } |
| 132 | |
| 133 | #ifdef __cplusplus |
| 134 | } |
| 135 | #endif |
| 136 | |
| 137 | #endif /* BOARD_H_ */ |