| Brian Silverman | 8d3816a | 2017-07-03 18:52:15 -0700 | [diff] [blame] | 1 | #ifndef MOTORS_PERIPHERAL_CONFIGURATION_H_ |
| 2 | #define MOTORS_PERIPHERAL_CONFIGURATION_H_ |
| 3 | |
| 4 | // We're just going to leave the default DMA priorities which correspond to the |
| 5 | // channel numbers and fixed priority mode, so channel 0 is the lowest priority |
| 6 | // and 15 is the highest. |
| 7 | // We're also going to leave DMA_CR alone except for setting EMLM. |
| 8 | |
| 9 | // The frequency of the peripheral bus(es) in hz. |
| 10 | #define BUS_CLOCK_FREQUENCY (F_CPU / 2) |
| 11 | |
| 12 | // The frequency we switch the motor FETs at in hz. |
| 13 | #define SWITCHING_FREQUENCY 20000 |
| 14 | |
| Brian Silverman | cabadaf | 2018-09-03 19:36:44 -0700 | [diff] [blame] | 15 | // The DMA channels which copy ADC results. |
| 16 | #define ADC_RESULT_DMA_CHANNEL0 7 |
| 17 | #define ADC_RESULT_DMA_CHANNEL1 8 |
| 18 | // The DMA channels which reconfigure the ADCs to take the next samples. |
| 19 | #define ADC_RECONFIGURE_DMA_CHANNEL0 9 |
| 20 | #define ADC_RECONFIGURE_DMA_CHANNEL1 10 |
| 21 | // The DMA channel which reads encoder values. |
| 22 | #define ENCODER_VALUE_DMA_CHANNEL 11 |
| Brian Silverman | 8d3816a | 2017-07-03 18:52:15 -0700 | [diff] [blame] | 23 | |
| 24 | #endif // MOTORS_PERIPHERAL_CONFIGURATION_H_ |