blob: ba48e87b11cb585c47c697c5a1e1492116946f43 [file] [log] [blame]
Austin Schuh208337d2022-01-01 14:29:11 -08001/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include "hardware/address_mapped.h"
8#include "hardware/platform_defs.h"
9#include "hardware/uart.h"
10
11#include "hardware/structs/uart.h"
12#include "hardware/resets.h"
13#include "hardware/clocks.h"
14#include "hardware/timer.h"
15
16#include "pico/assert.h"
17#include "pico.h"
18
19check_hw_layout(uart_hw_t, fr, UART_UARTFR_OFFSET);
20check_hw_layout(uart_hw_t, dmacr, UART_UARTDMACR_OFFSET);
21
22#if PICO_UART_ENABLE_CRLF_SUPPORT
23short uart_char_to_line_feed[NUM_UARTS];
24#endif
25
26/// \tag::uart_reset[]
27static inline void uart_reset(uart_inst_t *uart) {
28 invalid_params_if(UART, uart != uart0 && uart != uart1);
29 reset_block(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS);
30}
31
32static inline void uart_unreset(uart_inst_t *uart) {
33 invalid_params_if(UART, uart != uart0 && uart != uart1);
34 unreset_block_wait(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS);
35}
36/// \end::uart_reset[]
37
38/// \tag::uart_init[]
39uint uart_init(uart_inst_t *uart, uint baudrate) {
40 invalid_params_if(UART, uart != uart0 && uart != uart1);
41
42 if (clock_get_hz(clk_peri) == 0)
43 return 0;
44
45 uart_reset(uart);
46 uart_unreset(uart);
47
48#if PICO_UART_ENABLE_CRLF_SUPPORT
49 uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF);
50#endif
51
52 // Any LCR writes need to take place before enabling the UART
53 uint baud = uart_set_baudrate(uart, baudrate);
54 uart_set_format(uart, 8, 1, UART_PARITY_NONE);
55
56 // Enable the UART, both TX and RX
57 uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS;
58 // Enable FIFOs
59 hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS);
60 // Always enable DREQ signals -- no harm in this if DMA is not listening
61 uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS;
62
63 return baud;
64}
65/// \end::uart_init[]
66
67void uart_deinit(uart_inst_t *uart) {
68 invalid_params_if(UART, uart != uart0 && uart != uart1);
69 uart_reset(uart);
70}
71
72/// \tag::uart_set_baudrate[]
73uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) {
74 invalid_params_if(UART, baudrate == 0);
75 uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate);
76 uint32_t baud_ibrd = baud_rate_div >> 7;
77 uint32_t baud_fbrd;
78
79 if (baud_ibrd == 0) {
80 baud_ibrd = 1;
81 baud_fbrd = 0;
82 } else if (baud_ibrd >= 65535) {
83 baud_ibrd = 65535;
84 baud_fbrd = 0;
85 } else {
86 baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
87 }
88
89 // Load PL011's baud divisor registers
90 uart_get_hw(uart)->ibrd = baud_ibrd;
91 uart_get_hw(uart)->fbrd = baud_fbrd;
92
93 // PL011 needs a (dummy) line control register write to latch in the
94 // divisors. We don't want to actually change LCR contents here.
95 hw_set_bits(&uart_get_hw(uart)->lcr_h, 0);
96
97 // See datasheet
98 return (4 * clock_get_hz(clk_peri)) / (64 * baud_ibrd + baud_fbrd);
99}
100/// \end::uart_set_baudrate[]
101
102void uart_set_translate_crlf(uart_inst_t *uart, bool crlf) {
103#if PICO_UART_ENABLE_CRLF_SUPPORT
104 uart_char_to_line_feed[uart_get_index(uart)] = crlf ? '\n' : 0x100;
105#else
106 panic_unsupported();
107#endif
108}
109
110bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us) {
111 uint32_t t = time_us_32();
112 do {
113 if (uart_is_readable(uart)) return true;
114 } while ((time_us_32() - t) <= us);
115 return false;
116}