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realtimeroboticsgroup.org / RealtimeRoboticsGroup / test / 0ab60bb01508249fd798c872f872aeb891be714c / . / gyro_board / src / usb / LPC17xx.h
blob: 1743027e0c6aad76b619b08d6f1b5a7cbee4363e [file] [log] [blame]
brians0ab60bb2013-01-31 02:21:51 +0000[diff] [blame^]1#ifndef __LPC17xx_H
2#define __LPC17xx_H
3
4/* System Control Block (SCB) includes:
5 Flash Accelerator Module, Clocking and Power Control, External Interrupts,
6 Reset, System Control and Status
7*/
8#define SCB_BASE_ADDR 0x400FC000
9
10#define PCONP_PCTIM0 0x00000002
11#define PCONP_PCTIM1 0x00000004
12#define PCONP_PCUART0 0x00000008
13#define PCONP_PCUART1 0x00000010
14#define PCONP_PCPWM1 0x00000040
15#define PCONP_PCI2C0 0x00000080
16#define PCONP_PCSPI 0x00000100
17#define PCONP_PCRTC 0x00000200
18#define PCONP_PCSSP1 0x00000400
19#define PCONP_PCAD 0x00001000
20#define PCONP_PCCAN1 0x00002000
21#define PCONP_PCCAN2 0x00004000
22#define PCONP_PCGPIO 0x00008000
23#define PCONP_PCRIT 0x00010000
24#define PCONP_PCMCPWM 0x00020000
25#define PCONP_PCQEI 0x00040000
26#define PCONP_PCI2C1 0x00080000
27#define PCONP_PCSSP0 0x00200000
28#define PCONP_PCTIM2 0x00400000
29#define PCONP_PCTIM3 0x00800000
30#define PCONP_PCUART2 0x01000000
31#define PCONP_PCUART3 0x02000000
32#define PCONP_PCI2C2 0x04000000
33#define PCONP_PCI2S 0x08000000
34#define PCONP_PCGPDMA 0x20000000
35#define PCONP_PCENET 0x40000000
36#define PCONP_PCUSB 0x80000000
37
38#define PLLCON_PLLE 0x00000001
39#define PLLCON_PLLC 0x00000002
40#define PLLCON_MASK 0x00000003
41
42#define PLLCFG_MUL1 0x00000000
43#define PLLCFG_MUL2 0x00000001
44#define PLLCFG_MUL3 0x00000002
45#define PLLCFG_MUL4 0x00000003
46#define PLLCFG_MUL5 0x00000004
47#define PLLCFG_MUL6 0x00000005
48#define PLLCFG_MUL7 0x00000006
49#define PLLCFG_MUL8 0x00000007
50#define PLLCFG_MUL9 0x00000008
51#define PLLCFG_MUL10 0x00000009
52#define PLLCFG_MUL11 0x0000000A
53#define PLLCFG_MUL12 0x0000000B
54#define PLLCFG_MUL13 0x0000000C
55#define PLLCFG_MUL14 0x0000000D
56#define PLLCFG_MUL15 0x0000000E
57#define PLLCFG_MUL16 0x0000000F
58#define PLLCFG_MUL17 0x00000010
59#define PLLCFG_MUL18 0x00000011
60#define PLLCFG_MUL19 0x00000012
61#define PLLCFG_MUL20 0x00000013
62#define PLLCFG_MUL21 0x00000014
63#define PLLCFG_MUL22 0x00000015
64#define PLLCFG_MUL23 0x00000016
65#define PLLCFG_MUL24 0x00000017
66#define PLLCFG_MUL25 0x00000018
67#define PLLCFG_MUL26 0x00000019
68#define PLLCFG_MUL27 0x0000001A
69#define PLLCFG_MUL28 0x0000001B
70#define PLLCFG_MUL29 0x0000001C
71#define PLLCFG_MUL30 0x0000001D
72#define PLLCFG_MUL31 0x0000001E
73#define PLLCFG_MUL32 0x0000001F
74#define PLLCFG_MUL33 0x00000020
75#define PLLCFG_MUL34 0x00000021
76#define PLLCFG_MUL35 0x00000022
77#define PLLCFG_MUL36 0x00000023
78
79#define PLLCFG_DIV1 0x00000000
80#define PLLCFG_DIV2 0x00010000
81#define PLLCFG_DIV3 0x00020000
82#define PLLCFG_DIV4 0x00030000
83#define PLLCFG_DIV5 0x00040000
84#define PLLCFG_DIV6 0x00050000
85#define PLLCFG_DIV7 0x00060000
86#define PLLCFG_DIV8 0x00070000
87#define PLLCFG_DIV9 0x00080000
88#define PLLCFG_DIV10 0x00090000
89#define PLLCFG_MASK 0x00FF7FFF
90
91#define PLLSTAT_MSEL_MASK 0x00007FFF
92#define PLLSTAT_NSEL_MASK 0x00FF0000
93
94#define PLLSTAT_PLLE (1 << 24)
95#define PLLSTAT_PLLC (1 << 25)
96#define PLLSTAT_PLOCK (1 << 26)
97
98#define PLLFEED_FEED1 0x000000AA
99#define PLLFEED_FEED2 0x00000055
100
101#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16
102#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17
103#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18
104#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19
105#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20
106#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21
107#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22
108#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23
109#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24
110#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25
111#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26
112#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27
113#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28
114#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29
115#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30
116#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31
117#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32
118#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33
119#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34
120#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35
121#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36
122#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37
123#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38
124#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39
125#define NVIC_IRQ_USB 24u // IRQ24, exception number 40
126#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41
127#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42
128#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43
129#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44
130#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45
131#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46
132#define NVIC_IRQ_QE 31u // IRQ31, exception number 47
133#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48
134#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49
135#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50
136
137
138#endif // __LPC17xx_H
139
140
141#ifndef CMSIS_17xx_H
142#define CMSIS_17xx_H
143
144/******************************************************************************
145 * @file: LPC17xx.h
146 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
147 * NXP LPC17xx Device Series
148 * @version: V1.1
149 * @date: 14th May 2009
150 *----------------------------------------------------------------------------
151 *
152 * Copyright (C) 2008 ARM Limited. All rights reserved.
153 *
154 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
155 * processor based microcontrollers. This file can be freely distributed
156 * within development tools that are supporting such ARM based processors.
157 *
158 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
159 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
160 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
161 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
162 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
163 *
164 ******************************************************************************/
165
166
167#ifndef __LPC17xx_H__
168#define __LPC17xx_H__
169
170/*
171 * ==========================================================================
172 * ---------- Interrupt Number Definition -----------------------------------
173 * ==========================================================================
174 */
175
176typedef enum IRQn {
177 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
178 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
179 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
180 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
181 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
182 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
183 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
184 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
185 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
186
187 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
188 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
189 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
190 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
191 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
192 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
193 UART0_IRQn = 5, /*!< UART0 Interrupt */
194 UART1_IRQn = 6, /*!< UART1 Interrupt */
195 UART2_IRQn = 7, /*!< UART2 Interrupt */
196 UART3_IRQn = 8, /*!< UART3 Interrupt */
197 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
198 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
199 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
200 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
201 SPI_IRQn = 13, /*!< SPI Interrupt */
202 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
203 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
204 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
205 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
206 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
207 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
208 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
209 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
210 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
211 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
212 USB_IRQn = 24, /*!< USB Interrupt */
213 CAN_IRQn = 25, /*!< CAN Interrupt */
214 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
215 I2S_IRQn = 27, /*!< I2S Interrupt */
216 ENET_IRQn = 28, /*!< Ethernet Interrupt */
217 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
218 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
219 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
220 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
221} IRQn_Type;
222
223
224/*
225 * ==========================================================================
226 * ----------- Processor and Core Peripheral Section ------------------------
227 * ==========================================================================
228 */
229
230/* Configuration of the Cortex-M3 Processor and Core Peripherals */
231#define __MPU_PRESENT 1 /*!< MPU present or not */
232#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
233#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
234
235
236//#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */
237#include "core_cm3.h"
238#include "system_LPC17xx.h" /* System Header */
239
240
241
242/**
243 * Initialize the system clock
244 *
245 * @param none
246 * @return none
247 *
248 * @brief Setup the microcontroller system.
249 * Initialize the System and update the SystemFrequency variable.
250 */
251extern void SystemInit(void);
252
253
254/******************************************************************************/
255/* Device Specific Peripheral registers structures */
256/******************************************************************************/
257
258/*------------- System Control (SC) ------------------------------------------*/
259typedef struct {
260 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
261 uint32_t RESERVED0[31];
262 __IO uint32_t PLL0CON; /* Clocking and Power Control */
263 __IO uint32_t PLL0CFG;
264 __I uint32_t PLL0STAT;
265 __O uint32_t PLL0FEED;
266 uint32_t RESERVED1[4];
267 __IO uint32_t PLL1CON;
268 __IO uint32_t PLL1CFG;
269 __I uint32_t PLL1STAT;
270 __O uint32_t PLL1FEED;
271 uint32_t RESERVED2[4];
272 __IO uint32_t PCON;
273 __IO uint32_t PCONP;
274 uint32_t RESERVED3[15];
275 __IO uint32_t CCLKCFG;
276 __IO uint32_t USBCLKCFG;
277 __IO uint32_t CLKSRCSEL;
278 uint32_t RESERVED4[12];
279 __IO uint32_t EXTINT; /* External Interrupts */
280 uint32_t RESERVED5;
281 __IO uint32_t EXTMODE;
282 __IO uint32_t EXTPOLAR;
283 uint32_t RESERVED6[12];
284 __IO uint32_t RSID; /* Reset */
285 uint32_t RESERVED7[7];
286 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
287 __IO uint32_t IRCTRIM; /* Clock Dividers */
288 __IO uint32_t PCLKSEL0;
289 __IO uint32_t PCLKSEL1;
290 uint32_t RESERVED8[4];
291 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
292 uint32_t RESERVED9;
293 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
294} SC_TypeDef;
295
296/*------------- Pin Connect Block (PINCON) -----------------------------------*/
297typedef struct {
298 __IO uint32_t PINSEL0;
299 __IO uint32_t PINSEL1;
300 __IO uint32_t PINSEL2;
301 __IO uint32_t PINSEL3;
302 __IO uint32_t PINSEL4;
303 __IO uint32_t PINSEL5;
304 __IO uint32_t PINSEL6;
305 __IO uint32_t PINSEL7;
306 __IO uint32_t PINSEL8;
307 __IO uint32_t PINSEL9;
308 __IO uint32_t PINSEL10;
309 uint32_t RESERVED0[5];
310 __IO uint32_t PINMODE0;
311 __IO uint32_t PINMODE1;
312 __IO uint32_t PINMODE2;
313 __IO uint32_t PINMODE3;
314 __IO uint32_t PINMODE4;
315 __IO uint32_t PINMODE5;
316 __IO uint32_t PINMODE6;
317 __IO uint32_t PINMODE7;
318 __IO uint32_t PINMODE8;
319 __IO uint32_t PINMODE9;
320 __IO uint32_t PINMODE_OD0;
321 __IO uint32_t PINMODE_OD1;
322 __IO uint32_t PINMODE_OD2;
323 __IO uint32_t PINMODE_OD3;
324 __IO uint32_t PINMODE_OD4;
325} PINCON_TypeDef;
326
327/*------------- General Purpose Input/Output (GPIO) --------------------------*/
328typedef struct {
329 __IO uint32_t FIODIR;
330 uint32_t RESERVED0[3];
331 __IO uint32_t FIOMASK;
332 __IO uint32_t FIOPIN;
333 __IO uint32_t FIOSET;
334 __O uint32_t FIOCLR;
335} GPIO_TypeDef;
336
337typedef struct {
338 __I uint32_t IntStatus;
339 __I uint32_t IO0IntStatR;
340 __I uint32_t IO0IntStatF;
341 __O uint32_t IO0IntClr;
342 __IO uint32_t IO0IntEnR;
343 __IO uint32_t IO0IntEnF;
344 uint32_t RESERVED0[3];
345 __I uint32_t IO2IntStatR;
346 __I uint32_t IO2IntStatF;
347 __O uint32_t IO2IntClr;
348 __IO uint32_t IO2IntEnR;
349 __IO uint32_t IO2IntEnF;
350} GPIOINT_TypeDef;
351
352/*------------- Timer (TIM) --------------------------------------------------*/
353typedef struct {
354 __IO uint32_t IR;
355 __IO uint32_t TCR;
356 __IO uint32_t TC;
357 __IO uint32_t PR;
358 __IO uint32_t PC;
359 __IO uint32_t MCR;
360 __IO uint32_t MR0;
361 __IO uint32_t MR1;
362 __IO uint32_t MR2;
363 __IO uint32_t MR3;
364 __IO uint32_t CCR;
365 __I uint32_t CR0;
366 __I uint32_t CR1;
367 uint32_t RESERVED0[2];
368 __IO uint32_t EMR;
369 uint32_t RESERVED1[24];
370 __IO uint32_t CTCR;
371} TIM_TypeDef;
372
373/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
374typedef struct {
375 __IO uint32_t IR;
376 __IO uint32_t TCR;
377 __IO uint32_t TC;
378 __IO uint32_t PR;
379 __IO uint32_t PC;
380 __IO uint32_t MCR;
381 __IO uint32_t MR0;
382 __IO uint32_t MR1;
383 __IO uint32_t MR2;
384 __IO uint32_t MR3;
385 __IO uint32_t CCR;
386 __I uint32_t CR0;
387 __I uint32_t CR1;
388 __I uint32_t CR2;
389 __I uint32_t CR3;
390 __IO uint32_t MR4;
391 __IO uint32_t MR5;
392 __IO uint32_t MR6;
393 __IO uint32_t PCR;
394 __IO uint32_t LER;
395 uint32_t RESERVED0[7];
396 __IO uint32_t CTCR;
397} PWM_TypeDef;
398
399/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
400typedef struct {
401 union {
402 __I uint8_t RBR;
403 __O uint8_t THR;
404 __IO uint8_t DLL;
405 uint32_t RESERVED0;
406 };
407 union {
408 __IO uint8_t DLM;
409 __IO uint32_t IER;
410 };
411 union {
412 __I uint32_t IIR;
413 __O uint8_t FCR;
414 };
415 __IO uint8_t LCR;
416 uint8_t RESERVED1[7];
417 __IO uint8_t LSR;
418 uint8_t RESERVED2[7];
419 __IO uint8_t SCR;
420 uint8_t RESERVED3[3];
421 __IO uint32_t ACR;
422 __IO uint8_t ICR;
423 uint8_t RESERVED4[3];
424 __IO uint8_t FDR;
425 uint8_t RESERVED5[7];
426 __IO uint8_t TER;
427 uint8_t RESERVED6[27];
428 __IO uint8_t RS485CTRL;
429 uint8_t RESERVED7[3];
430 __IO uint8_t ADRMATCH;
431} UART_TypeDef;
432
433typedef struct {
434 union {
435 __I uint8_t RBR;
436 __O uint8_t THR;
437 __IO uint8_t DLL;
438 uint32_t RESERVED0;
439 };
440 union {
441 __IO uint8_t DLM;
442 __IO uint32_t IER;
443 };
444 union {
445 __I uint32_t IIR;
446 __O uint8_t FCR;
447 };
448 __IO uint8_t LCR;
449 uint8_t RESERVED1[3];
450 __IO uint8_t MCR;
451 uint8_t RESERVED2[3];
452 __IO uint8_t LSR;
453 uint8_t RESERVED3[3];
454 __IO uint8_t MSR;
455 uint8_t RESERVED4[3];
456 __IO uint8_t SCR;
457 uint8_t RESERVED5[3];
458 __IO uint32_t ACR;
459 uint32_t RESERVED6;
460 __IO uint32_t FDR;
461 uint32_t RESERVED7;
462 __IO uint8_t TER;
463 uint8_t RESERVED8[27];
464 __IO uint8_t RS485CTRL;
465 uint8_t RESERVED9[3];
466 __IO uint8_t ADRMATCH;
467 uint8_t RESERVED10[3];
468 __IO uint8_t RS485DLY;
469} UART1_TypeDef;
470
471/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
472typedef struct {
473 __IO uint32_t SPCR;
474 __I uint32_t SPSR;
475 __IO uint32_t SPDR;
476 __IO uint32_t SPCCR;
477 uint32_t RESERVED0[3];
478 __IO uint32_t SPINT;
479} SPI_TypeDef;
480
481/*------------- Synchronous Serial Communication (SSP) -----------------------*/
482typedef struct {
483 __IO uint32_t CR0;
484 __IO uint32_t CR1;
485 __IO uint32_t DR;
486 __I uint32_t SR;
487 __IO uint32_t CPSR;
488 __IO uint32_t IMSC;
489 __IO uint32_t RIS;
490 __IO uint32_t MIS;
491 __IO uint32_t ICR;
492 __IO uint32_t DMACR;
493} SSP_TypeDef;
494
495/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
496typedef struct {
497 __IO uint32_t I2CONSET;
498 __I uint32_t I2STAT;
499 __IO uint32_t I2DAT;
500 __IO uint32_t I2ADR0;
501 __IO uint32_t I2SCLH;
502 __IO uint32_t I2SCLL;
503 __O uint32_t I2CONCLR;
504 __IO uint32_t MMCTRL;
505 __IO uint32_t I2ADR1;
506 __IO uint32_t I2ADR2;
507 __IO uint32_t I2ADR3;
508 __I uint32_t I2DATA_BUFFER;
509 __IO uint32_t I2MASK0;
510 __IO uint32_t I2MASK1;
511 __IO uint32_t I2MASK2;
512 __IO uint32_t I2MASK3;
513} I2C_TypeDef;
514
515/*------------- Inter IC Sound (I2S) -----------------------------------------*/
516typedef struct {
517 __IO uint32_t I2SDAO;
518 __IO uint32_t I2SDAI;
519 __O uint32_t I2STXFIFO;
520 __I uint32_t I2SRXFIFO;
521 __I uint32_t I2SSTATE;
522 __IO uint32_t I2SDMA1;
523 __IO uint32_t I2SDMA2;
524 __IO uint32_t I2SIRQ;
525 __IO uint32_t I2STXRATE;
526 __IO uint32_t I2SRXRATE;
527 __IO uint32_t I2STXBITRATE;
528 __IO uint32_t I2SRXBITRATE;
529 __IO uint32_t I2STXMODE;
530 __IO uint32_t I2SRXMODE;
531} I2S_TypeDef;
532
533/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
534typedef struct {
535 __IO uint32_t RICOMPVAL;
536 __IO uint32_t RIMASK;
537 __IO uint8_t RICTRL;
538 uint8_t RESERVED0[3];
539 __IO uint32_t RICOUNTER;
540} RIT_TypeDef;
541
542/*------------- Real-Time Clock (RTC) ----------------------------------------*/
543typedef struct {
544 __IO uint8_t ILR;
545 uint8_t RESERVED0[3];
546 __IO uint8_t CCR;
547 uint8_t RESERVED1[3];
548 __IO uint8_t CIIR;
549 uint8_t RESERVED2[3];
550 __IO uint8_t AMR;
551 uint8_t RESERVED3[3];
552 __I uint32_t CTIME0;
553 __I uint32_t CTIME1;
554 __I uint32_t CTIME2;
555 __IO uint8_t SEC;
556 uint8_t RESERVED4[3];
557 __IO uint8_t MIN;
558 uint8_t RESERVED5[3];
559 __IO uint8_t HOUR;
560 uint8_t RESERVED6[3];
561 __IO uint8_t DOM;
562 uint8_t RESERVED7[3];
563 __IO uint8_t DOW;
564 uint8_t RESERVED8[3];
565 __IO uint16_t DOY;
566 uint16_t RESERVED9;
567 __IO uint8_t MONTH;
568 uint8_t RESERVED10[3];
569 __IO uint16_t YEAR;
570 uint16_t RESERVED11;
571 __IO uint32_t CALIBRATION;
572 __IO uint32_t GPREG0;
573 __IO uint32_t GPREG1;
574 __IO uint32_t GPREG2;
575 __IO uint32_t GPREG3;
576 __IO uint32_t GPREG4;
577 __IO uint8_t WAKEUPDIS;
578 uint8_t RESERVED12[3];
579 __IO uint8_t PWRCTRL;
580 uint8_t RESERVED13[3];
581 __IO uint8_t ALSEC;
582 uint8_t RESERVED14[3];
583 __IO uint8_t ALMIN;
584 uint8_t RESERVED15[3];
585 __IO uint8_t ALHOUR;
586 uint8_t RESERVED16[3];
587 __IO uint8_t ALDOM;
588 uint8_t RESERVED17[3];
589 __IO uint8_t ALDOW;
590 uint8_t RESERVED18[3];
591 __IO uint16_t ALDOY;
592 uint16_t RESERVED19;
593 __IO uint8_t ALMON;
594 uint8_t RESERVED20[3];
595 __IO uint16_t ALYEAR;
596 uint16_t RESERVED21;
597} RTC_TypeDef;
598
599/*------------- Watchdog Timer (WDT) -----------------------------------------*/
600typedef struct {
601 __IO uint8_t WDMOD;
602 uint8_t RESERVED0[3];
603 __IO uint32_t WDTC;
604 __O uint8_t WDFEED;
605 uint8_t RESERVED1[3];
606 __I uint32_t WDTV;
607 __IO uint32_t WDCLKSEL;
608} WDT_TypeDef;
609
610/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
611typedef struct {
612 __IO uint32_t ADCR;
613 __IO uint32_t ADGDR;
614 uint32_t RESERVED0;
615 __IO uint32_t ADINTEN;
616 __I uint32_t ADDR0;
617 __I uint32_t ADDR1;
618 __I uint32_t ADDR2;
619 __I uint32_t ADDR3;
620 __I uint32_t ADDR4;
621 __I uint32_t ADDR5;
622 __I uint32_t ADDR6;
623 __I uint32_t ADDR7;
624 __I uint32_t ADSTAT;
625 __IO uint32_t ADTRM;
626} ADC_TypeDef;
627
628/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
629typedef struct {
630 __IO uint32_t DACR;
631 __IO uint32_t DACCTRL;
632 __IO uint16_t DACCNTVAL;
633} DAC_TypeDef;
634
635/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
636typedef struct {
637 __I uint32_t MCCON;
638 __O uint32_t MCCON_SET;
639 __O uint32_t MCCON_CLR;
640 __I uint32_t MCCAPCON;
641 __O uint32_t MCCAPCON_SET;
642 __O uint32_t MCCAPCON_CLR;
643 __IO uint32_t MCTC0;
644 __IO uint32_t MCTC1;
645 __IO uint32_t MCTC2;
646 __IO uint32_t MCLIM0;
647 __IO uint32_t MCLIM1;
648 __IO uint32_t MCLIM2;
649 __IO uint32_t MCMAT0;
650 __IO uint32_t MCMAT1;
651 __IO uint32_t MCMAT2;
652 __IO uint32_t MCDEADTIME;
653 __IO uint32_t MCCP;
654 __IO uint32_t MCCR0;
655 __IO uint32_t MCCR1;
656 __IO uint32_t MCCR2;
657 __I uint32_t MCINTEN;
658 __O uint32_t MCINTEN_SET;
659 __O uint32_t MCINTEN_CLR;
660 __I uint32_t MCCNTCON;
661 __O uint32_t MCCNTCON_SET;
662 __O uint32_t MCCNTCON_CLR;
663 __I uint32_t MCINTFLAG;
664 __O uint32_t MCINTFLAG_SET;
665 __O uint32_t MCINTFLAG_CLR;
666 __O uint32_t MCCAP_CLR;
667} MCPWM_TypeDef;
668
669/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
670typedef struct {
671 __O uint32_t QEICON;
672 __I uint32_t QEISTAT;
673 __IO uint32_t QEICONF;
674 __I uint32_t QEIPOS;
675 __IO uint32_t QEIMAXPOS;
676 __IO uint32_t CMPOS0;
677 __IO uint32_t CMPOS1;
678 __IO uint32_t CMPOS2;
679 __I uint32_t INXCNT;
680 __IO uint32_t INXCMP;
681 __IO uint32_t QEILOAD;
682 __I uint32_t QEITIME;
683 __I uint32_t QEIVEL;
684 __I uint32_t QEICAP;
685 __IO uint32_t VELCOMP;
686 __IO uint32_t FILTER;
687 uint32_t RESERVED0[998];
688 __O uint32_t QEIIEC;
689 __O uint32_t QEIIES;
690 __I uint32_t QEIINTSTAT;
691 __I uint32_t QEIIE;
692 __O uint32_t QEICLR;
693 __O uint32_t QEISET;
694} QEI_TypeDef;
695
696/*------------- Controller Area Network (CAN) --------------------------------*/
697typedef struct {
698 __IO uint32_t mask[512]; /* ID Masks */
699} CANAF_RAM_TypeDef;
700
701typedef struct { /* Acceptance Filter Registers */
702 __IO uint32_t AFMR;
703 __IO uint32_t SFF_sa;
704 __IO uint32_t SFF_GRP_sa;
705 __IO uint32_t EFF_sa;
706 __IO uint32_t EFF_GRP_sa;
707 __IO uint32_t ENDofTable;
708 __I uint32_t LUTerrAd;
709 __I uint32_t LUTerr;
710} CANAF_TypeDef;
711
712typedef struct { /* Central Registers */
713 __I uint32_t CANTxSR;
714 __I uint32_t CANRxSR;
715 __I uint32_t CANMSR;
716} CANCR_TypeDef;
717
718typedef struct { /* Controller Registers */
719 __IO uint32_t MOD;
720 __O uint32_t CMR;
721 __IO uint32_t GSR;
722 __I uint32_t ICR;
723 __IO uint32_t IER;
724 __IO uint32_t BTR;
725 __IO uint32_t EWL;
726 __I uint32_t SR;
727 __IO uint32_t RFS;
728 __IO uint32_t RID;
729 __IO uint32_t RDA;
730 __IO uint32_t RDB;
731 __IO uint32_t TFI1;
732 __IO uint32_t TID1;
733 __IO uint32_t TDA1;
734 __IO uint32_t TDB1;
735 __IO uint32_t TFI2;
736 __IO uint32_t TID2;
737 __IO uint32_t TDA2;
738 __IO uint32_t TDB2;
739 __IO uint32_t TFI3;
740 __IO uint32_t TID3;
741 __IO uint32_t TDA3;
742 __IO uint32_t TDB3;
743} CAN_TypeDef;
744
745/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
746typedef struct { /* Common Registers */
747 __I uint32_t DMACIntStat;
748 __I uint32_t DMACIntTCStat;
749 __O uint32_t DMACIntTCClear;
750 __I uint32_t DMACIntErrStat;
751 __O uint32_t DMACIntErrClr;
752 __I uint32_t DMACRawIntTCStat;
753 __I uint32_t DMACRawIntErrStat;
754 __I uint32_t DMACEnbldChns;
755 __IO uint32_t DMACSoftBReq;
756 __IO uint32_t DMACSoftSReq;
757 __IO uint32_t DMACSoftLBReq;
758 __IO uint32_t DMACSoftLSReq;
759 __IO uint32_t DMACConfig;
760 __IO uint32_t DMACSync;
761} GPDMA_TypeDef;
762
763typedef struct { /* Channel Registers */
764 __IO uint32_t DMACCSrcAddr;
765 __IO uint32_t DMACCDestAddr;
766 __IO uint32_t DMACCLLI;
767 __IO uint32_t DMACCControl;
768 __IO uint32_t DMACCConfig;
769} GPDMACH_TypeDef;
770
771/*------------- Universal Serial Bus (USB) -----------------------------------*/
772typedef struct {
773 __I uint32_t HcRevision; /* USB Host Registers */
774 __IO uint32_t HcControl;
775 __IO uint32_t HcCommandStatus;
776 __IO uint32_t HcInterruptStatus;
777 __IO uint32_t HcInterruptEnable;
778 __IO uint32_t HcInterruptDisable;
779 __IO uint32_t HcHCCA;
780 __I uint32_t HcPeriodCurrentED;
781 __IO uint32_t HcControlHeadED;
782 __IO uint32_t HcControlCurrentED;
783 __IO uint32_t HcBulkHeadED;
784 __IO uint32_t HcBulkCurrentED;
785 __I uint32_t HcDoneHead;
786 __IO uint32_t HcFmInterval;
787 __I uint32_t HcFmRemaining;
788 __I uint32_t HcFmNumber;
789 __IO uint32_t HcPeriodicStart;
790 __IO uint32_t HcLSTreshold;
791 __IO uint32_t HcRhDescriptorA;
792 __IO uint32_t HcRhDescriptorB;
793 __IO uint32_t HcRhStatus;
794 __IO uint32_t HcRhPortStatus1;
795 __IO uint32_t HcRhPortStatus2;
796 uint32_t RESERVED0[40];
797 __I uint32_t Module_ID;
798
799 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
800 __IO uint32_t OTGIntEn;
801 __O uint32_t OTGIntSet;
802 __O uint32_t OTGIntClr;
803 __IO uint32_t OTGStCtrl;
804 __IO uint32_t OTGTmr;
805 uint32_t RESERVED1[58];
806
807 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
808 __IO uint32_t USBDevIntEn;
809 __O uint32_t USBDevIntClr;
810 __O uint32_t USBDevIntSet;
811
812 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
813 __I uint32_t USBCmdData;
814
815 __I uint32_t USBRxData; /* USB Device Transfer Registers */
816 __O uint32_t USBTxData;
817 __I uint32_t USBRxPLen;
818 __O uint32_t USBTxPLen;
819 __IO uint32_t USBCtrl;
820 __O uint32_t USBDevIntPri;
821
822 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
823 __IO uint32_t USBEpIntEn;
824 __O uint32_t USBEpIntClr;
825 __O uint32_t USBEpIntSet;
826 __O uint32_t USBEpIntPri;
827
828 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
829 __O uint32_t USBEpInd;
830 __IO uint32_t USBMaxPSize;
831
832 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
833 __O uint32_t USBDMARClr;
834 __O uint32_t USBDMARSet;
835 uint32_t RESERVED2[9];
836 __IO uint32_t USBUDCAH;
837 __I uint32_t USBEpDMASt;
838 __O uint32_t USBEpDMAEn;
839 __O uint32_t USBEpDMADis;
840 __I uint32_t USBDMAIntSt;
841 __IO uint32_t USBDMAIntEn;
842 uint32_t RESERVED3[2];
843 __I uint32_t USBEoTIntSt;
844 __O uint32_t USBEoTIntClr;
845 __O uint32_t USBEoTIntSet;
846 __I uint32_t USBNDDRIntSt;
847 __O uint32_t USBNDDRIntClr;
848 __O uint32_t USBNDDRIntSet;
849 __I uint32_t USBSysErrIntSt;
850 __O uint32_t USBSysErrIntClr;
851 __O uint32_t USBSysErrIntSet;
852 uint32_t RESERVED4[15];
853
854 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
855 __O uint32_t I2C_WO;
856 __I uint32_t I2C_STS;
857 __IO uint32_t I2C_CTL;
858 __IO uint32_t I2C_CLKHI;
859 __O uint32_t I2C_CLKLO;
860 uint32_t RESERVED5[823];
861
862 union {
863 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
864 __IO uint32_t OTGClkCtrl;
865 } ;
866 union {
867 __I uint32_t USBClkSt;
868 __I uint32_t OTGClkSt;
869 };
870} USB_TypeDef;
871
872/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
873typedef struct {
874 __IO uint32_t MAC1; /* MAC Registers */
875 __IO uint32_t MAC2;
876 __IO uint32_t IPGT;
877 __IO uint32_t IPGR;
878 __IO uint32_t CLRT;
879 __IO uint32_t MAXF;
880 __IO uint32_t SUPP;
881 __IO uint32_t TEST;
882 __IO uint32_t MCFG;
883 __IO uint32_t MCMD;
884 __IO uint32_t MADR;
885 __O uint32_t MWTD;
886 __I uint32_t MRDD;
887 __I uint32_t MIND;
888 uint32_t RESERVED0[2];
889 __IO uint32_t SA0;
890 __IO uint32_t SA1;
891 __IO uint32_t SA2;
892 uint32_t RESERVED1[45];
893 __IO uint32_t Command; /* Control Registers */
894 __I uint32_t Status;
895 __IO uint32_t RxDescriptor;
896 __IO uint32_t RxStatus;
897 __IO uint32_t RxDescriptorNumber;
898 __I uint32_t RxProduceIndex;
899 __IO uint32_t RxConsumeIndex;
900 __IO uint32_t TxDescriptor;
901 __IO uint32_t TxStatus;
902 __IO uint32_t TxDescriptorNumber;
903 __IO uint32_t TxProduceIndex;
904 __I uint32_t TxConsumeIndex;
905 uint32_t RESERVED2[10];
906 __I uint32_t TSV0;
907 __I uint32_t TSV1;
908 __I uint32_t RSV;
909 uint32_t RESERVED3[3];
910 __IO uint32_t FlowControlCounter;
911 __I uint32_t FlowControlStatus;
912 uint32_t RESERVED4[34];
913 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
914 __IO uint32_t RxFilterWoLStatus;
915 __IO uint32_t RxFilterWoLClear;
916 uint32_t RESERVED5;
917 __IO uint32_t HashFilterL;
918 __IO uint32_t HashFilterH;
919 uint32_t RESERVED6[882];
920 __I uint32_t IntStatus; /* Module Control Registers */
921 __IO uint32_t IntEnable;
922 __O uint32_t IntClear;
923 __O uint32_t IntSet;
924 uint32_t RESERVED7;
925 __IO uint32_t PowerDown;
926 uint32_t RESERVED8;
927 __IO uint32_t Module_ID;
928} EMAC_TypeDef;
929
930/******************************************************************************/
931/* Peripheral memory map */
932/******************************************************************************/
933/* Base addresses */
934#define FLASH_BASE (0x00000000UL)
935#define RAM_BASE (0x10000000UL)
936#define GPIO_BASE (0x2009C000UL)
937#define APB0_BASE (0x40000000UL)
938#define APB1_BASE (0x40080000UL)
939#define AHB_BASE (0x50000000UL)
940#define CM3_BASE (0xE0000000UL)
941
942/* APB0 peripherals */
943#define WDT_BASE (APB0_BASE + 0x00000)
944#define TIM0_BASE (APB0_BASE + 0x04000)
945#define TIM1_BASE (APB0_BASE + 0x08000)
946#define UART0_BASE (APB0_BASE + 0x0C000)
947#define UART1_BASE (APB0_BASE + 0x10000)
948#define PWM1_BASE (APB0_BASE + 0x18000)
949#define I2C0_BASE (APB0_BASE + 0x1C000)
950#define SPI_BASE (APB0_BASE + 0x20000)
951#define RTC_BASE (APB0_BASE + 0x24000)
952#define GPIOINT_BASE (APB0_BASE + 0x28080)
953#define PINCON_BASE (APB0_BASE + 0x2C000)
954#define SSP1_BASE (APB0_BASE + 0x30000)
955#define ADC_BASE (APB0_BASE + 0x34000)
956#define CANAF_RAM_BASE (APB0_BASE + 0x38000)
957#define CANAF_BASE (APB0_BASE + 0x3C000)
958#define CANCR_BASE (APB0_BASE + 0x40000)
959#define CAN1_BASE (APB0_BASE + 0x44000)
960#define CAN2_BASE (APB0_BASE + 0x48000)
961#define I2C1_BASE (APB0_BASE + 0x5C000)
962
963/* APB1 peripherals */
964#define SSP0_BASE (APB1_BASE + 0x08000)
965#define DAC_BASE (APB1_BASE + 0x0C000)
966#define TIM2_BASE (APB1_BASE + 0x10000)
967#define TIM3_BASE (APB1_BASE + 0x14000)
968#define UART2_BASE (APB1_BASE + 0x18000)
969#define UART3_BASE (APB1_BASE + 0x1C000)
970#define I2C2_BASE (APB1_BASE + 0x20000)
971#define I2S_BASE (APB1_BASE + 0x28000)
972#define RIT_BASE (APB1_BASE + 0x30000)
973#define MCPWM_BASE (APB1_BASE + 0x38000)
974#define QEI_BASE (APB1_BASE + 0x3C000)
975#define SC_BASE (APB1_BASE + 0x7C000)
976
977/* AHB peripherals */
978#define EMAC_BASE (AHB_BASE + 0x00000)
979#define GPDMA_BASE (AHB_BASE + 0x04000)
980#define GPDMACH0_BASE (AHB_BASE + 0x04100)
981#define GPDMACH1_BASE (AHB_BASE + 0x04120)
982#define GPDMACH2_BASE (AHB_BASE + 0x04140)
983#define GPDMACH3_BASE (AHB_BASE + 0x04160)
984#define GPDMACH4_BASE (AHB_BASE + 0x04180)
985#define GPDMACH5_BASE (AHB_BASE + 0x041A0)
986#define GPDMACH6_BASE (AHB_BASE + 0x041C0)
987#define GPDMACH7_BASE (AHB_BASE + 0x041E0)
988#define USB_BASE (AHB_BASE + 0x0C000)
989
990/* GPIOs */
991#define GPIO0_BASE (GPIO_BASE + 0x00000)
992#define GPIO1_BASE (GPIO_BASE + 0x00020)
993#define GPIO2_BASE (GPIO_BASE + 0x00040)
994#define GPIO3_BASE (GPIO_BASE + 0x00060)
995#define GPIO4_BASE (GPIO_BASE + 0x00080)
996
997
998/******************************************************************************/
999/* Peripheral declaration */
1000/******************************************************************************/
1001#define SC (( SC_TypeDef *) SC_BASE)
1002#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
1003#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
1004#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
1005#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
1006#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
1007#define WDT (( WDT_TypeDef *) WDT_BASE)
1008#define TIM0 (( TIM_TypeDef *) TIM0_BASE)
1009#define TIM1 (( TIM_TypeDef *) TIM1_BASE)
1010#define TIM2 (( TIM_TypeDef *) TIM2_BASE)
1011#define TIM3 (( TIM_TypeDef *) TIM3_BASE)
1012#define RIT (( RIT_TypeDef *) RIT_BASE)
1013#define UART0 (( UART_TypeDef *) UART0_BASE)
1014#define UART1 (( UART1_TypeDef *) UART1_BASE)
1015#define UART2 (( UART_TypeDef *) UART2_BASE)
1016#define UART3 (( UART_TypeDef *) UART3_BASE)
1017#define PWM1 (( PWM_TypeDef *) PWM1_BASE)
1018#define I2C0 (( I2C_TypeDef *) I2C0_BASE)
1019#define I2C1 (( I2C_TypeDef *) I2C1_BASE)
1020#define I2C2 (( I2C_TypeDef *) I2C2_BASE)
1021#define I2S (( I2S_TypeDef *) I2S_BASE)
1022#define SPI (( SPI_TypeDef *) SPI_BASE)
1023#define RTC (( RTC_TypeDef *) RTC_BASE)
1024#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
1025#define PINCON (( PINCON_TypeDef *) PINCON_BASE)
1026#define SSP0 (( SSP_TypeDef *) SSP0_BASE)
1027#define SSP1 (( SSP_TypeDef *) SSP1_BASE)
1028#define ADC (( ADC_TypeDef *) ADC_BASE)
1029#define DAC (( DAC_TypeDef *) DAC_BASE)
1030#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
1031#define CANAF (( CANAF_TypeDef *) CANAF_BASE)
1032#define CANCR (( CANCR_TypeDef *) CANCR_BASE)
1033#define CAN1 (( CAN_TypeDef *) CAN1_BASE)
1034#define CAN2 (( CAN_TypeDef *) CAN2_BASE)
1035#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
1036#define QEI (( QEI_TypeDef *) QEI_BASE)
1037#define EMAC (( EMAC_TypeDef *) EMAC_BASE)
1038#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
1039#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
1040#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
1041#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
1042#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
1043#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
1044#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
1045#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
1046#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
1047#define USB (( USB_TypeDef *) USB_BASE)
1048
1049#endif // __LPC17xx_H__
1050
1051
1052#endif