commit 53f2918cd864a41593cfe36bae75cd5d5c7138df
author Brian Silverman <brians> Sat Dec 21 15:16:27 2013 -0800
committer Brian Silverman <brians> Sat Dec 21 15:16:27 2013 -0800
tree 2a7336da4cadbdab37db5f687d3842f56d155c38
parent cec3c8d3ac5b5660bc9ca48d4de8d2da5b4e4fd4

got sending packets actually working

bbb_cape/src/cape/uart_dma.c

diff --git a/bbb_cape/src/cape/uart_dma.c b/bbb_cape/src/cape/uart_dma.c
index 8493632..ed576b4 100644
--- a/bbb_cape/src/cape/uart_dma.c
+++ b/bbb_cape/src/cape/uart_dma.c
@@ -46,28 +46,30 @@
   uart_dma_callback(buffer1);
 
   UART->CR3 = USART_CR3_DMAT;
+  UART->CR1 |= USART_CR1_TE;
 
   RCC->AHB1ENR |= RCC_AHB1ENR_DMAEN;
-  DMA_Stream->CR = DMA_CHANNEL_NUMBER << 25 |
-      DMA_SxCR_DBM /* enable double buffer mode */ |
-      2 << 16 /* priority */ |
-      //2 << 13 /* memory data size = 32 bits */ |
-      0 << 13 /* memory data size = 8 bits */ |
-      0 << 11 /* peripherial data size = 8 bits */ |
-      DMA_SxCR_MINC /* increment memory address */ |
-      1 << 6 /* memory to peripherial */ |
-      DMA_SxCR_HTIE | DMA_SxCR_DMEIE |
-      DMA_SxCR_TCIE | DMA_SxCR_TEIE;
+  DMA_Stream->CR = 0;
+  while (DMA_Stream->CR & DMA_SxCR_EN);  // make sure it's disabled
   DMA_Stream->PAR = (uint32_t)&UART->DR;
   DMA_Stream->M0AR = (uint32_t)buffer1;
   DMA_Stream->M1AR = (uint32_t)buffer2;
   // This is measured in chunks of PSIZE bytes, not MSIZE.
   DMA_Stream->NDTR = bytes;
-  DMA_FCR = 0xF << DMA_SR_SHIFT;
+  DMA_Stream->CR = DMA_CHANNEL_NUMBER << 25 |
+      DMA_SxCR_DBM /* enable double buffer mode */ |
+      2 << 16 /* priority */ |
+      2 << 13 /* memory data size = 32 bits */ |
+      0 << 11 /* peripherial data size = 8 bits */ |
+      DMA_SxCR_MINC /* increment memory address */ |
+      1 << 6 /* memory to peripherial */ |
+      //DMA_SxCR_PFCTRL /* peripherial controls flow */ |
+      DMA_SxCR_TCIE | DMA_SxCR_TEIE;
   DMA_Stream->FCR =
       DMA_SxFCR_DMDIS /* disable direct mode (enable the FIFO) */ |
-      //1 /* 1/2 full threshold */;
-      3 /* 100% full threshold */;
+      1 /* 1/2 full threshold */;
+  UART->SR = ~USART_SR_TC;
+  DMA_FCR = 0xF << DMA_SR_SHIFT;
   DMA_Stream->CR |= DMA_SxCR_EN;  // enable it
   NVIC_SetPriority(DMA_Stream_IRQn, 8);
   NVIC_EnableIRQ(DMA_Stream_IRQn);