got sending packets actually working
diff --git a/bbb_cape/src/cape/cows.c b/bbb_cape/src/cape/cows.c
index 16ed1fc..bad2b30 100644
--- a/bbb_cape/src/cape/cows.c
+++ b/bbb_cape/src/cape/cows.c
@@ -51,7 +51,7 @@
     for (uint32_t i = 1; i < code; ++i) {
       destination[destination_index++] = source[source_index++];
     }
-    if (code != UINT32_MAX && source_index != source_length) {
+    if (code != UINT32_MAX && source_index != source_length / 4) {
       destination[destination_index++] = 0;
     }
   }
diff --git a/bbb_cape/src/cape/fill_packet.c b/bbb_cape/src/cape/fill_packet.c
index eb7d565..4f1c717 100644
--- a/bbb_cape/src/cape/fill_packet.c
+++ b/bbb_cape/src/cape/fill_packet.c
@@ -58,11 +58,11 @@
                 The_size_of_the_data_is_wrong);
   struct DataStruct *packet = &data.packet;
 
-  do_fill_packet(packet);
+  //do_fill_packet(packet);
 
   uint32_t *p;
   memcpy(&p, &packet, sizeof(void *));
-  data.checksum = crc_calculate(p, sizeof(*packet) / 4);
+  data.checksum = crc_calculate(p, (sizeof(data) - 4) / 4);
 
   ((uint32_t *)buffer)[0] = 0;
   cows_stuff(&data, sizeof(data), buffer + 4);
@@ -87,19 +87,6 @@
   //gyro_init();
 
   //uart_common_configure(3000000);
-  uart_common_configure(300000);
-  //uart_common_configure(19200);
-#if 0
-  //for (int i = 0; i < 5; ++i) uart_byte_send(255);
-  for (int i = 0; i < 10; ++i) uart_byte_send(i + 20);
-  //uart_byte_send('a');
-  //uart_byte_send('b');
-  //uart_byte_send('c');
-  //uart_byte_send('d');
-  led_set(LED_DB, 1);
-  (void)buffer1;
-  (void)buffer2;
-#else
+  uart_common_configure(30000);
   uart_dma_configure(DATA_STRUCT_SEND_SIZE, buffer1, buffer2);
-#endif
 }
diff --git a/bbb_cape/src/cape/uart_common.c b/bbb_cape/src/cape/uart_common.c
index 0cb7507..7b05102 100644
--- a/bbb_cape/src/cape/uart_common.c
+++ b/bbb_cape/src/cape/uart_common.c
@@ -26,7 +26,7 @@
   UART->CR1 =
       //USART_CR1_M /* 9th bit for the parity */ |
       //USART_CR1_PCE /* enable parity (even by default) */ |
-      USART_CR1_TE /* enable transmitter */ |
-      USART_CR1_RE /* enable receiver */;
+      //USART_CR1_OVER8 /* support going faster */ |
+      0;
   UART->CR1 |= USART_CR1_UE;  // enable it
 }
diff --git a/bbb_cape/src/cape/uart_dma.c b/bbb_cape/src/cape/uart_dma.c
index 8493632..ed576b4 100644
--- a/bbb_cape/src/cape/uart_dma.c
+++ b/bbb_cape/src/cape/uart_dma.c
@@ -46,28 +46,30 @@
   uart_dma_callback(buffer1);
 
   UART->CR3 = USART_CR3_DMAT;
+  UART->CR1 |= USART_CR1_TE;
 
   RCC->AHB1ENR |= RCC_AHB1ENR_DMAEN;
-  DMA_Stream->CR = DMA_CHANNEL_NUMBER << 25 |
-      DMA_SxCR_DBM /* enable double buffer mode */ |
-      2 << 16 /* priority */ |
-      //2 << 13 /* memory data size = 32 bits */ |
-      0 << 13 /* memory data size = 8 bits */ |
-      0 << 11 /* peripherial data size = 8 bits */ |
-      DMA_SxCR_MINC /* increment memory address */ |
-      1 << 6 /* memory to peripherial */ |
-      DMA_SxCR_HTIE | DMA_SxCR_DMEIE |
-      DMA_SxCR_TCIE | DMA_SxCR_TEIE;
+  DMA_Stream->CR = 0;
+  while (DMA_Stream->CR & DMA_SxCR_EN);  // make sure it's disabled
   DMA_Stream->PAR = (uint32_t)&UART->DR;
   DMA_Stream->M0AR = (uint32_t)buffer1;
   DMA_Stream->M1AR = (uint32_t)buffer2;
   // This is measured in chunks of PSIZE bytes, not MSIZE.
   DMA_Stream->NDTR = bytes;
-  DMA_FCR = 0xF << DMA_SR_SHIFT;
+  DMA_Stream->CR = DMA_CHANNEL_NUMBER << 25 |
+      DMA_SxCR_DBM /* enable double buffer mode */ |
+      2 << 16 /* priority */ |
+      2 << 13 /* memory data size = 32 bits */ |
+      0 << 11 /* peripherial data size = 8 bits */ |
+      DMA_SxCR_MINC /* increment memory address */ |
+      1 << 6 /* memory to peripherial */ |
+      //DMA_SxCR_PFCTRL /* peripherial controls flow */ |
+      DMA_SxCR_TCIE | DMA_SxCR_TEIE;
   DMA_Stream->FCR =
       DMA_SxFCR_DMDIS /* disable direct mode (enable the FIFO) */ |
-      //1 /* 1/2 full threshold */;
-      3 /* 100% full threshold */;
+      1 /* 1/2 full threshold */;
+  UART->SR = ~USART_SR_TC;
+  DMA_FCR = 0xF << DMA_SR_SHIFT;
   DMA_Stream->CR |= DMA_SxCR_EN;  // enable it
   NVIC_SetPriority(DMA_Stream_IRQn, 8);
   NVIC_EnableIRQ(DMA_Stream_IRQn);