Squashed 'third_party/pico-sdk/lib/tinyusb/' content from commit 868948f67c
Change-Id: I5d33c2566dd597be9d4b1c30d4b3723c5ef4a265
git-subtree-dir: third_party/pico-sdk/lib/tinyusb
git-subtree-split: 868948f67c90fa7c2553cdcd604b52862cf55720
Signed-off-by: Austin Schuh <austin.linux@gmail.com>
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
new file mode 100644
index 0000000..b3a7bc4
--- /dev/null
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
@@ -0,0 +1,77 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+// Note: For USB Host demo, install JP4
+// WARNING: don't install JP4 when running as device
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED Red
+#define LED_PORT 3
+#define LED_PIN 7
+
+// ISP Button
+#define BUTTON_PORT 0
+#define BUTTON_PIN 7
+
+#define UART_DEV LPC_USART0
+
+static inline void board_lpc18_pinmux(void)
+{
+ const PINMUX_GRP_T pinmuxing[] =
+ {
+ // LEDs
+ { 0x6, 9 , SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
+ { 0x6, 11, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
+
+ // Button
+ { 0x2, 7, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0 },
+
+ // UART
+ { 0x06, 4, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
+ { 0x02, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
+
+ // USB0
+ //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 }, // P6_3 USB0_PWR_EN, USB0 VBus function
+
+ //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 }, // P9_5 USB1_VBUS_EN, USB1 VBus function
+ //{ 0x2, 5, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+ {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
+ };
+
+ Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.mk b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.mk
new file mode 100644
index 0000000..29b1291
--- /dev/null
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.mk
@@ -0,0 +1,6 @@
+LD_FILE = $(BOARD_PATH)/lpc1837.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC18S37
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
new file mode 100644
index 0000000..51fd153
--- /dev/null
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
@@ -0,0 +1,404 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2021
+ * Generated linker script file for LPC1837
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v11.2.0 [Build 4120] [2020-07-09] on Mar 3, 2021 4:22:49 PM
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+}
+
+/* Define a symbol for the top of each memory region */
+__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ .text_Flash2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.text_Flash2) /* for compatibility with previous releases */
+ *(.text_MFlashB512) /* for compatibility with previous releases */
+ *(.text.$Flash2)
+ *(.text.$MFlashB512)
+ *(.text_Flash2.*) /* for compatibility with previous releases */
+ *(.text_MFlashB512.*) /* for compatibility with previous releases */
+ *(.text.$Flash2.*)
+ *(.text.$MFlashB512.*)
+ *(.rodata.$Flash2)
+ *(.rodata.$MFlashB512)
+ *(.rodata.$Flash2.*)
+ *(.rodata.$MFlashB512.*) } > MFlashB512
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ LONG(LOADADDR(.data_RAM4));
+ LONG( ADDR(.data_RAM4));
+ LONG( SIZEOF(.data_RAM4));
+ LONG(LOADADDR(.data_RAM5));
+ LONG( ADDR(.data_RAM5));
+ LONG( SIZEOF(.data_RAM5));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ LONG( ADDR(.bss_RAM4));
+ LONG( SIZEOF(.bss_RAM4));
+ LONG( ADDR(.bss_RAM5));
+ LONG( SIZEOF(.bss_RAM5));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ } > MFlashA512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlashA512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlashA512
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > MFlashA512
+
+ _etext = .;
+
+ /* DATA section for RamLoc40 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_RamLoc40 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamLoc40)
+ *(.data.$RAM2)
+ *(.data.$RamLoc40)
+ *(.data.$RAM2.*)
+ *(.data.$RamLoc40.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_RamLoc40 = .) ;
+ } > RamLoc40 AT>MFlashA512
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM3 = .) ;
+ PROVIDE(__start_data_RamAHB32 = .) ;
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM3)
+ *(.data.$RamAHB32)
+ *(.data.$RAM3.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM3 = .) ;
+ PROVIDE(__end_data_RamAHB32 = .) ;
+ } > RamAHB32 AT>MFlashA512
+
+ /* DATA section for RamAHB16 */
+
+ .data_RAM4 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM4 = .) ;
+ PROVIDE(__start_data_RamAHB16 = .) ;
+ *(.ramfunc.$RAM4)
+ *(.ramfunc.$RamAHB16)
+ *(.data.$RAM4)
+ *(.data.$RamAHB16)
+ *(.data.$RAM4.*)
+ *(.data.$RamAHB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM4 = .) ;
+ PROVIDE(__end_data_RamAHB16 = .) ;
+ } > RamAHB16 AT>MFlashA512
+
+ /* DATA section for RamAHB_ETB16 */
+
+ .data_RAM5 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM5 = .) ;
+ PROVIDE(__start_data_RamAHB_ETB16 = .) ;
+ *(.ramfunc.$RAM5)
+ *(.ramfunc.$RamAHB_ETB16)
+ *(.data.$RAM5)
+ *(.data.$RamAHB_ETB16)
+ *(.data.$RAM5.*)
+ *(.data.$RamAHB_ETB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM5 = .) ;
+ PROVIDE(__end_data_RamAHB_ETB16 = .) ;
+ } > RamAHB_ETB16 AT>MFlashA512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32 AT> RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_RamLoc32 = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_RamLoc32 = .) ;
+ } > RamLoc32 AT>MFlashA512
+
+ /* BSS section for RamLoc40 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_RamLoc40 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamLoc40)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamLoc40.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_RamLoc40 = .) ;
+ } > RamLoc40 AT> RamLoc40
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM3 = .) ;
+ PROVIDE(__start_bss_RamAHB32 = .) ;
+ *(.bss.$RAM3)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM3.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM3 = .) ;
+ PROVIDE(__end_bss_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* BSS section for RamAHB16 */
+ .bss_RAM4 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM4 = .) ;
+ PROVIDE(__start_bss_RamAHB16 = .) ;
+ *(.bss.$RAM4)
+ *(.bss.$RamAHB16)
+ *(.bss.$RAM4.*)
+ *(.bss.$RamAHB16.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM4 = .) ;
+ PROVIDE(__end_bss_RamAHB16 = .) ;
+ } > RamAHB16 AT> RamAHB16
+
+ /* BSS section for RamAHB_ETB16 */
+ .bss_RAM5 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM5 = .) ;
+ PROVIDE(__start_bss_RamAHB_ETB16 = .) ;
+ *(.bss.$RAM5)
+ *(.bss.$RamAHB_ETB16)
+ *(.bss.$RAM5.*)
+ *(.bss.$RamAHB_ETB16.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM5 = .) ;
+ PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
+ } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_RamLoc32 = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_RamLoc32 = .) ;
+ PROVIDE(end = .);
+ } > RamLoc32 AT> RamLoc32
+
+ /* NOINIT section for RamLoc40 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_RamLoc40 = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamLoc40)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamLoc40.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_RamLoc40 = .) ;
+ } > RamLoc40 AT> RamLoc40
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM3 = .) ;
+ PROVIDE(__start_noinit_RamAHB32 = .) ;
+ *(.noinit.$RAM3)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM3.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM3 = .) ;
+ PROVIDE(__end_noinit_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* NOINIT section for RamAHB16 */
+ .noinit_RAM4 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM4 = .) ;
+ PROVIDE(__start_noinit_RamAHB16 = .) ;
+ *(.noinit.$RAM4)
+ *(.noinit.$RamAHB16)
+ *(.noinit.$RAM4.*)
+ *(.noinit.$RamAHB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM4 = .) ;
+ PROVIDE(__end_noinit_RamAHB16 = .) ;
+ } > RamAHB16 AT> RamAHB16
+
+ /* NOINIT section for RamAHB_ETB16 */
+ .noinit_RAM5 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM5 = .) ;
+ PROVIDE(__start_noinit_RamAHB_ETB16 = .) ;
+ *(.noinit.$RAM5)
+ *(.noinit.$RamAHB_ETB16)
+ *(.noinit.$RAM5.*)
+ *(.noinit.$RamAHB_ETB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM5 = .) ;
+ PROVIDE(__end_noinit_RamAHB_ETB16 = .) ;
+ } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_RamLoc32 = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
+ } > RamLoc32 AT> RamLoc32
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h
new file mode 100644
index 0000000..6111da9
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/board.h
@@ -0,0 +1,94 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// PD_10
+#define LED_PORT 6
+#define LED_PIN 24
+
+// P4_0
+#define BUTTON_PORT 2
+#define BUTTON_PIN 0
+
+#define UART_DEV LPC_USART3
+
+static inline void board_lpc18_pinmux(void)
+{
+ const PINMUX_GRP_T pinmuxing[] =
+ {
+ // LEDs
+ { 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
+ { 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
+ { 0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
+ { 0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
+ { 0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
+ { 0x9, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
+ { 0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
+ { 0x9, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
+
+ // Button
+ { 0x4, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP) },
+
+ // UART
+ { 2, 3, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
+ { 2, 4, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 },
+
+ // USB0
+ { 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 }, // P6_3 USB0_PWR_EN, USB0 VBus function
+
+ { 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 }, // P9_5 USB1_VBUS_EN, USB1 VBus function
+ { 0x2, 5, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+ };
+
+ Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+
+ /* Pin clock mux values, re-used structure, value in first index is meaningless */
+ const PINMUX_GRP_T pinclockmuxing[] =
+ {
+ { 0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+ { 0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+ { 0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+ { 0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+ };
+
+ /* Clock pins only, group field not used */
+ for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
+ {
+ Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+ }
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.mk b/hw/bsp/lpc18/boards/mcb1800/board.mk
new file mode 100644
index 0000000..0307a21
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/board.mk
@@ -0,0 +1,7 @@
+LD_FILE = $(BOARD_PATH)/lpc1857.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1857
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
new file mode 100644
index 0000000..9a308e3
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
@@ -0,0 +1,323 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2019
+ * Generated linker script file for LPC1857
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 1:01:52 PM
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+}
+
+/* Define a symbol for the top of each memory region */
+__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ .text_Flash2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.text_Flash2*) /* for compatibility with previous releases */
+ *(.text_MFlashB512*) /* for compatibility with previous releases */
+ *(.text.$Flash2*)
+ *(.text.$MFlashB512*)
+ *(.rodata.$Flash2*)
+ *(.rodata.$MFlashB512*)
+ } > MFlashB512
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ LONG(LOADADDR(.data_RAM4));
+ LONG( ADDR(.data_RAM4));
+ LONG( SIZEOF(.data_RAM4));
+ LONG(LOADADDR(.data_RAM5));
+ LONG( ADDR(.data_RAM5));
+ LONG( SIZEOF(.data_RAM5));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ LONG( ADDR(.bss_RAM4));
+ LONG( SIZEOF(.bss_RAM4));
+ LONG( ADDR(.bss_RAM5));
+ LONG( SIZEOF(.bss_RAM5));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ } > MFlashA512
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlashA512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlashA512
+
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlashA512
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* DATA section for RamLoc40 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamLoc40)
+ *(.data.$RAM2*)
+ *(.data.$RamLoc40*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamLoc40 AT>MFlashA512
+ /* DATA section for RamAHB32 */
+
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM3 = .) ;
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM3*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM3 = .) ;
+ } > RamAHB32 AT>MFlashA512
+ /* DATA section for RamAHB16 */
+
+ .data_RAM4 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM4 = .) ;
+ *(.ramfunc.$RAM4)
+ *(.ramfunc.$RamAHB16)
+ *(.data.$RAM4*)
+ *(.data.$RamAHB16*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM4 = .) ;
+ } > RamAHB16 AT>MFlashA512
+ /* DATA section for RamAHB_ETB16 */
+
+ .data_RAM5 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM5 = .) ;
+ *(.ramfunc.$RAM5)
+ *(.ramfunc.$RamAHB_ETB16)
+ *(.data.$RAM5*)
+ *(.data.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM5 = .) ;
+ } > RamAHB_ETB16 AT>MFlashA512
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc32 AT>MFlashA512
+
+ /* BSS section for RamLoc40 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamLoc40*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamLoc40
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM3 = .) ;
+ *(.bss.$RAM3*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM3 = .) ;
+ } > RamAHB32
+
+ /* BSS section for RamAHB16 */
+ .bss_RAM4 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM4 = .) ;
+ *(.bss.$RAM4*)
+ *(.bss.$RamAHB16*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM4 = .) ;
+ } > RamAHB16
+
+ /* BSS section for RamAHB_ETB16 */
+ .bss_RAM5 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM5 = .) ;
+ *(.bss.$RAM5*)
+ *(.bss.$RamAHB_ETB16*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM5 = .) ;
+ } > RamAHB_ETB16
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ /* NOINIT section for RamLoc40 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamLoc40*)
+ . = ALIGN(4) ;
+ } > RamLoc40
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* NOINIT section for RamAHB16 */
+ .noinit_RAM4 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM4*)
+ *(.noinit.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16
+
+ /* NOINIT section for RamAHB_ETB16 */
+ .noinit_RAM5 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM5*)
+ *(.noinit.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc32
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
new file mode 100644
index 0000000..d74ebcd
--- /dev/null
+++ b/hw/bsp/lpc18/family.c
@@ -0,0 +1,159 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "chip.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+ #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+ tuh_int_handler(0);
+ #endif
+
+ #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+ tud_int_handler(0);
+ #endif
+}
+
+void USB1_IRQHandler(void)
+{
+ #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+ tuh_int_handler(1);
+ #endif
+
+ #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+ tud_int_handler(1);
+ #endif
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+/* System configuration variables used by chip driver */
+const uint32_t OscRateIn = 12000000;
+const uint32_t ExtRateIn = 0;
+
+// Invoked by startup code
+void SystemInit(void)
+{
+#ifdef __USE_LPCOPEN
+ extern void (* const g_pfnVectors[])(void);
+ unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ *pSCB_VTOR = (unsigned int) g_pfnVectors;
+#endif
+
+ board_lpc18_pinmux();
+ Chip_SetupXtalClocking();
+}
+
+void board_init(void)
+{
+ SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+ Chip_GPIO_Init(LPC_GPIO_PORT);
+
+ // LED
+ Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
+
+ // Button
+ Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
+
+ //------------- UART -------------//
+ Chip_UART_Init(UART_DEV);
+ Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE);
+ Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS);
+ Chip_UART_TXEnable(UART_DEV);
+
+ //------------- USB -------------//
+#if CFG_TUSB_RHPORT0_MODE
+ Chip_USB0_Init();
+#endif
+
+#if CFG_TUSB_RHPORT1_MODE
+ Chip_USB1_Init();
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+ Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+ // active low
+ return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+ //return UART_ReceiveByte(BOARD_UART_PORT);
+ (void) buf; (void) len;
+ return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+ uint8_t const* buf8 = (uint8_t const*) buf;
+ for(int i=0; i<len; i++)
+ {
+ while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
+ Chip_UART_SendByte(UART_DEV, buf8[i]);
+ }
+
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+ return system_ticks;
+}
+#endif
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
new file mode 100644
index 0000000..7aa36ab
--- /dev/null
+++ b/hw/bsp/lpc18/family.mk
@@ -0,0 +1,37 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+ -flto \
+ -mthumb \
+ -mabi=aapcs \
+ -mcpu=cortex-m3 \
+ -nostdlib \
+ -DCORE_M3 \
+ -D__USE_LPCOPEN \
+ -DCFG_TUSB_MCU=OPT_MCU_LPC18XX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual
+
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
+
+SRC_C += \
+ src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+ src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+ src/portable/ehci/ehci.c \
+ $(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \
+ $(MCU_DIR)/src/chip_18xx_43xx.c \
+ $(MCU_DIR)/src/clock_18xx_43xx.c \
+ $(MCU_DIR)/src/gpio_18xx_43xx.c \
+ $(MCU_DIR)/src/sysinit_18xx_43xx.c \
+ $(MCU_DIR)/src/uart_18xx_43xx.c
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MCU_DIR)/inc \
+ $(TOP)/$(MCU_DIR)/inc/config_18xx
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM3