Squashed 'third_party/pico-sdk/lib/tinyusb/' content from commit 868948f67c
Change-Id: I5d33c2566dd597be9d4b1c30d4b3723c5ef4a265
git-subtree-dir: third_party/pico-sdk/lib/tinyusb
git-subtree-split: 868948f67c90fa7c2553cdcd604b52862cf55720
Signed-off-by: Austin Schuh <austin.linux@gmail.com>
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
new file mode 100644
index 0000000..5ed5b75
--- /dev/null
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// XTAL
+#define XTAL_OscRateIn 12000000
+#define XTAL_RTCOscRateIn 32768
+
+// LED
+#define LED_PORT 0
+#define LED_PIN 25
+
+// Wake Switch
+#define BUTTON_PORT 0
+#define BUTTON_PIN 17
+
+#define UART_PORT LPC_USART0
+
+static inline void board_lpc15_pinmux_swm_init(void)
+{
+ // Pinmux
+ const PINMUX_GRP_T pinmuxing[] =
+ {
+ {0, 25, (IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // PIO0_25-BREAK_CTRL-RED (low enable)
+ {0, 13, (IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // PIO0_13-ISP_RX
+ {0, 18, (IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // PIO0_18-ISP_TX
+ {1, 11, (IOCON_MODE_PULLDOWN | IOCON_DIGMODE_EN)}, // PIO1_11-ISP_1 (VBUS)
+ };
+
+ // Pin Mux
+ Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+
+ // SWIM
+ Chip_SWM_MovablePortPinAssign(SWM_USB_VBUS_I , 1, 11);
+ Chip_SWM_MovablePortPinAssign(SWM_UART0_RXD_I, 0, 13);
+ Chip_SWM_MovablePortPinAssign(SWM_UART0_TXD_O, 0, 18);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
new file mode 100644
index 0000000..b00fc71
--- /dev/null
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
@@ -0,0 +1,7 @@
+CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY
+LD_FILE = $(BOARD_PATH)/lpc1549.ld
+
+JLINK_DEVICE = LPC1549
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
new file mode 100644
index 0000000..6dd12ad
--- /dev/null
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
@@ -0,0 +1,246 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2019
+ * Generated linker script file for LPC1549
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Oct 3, 2019 2:55:18 PM
+ */
+
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+ Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */
+ Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
+ Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlash256 = 0x0 ; /* MFlash256 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+ __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+ __base_Ram0_16 = 0x2000000 ; /* Ram0_16 */
+ __base_RAM = 0x2000000 ; /* RAM */
+ __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */
+ __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */
+ __base_Ram1_16 = 0x2004000 ; /* Ram1_16 */
+ __base_RAM2 = 0x2004000 ; /* RAM2 */
+ __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */
+ __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */
+ __base_Ram2_4 = 0x2008000 ; /* Ram2_4 */
+ __base_RAM3 = 0x2008000 ; /* RAM3 */
+ __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */
+ __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ } > MFlash256
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlash256
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash256
+
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash256
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* DATA section for Ram1_16 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$Ram1_16)
+ *(.data.$RAM2)
+ *(.data.$Ram1_16)
+ *(.data.$RAM2.*)
+ *(.data.$Ram1_16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > Ram1_16 AT>MFlash256
+ /* DATA section for Ram2_4 */
+
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM3 = .) ;
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$Ram2_4)
+ *(.data.$RAM3)
+ *(.data.$Ram2_4)
+ *(.data.$RAM3.*)
+ *(.data.$Ram2_4.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM3 = .) ;
+ } > Ram2_4 AT>MFlash256
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) :
+ {
+ . = ALIGN(4) ;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > Ram0_16
+
+ /* Main DATA section (Ram0_16) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > Ram0_16 AT>MFlash256
+
+ /* BSS section for Ram1_16 */
+ .bss_RAM2 :
+ {
+ . = ALIGN(4) ;
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$Ram1_16)
+ *(.bss.$RAM2.*)
+ *(.bss.$Ram1_16.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > Ram1_16
+
+ /* BSS section for Ram2_4 */
+ .bss_RAM3 :
+ {
+ . = ALIGN(4) ;
+ PROVIDE(__start_bss_RAM3 = .) ;
+ *(.bss.$RAM3)
+ *(.bss.$Ram2_4)
+ *(.bss.$RAM3.*)
+ *(.bss.$Ram2_4.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM3 = .) ;
+ } > Ram2_4
+
+ /* MAIN BSS SECTION */
+ .bss :
+ {
+ . = ALIGN(4) ;
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > Ram0_16
+
+ /* NOINIT section for Ram1_16 */
+ .noinit_RAM2 (NOLOAD) :
+ {
+ . = ALIGN(4) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$Ram1_16)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$Ram1_16.*)
+ . = ALIGN(4) ;
+ } > Ram1_16
+
+ /* NOINIT section for Ram2_4 */
+ .noinit_RAM3 (NOLOAD) :
+ {
+ . = ALIGN(4) ;
+ *(.noinit.$RAM3)
+ *(.noinit.$Ram2_4)
+ *(.noinit.$RAM3.*)
+ *(.noinit.$Ram2_4.*)
+ . = ALIGN(4) ;
+ } > Ram2_4
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4) ;
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > Ram0_16
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
\ No newline at end of file
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
new file mode 100644
index 0000000..7f5984a
--- /dev/null
+++ b/hw/bsp/lpc15/family.c
@@ -0,0 +1,130 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "chip.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+ tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = XTAL_OscRateIn;
+const uint32_t RTCOscRateIn = XTAL_RTCOscRateIn;
+
+// Invoked by startup code
+void SystemInit(void)
+{
+ Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SRAM1);
+ Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SRAM2);
+ Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
+ Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
+ Chip_SYSCTL_PeriphReset(RESET_IOCON);
+
+ board_lpc15_pinmux_swm_init();
+
+ Chip_SetupXtalClocking();
+}
+
+void board_init(void)
+{
+ SystemCoreClockUpdate();
+
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+ Chip_GPIO_Init(LPC_GPIO);
+
+ // LED
+ Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
+
+ // Button
+ Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
+
+ // UART
+ Chip_Clock_SetUARTBaseClockRate(Chip_Clock_GetMainClockRate(), false);
+ Chip_UART_Init(UART_PORT);
+ Chip_UART_ConfigData(UART_PORT, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
+ Chip_UART_SetBaud(UART_PORT, CFG_BOARD_UART_BAUDRATE);
+ Chip_UART_Enable(UART_PORT);
+ Chip_UART_TXEnable(UART_PORT);
+
+ // USB: Setup PLL clock, and power
+ Chip_USB_Init();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+ Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+ // active low
+ return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+ (void) buf; (void) len;
+ return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+ return Chip_UART_SendBlocking(UART_PORT, buf, len);
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+ return system_ticks;
+}
+#endif
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
new file mode 100644
index 0000000..c7dd3f8
--- /dev/null
+++ b/hw/bsp/lpc15/family.mk
@@ -0,0 +1,39 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+ -flto \
+ -mthumb \
+ -mabi=aapcs \
+ -mcpu=cortex-m3 \
+ -nostdlib \
+ -DCORE_M3 \
+ -D__USE_LPCOPEN \
+ -DCFG_EXAMPLE_MSC_READONLY \
+ -DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
+ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
+
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx
+
+SRC_C += \
+ src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+ $(MCU_DIR)/../gcc/cr_startup_lpc15xx.c \
+ $(MCU_DIR)/src/chip_15xx.c \
+ $(MCU_DIR)/src/clock_15xx.c \
+ $(MCU_DIR)/src/gpio_15xx.c \
+ $(MCU_DIR)/src/iocon_15xx.c \
+ $(MCU_DIR)/src/swm_15xx.c \
+ $(MCU_DIR)/src/sysctl_15xx.c \
+ $(MCU_DIR)/src/uart_15xx.c \
+ $(MCU_DIR)/src/sysinit_15xx.c
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MCU_DIR)/inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM3