blob: 90fde06b4acafbba28819494df036a1869a21575 [file] [log] [blame]
Austin Schuh208337d2022-01-01 14:29:11 -08001/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdio.h>
8#include "hardware/dma.h"
9#include "hardware/claim.h"
10
11#define DMA_CHAN_STRIDE (DMA_CH1_CTRL_TRIG_OFFSET - DMA_CH0_CTRL_TRIG_OFFSET)
12check_hw_size(dma_channel_hw_t, DMA_CHAN_STRIDE);
13check_hw_layout(dma_hw_t, abort, DMA_CHAN_ABORT_OFFSET);
14
15// sanity check
16static_assert(__builtin_offsetof(dma_hw_t, ch[0].ctrl_trig) == DMA_CH0_CTRL_TRIG_OFFSET, "hw mismatch");
17static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG_OFFSET, "hw mismatch");
18
19static_assert(NUM_DMA_CHANNELS <= 16, "");
20static uint16_t _claimed;
21static uint8_t _timer_claimed;
22
23void dma_channel_claim(uint channel) {
24 check_dma_channel_param(channel);
25 hw_claim_or_assert((uint8_t *) &_claimed, channel, "DMA channel %d is already claimed");
26}
27
28void dma_claim_mask(uint32_t mask) {
29 for(uint i = 0; mask; i++, mask >>= 1u) {
30 if (mask & 1u) dma_channel_claim(i);
31 }
32}
33
34void dma_channel_unclaim(uint channel) {
35 check_dma_channel_param(channel);
36 hw_claim_clear((uint8_t *) &_claimed, channel);
37}
38
39int dma_claim_unused_channel(bool required) {
40 return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available");
41}
42
43bool dma_channel_is_claimed(uint channel) {
44 check_dma_channel_param(channel);
45 return hw_is_claimed((uint8_t *) &_claimed, channel);
46}
47
48void dma_timer_claim(uint timer) {
49 check_dma_timer_param(timer);
50 hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed");
51}
52
53void dma_timer_unclaim(uint timer) {
54 check_dma_timer_param(timer);
55 hw_claim_clear(&_timer_claimed, timer);
56}
57
58int dma_claim_unused_timer(bool required) {
59 return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available");
60}
61
62bool dma_timer_is_claimed(uint timer) {
63 check_dma_timer_param(timer);
64 return hw_is_claimed(&_timer_claimed, timer);
65}
66
67#ifndef NDEBUG
68
69void print_dma_ctrl(dma_channel_hw_t *channel) {
70 uint32_t ctrl = channel->ctrl_trig;
71 int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB;
72 printf("(%08x) ber %d rer %d wer %d busy %d trq %d cto %d rgsl %d rgsz %d inw %d inr %d sz %d hip %d en %d",
73 (uint) ctrl,
74 ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0,
75 ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0,
76 ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0,
77 ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0,
78 (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB),
79 (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB),
80 ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0,
81 rgsz ? (1 << rgsz) : 0,
82 ctrl & DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS ? 1 : 0,
83 ctrl & DMA_CH0_CTRL_TRIG_INCR_READ_BITS ? 1 : 0,
84 1 << ((ctrl & DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB),
85 ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0,
86 ctrl & DMA_CH0_CTRL_TRIG_EN_BITS ? 1 : 0);
87}
88#endif
89
90#if PARAM_ASSERTIONS_ENABLED(DMA)
91void check_dma_channel_param_impl(uint __unused channel) {
92 valid_params_if(DMA, channel < NUM_DMA_CHANNELS);
93}
94#endif