commit f63b0aea3290b2d0c21005257c21b1f433d0c259
author James Kuszmaul <james@hp-debian> Tue Mar 25 16:52:11 2014 -0700
committer James Kuszmaul <james@hp-debian> Tue Mar 25 16:52:11 2014 -0700
tree f7f7917684455e8ef689125255f7f632e4bd220b
parent fb0e0ae6e502c59a42e6ca68731bed9843f1fef7

Added stuff for properly capping voltage on claw.

Compiles, tests pass, generally good :).

frc971/control_loops/claw/claw.gyp

diff --git a/frc971/control_loops/claw/claw.gyp b/frc971/control_loops/claw/claw.gyp
index 8bb94c0..f71bf6b 100644
--- a/frc971/control_loops/claw/claw.gyp
+++ b/frc971/control_loops/claw/claw.gyp
@@ -29,11 +29,15 @@
         '<(AOS)/common/common.gyp:controls',
         '<(DEPTH)/frc971/frc971.gyp:constants',
         '<(DEPTH)/frc971/control_loops/control_loops.gyp:state_feedback_loop',
+        '<(DEPTH)/aos/build/externals.gyp:libcdd',
+        '<(DEPTH)/frc971/control_loops/control_loops.gyp:coerce_goal',
       ],
       'export_dependent_settings': [
         'claw_loop',
         '<(AOS)/common/common.gyp:controls',
         '<(DEPTH)/frc971/control_loops/control_loops.gyp:state_feedback_loop',
+        '<(DEPTH)/aos/build/externals.gyp:libcdd',
+        '<(DEPTH)/frc971/control_loops/control_loops.gyp:coerce_goal',
       ],
     },
     {