Increase alignment to 128 bytes
Rockpi's DMA engine requires 128 byte alignment. Since this is the new
high point, up it.
Change-Id: Iac4f7c0a5e6e98c7f3e5d21c1cb7d03483a511df
Signed-off-by: Austin Schuh <austin.linux@gmail.com>
diff --git a/aos/ipc_lib/data_alignment.h b/aos/ipc_lib/data_alignment.h
index 72a7456..3bf38ce 100644
--- a/aos/ipc_lib/data_alignment.h
+++ b/aos/ipc_lib/data_alignment.h
@@ -9,11 +9,13 @@
// alignment for their end. Flatbuffers aligns from the end, so this is what
// matters.
//
-// 64 is a reasonable choice for now:
+// 128 is a reasonable choice for now:
// Cortex-A72 (Raspberry Pi 4) and Cortex-A53 (Xavier AGX) both have 64 byte
// cache lines.
// V4L2 requires 64 byte alignment for USERPTR buffers.
-static constexpr size_t kChannelDataAlignment = 64;
+//
+// rockpi v4l2 requires 128 byte alignment for USERPTR buffers.
+static constexpr size_t kChannelDataAlignment = 128;
template <typename T>
inline void CheckChannelDataAlignment(T *data, size_t size) {