Configure watchdog on IMU
Watchdog triggers system reset after 100 ms. Addresses issues such as
processor or interrupt overload. See doc for details:
https://docs.google.com/document/d/1XBOxFHc8P92KlShVC_kKH3husulU-NNYZqSwnIabMKc/edit?usp=sharing
Testing:
- Check that system runs with no resets under ~5 mins of normal operation.
- Manually trigger timeout by starving each interrupt loop.
Signed-off-by: Sindy Tan <sindytn@gmail.com>
Change-Id: I124c0f2513f821b10ddf7b95efc434a2191704ab
diff --git a/frc971/imu_fdcan/Dual_IMU/Core/Inc/main.h b/frc971/imu_fdcan/Dual_IMU/Core/Inc/main.h
index f4e0ee8..6ecca0d 100644
--- a/frc971/imu_fdcan/Dual_IMU/Core/Inc/main.h
+++ b/frc971/imu_fdcan/Dual_IMU/Core/Inc/main.h
@@ -185,7 +185,11 @@
/* USER CODE BEGIN Private defines */
+#define LSI_CLOCK_FREQ_HZ 32000 // 32 kHz
#define IMU_SAMPLES_PER_MS 3
+#define CAN_WATCHDOG_TIMEOUT_US 20000 // 20 ms
+#define PWM_WATCHDOG_TIMEOUT_US 20000 // 20 ms
+#define SPI_WATCHDOG_TIMEOUT_US 20000 // 20 ms
/* USER CODE END Private defines */
diff --git a/frc971/imu_fdcan/Dual_IMU/Core/Inc/stm32g4xx_hal_conf.h b/frc971/imu_fdcan/Dual_IMU/Core/Inc/stm32g4xx_hal_conf.h
index c2618b2..bef4ebf 100644
--- a/frc971/imu_fdcan/Dual_IMU/Core/Inc/stm32g4xx_hal_conf.h
+++ b/frc971/imu_fdcan/Dual_IMU/Core/Inc/stm32g4xx_hal_conf.h
@@ -46,7 +46,7 @@
/*#define HAL_FMAC_MODULE_ENABLED */
/*#define HAL_HRTIM_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
-/*#define HAL_IWDG_MODULE_ENABLED */
+#define HAL_IWDG_MODULE_ENABLED
/*#define HAL_I2C_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
diff --git a/frc971/imu_fdcan/Dual_IMU/Core/Src/main.c b/frc971/imu_fdcan/Dual_IMU/Core/Src/main.c
index c0758f8..65a2d42 100644
--- a/frc971/imu_fdcan/Dual_IMU/Core/Src/main.c
+++ b/frc971/imu_fdcan/Dual_IMU/Core/Src/main.c
@@ -49,6 +49,8 @@
FDCAN_HandleTypeDef hfdcan2;
+IWDG_HandleTypeDef hiwdg;
+
SPI_HandleTypeDef hspi1;
SPI_HandleTypeDef hspi2;
SPI_HandleTypeDef hspi3;
@@ -85,7 +87,7 @@
static uint8_t can_tx[64];
static int can_tx_packet_counter;
static CanData can_out;
-static int timer_index;
+static int timer_index = 0;
static DataMurata murata_averaged;
static DataTdk tdk_averaged;
@@ -106,6 +108,15 @@
static FourBytes spi3_tx;
static FourBytes spi_murata_rx;
+// Watchdog
+// Watchpuppies, really. When they starve, the main watchdog also starves;
+// system reset is triggered on main watchdog timeout.
+unsigned long last_can_watchdog_us;
+unsigned long last_pwm_watchdog_us;
+unsigned long last_spi_uno_watchdog_us;
+unsigned long last_spi_due_watchdog_us;
+unsigned long last_spi_tdk_watchdog_us;
+
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
@@ -121,6 +132,7 @@
static void MX_USB_PCD_Init(void);
static void MX_TIM2_Init(void);
static void MX_TIM1_Init(void);
+static void MX_IWDG_Init(void);
/* USER CODE BEGIN PFP */
static void EnableLeds(void);
@@ -152,6 +164,11 @@
SpiIn call);
static void SpiMurata(DataRawInt16 *data, SPI_HandleTypeDef *hspix, SpiOut *res,
SpiIn call);
+
+// Watchdog
+static uint16_t GetWatchdogTimeoutMs(void);
+static void DelayWithWatchdog(uint16_t delay_ms);
+
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
@@ -197,17 +214,27 @@
MX_USB_PCD_Init();
MX_TIM2_Init();
MX_TIM1_Init();
+ MX_IWDG_Init();
/* USER CODE BEGIN 2 */
- EnableLeds(); // Set LEDs to red
+ HAL_IWDG_Refresh(&hiwdg);
+ EnableLeds(); // Set LEDs to red
+ HAL_IWDG_Refresh(&hiwdg);
+
InitCan(&tx_header, 0x01); // Initialize the CAN module
+ HAL_IWDG_Refresh(&hiwdg);
+
InitMurata(); // Run the Murata power up sequence (see pg 30 of datasheet)
- InitTdk(); // Run the TDK power up sequence (see pg 22 of datasheet)
+ HAL_IWDG_Refresh(&hiwdg);
+
+ InitTdk(); // Run the TDK power up sequence (see pg 22 of datasheet)
+ HAL_IWDG_Refresh(&hiwdg);
+
HAL_TIM_Base_Start_IT(&htim2); // Start 1 us timer
HAL_TIM_Base_Start_IT(&htim1); // Start 1 ms timer
-
HAL_TIM_PWM_Start_IT(&htim3, TIM_CHANNEL_3);
HAL_TIM_PWM_Start_IT(&htim3, TIM_CHANNEL_4);
+ HAL_IWDG_Refresh(&hiwdg);
/* USER CODE END 2 */
@@ -218,6 +245,41 @@
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
+
+ // Check when CAN, PWM and SPI were last successfully written. Use
+ // snapshotted timestamps to prevent race condition from interrupt loop
+ // updating during check.
+ unsigned long last_can_watchdog_us_copy = last_can_watchdog_us;
+ unsigned long last_pwm_watchdog_us_copy = last_pwm_watchdog_us;
+ unsigned long last_spi_uno_watchdog_us_copy = last_spi_uno_watchdog_us;
+ unsigned long last_spi_due_watchdog_us_copy = last_spi_due_watchdog_us;
+ unsigned long last_spi_tdk_watchdog_us_copy = last_spi_tdk_watchdog_us;
+ unsigned long current_time_us = __HAL_TIM_GetCounter(&htim2);
+
+ // Feed watchdog. Triggers system reset after 100 ms.
+ // We also check 3 sub-watchdogs that monitor the (interrupt) loops for CAN,
+ // PWM and SPI. This main watchdog is only fed when all are fed.
+
+ if (current_time_us - last_can_watchdog_us_copy > CAN_WATCHDOG_TIMEOUT_US) {
+ // TODO(sindy): add uart logging in future PR -- "CAN watchdog timeout"
+ } else if (current_time_us - last_pwm_watchdog_us_copy >
+ PWM_WATCHDOG_TIMEOUT_US) {
+ // TODO(sindy): add uart logging in future PR -- "PWM watchdog timeout"
+ } else if (current_time_us - last_spi_uno_watchdog_us_copy >
+ SPI_WATCHDOG_TIMEOUT_US) {
+ // TODO(sindy): add uart logging in future PR -- "SPI UNO watchdog
+ // timeout"
+ } else if (current_time_us - last_spi_due_watchdog_us_copy >
+ SPI_WATCHDOG_TIMEOUT_US) {
+ // TODO(sindy): add uart logging in future PR -- "SPI DUE watchdog
+ // timeout"
+ } else if (current_time_us - last_spi_tdk_watchdog_us_copy >
+ SPI_WATCHDOG_TIMEOUT_US) {
+ // TODO(sindy): add uart logging in future PR -- "SPI TDK watchdog
+ // timeout"
+ } else {
+ HAL_IWDG_Refresh(&hiwdg);
+ }
}
/* USER CODE END 3 */
}
@@ -237,9 +299,11 @@
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
- RCC_OscInitStruct.OscillatorType =
- RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 |
+ RCC_OSCILLATORTYPE_LSI |
+ RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@@ -360,6 +424,31 @@
}
/**
+ * @brief IWDG Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_IWDG_Init(void) {
+ /* USER CODE BEGIN IWDG_Init 0 */
+
+ /* USER CODE END IWDG_Init 0 */
+
+ /* USER CODE BEGIN IWDG_Init 1 */
+
+ /* USER CODE END IWDG_Init 1 */
+ hiwdg.Instance = IWDG;
+ hiwdg.Init.Prescaler = IWDG_PRESCALER_16;
+ hiwdg.Init.Window = 4095;
+ hiwdg.Init.Reload = 200;
+ if (HAL_IWDG_Init(&hiwdg) != HAL_OK) {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN IWDG_Init 2 */
+
+ /* USER CODE END IWDG_Init 2 */
+}
+
+/**
* @brief SPI1 Initialization Function
* @param None
* @retval None
@@ -527,7 +616,7 @@
htim2.Instance = TIM2;
htim2.Init.Prescaler = 168 - 1;
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- htim2.Init.Period = 4.294967295E9;
+ htim2.Init.Period = 4294967295;
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
if (HAL_TIM_Base_Init(&htim2) != HAL_OK) {
@@ -777,7 +866,9 @@
// TDK_PWR_EN starts high, must be set low before reading
HAL_GPIO_WritePin(TDK_PWR_EN_GPIO_Port, TDK_PWR_EN_Pin, GPIO_PIN_RESET);
// TDK_EN starts high, must be set low after a delay from TDK_PWR_EN
- HAL_Delay(1000);
+
+ DelayWithWatchdog(1000);
+
HAL_GPIO_WritePin(TDK_EN_GPIO_Port, TDK_EN_Pin, GPIO_PIN_RESET);
}
@@ -876,21 +967,21 @@
HAL_GPIO_WritePin(RESET_UNO_GPIO_Port, RESET_UNO_Pin,
GPIO_PIN_RESET); // Reset UNO
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_UNO_GPIO_Port, RESET_UNO_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin,
GPIO_PIN_RESET); // Reset DUE
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin, GPIO_PIN_SET);
- HAL_Delay(25);
+ DelayWithWatchdog(25);
SendSpiDue(MakeSpiReadMsgMurata(ACC_DC1_ADDRESS)); // cxx_cxy address
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiUno(WRITE_OP_MODE_NORMAL);
- HAL_Delay(70);
+ DelayWithWatchdog(70);
SendSpiDue(WRITE_MODE_ASM_010);
SendSpiDue(READ_MODE);
@@ -948,19 +1039,19 @@
HAL_GPIO_WritePin(RESET_UNO_GPIO_Port, RESET_UNO_Pin,
GPIO_PIN_RESET); // Reset UNO
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_UNO_GPIO_Port, RESET_UNO_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin,
GPIO_PIN_RESET); // Reset DUE
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin, GPIO_PIN_SET);
- HAL_Delay(25);
+ DelayWithWatchdog(25);
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiUno(WRITE_OP_MODE_NORMAL);
- HAL_Delay(70);
+ DelayWithWatchdog(70);
SendSpiUno(
MakeSpiMsgMurata(MURATA_GYRO_FILTER_ADDR, MURATA_GYRO_FILTER_300HZ));
@@ -968,19 +1059,19 @@
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin,
GPIO_PIN_RESET); // Reset DUE
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin, GPIO_PIN_SET);
- HAL_Delay(25);
+ DelayWithWatchdog(25);
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiDue(WRITE_OP_MODE_NORMAL);
- HAL_Delay(1);
+ DelayWithWatchdog(1);
SendSpiDue(
MakeSpiMsgMurata(MURATA_GYRO_FILTER_ADDR, MURATA_GYRO_FILTER_300HZ));
for (num_attempts = 0; num_attempts < 2; num_attempts++) {
- HAL_Delay(405);
+ DelayWithWatchdog(405);
SendSpiDue(WRITE_EOI_BIT);
SendSpiUno(WRITE_EOI_BIT);
@@ -988,32 +1079,32 @@
/* UNO */
SendSpiUno(READ_SUMMARY_STATUS);
SendSpiUno(READ_SUMMARY_STATUS);
- HAL_Delay(3);
+ DelayWithWatchdog(3);
response_uno = SendSpiUno(READ_SUMMARY_STATUS);
uno_ok = !CHECK_RS_ERROR(response_uno);
/* DUE */
SendSpiDue(READ_SUMMARY_STATUS);
SendSpiDue(READ_SUMMARY_STATUS);
- HAL_Delay(3);
+ DelayWithWatchdog(3);
response_due = SendSpiDue(READ_SUMMARY_STATUS);
due_ok = !CHECK_RS_ERROR(response_due);
if ((due_ok == false || uno_ok == false) && (num_attempts == 0)) {
HAL_GPIO_WritePin(RESET_UNO_GPIO_Port, RESET_UNO_Pin,
GPIO_PIN_RESET); // Reset UNO
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_UNO_GPIO_Port, RESET_UNO_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin,
GPIO_PIN_RESET); // Reset DUE
- HAL_Delay(1);
+ DelayWithWatchdog(1);
HAL_GPIO_WritePin(RESET_DUE_GPIO_Port, RESET_DUE_Pin, GPIO_PIN_SET);
- HAL_Delay(25);
+ DelayWithWatchdog(25);
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiDue(WRITE_OP_MODE_NORMAL);
SendSpiUno(WRITE_OP_MODE_NORMAL);
- HAL_Delay(50);
+ DelayWithWatchdog(50);
SendSpiUno(
MakeSpiMsgMurata(MURATA_GYRO_FILTER_ADDR, MURATA_GYRO_FILTER_300HZ));
@@ -1021,7 +1112,7 @@
MakeSpiMsgMurata(MURATA_ACC_FILTER_ADDR, MURATA_ACC_FILTER_300HZ));
SendSpiDue(
MakeSpiMsgMurata(MURATA_GYRO_FILTER_ADDR, MURATA_GYRO_FILTER_300HZ));
- HAL_Delay(45);
+ DelayWithWatchdog(45);
} else {
break;
}
@@ -1041,7 +1132,7 @@
// Send 0x81 to PWR_MGMT to initialize SPI
SendSpiTdk(PWR_MGMT_1, 0x81, false);
- HAL_Delay(100);
+ DelayWithWatchdog(100);
// Setting the sample rates for TDK
SendSpiTdk(USER_CTRL, 0x55, false);
@@ -1100,6 +1191,7 @@
result = pwm_period * .9f;
}
TIM3->CCR3 = result;
+ last_pwm_watchdog_us = __HAL_TIM_GetCounter(&htim2);
break;
case TIM_CHANNEL_4:
@@ -1117,6 +1209,7 @@
result = pwm_period * .9f;
}
TIM3->CCR4 = result;
+ last_pwm_watchdog_us = __HAL_TIM_GetCounter(&htim2);
break;
default:
@@ -1377,6 +1470,7 @@
}
*res = SPI_READY;
+ last_spi_tdk_watchdog_us = __HAL_TIM_GetCounter(&htim2);
break;
}
}
@@ -1426,10 +1520,32 @@
}
*res = SPI_READY;
+ last_spi_uno_watchdog_us = __HAL_TIM_GetCounter(&htim2);
+ last_spi_due_watchdog_us = __HAL_TIM_GetCounter(&htim2);
break;
}
}
+static uint16_t GetWatchdogTimeoutMs(void) {
+ return (uint16_t)((uint32_t)(1000) * hiwdg.Init.Reload *
+ hiwdg.Init.Prescaler / LSI_CLOCK_FREQ_HZ);
+}
+
+static void DelayWithWatchdog(uint16_t delay_ms) {
+ // Delay without triggering watchdog reset. We do this by feeding the watchdog
+ // at least once during this interval; here we arbitrarily choose do it 3
+ // times. Note that this function will cause a delay of slightly longer than
+ // the requested due to nonzero compute time.
+ uint16_t watchdog_pet_period_ms = GetWatchdogTimeoutMs() / 3;
+ uint16_t remaining_delay_time_ms = delay_ms;
+ while (watchdog_pet_period_ms < remaining_delay_time_ms) {
+ HAL_Delay(watchdog_pet_period_ms);
+ HAL_IWDG_Refresh(&hiwdg);
+ remaining_delay_time_ms -= watchdog_pet_period_ms;
+ }
+ HAL_Delay(remaining_delay_time_ms);
+}
+
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
if (htim == &htim1) {
timer_index++;
@@ -1472,6 +1588,7 @@
}
}
can_tx_packet_counter += 3;
+ last_can_watchdog_us = __HAL_TIM_GetCounter(&htim2);
SpiTdk(tdk_data, &hspi1, &tdk_state, SPI_RUN);
SpiMurata(uno_data, &hspi2, &uno_state, SPI_RUN);
@@ -1519,7 +1636,7 @@
}
tdk_data[timer_index].state++;
- if (tdk_data[timer_index].state == 8) {
+ if (tdk_data[timer_index].state >= 8) {
SpiCsEnd(hspi);
tdk_data[timer_index].state = 0;
can_out.tdk_counter++;
diff --git a/frc971/imu_fdcan/Dual_IMU/Core/Src/stm32g4xx_hal_msp.c b/frc971/imu_fdcan/Dual_IMU/Core/Src/stm32g4xx_hal_msp.c
index f315dfa..e414210 100644
--- a/frc971/imu_fdcan/Dual_IMU/Core/Src/stm32g4xx_hal_msp.c
+++ b/frc971/imu_fdcan/Dual_IMU/Core/Src/stm32g4xx_hal_msp.c
@@ -1,3 +1,4 @@
+
/* USER CODE BEGIN Header */
/**
******************************************************************************
@@ -20,7 +21,6 @@
/* Includes ------------------------------------------------------------------*/
#include "main.h"
-
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/Core/Src/subdir.mk b/frc971/imu_fdcan/Dual_IMU/Debug/Core/Src/subdir.mk
index f4c8103..8fe9140 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/Core/Src/subdir.mk
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/Core/Src/subdir.mk
@@ -1,6 +1,6 @@
################################################################################
# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/Core/Startup/subdir.mk b/frc971/imu_fdcan/Dual_IMU/Debug/Core/Startup/subdir.mk
index 954a6be..d6b7b63 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/Core/Startup/subdir.mk
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/Core/Startup/subdir.mk
@@ -1,6 +1,6 @@
################################################################################
# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk b/frc971/imu_fdcan/Dual_IMU/Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk
index 07aee83..7d086fa 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk
@@ -1,6 +1,6 @@
################################################################################
# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
@@ -17,6 +17,7 @@
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \
+../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \
@@ -45,6 +46,7 @@
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o \
+./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o \
@@ -73,6 +75,7 @@
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d \
+./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d \
@@ -96,8 +99,8 @@
clean: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src
clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src:
- -$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.o
- -$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.su
+ -$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o
+ -$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.su
.PHONY: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/makefile b/frc971/imu_fdcan/Dual_IMU/Debug/makefile
index e7cf0db..eed7aeb 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/makefile
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/makefile
@@ -1,6 +1,6 @@
################################################################################
# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
-include ../makefile.init
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/objects.list b/frc971/imu_fdcan/Dual_IMU/Debug/objects.list
index 071b052..3fed242 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/objects.list
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/objects.list
@@ -17,6 +17,7 @@
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o"
+"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o"
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/objects.mk b/frc971/imu_fdcan/Dual_IMU/Debug/objects.mk
index 820854b..94e86f7 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/objects.mk
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/objects.mk
@@ -1,6 +1,6 @@
################################################################################
# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
USER_OBJS :=
diff --git a/frc971/imu_fdcan/Dual_IMU/Debug/sources.mk b/frc971/imu_fdcan/Dual_IMU/Debug/sources.mk
index aa5c15b..c9a4855 100644
--- a/frc971/imu_fdcan/Dual_IMU/Debug/sources.mk
+++ b/frc971/imu_fdcan/Dual_IMU/Debug/sources.mk
@@ -1,6 +1,6 @@
################################################################################
# Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (11.3.rel1)
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
ELF_SRCS :=
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h
index 59ffec4..da98cbe 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h
@@ -1058,10 +1058,8 @@
*/
typedef struct {
- __IO uint32_t GCR; /*!< SAI global configuration register, Address
- offset: 0x00 */
- uint32_t RESERVED[16]; /*!< Reserved, Address offset:
- 0x04 to 0x40 */
+ uint32_t RESERVED[17]; /*!< Reserved, Address
+ offset: 0x00 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address
offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address
@@ -1750,7 +1748,7 @@
/*
* @brief Specific device feature definitions (not present on all devices in the
- * STM32G4 serie)
+ * STM32G4 series)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific \
devices: multimode available on devices with \
@@ -1932,7 +1930,7 @@
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN \
@@ -5763,7 +5761,7 @@
#define FDCAN_ENDN_ETV_Msk \
(0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV \
- FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+ FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -7065,7 +7063,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9278,7 +9276,7 @@
#define OPAMP_CSR_OUTCAL_Msk \
(0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 \
*/
-#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK \
@@ -10557,7 +10555,7 @@
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in
- * the STM32G4 serie)
+ * the STM32G4 series)
*/
#define RCC_HSI48_SUPPORT
@@ -12673,21 +12671,18 @@
#define TAMP_CR2_TAMP3NOERASE_Msk \
(0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
-#define TAMP_CR2_TAMP1MF_Pos (16U)
-#define TAMP_CR2_TAMP1MF_Msk \
- (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 \
- */
-#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
-#define TAMP_CR2_TAMP2MF_Pos (17U)
-#define TAMP_CR2_TAMP2MF_Msk \
- (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 \
- */
-#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
-#define TAMP_CR2_TAMP3MF_Pos (18U)
-#define TAMP_CR2_TAMP3MF_Msk \
- (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 \
- */
-#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
+#define TAMP_CR2_TAMP1MSK_Pos (16U)
+#define TAMP_CR2_TAMP1MSK_Msk \
+ (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos (17U)
+#define TAMP_CR2_TAMP2MSK_Msk \
+ (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos (18U)
+#define TAMP_CR2_TAMP3MSK_Msk \
+ (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk \
(0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
@@ -12701,6 +12696,17 @@
(0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
+/* Legacy aliases */
+#define TAMP_CR2_TAMP1MF_Pos TAMP_CR2_TAMP1MSK_Pos
+#define TAMP_CR2_TAMP1MF_Msk TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MSK
+#define TAMP_CR2_TAMP2MF_Pos TAMP_CR2_TAMP2MSK_Pos
+#define TAMP_CR2_TAMP2MF_Msk TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MSK
+#define TAMP_CR2_TAMP3MF_Pos TAMP_CR2_TAMP3MSK_Pos
+#define TAMP_CR2_TAMP3MF_Msk TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MSK
+
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
@@ -13010,21 +13016,6 @@
/* Serial Audio Interface */
/* */
/******************************************************************************/
-/******************** Bit definition for SAI_GCR register *******************/
-#define SAI_GCR_SYNCIN_Pos (0U)
-#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
-#define SAI_GCR_SYNCIN \
- SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
-#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
-#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
-
-#define SAI_GCR_SYNCOUT_Pos (4U)
-#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
-#define SAI_GCR_SYNCOUT \
- SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
-#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
-
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
@@ -13526,7 +13517,7 @@
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the
- * STM32G4 serie)
+ * STM32G4 series)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
index 1a25fc5..300bb5f 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
@@ -1,245 +1,255 @@
-/**
- ******************************************************************************
- * @file stm32g4xx.h
- * @author MCD Application Team
- * @brief CMSIS STM32G4xx Device Peripheral Access Layer Header File.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file
- *contains:
- * - Configuration section that allows to select:
- * - The STM32G4xx device used in the target application
- * - To use or not the peripheralÂ’s drivers in application
- *code(i.e. code will be based on direct access to peripheralÂ’s registers rather
- *than drivers API), this option is controlled by
- * "#define USE_HAL_DRIVER"
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32g4xx
- * @{
- */
-
-#ifndef __STM32G4xx_H
-#define __STM32G4xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/**
- * @brief STM32 Family
- */
-#if !defined(STM32G4)
-#define STM32G4
-#endif /* STM32G4 */
-
-/* Uncomment the line below according to the target STM32G4 device used in your
- application
- */
-
-#if !defined(STM32G431xx) && !defined(STM32G441xx) && !defined(STM32G471xx) && \
- !defined(STM32G473xx) && !defined(STM32G474xx) && !defined(STM32G484xx) && \
- !defined(STM32GBK1CB) && !defined(STM32G491xx) && !defined(STM32G4A1xx)
-/* #define STM32G431xx */ /*!< STM32G431xx Devices */
-/* #define STM32G441xx */ /*!< STM32G441xx Devices */
-/* #define STM32G471xx */ /*!< STM32G471xx Devices */
-/* #define STM32G473xx */ /*!< STM32G473xx Devices */
-/* #define STM32G483xx */ /*!< STM32G483xx Devices */
-/* #define STM32G474xx */ /*!< STM32G474xx Devices */
-/* #define STM32G484xx */ /*!< STM32G484xx Devices */
-/* #define STM32G491xx */ /*!< STM32G491xx Devices */
-/* #define STM32G4A1xx */ /*!< STM32G4A1xx Devices */
-/* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler
- preprocessor.
- */
-#if !defined(USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code
- will be based on direct access to peripherals registers
- */
-/*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
- * @brief CMSIS Device version number V1.2.2
- */
-#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
-#define __STM32G4_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
-#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
-#define __STM32G4_CMSIS_VERSION \
- ((__STM32G4_CMSIS_VERSION_MAIN << 24) | \
- (__STM32G4_CMSIS_VERSION_SUB1 << 16) | \
- (__STM32G4_CMSIS_VERSION_SUB2 << 8) | (__STM32G4_CMSIS_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Device_Included
- * @{
- */
-
-#if defined(STM32G431xx)
-#include "stm32g431xx.h"
-#elif defined(STM32G441xx)
-#include "stm32g441xx.h"
-#elif defined(STM32G471xx)
-#include "stm32g471xx.h"
-#elif defined(STM32G473xx)
-#include "stm32g473xx.h"
-#elif defined(STM32G483xx)
-#include "stm32g483xx.h"
-#elif defined(STM32G474xx)
-#include "stm32g474xx.h"
-#elif defined(STM32G484xx)
-#include "stm32g484xx.h"
-#elif defined(STM32G491xx)
-#include "stm32g491xx.h"
-#elif defined(STM32G4A1xx)
-#include "stm32g4a1xx.h"
-#elif defined(STM32GBK1CB)
-#include "stm32gbk1cb.h"
-#else
-#error \
- "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)"
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
-
-typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum { SUCCESS = 0, ERROR = !SUCCESS } ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_macros
- * @{
- */
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
- WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
-
-/* Use of CMSIS compiler intrinsics for register exclusive access */
-/* Atomic 32-bit register access macro to set one or several bits */
-#define ATOMIC_SET_BIT(REG, BIT) \
- do { \
- uint32_t val; \
- do { \
- val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
- } while ((__STREXW(val, (__IO uint32_t *)&(REG))) != 0U); \
- } while (0)
-
-/* Atomic 32-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEAR_BIT(REG, BIT) \
- do { \
- uint32_t val; \
- do { \
- val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
- } while ((__STREXW(val, (__IO uint32_t *)&(REG))) != 0U); \
- } while (0)
-
-/* Atomic 32-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
- do { \
- uint32_t val; \
- do { \
- val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
- } while ((__STREXW(val, (__IO uint32_t *)&(REG))) != 0U); \
- } while (0)
-
-/* Atomic 16-bit register access macro to set one or several bits */
-#define ATOMIC_SETH_BIT(REG, BIT) \
- do { \
- uint16_t val; \
- do { \
- val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
- } while ((__STREXH(val, (__IO uint16_t *)&(REG))) != 0U); \
- } while (0)
-
-/* Atomic 16-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEARH_BIT(REG, BIT) \
- do { \
- uint16_t val; \
- do { \
- val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
- } while ((__STREXH(val, (__IO uint16_t *)&(REG))) != 0U); \
- } while (0)
-
-/* Atomic 16-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
- do { \
- uint16_t val; \
- do { \
- val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
- } while ((__STREXH(val, (__IO uint16_t *)&(REG))) != 0U); \
- } while (0)
-
-/**
- * @}
- */
-
-#if defined(USE_HAL_DRIVER)
-#include "stm32g4xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32G4xx_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32G4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file
+ *contains:
+ * - Configuration section that allows to select:
+ * - The STM32G4xx device used in the target application
+ * - To use or not the peripheralÂ’s drivers in application
+ *code(i.e. code will be based on direct access to peripheralÂ’s registers rather
+ *than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32g4xx
+ * @{
+ */
+
+#ifndef __STM32G4xx_H
+#define __STM32G4xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined(STM32G4)
+#define STM32G4
+#endif /* STM32G4 */
+
+/* Uncomment the line below according to the target STM32G4 device used in your
+ application
+ */
+
+#if !defined(STM32G431xx) && !defined(STM32G441xx) && !defined(STM32G471xx) && \
+ !defined(STM32G473xx) && !defined(STM32G474xx) && !defined(STM32G484xx) && \
+ !defined(STM32GBK1CB) && !defined(STM32G491xx) && !defined(STM32G4A1xx) && \
+ !defined(STM32G411xB) && !defined(STM32G411xC) && !defined(STM32G414xx)
+/* #define STM32G411xB */ /*!< STM32G411xB Devices */
+/* #define STM32G411xC */ /*!< STM32G411xC Devices */
+/* #define STM32G414xx */ /*!< STM32G414xx Devices */
+/* #define STM32G431xx */ /*!< STM32G431xx Devices */
+/* #define STM32G441xx */ /*!< STM32G441xx Devices */
+/* #define STM32G471xx */ /*!< STM32G471xx Devices */
+/* #define STM32G473xx */ /*!< STM32G473xx Devices */
+/* #define STM32G483xx */ /*!< STM32G483xx Devices */
+/* #define STM32G474xx */ /*!< STM32G474xx Devices */
+/* #define STM32G484xx */ /*!< STM32G484xx Devices */
+/* #define STM32G491xx */ /*!< STM32G491xx Devices */
+/* #define STM32G4A1xx */ /*!< STM32G4A1xx Devices */
+/* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler
+ preprocessor.
+ */
+#if !defined(USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code
+ will be based on direct access to peripherals registers
+ */
+/*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V1.2.5
+ */
+#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32G4_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
+#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32G4_CMSIS_VERSION \
+ ((__STM32G4_CMSIS_VERSION_MAIN << 24) | \
+ (__STM32G4_CMSIS_VERSION_SUB1 << 16) | \
+ (__STM32G4_CMSIS_VERSION_SUB2 << 8) | (__STM32G4_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32G431xx)
+#include "stm32g431xx.h"
+#elif defined(STM32G441xx)
+#include "stm32g441xx.h"
+#elif defined(STM32G471xx)
+#include "stm32g471xx.h"
+#elif defined(STM32G473xx)
+#include "stm32g473xx.h"
+#elif defined(STM32G483xx)
+#include "stm32g483xx.h"
+#elif defined(STM32G474xx)
+#include "stm32g474xx.h"
+#elif defined(STM32G484xx)
+#include "stm32g484xx.h"
+#elif defined(STM32G491xx)
+#include "stm32g491xx.h"
+#elif defined(STM32G4A1xx)
+#include "stm32g4a1xx.h"
+#elif defined(STM32GBK1CB)
+#include "stm32gbk1cb.h"
+#elif defined(STM32G411xB)
+#include "stm32g411xb.h"
+#elif defined(STM32G411xC)
+#include "stm32g411xc.h"
+#elif defined(STM32G414xx)
+#include "stm32g414xx.h"
+#else
+#error \
+ "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
+
+typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum { SUCCESS = 0, ERROR = !SUCCESS } ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
+ WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
+ } while ((__STREXW(val, (__IO uint32_t *)&(REG))) != 0U); \
+ } while (0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXW(val, (__IO uint32_t *)&(REG))) != 0U); \
+ } while (0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXW(val, (__IO uint32_t *)&(REG))) != 0U); \
+ } while (0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
+ } while ((__STREXH(val, (__IO uint16_t *)&(REG))) != 0U); \
+ } while (0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXH(val, (__IO uint16_t *)&(REG))) != 0U); \
+ } while (0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXH(val, (__IO uint16_t *)&(REG))) != 0U); \
+ } while (0)
+
+/**
+ * @}
+ */
+
+#if defined(USE_HAL_DRIVER)
+#include "stm32g4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32G4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
index 71a93a2..af30de1 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
@@ -1,103 +1,103 @@
-/**
- ******************************************************************************
- * @file system_stm32g4xx.h
- * @author MCD Application Team
- * @brief CMSIS Cortex-M4 Device System Source File for STM32G4xx devices.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32g4xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32G4XX_H
-#define __SYSTEM_STM32G4XX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32G4xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32G4xx_System_Exported_Variables
- * @{
- */
-/* The SystemCoreClock variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock
- frequency Note: If you use this function to configure the system clock; then
- there is no need to call the 2 first functions listed above, since
- SystemCoreClock variable is updated automatically.
-*/
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32G4xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32G4xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32G4xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32G4XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file system_stm32g4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32G4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32g4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32G4XX_H
+#define __SYSTEM_STM32G4XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32G4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Exported_Variables
+ * @{
+ */
+/* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock
+ frequency Note: If you use this function to configure the system clock; then
+ there is no need to call the 2 first functions listed above, since
+ SystemCoreClock variable is updated automatically.
+*/
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32G4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt
index 5306686..872e82b 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt
@@ -1,6 +1,6 @@
-This software component is provided to you as part of a software package and
-applicable license terms are in the Package_license file. If you received this
-software component outside of a package or without applicable license terms,
-the terms of the Apache-2.0 license shall apply.
-You may obtain a copy of the Apache-2.0 at:
-https://opensource.org/licenses/Apache-2.0
+This software component is provided to you as part of a software package and
+applicable license terms are in the Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply.
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 461a7d5..fa057b3 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -1,4351 +1,4800 @@
-/**
- ******************************************************************************
- * @file stm32_hal_legacy.h
- * @author MCD Application Team
- * @brief This file contains aliases definition for the STM32Cube HAL
- *constants macros and functions maintained for legacy purpose.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
-#define CRYP_DATATYPE_32B CRYP_NO_SWAP
-#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
-#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
-#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
-#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP ADC_REGULAR_GROUP
-#define INJECTED_GROUP ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT ADC_AWD_EVENT
-#define AWD1_EVENT ADC_AWD1_EVENT
-#define AWD2_EVENT ADC_AWD2_EVENT
-#define AWD3_EVENT ADC_AWD3_EVENT
-#define OVR_EVENT ADC_OVR_EVENT
-#define JQOVF_EVENT ADC_JQOVF_EVENT
-#define ALL_CHANNELS ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING \
- ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED \
- ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM \
- input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
-/* to the second dedicated IO (only for COMP2). */
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained
- * for legacy purpose
- * @{
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-#if defined(STM32U5)
-#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
-#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
-#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
-#endif /* STM32U5 */
-/**
- * @}
- */
-
-/** @defgroup CRC_Aliases CRC API aliases
- * @{
- */
-#define HAL_CRC_Input_Data_Reverse \
- HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse \
- for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse \
- HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse \
- for inter STM32 series compatibility */
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE 0x00000000U
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7) || defined(STM32U5)
-#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32U5)
-#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
-#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
-#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
-#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || \
- defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || \
- defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || \
- defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT \
- HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT \
- HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP \
- HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP \
- HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW OB_IWDG_SW
-#define OB_WDG_HW OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
-#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-#if defined(STM32U5)
-#define OB_USER_nRST_STOP OB_USER_NRST_STOP
-#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
-#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
-#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
-#define OB_USER_nBOOT0 OB_USER_NBOOT0
-#define OB_nBOOT0_RESET OB_NBOOT0_RESET
-#define OB_nBOOT0_SET OB_NBOOT0_SET
-#endif /* STM32U5 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained
- * for legacy purpose
- * @{
- */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster \
- HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-
-/**
- * @}
- */
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for
- * compatibility purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || \
- defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
- * @}
- */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
-/**
- * @}
- */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define GET_GPIO_SOURCE GPIO_GET_INDEX
-#define GET_GPIO_INDEX GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-
-#if defined(STM32H743xx) || defined(STM32H753xx) || defined(STM32H750xx) || \
- defined(STM32H742xx) || defined(STM32H745xx) || defined(STM32H755xx) || \
- defined(STM32H747xx) || defined(STM32H757xx)
-#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || \
- STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || \
- defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || \
- defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || \
- STM32H7 || STM32WB || STM32U5*/
-
-#if defined(STM32L1)
-#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-
-#if defined(STM32U5)
-#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
-#endif /* STM32U5 */
-/**
- * @}
- */
-
-/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#if defined(STM32U5)
-#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
-#endif /* STM32U5 */
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 \
- HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL \
- HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL \
- HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
- */
-#define HRTIM_EVENTSRC_1 (0x00000000U)
-#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
- */
-#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
-#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || \
- defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || \
- defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION \
- LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION \
- LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of
- * lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
-#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
-#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
-#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
-/**
- * @}
- */
-
-#if defined(STM32U5)
-#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
-#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
-#define LPTIM_CHANNEL_ALL 0x00000000U
-#endif /* STM32U5 */
-/**
- * @}
- */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
-/**
- * @}
- */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE NOR_WRITE
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || \
- defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-#if defined(STM32L4) || defined(STM32L5)
-#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
-#elif defined(STM32G4)
-#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
-#define I2S_IT_TXE I2S_IT_TXP
-#define I2S_IT_RXNE I2S_IT_RXP
-
-#define I2S_FLAG_TXE I2S_FLAG_TXP
-#define I2S_FLAG_RXNE I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
-#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained
- * for legacy purpose
- * @{
- */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define FORMAT_BIN RTC_FORMAT_BIN
-#define FORMAT_BCD RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
-
-#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines
- * maintained for legacy purpose
- * @{
- */
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
-#define SPI_FLAG_TXE SPI_FLAG_TXP
-#define SPI_FLAG_RXNE SPI_FLAG_RXP
-
-#define SPI_IT_TXE SPI_IT_TXP
-#define SPI_IT_RXNE SPI_IT_RXP
-
-#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
-#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
-#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
-#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER TIM_DMABASE_DIER
-#define TIM_DMABase_SR TIM_DMABASE_SR
-#define TIM_DMABase_EGR TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER TIM_DMABASE_CCER
-#define TIM_DMABase_CNT TIM_DMABASE_CNT
-#define TIM_DMABase_PSC TIM_DMABASE_PSC
-#define TIM_DMABase_ARR TIM_DMABASE_ARR
-#define TIM_DMABase_RCR TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3
-#define TIM_DMABase_OR TIM_DMABASE_OR
-
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
-
-#define __DIV_LPUART UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
- * @}
- */
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED USART_NACK_ENABLE
-#define USARTNACK_DISABLED USART_NACK_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define CFR_BASE WWDG_CFR_BASE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-#define VLAN_TAG ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR 0x00000100U
-#define ETH_MMCRIR 0x00000104U
-#define ETH_MMCTIR 0x00000108U
-#define ETH_MMCRIMR 0x0000010CU
-#define ETH_MMCTIMR 0x00000110U
-#define ETH_MMCTGFSCCR 0x0000014CU
-#define ETH_MMCTGFMSCCR 0x00000150U
-#define ETH_MMCTGFCR 0x00000168U
-#define ETH_MMCRFCECR 0x00000194U
-#define ETH_MMCRFAECR 0x00000198U
-#define ETH_MMCRGUFCR 0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ \
- 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC \
- transmitter) */
-#define ETH_MAC_TXFIFO_WAITING \
- 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC \
- transmitter */
-#define ETH_MAC_TXFIFO_WRITING \
- 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or \
- flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE \
- 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING \
- 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous \
- frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF \
- 0x00040000U /* MAC transmit frame controller: Generating and transmitting a \
- Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING \
- 0x00060000U /* MAC transmit frame controller: Transferring input frame for \
- transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE \
- 0x00010000U /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD \
- 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate \
- threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD \
- 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate \
- threshold */
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE \
- 0x00000000U /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA \
- 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS \
- 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) \
- */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING \
- 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE \
- 0x00000010U /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE \
- 0x00000000U /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE \
- 0x00000002U /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE \
- 0x00000004U /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE \
- 0x00000006U /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE \
- 0x00000001U /* MAC MII receive protocol engine active */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
-
-/**
- * @}
- */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || \
- defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
-/**
- * @}
- */
-#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || \
- defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) || \
- defined(STM32U5)
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
- * @{
- */
-#define HAL_DMA2D_DisableCLUT \
- HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort \
- for compatibility with legacy code */
-/**
- * @}
- */
-
-#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for
- * legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions
- * maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32U5)
-#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
-#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
-#endif /* STM32U5 */
-
-/**
- * @}
- */
-
-#if !defined(STM32F2)
-/** @defgroup HASH_alias HASH API alias
- * @{
- */
-#define HAL_HASHEx_IRQHandler \
- HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
-/**
- *
- * @}
- */
-#endif /* STM32F2 */
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || \
- defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for
- * legacy purpose
- * @{
- */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) \
- (((cmd) == ENABLE) ? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) \
- : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) \
- (((cmd) == ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() \
- : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) \
- (((cmd) == ENABLE) ? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd) \
- (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) \
- (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() \
- : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || \
- defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || \
- STM32H7B3xxQ || STM32H7B0xxQ */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for
- * legacy purpose
- * @{
- */
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) \
- (((cmd) == ENABLE) ? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus) \
- : HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || \
- defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
- defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || \
- defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || \
- defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || \
- STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || \
- STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || \
- defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
- defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || \
- defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || \
- STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT \
- HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA \
- HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA \
- HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA \
- HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
-#define CR_PMODE_BB CR_VOS_BB
-
-#define DBP_BitNumber DBP_BIT_NUMBER
-#define PVDE_BitNumber PVDE_BIT_NUMBER
-#define PMODE_BitNumber PMODE_BIT_NUMBER
-#define EWUP_BitNumber EWUP_BIT_NUMBER
-#define FPDS_BitNumber FPDS_BIT_NUMBER
-#define ODEN_BitNumber ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
-#define BRE_BitNumber BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for
- * legacy purpose
- * @{
- */
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for
- * legacy purpose
- * @{
- */
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError TIM_DMAError
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || \
- defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || \
- defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
- defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || \
- STM32F4 || STM32F7 || STM32L0 */
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig \
- HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
- * @}
- */
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for
- * legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros
- * ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define AES_IT_CC CRYP_IT_CC
-#define AES_IT_ERR CRYP_IT_ERR
-#define AES_FLAG_CCF CRYP_FLAG_CCF
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __ADC_ENABLE __HAL_ADC_ENABLE
-#define __ADC_DISABLE __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
-#define __ADC_IS_ENABLED ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED \
- ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR \
- ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED \
- ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION \
- ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION \
- ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER \
- ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1 ADC_SQR1
-#define __HAL_ADC_SMPR1 ADC_SMPR1
-#define __HAL_ADC_SMPR2 ADC_SMPR2
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#if defined(STM32F3)
-#define COMP_START __HAL_COMP_ENABLE
-#define COMP_STOP __HAL_COMP_DISABLE
-#define COMP_LOCK __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
- : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
- : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
- : __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
- : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-#endif
-#if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
- : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
- : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
- : __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
- : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-#endif
-#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || \
- defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
- ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
- ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
- : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
- ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
- ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
- : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
- ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
- ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
- ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
- ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
- ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
- ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \
- : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
- ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
- ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
- ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
- ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
- : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \
- : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \
- : __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
- : ((__FLAG__) == COMP_EXTI_LINE_COMP6) \
- ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \
- : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-#endif
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
- : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
- : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
- : __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
- : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
- : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
- : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
- (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
- ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
- : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
- : __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
- (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
- : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro */
-/* is COMP_FLAG_LOCK. */
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
-/* argument. */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \
- (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
- * @}
- */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#define HAL_COMP_Start_IT \
- HAL_COMP_Start /* Function considered as legacy as EXTI event or IT \
- configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT \
- HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT \
- configuration is done into HAL_COMP_Init() */
-/**
- * @}
- */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define IS_DAC_WAVE(WAVE) \
- (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define IS_WRPAREA IS_OB_WRPAREA
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE IS_FLASH_TYPEERASE
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
-#define __HAL_I2C_SPEED I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
-#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
-
-/**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE \
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE \
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE \
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE \
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE \
- __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE \
- __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE \
- __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE \
- __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE \
- HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE \
- HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \
- do { \
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE \
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE \
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE \
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE \
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER \
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER \
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() \
- do { \
- HAL_PWREx_DisablePVM1(); \
- HAL_PWREx_DisablePVM2(); \
- HAL_PWREx_DisablePVM3(); \
- HAL_PWREx_DisablePVM4(); \
- } while (0)
-#define __HAL_PWR_PVM_ENABLE() \
- do { \
- HAL_PWREx_EnablePVM1(); \
- HAL_PWREx_EnablePVM2(); \
- HAL_PWREx_EnablePVM3(); \
- HAL_PWREx_EnablePVM4(); \
- } while (0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE \
- HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE \
- HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER \
- __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER \
- __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
-
-#if defined(STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) \
- __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) \
- __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) \
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) \
- __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
- * @{
- */
-
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) \
- (((cmd) == ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() \
- : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED \
- __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED \
- __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET \
- ((void)0U) /* Not available on the \
- STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET \
- ((void)0U) /* Not available on the STM32H7*/
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE \
- __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED \
- __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED \
- __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE \
- __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE \
- __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED \
- __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED \
- __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() \
- __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() \
- __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() \
- __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() \
- __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() \
- __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() \
- __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() \
- __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() \
- __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() \
- __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() \
- __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() \
- __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() \
- __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() \
- __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() \
- __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE RCC_IT_LSECSS
-#define RCC_IT_CSSHSE RCC_IT_CSS
-
-#define RCC_PLLMUL_3 RCC_PLL_MUL3
-#define RCC_PLLMUL_4 RCC_PLL_MUL4
-#define RCC_PLLMUL_6 RCC_PLL_MUL6
-#define RCC_PLLMUL_8 RCC_PLL_MUL8
-#define RCC_PLLMUL_12 RCC_PLL_MUL12
-#define RCC_PLLMUL_16 RCC_PLL_MUL16
-#define RCC_PLLMUL_24 RCC_PLL_MUL24
-#define RCC_PLLMUL_32 RCC_PLL_MUL32
-#define RCC_PLLMUL_48 RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2 RCC_PLL_DIV2
-#define RCC_PLLDIV_3 RCC_PLL_DIV3
-#define RCC_PLLDIV_4 RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV RCC_MCODIV_1
-#define RCC_MCO_DIV1 RCC_MCODIV_1
-#define RCC_MCO_DIV2 RCC_MCODIV_2
-#define RCC_MCO_DIV4 RCC_MCODIV_4
-#define RCC_MCO_DIV8 RCC_MCODIV_8
-#define RCC_MCO_DIV16 RCC_MCODIV_16
-#define RCC_MCO_DIV32 RCC_MCODIV_32
-#define RCC_MCO_DIV64 RCC_MCODIV_64
-#define RCC_MCO_DIV128 RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || \
- defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
-#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB RCC_CR_HSION_BB
-#define CR_CSSON_BB RCC_CR_CSSON_BB
-#define CR_PLLON_BB RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB RCC_CR_MSION_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB RCC_CR_HSEON_BB
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER \
- __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER \
- __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB \
- __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB \
- __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED \
- __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED \
- __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
-#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
-#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
-#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
-#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
-#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
-#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
-#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
-#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
-#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
-#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
-#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
-#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
-#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
-#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
-#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
-#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define HAL_RNG_ReadyCallback(__HANDLE__) \
- HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#if defined(STM32G0) || defined(STM32L5) || defined(STM32L412xx) || \
- defined(STM32L422xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32G4) || defined(STM32WL) || defined(STM32U5)
-#else
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined(STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) \
- __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) \
- __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) \
- __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) \
- __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) \
- __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
- ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \
- : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
- ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() \
- : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
- ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \
- : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
- ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() \
- : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
- ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \
- : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
- ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() \
- : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
- ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \
- : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
- ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() \
- : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
- ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() \
- : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
- ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() \
- : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif /* STM32F1 */
-
-#define IS_ALARM IS_RTC_ALARM
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK
-#define IS_TAMPER IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION \
- IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && \
- !defined(STM32F7) && !defined(STM32L1)
-#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
-#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
-#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
-
-#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
-#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
-#endif
-
-#if defined(STM32F4) || defined(STM32F2)
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define SDMMC1_IRQn SDIO_IRQn
-#define SDMMC1_IRQHandler SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define SDIO_IRQn SDMMC1_IRQn
-#define SDIO_IRQHandler SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || \
- defined(STM32L4) || defined(STM32H7)
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback \
- HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback \
- HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback \
- HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback \
- HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback \
- HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback \
- HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback \
- HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback \
- HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback \
- HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros
- * maintained for legacy purpose
- * @{
- */
-
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
-
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
-#define __USART_ENABLE __HAL_USART_ENABLE
-#define __USART_DISABLE __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
-#define USART_OVERSAMPLING_16 0x00000000U
-#define USART_OVERSAMPLING_8 USART_CR1_OVER8
-
-#define IS_USART_OVERSAMPLING(__SAMPLING__) \
- (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-#endif /* STM32F0 || STM32F3 || STM32F7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER \
- __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER \
- __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER \
- __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER \
- __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER \
- __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER \
- __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT \
- __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER \
- __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER \
- __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER \
- __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT \
- __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER \
- __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER \
- __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER \
- __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
- * @}
- */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained
- * for legacy purpose
- * @{
- */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained
- * for legacy purpose
- * @{
- */
-#if defined(STM32H7) || defined(STM32G4) || defined(STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained
- * for legacy purpose
- * @{
- */
-#if defined(STM32F7)
-#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
-#endif /* STM32F7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for
- * legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL
+ *constants macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+#if defined(STM32H7) || defined(STM32MP1)
+#define CRYP_DATATYPE_32B CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#endif /* STM32H7 || STM32MP1 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING \
+ ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED \
+ ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM \
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG \
+ __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained
+ * for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse \
+ HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse \
+ for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse \
+ HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse \
+ for inter STM32 series compatibility */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined(STM32U5)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || \
+ defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || \
+ defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || \
+ defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT \
+ HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT \
+ HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP \
+ HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP \
+ HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && \
+ !defined(STM32H7)
+#define PAGESIZE FLASH_PAGE_SIZE
+#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0) || defined(STM32C0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
+#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained
+ * for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster \
+ HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+#if defined(STM32U5)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster \
+ HAL_SYSCFG_DisableIOAnalogBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection \
+ HAL_SYSCFG_EnableIOAnalogVoltageSelection
+#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection \
+ HAL_SYSCFG_DisableIOAnalogVoltageSelection
+
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS \
+ __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS \
+ __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster \
+ HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster \
+ HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for
+ * compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || \
+ defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+
+#if defined(STM32H743xx) || defined(STM32H753xx) || defined(STM32H750xx) || \
+ defined(STM32H742xx) || defined(STM32H745xx) || defined(STM32H755xx) || \
+ defined(STM32H747xx) || defined(STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || \
+ STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || \
+ defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || \
+ defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || \
+ STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+
+#if defined(STM32WBA)
+#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
+#endif /* STM32WBA */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 \
+ HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
+#define HRTIMInterruptResquests HRTIMInterruptRequests
+#endif /* STM32F3 || STM32G4 || STM32H7 */
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL \
+ HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL \
+ HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+#endif /* STM32F3 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || \
+ defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || \
+ defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION \
+ LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION \
+ LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of
+ * lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || \
+ defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
+
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained
+ * for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+#if defined(STM32H5) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH \
+ TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines
+ * maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ \
+ 0x00100000U /* Tx FIFO read status: Read (transferring data to \
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING \
+ 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from \
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING \
+ 0x00300000U /* Tx FIFO read status: Writing the received TxStatus \
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE \
+ 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING \
+ 0x00020000U /* MAC transmit frame controller: Waiting for Status \
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF \
+ 0x00040000U /* MAC transmit frame controller: Generating and \
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING \
+ 0x00060000U /* MAC transmit frame controller: Transferring input \
+ frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE \
+ 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD \
+ 0x00000100U /* Rx FIFO fill level: fill-level below flow-control \
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD \
+ 0x00000200U /* Rx FIFO fill level: fill-level above flow-control \
+ activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE \
+ 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA \
+ 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS \
+ 0x00000040U /* Rx FIFO read controller Reading frame status \
+ (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING \
+ 0x00000060U /* Rx FIFO read controller Flushing the frame data and \
+ status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE \
+ 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE \
+ 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE \
+ 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE \
+ 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE \
+ 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE \
+ 0x00000001U /* MAC MII receive protocol engine active */
+
+#define ETH_TxPacketConfig \
+ ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure \
+ definition */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || \
+ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || \
+ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) || \
+ defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT \
+ HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort \
+ for compatibility with legacy code */
+/**
+ * @}
+ */
+
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for
+ * legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions
+ * maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler \
+ HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
+/**
+ *
+ * @}
+ */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || \
+ defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) \
+ (((cmd) == ENABLE) ? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) \
+ : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) \
+ (((cmd) == ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() \
+ : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) \
+ (((cmd) == ENABLE) ? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) \
+ (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) \
+ (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() \
+ : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || \
+ defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || \
+ STM32H7B3xxQ || STM32H7B0xxQ */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) \
+ (((cmd) == ENABLE) ? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus) \
+ : HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || \
+ defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || \
+ defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || \
+ STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || \
+ STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || \
+ defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || \
+ defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || \
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT \
+ HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA \
+ HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA \
+ HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA \
+ HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+#if defined(STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for
+ * legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || \
+ defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || \
+ defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || \
+ STM32F4 || STM32F7 || STM32L0 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig \
+ HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for
+ * legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros
+ * ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED \
+ ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR \
+ ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED \
+ ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION \
+ ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION \
+ ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER \
+ ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
+ : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
+ : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
+ : __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
+ : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
+ : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
+ : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
+ : __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
+ : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || \
+ defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
+ ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
+ ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
+ ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
+ ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
+ ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
+ ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
+ ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
+ ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
+ ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
+ ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \
+ : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
+ ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
+ ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
+ ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) \
+ ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
+ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \
+ : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \
+ : __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
+ : ((__FLAG__) == COMP_EXTI_LINE_COMP6) \
+ ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \
+ : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
+ : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
+ : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
+ : __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
+ : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
+ : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
+ : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
+ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
+ ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
+ : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
+ : __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
+ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
+ : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \
+ (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT \
+ HAL_COMP_Start /* Function considered as legacy as EXTI event or IT \
+ configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT \
+ HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT \
+ configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) \
+ (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE \
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE \
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE \
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE \
+ __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE \
+ __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE \
+ __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE \
+ __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE \
+ HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE \
+ HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \
+ do { \
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE \
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE \
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE \
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER \
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER \
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() \
+ do { \
+ HAL_PWREx_DisablePVM1(); \
+ HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3(); \
+ HAL_PWREx_DisablePVM4(); \
+ } while (0)
+#define __HAL_PWR_PVM_ENABLE() \
+ do { \
+ HAL_PWREx_EnablePVM1(); \
+ HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3(); \
+ HAL_PWREx_EnablePVM4(); \
+ } while (0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE \
+ HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE \
+ HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER \
+ __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER \
+ __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined(STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) \
+ __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) \
+ __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) \
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) \
+ __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) \
+ (((cmd) == ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() \
+ : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#if defined(STM32C0)
+#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
+#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
+#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
+#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
+#endif /* STM32C0 */
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED \
+ __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED \
+ __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET \
+ ((void)0U) /* Not available on the \
+ STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET \
+ ((void)0U) /* Not available on the STM32H7*/
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE \
+ __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED \
+ __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED \
+ __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE \
+ __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE \
+ __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED \
+ __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED \
+ __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() \
+ __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() \
+ __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() \
+ __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() \
+ __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() \
+ __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() \
+ __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() \
+ __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() \
+ __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() \
+ __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() \
+ __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() \
+ __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() \
+ __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() \
+ __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() \
+ __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || \
+ defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || \
+ defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER \
+ __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER \
+ __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB \
+ __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB \
+ __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED \
+ __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED \
+ __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+#endif /* STM32H5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) \
+ HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#if defined(STM32G0) || defined(STM32L5) || defined(STM32L412xx) || \
+ defined(STM32L422xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32G4) || defined(STM32WL) || defined(STM32U5) || \
+ defined(STM32WBA) || defined(STM32H5) || defined(STM32C0) || \
+ defined(STM32H7RS) || defined(STM32U0)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined(STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) \
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) \
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) \
+ __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) \
+ __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) \
+ __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
+ ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \
+ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
+ ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() \
+ : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
+ ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \
+ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
+ ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() \
+ : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
+ ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \
+ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
+ ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() \
+ : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
+ ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \
+ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
+ ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() \
+ : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
+ ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() \
+ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) \
+ ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() \
+ : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#if defined(STM32F0) || defined(STM32F2) || defined(STM32F3) || \
+ defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || \
+ defined(STM32L0) || defined(STM32L1) || defined(STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION \
+ IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+#if defined(STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && \
+ !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || \
+ defined(STM32L4) || defined(STM32H7)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback \
+ HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback \
+ HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback \
+ HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback \
+ HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback \
+ HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback \
+ HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback \
+ HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback \
+ HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback \
+ HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros
+ * maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) \
+ (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER \
+ __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER \
+ __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER \
+ __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER \
+ __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER \
+ __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER \
+ __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT \
+ __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER \
+ __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER \
+ __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER \
+ __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT \
+ __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER \
+ __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER \
+ __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER \
+ __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained
+ * for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained
+ * for legacy purpose
+ * @{
+ */
+#if defined(STM32H7) || defined(STM32G4) || defined(STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained
+ * for legacy purpose
+ * @{
+ */
+#if defined(STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for
+ * legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
index c750d6b..ec0bcfa 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
@@ -1,770 +1,782 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the HAL
- * module driver.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_H
-#define STM32G4xx_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_conf.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL HAL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
- */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
- * @{
- */
-#define HAL_TICK_FREQ_10HZ 100U
-#define HAL_TICK_FREQ_100HZ 10U
-#define HAL_TICK_FREQ_1KHZ 1U
-#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
- * @{
- */
-
-/** @defgroup SYSCFG_BootMode Boot Mode
- * @{
- */
-#define SYSCFG_BOOT_MAINFLASH 0x00000000U
-#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
-
-#if defined(FMC_BANK1)
-#define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1
-#endif /* FMC_BANK1 */
-
-#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
-
-#if defined(QUADSPI)
-#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
-#endif /* QUADSPI */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
- * @{
- */
-#define SYSCFG_IT_FPU_IOC \
- SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt \
- */
-#define SYSCFG_IT_FPU_DZC \
- SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
-#define SYSCFG_IT_FPU_UFC \
- SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
-#define SYSCFG_IT_FPU_OFC \
- SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
-#define SYSCFG_IT_FPU_IDC \
- SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
-#define SYSCFG_IT_FPU_IXC \
- SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
- * @{
- */
-#define SYSCFG_CCMSRAMWRP_PAGE0 \
- SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
-#define SYSCFG_CCMSRAMWRP_PAGE1 \
- SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
-#define SYSCFG_CCMSRAMWRP_PAGE2 \
- SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
-#define SYSCFG_CCMSRAMWRP_PAGE3 \
- SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
-#define SYSCFG_CCMSRAMWRP_PAGE4 \
- SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
-#define SYSCFG_CCMSRAMWRP_PAGE5 \
- SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
-#define SYSCFG_CCMSRAMWRP_PAGE6 \
- SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
-#define SYSCFG_CCMSRAMWRP_PAGE7 \
- SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
-#define SYSCFG_CCMSRAMWRP_PAGE8 \
- SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
-#define SYSCFG_CCMSRAMWRP_PAGE9 \
- SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
-#define SYSCFG_CCMSRAMWRP_PAGE10 \
- SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
-#define SYSCFG_CCMSRAMWRP_PAGE11 \
- SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
-#define SYSCFG_CCMSRAMWRP_PAGE12 \
- SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
-#define SYSCFG_CCMSRAMWRP_PAGE13 \
- SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
-#define SYSCFG_CCMSRAMWRP_PAGE14 \
- SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
-#define SYSCFG_CCMSRAMWRP_PAGE15 \
- SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
-#define SYSCFG_CCMSRAMWRP_PAGE16 \
- SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
-#define SYSCFG_CCMSRAMWRP_PAGE17 \
- SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
-#define SYSCFG_CCMSRAMWRP_PAGE18 \
- SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
-#define SYSCFG_CCMSRAMWRP_PAGE19 \
- SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
-#define SYSCFG_CCMSRAMWRP_PAGE20 \
- SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
-#define SYSCFG_CCMSRAMWRP_PAGE21 \
- SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
-#define SYSCFG_CCMSRAMWRP_PAGE22 \
- SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
-#define SYSCFG_CCMSRAMWRP_PAGE23 \
- SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
-#define SYSCFG_CCMSRAMWRP_PAGE24 \
- SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
-#define SYSCFG_CCMSRAMWRP_PAGE25 \
- SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
-#define SYSCFG_CCMSRAMWRP_PAGE26 \
- SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
-#define SYSCFG_CCMSRAMWRP_PAGE27 \
- SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
-#define SYSCFG_CCMSRAMWRP_PAGE28 \
- SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
-#define SYSCFG_CCMSRAMWRP_PAGE29 \
- SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
-#define SYSCFG_CCMSRAMWRP_PAGE30 \
- SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
-#define SYSCFG_CCMSRAMWRP_PAGE31 \
- SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
-
-/**
- * @}
- */
-
-#if defined(VREFBUF)
-/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
- * @{
- */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 \
- 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 \
- VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 \
- VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
- * @{
- */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE \
- 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference \
- buffer output */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE \
- VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
-
-/**
- * @}
- */
-#endif /* VREFBUF */
-
-/** @defgroup SYSCFG_flags_definition Flags
- * @{
- */
-
-#define SYSCFG_FLAG_SRAM_PE \
- SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
-#define SYSCFG_FLAG_CCMSRAM_BUSY \
- SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
- * @{
- */
-
-/** @brief Fast-mode Plus driving capability on a specific GPIO
- */
-#define SYSCFG_FASTMODEPLUS_PB6 \
- SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
-#define SYSCFG_FASTMODEPLUS_PB7 \
- SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
-#define SYSCFG_FASTMODEPLUS_PB8 \
- SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
-#define SYSCFG_FASTMODEPLUS_PB9 \
- SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
- * @{
- */
-
-/** @brief Freeze/Unfreeze Peripherals in Debug mode
- */
-#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM2() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM3() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM4() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM5() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM6() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM7() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#define __HAL_DBGMCU_FREEZE_RTC() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#define __HAL_DBGMCU_UNFREEZE_RTC() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_WWDG() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_IWDG() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
-
-#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM1() \
- SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1() \
- CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
-
-#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() \
- SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() \
- CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
-#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM1() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM8() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM8() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM15() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM15() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM16() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM17() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM20() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM20() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
-
-#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_HRTIM1() \
- SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_HRTIM1() \
- CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
-#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
- * @{
- */
-
-/** @brief Main Flash memory mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH() \
- CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief System Flash memory mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() \
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
-
-/** @brief Embedded SRAM mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, \
- (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0))
-
-#if defined(FMC_BANK1)
-/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC() \
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-/** @brief QUADSPI mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() \
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, \
- (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1))
-#endif /* QUADSPI */
-
-/**
- * @brief Return the boot mode as configured by user.
- * @retval The boot mode as configured by user. The returned value can be one
- * of the following values:
- * @arg @ref SYSCFG_BOOT_MAINFLASH
- * @arg @ref SYSCFG_BOOT_SYSTEMFLASH
- * @arg @ref SYSCFG_BOOT_FMC (*)
- * @arg @ref SYSCFG_BOOT_QUADSPI (*)
- * @arg @ref SYSCFG_BOOT_SRAM
- * @note (*) availability depends on devices
- */
-#define __HAL_SYSCFG_GET_BOOT_MODE() \
- READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief CCMSRAM page write protection enable macro
- * @param __CCMSRAMWRP__: This parameter can be a value of @ref
- * SYSCFG_CCMSRAMWRP
- * @note write protection can only be disabled by a system reset
- * @retval None
- */
-/* Legacy define */
-#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE \
- __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
-#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) \
- do { \
- assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__))); \
- SET_BIT(SYSCFG->SWPR, (__CCMSRAMWRP__)); \
- } while (0)
-
-/** @brief CCMSRAM page write protection unlock prior to erase
- * @note Writing a wrong key reactivates the write protection
- */
-#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() \
- do { \
- SYSCFG->SKR = 0xCA; \
- SYSCFG->SKR = 0x53; \
- } while (0)
-
-/** @brief CCMSRAM erase
- * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end
- * of erase
- */
-#define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
-
-/** @brief Floating Point Unit interrupt enable/disable macros
- * @param __INTERRUPT__: This parameter can be a value of @ref
- * SYSCFG_FPU_Interrupts
- */
-#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) \
- do { \
- assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \
- SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \
- } while (0)
-
-#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) \
- do { \
- assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \
- CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \
- } while (0)
-
-/** @brief SYSCFG Break ECC lock.
- * Enable and lock the connection of Flash ECC error connection to
- * TIM1/8/15/16/17 Break input.
- * @note The selected configuration is locked and can be unlocked only by
- * system reset.
- */
-#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
-
-/** @brief SYSCFG Break Cortex-M4 Lockup lock.
- * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output
- * to TIM1/8/15/16/17 Break input.
- * @note The selected configuration is locked and can be unlocked only by
- * system reset.
- */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() \
- SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
-
-/** @brief SYSCFG Break PVD lock.
- * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input,
- * as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
- * @note The selected configuration is locked and can be unlocked only by
- * system reset.
- */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
-
-/** @brief SYSCFG Break SRAM parity lock.
- * Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM
- * SRAM) signal connection to TIM1/8/15/16/17 Break input.
- * @note The selected configuration is locked and can be unlocked by system
- * reset.
- */
-#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() \
- SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
-
-/** @brief Check SYSCFG flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag
- * @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) \
- ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY) ? SYSCFG->SCSR : SYSCFG->CFGR2) & \
- (__FLAG__)) != 0U) \
- ? 1U \
- : 0U)
-
-/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
- */
-#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
-
-/** @brief Fast-mode Plus driving capability enable/disable macros
- * @param __FASTMODEPLUS__: This parameter can be a value of :
- * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability
- * activation on PB6
- * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability
- * activation on PB7
- * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability
- * activation on PB8
- * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability
- * activation on PB9
- */
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
- do { \
- assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
- SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__)); \
- } while (0)
-
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
- do { \
- assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
- CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__)); \
- } while (0)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
- * @{
- */
-
-#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) \
- ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
-
-#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) \
- (((__CONFIG__) == SYSCFG_BREAK_ECC) || ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
- ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \
- ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
-
-#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL)
-#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U)
-#elif (CCMSRAM_SIZE == 0x00002800UL)
-#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) \
- (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
-#endif /* CCMSRAM_SIZE */
-
-#if defined(VREFBUF)
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) \
- (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
-
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) \
- (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
- ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
-
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) \
- (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
-#endif /* VREFBUF */
-
-#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
- ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#elif defined(SYSCFG_FASTMODEPLUS_PB8)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
- ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
-#elif defined(SYSCFG_FASTMODEPLUS_PB9)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
- ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#else
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
- ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
-#endif /* SYSCFG_FASTMODEPLUS_PB */
-/**
- * @}
- */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
- * @{
- */
-#define IS_TICKFREQ(FREQ) \
- (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || \
- ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Functions
- * @{
- */
-
-/** @addtogroup HAL_Exported_Functions_Group1
- * @{
- */
-/* Initialization and Configuration functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
-
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
- * @{
- */
-
-/* Peripheral Control functions
- * ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
-uint32_t HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group3
- * @{
- */
-
-/* DBGMCU Peripheral Control functions
- * *****************************************/
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-
-/**
- * @}
- */
-
-/* Exported variables
- * ---------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
- * @{
- */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern uint32_t uwTickFreq;
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group4
- * @{
- */
-
-/* SYSCFG Control functions
- * ****************************************************/
-void HAL_SYSCFG_CCMSRAMErase(void);
-void HAL_SYSCFG_EnableMemorySwappingBank(void);
-void HAL_SYSCFG_DisableMemorySwappingBank(void);
-
-#if defined(VREFBUF)
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
-void HAL_SYSCFG_DisableVREFBUF(void);
-#endif /* VREFBUF */
-
-void HAL_SYSCFG_EnableIOSwitchBooster(void);
-void HAL_SYSCFG_DisableIOSwitchBooster(void);
-void HAL_SYSCFG_EnableIOSwitchVDD(void);
-void HAL_SYSCFG_DisableIOSwitchVDD(void);
-
-void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_H
+#define STM32G4xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_conf.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+#define HAL_TICK_FREQ_10HZ 100U
+#define HAL_TICK_FREQ_100HZ 10U
+#define HAL_TICK_FREQ_1KHZ 1U
+#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+ * @{
+ */
+#define SYSCFG_BOOT_MAINFLASH 0x00000000U
+#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
+
+#if defined(FMC_BANK1)
+#define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1
+#endif /* FMC_BANK1 */
+
+#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
+
+#if defined(QUADSPI)
+#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
+#endif /* QUADSPI */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+ * @{
+ */
+#define SYSCFG_IT_FPU_IOC \
+ SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt \
+ */
+#define SYSCFG_IT_FPU_DZC \
+ SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC \
+ SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC \
+ SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC \
+ SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC \
+ SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
+ * @{
+ */
+#define SYSCFG_CCMSRAMWRP_PAGE0 \
+ SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_CCMSRAMWRP_PAGE1 \
+ SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_CCMSRAMWRP_PAGE2 \
+ SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_CCMSRAMWRP_PAGE3 \
+ SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_CCMSRAMWRP_PAGE4 \
+ SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_CCMSRAMWRP_PAGE5 \
+ SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_CCMSRAMWRP_PAGE6 \
+ SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_CCMSRAMWRP_PAGE7 \
+ SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_CCMSRAMWRP_PAGE8 \
+ SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_CCMSRAMWRP_PAGE9 \
+ SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_CCMSRAMWRP_PAGE10 \
+ SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
+#define SYSCFG_CCMSRAMWRP_PAGE11 \
+ SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
+#define SYSCFG_CCMSRAMWRP_PAGE12 \
+ SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
+#define SYSCFG_CCMSRAMWRP_PAGE13 \
+ SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
+#define SYSCFG_CCMSRAMWRP_PAGE14 \
+ SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
+#define SYSCFG_CCMSRAMWRP_PAGE15 \
+ SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
+#define SYSCFG_CCMSRAMWRP_PAGE16 \
+ SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
+#define SYSCFG_CCMSRAMWRP_PAGE17 \
+ SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
+#define SYSCFG_CCMSRAMWRP_PAGE18 \
+ SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
+#define SYSCFG_CCMSRAMWRP_PAGE19 \
+ SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
+#define SYSCFG_CCMSRAMWRP_PAGE20 \
+ SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
+#define SYSCFG_CCMSRAMWRP_PAGE21 \
+ SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
+#define SYSCFG_CCMSRAMWRP_PAGE22 \
+ SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
+#define SYSCFG_CCMSRAMWRP_PAGE23 \
+ SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
+#define SYSCFG_CCMSRAMWRP_PAGE24 \
+ SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
+#define SYSCFG_CCMSRAMWRP_PAGE25 \
+ SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
+#define SYSCFG_CCMSRAMWRP_PAGE26 \
+ SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
+#define SYSCFG_CCMSRAMWRP_PAGE27 \
+ SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
+#define SYSCFG_CCMSRAMWRP_PAGE28 \
+ SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
+#define SYSCFG_CCMSRAMWRP_PAGE29 \
+ SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
+#define SYSCFG_CCMSRAMWRP_PAGE30 \
+ SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
+#define SYSCFG_CCMSRAMWRP_PAGE31 \
+ SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
+
+/**
+ * @}
+ */
+
+#if defined(VREFBUF)
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+ * @{
+ */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 \
+ 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 \
+ VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 \
+ VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+ * @{
+ */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE \
+ 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference \
+ buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE \
+ VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
+
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSCFG_flags_definition Flags
+ * @{
+ */
+
+#define SYSCFG_FLAG_SRAM_PE \
+ SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
+#define SYSCFG_FLAG_CCMSRAM_BUSY \
+ SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+
+/** @brief Fast-mode Plus driving capability on a specific GPIO
+ */
+#define SYSCFG_FASTMODEPLUS_PB6 \
+ SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7 \
+ SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8 \
+ SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9 \
+ SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+ * @{
+ */
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1() \
+ SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() \
+ CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() \
+ SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() \
+ CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM20() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM20() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_HRTIM1() \
+ SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HRTIM1() \
+ CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+ * @{
+ */
+
+/** @brief Main Flash memory mapped at 0x00000000.
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() \
+ CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief System Flash memory mapped at 0x00000000.
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() \
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
+
+/** @brief Embedded SRAM mapped at 0x00000000.
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, \
+ (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0))
+
+#if defined(FMC_BANK1)
+/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC() \
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+/** @brief QUADSPI mapped at 0x00000000.
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() \
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, \
+ (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1))
+#endif /* QUADSPI */
+
+/**
+ * @brief Return the boot mode as configured by user.
+ * @retval The boot mode as configured by user. The returned value can be one
+ * of the following values:
+ * @arg @ref SYSCFG_BOOT_MAINFLASH
+ * @arg @ref SYSCFG_BOOT_SYSTEMFLASH
+ * @arg @ref SYSCFG_BOOT_FMC (*)
+ * @arg @ref SYSCFG_BOOT_QUADSPI (*)
+ * @arg @ref SYSCFG_BOOT_SRAM
+ * @note (*) availability depends on devices
+ */
+#define __HAL_SYSCFG_GET_BOOT_MODE() \
+ READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief CCMSRAM page write protection enable macro
+ * @param __CCMSRAMWRP__: This parameter can be a value of @ref
+ * SYSCFG_CCMSRAMWRP
+ * @note write protection can only be disabled by a system reset
+ * @retval None
+ */
+/* Legacy define */
+#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE \
+ __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
+#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) \
+ do { \
+ assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__))); \
+ SET_BIT(SYSCFG->SWPR, (__CCMSRAMWRP__)); \
+ } while (0)
+
+/** @brief CCMSRAM page write protection unlock prior to erase
+ * @note Writing a wrong key reactivates the write protection
+ */
+#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() \
+ do { \
+ SYSCFG->SKR = 0xCA; \
+ SYSCFG->SKR = 0x53; \
+ } while (0)
+
+/** @brief CCMSRAM erase
+ * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end
+ * of erase
+ */
+#define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
+
+/** @brief Floating Point Unit interrupt enable/disable macros
+ * @param __INTERRUPT__: This parameter can be a value of @ref
+ * SYSCFG_FPU_Interrupts
+ */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) \
+ do { \
+ assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \
+ SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \
+ } while (0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) \
+ do { \
+ assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \
+ CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \
+ } while (0)
+
+/** @brief SYSCFG Break ECC lock.
+ * Enable and lock the connection of Flash ECC error connection to
+ * TIM1/8/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked only by
+ * system reset.
+ */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief SYSCFG Break Cortex-M4 Lockup lock.
+ * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output
+ * to TIM1/8/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked only by
+ * system reset.
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() \
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief SYSCFG Break PVD lock.
+ * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input,
+ * as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
+ * @note The selected configuration is locked and can be unlocked only by
+ * system reset.
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief SYSCFG Break SRAM parity lock.
+ * Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM
+ * SRAM) signal connection to TIM1/8/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked by system
+ * reset.
+ */
+#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() \
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief Check SYSCFG flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag
+ * @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__) \
+ ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY) ? SYSCFG->SCSR : SYSCFG->CFGR2) & \
+ (__FLAG__)) != 0U) \
+ ? 1U \
+ : 0U)
+
+/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
+ */
+#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__: This parameter can be a value of :
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability
+ * activation on PB6
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability
+ * activation on PB7
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability
+ * activation on PB8
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability
+ * activation on PB9
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
+ do { \
+ assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__)); \
+ } while (0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
+ do { \
+ assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__)); \
+ } while (0)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+ * @{
+ */
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) \
+ ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) \
+ (((__CONFIG__) == SYSCFG_BREAK_ECC) || ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
+ ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \
+ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+
+#if (CCMSRAM_SIZE == \
+ 0x00008000UL) /* STM32G4 devices with CCMSRAM_SIZE = 32 Kbytes */
+#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U)
+#elif (CCMSRAM_SIZE == \
+ 0x00005000UL) /* STM32G4 devices with CCMSRAM_SIZE = 20 Kbytes */
+#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) \
+ (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FFFFFU))
+#elif (CCMSRAM_SIZE == \
+ 0x00004000UL) /* STM32G4 devices with CCMSRAM_SIZE = 16 Kbytes */
+#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) \
+ (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000FFFFU))
+#elif (CCMSRAM_SIZE == \
+ 0x00002800UL) /* STM32G4 devices with CCMSRAM_SIZE = 10 Kbytes */
+#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) \
+ (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
+#endif /* CCMSRAM_SIZE */
+
+#if defined(VREFBUF)
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) \
+ (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) \
+ (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) \
+ (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+#endif /* VREFBUF */
+
+#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
+ ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#elif defined(SYSCFG_FASTMODEPLUS_PB8)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
+ ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
+#elif defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
+ ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#else
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) \
+ ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
+#endif /* SYSCFG_FASTMODEPLUS_PB */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) \
+ (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and Configuration functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @{
+ */
+
+/* Peripheral Control functions
+ * ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
+uint32_t HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+ * @{
+ */
+
+/* DBGMCU Peripheral Control functions
+ * *****************************************/
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+ * @}
+ */
+
+/* Exported variables
+ * ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern uint32_t uwTickFreq;
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+ * @{
+ */
+
+/* SYSCFG Control functions
+ * ****************************************************/
+void HAL_SYSCFG_CCMSRAMErase(void);
+void HAL_SYSCFG_EnableMemorySwappingBank(void);
+void HAL_SYSCFG_DisableMemorySwappingBank(void);
+
+#if defined(VREFBUF)
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+#endif /* VREFBUF */
+
+void HAL_SYSCFG_EnableIOSwitchBooster(void);
+void HAL_SYSCFG_DisableIOSwitchBooster(void);
+void HAL_SYSCFG_EnableIOSwitchVDD(void);
+void HAL_SYSCFG_DisableIOSwitchVDD(void);
+void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
index 4e0a94a..fa77a52 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
@@ -1,2864 +1,2737 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_ADC_H
-#define STM32G4xx_HAL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/* Include low level driver */
-#include "stm32g4xx_ll_adc.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
- * @{
- */
-
-/**
- * @brief ADC group regular oversampling structure definition
- */
-typedef struct {
- uint32_t
- Ratio; /*!< Configures the oversampling ratio.
- This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
-
- uint32_t RightBitShift; /*!< Configures the division coefficient for the
- Oversampler. This parameter can be a value of @ref
- ADC_HAL_EC_OVS_SHIFT */
-
- uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
- This parameter can be a value of @ref
- ADC_HAL_EC_OVS_DISCONT_MODE */
-
- uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
- The oversampling is either temporary
- stopped or reset upon an injected sequence
- interruption. If oversampling is enabled on
- both regular and injected groups, this
- parameter is discarded and forced to
- setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
- (the oversampling buffer is zeroed during
- injection sequence). This parameter can be
- a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
-
-} ADC_OversamplingTypeDef;
-
-/**
- * @brief Structure definition of ADC instance and ADC group regular.
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (affects ADC groups regular and injected):
- * ClockPrescaler, Resolution, DataAlign, GainCompensation, ScanConvMode,
- * EOCSelection, LowPowerAutoWait.
- * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion,
- * DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConv,
- * ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode,
- * Oversampling, SamplingMode.
- * @note The setting of these parameters by function HAL_ADC_Init() is
- * conditioned to ADC state. ADC state can be either:
- * - For all parameters: ADC disabled
- * - For all parameters except 'LowPowerAutoWait',
- * 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on
- * going on group regular.
- * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC
- * enabled without conversion on going on groups regular and injected. If ADC is
- * not in the appropriate state to modify some parameters, these parameters
- * setting is bypassed without error reporting (as it can be the expected
- * behavior in case of intended action to update another parameter (which
- * fulfills the ADC state condition) on the fly).
- */
-typedef struct {
- uint32_t
- ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived
- from APB clock or asynchronous clock derived from
- system clock or PLL (Refer to reference manual for list
- of clocks available)) and clock prescaler. This
- parameter can be a value of @ref
- ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock
- configuration is common to all ADC instances. Note: In
- case of usage of channels on injected group, ADC
- frequency should be lower than AHB clock frequency /4
- for resolution 12 or 10 bits, AHB clock frequency /3
- for resolution 8 bits, AHB clock frequency /2 for
- resolution 6 bits. Note: In case of synchronous clock
- mode based on HCLK/1, the configuration must be enabled
- only if the system clock has a 50% duty clock cycle
- (APB prescaler configured inside RCC must be bypassed
- and PCLK clock must have 50% duty cycle). Refer to
- reference manual for details. Note: In case of usage of
- asynchronous clock, the selected clock must be
- preliminarily enabled at RCC top level. Note: This
- parameter can be modified only if all ADC instances are
- disabled. */
-
- uint32_t Resolution; /*!< Configure the ADC resolution.
- This parameter can be a value of @ref
- ADC_HAL_EC_RESOLUTION */
-
- uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data
- register (right or left). Refer to reference manual for
- alignments formats versus resolutions. This parameter
- can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
-
- uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient
- to be applied to ADC raw conversion data, based
- on following formula: DATA = DATA(raw) * (gain
- compensation coef) / 4096 2.12 bit format,
- unsigned: 2 bits exponents / 12 bits mantissa
- Gain step is 1/4096 = 0.000244 Gain range is
- 0.0000 to 3.999756 This parameter value can be
- 0 Gain compensation will be
- disabled and coefficient set to 0 1 -> 0x3FFF
- Gain compensation will be enabled and
- coefficient set to specified value
-
- Note: Gain compensation when enabled is
- applied to all channels. */
-
- uint32_t
- ScanConvMode; /*!< Configure the sequencer of ADC groups regular and
- injected. This parameter can be associated to parameter
- 'DiscontinuousConvMode' to have main sequence subdivided
- in successive parts. If disabled: Conversion is performed
- in single mode (one channel converted, the one defined in
- rank 1). Parameters 'NbrOfConversion' and
- 'InjectedNbrOfConversion' are discarded (equivalent to
- set to 1). If enabled: Conversions are performed in
- sequence mode (multiple ranks defined by
- 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank
- of each channel in sequencer). Scan direction is upward:
- from rank 1 to rank 'n'. This parameter can be a value of
- @ref ADC_Scan_mode */
-
- uint32_t
- EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for
- conversion by polling and interruption: end of unitary
- conversion or end of sequence conversions. This parameter
- can be a value of @ref ADC_EOCSelection. */
-
- FunctionalState
- LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new
- conversion start only when the previous conversion
- (for ADC group regular) or previous sequence (for ADC
- group injected) has been retrieved by user software,
- using function HAL_ADC_GetValue() or
- HAL_ADCEx_InjectedGetValue(). This feature
- automatically adapts the frequency of ADC conversions
- triggers to the speed of the system that reads the
- data. Moreover, this avoids risk of overrun for low
- frequency applications. This parameter can be set to
- ENABLE or DISABLE. Note: It is not recommended to use
- with interruption or DMA (HAL_ADC_Start_IT(),
- HAL_ADC_Start_DMA()) since these modes have to clear
- immediately the EOC flag (by CPU to free the IRQ
- pending event or by DMA). Auto wait will work but
- fort a very short time, discarding its intended
- benefit (except specific case of high load of CPU or
- DMA transfers which can justify usage of auto wait).
- Do use with polling: 1. Start conversion with
- HAL_ADC_Start(), 2. Later on, when ADC conversion
- data is needed: use HAL_ADC_PollForConversion() to
- ensure that conversion is completed and
- HAL_ADC_GetValue() to retrieve conversion result and
- trig another conversion start. (in case of usage of
- ADC group injected, use the equivalent functions
- HAL_ADCExInjected_Start(),
- HAL_ADCEx_InjectedGetValue(), ...). */
-
- FunctionalState
- ContinuousConvMode; /*!< Specify whether the conversion is performed in
- single mode (one conversion) or continuous mode for
- ADC group regular, after the first ADC conversion
- start trigger occurred (software start or external
- trigger). This parameter can be set to ENABLE or
- DISABLE. */
-
- uint32_t
- NbrOfConversion; /*!< Specify the number of ranks that will be converted
- within the regular group sequencer. To use the regular
- group sequencer and convert several ranks, parameter
- 'ScanConvMode' must be enabled. This parameter must be
- a number between Min_Data = 1 and Max_Data = 16. Note:
- This parameter must be modified when no conversion is
- on going on regular group (ADC disabled, or ADC
- enabled without continuous mode or external trigger
- that could launch a conversion). */
-
- FunctionalState
- DiscontinuousConvMode; /*!< Specify whether the conversions sequence of
- ADC group regular is performed in
- Complete-sequence/Discontinuous-sequence (main
- sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is
- enabled (parameter 'ScanConvMode'). If sequencer is
- disabled, this parameter is discarded. Discontinuous
- mode can be enabled only if continuous mode is
- disabled. If continuous mode is enabled, this
- parameter setting is discarded. This parameter can be
- set to ENABLE or DISABLE. */
-
- uint32_t
- NbrOfDiscConversion; /*!< Specifies the number of discontinuous
- conversions in which the main sequence of ADC
- group regular (parameter NbrOfConversion) will be
- subdivided. If parameter 'DiscontinuousConvMode'
- is disabled, this parameter is discarded. This
- parameter must be a number between Min_Data = 1
- and Max_Data = 8. */
-
- uint32_t ExternalTrigConv; /*!< Select the external event source used to
- trigger ADC group regular conversion start. If
- set to ADC_SOFTWARE_START, external triggers are
- disabled and software trigger is used instead.
- This parameter can be a value of @ref
- ADC_regular_external_trigger_source. Caution:
- external trigger source is common to all ADC
- instances. */
-
- uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to
- trigger ADC group regular conversion start.
- If trigger source is set to
- ADC_SOFTWARE_START, this parameter is
- discarded. This parameter can be a value of
- @ref ADC_regular_external_trigger_edge */
-
- uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group
- regular conversion. This parameter can be a value of
- @ref ADC_regular_sampling_mode */
-
- FunctionalState
- DMAContinuousRequests; /*!< Specify whether the DMA requests are performed
- in one shot mode (DMA transfer stops when number of
- conversions is reached) or in continuous mode (DMA
- transfer unlimited, whatever number of conversions).
- This parameter can be set to ENABLE or DISABLE.
- Note: In continuous mode, DMA must be configured in
- circular mode. Otherwise an overrun will be triggered
- when DMA buffer maximum pointer is reached. */
-
- uint32_t
- Overrun; /*!< Select the behavior in case of overrun: data overwritten or
- preserved (default). This parameter applies to ADC group
- regular only. This parameter can be a value of @ref
- ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. Note: In case of overrun set
- to data preserved and usage with programming model with
- interruption (HAL_Start_IT()): ADC IRQ handler has to clear
- end of conversion flags, this induces the release of the
- preserved data. If needed, this data can be saved in function
- HAL_ADC_ConvCpltCallback(), placed in user program code
- (called before end of conversion flags clear). Note: Error
- reporting with respect to the conversion mode:
- - Usage with ADC conversion by polling for event or
- interruption: Error is reported only if overrun is set to data
- preserved. If overrun is set to data overwritten, user can
- willingly not read all the converted data, this is not
- considered as an erroneous case.
- - Usage with ADC conversion by DMA: Error is reported
- whatever overrun setting (DMA is expected to process all data
- from data register). */
-
- FunctionalState
- OversamplingMode; /*!< Specify whether the oversampling feature is enabled
- or disabled. This parameter can be set to ENABLE or
- DISABLE. Note: This parameter can be modified only if
- there is no conversion is ongoing on ADC groups
- regular and injected */
-
- ADC_OversamplingTypeDef
- Oversampling; /*!< Specify the Oversampling parameters.
- Caution: this setting overwrites the previous
- oversampling configuration if oversampling is already
- enabled. */
-
-} ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of ADC channel for regular group
- * @note The setting of these parameters by function HAL_ADC_ConfigChannel()
- * is conditioned to ADC state. ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC
- * state to modify parameter 'SingleDiff')
- * - For all except parameters 'SamplingTime', 'Offset',
- * 'OffsetNumber': ADC enabled without conversion on going on regular group.
- * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC
- * enabled without conversion on going on regular and injected groups. If ADC is
- * not in the appropriate state to modify some parameters, these parameters
- * setting is bypassed without error reporting (as it can be the expected
- * behavior in case of intended action to update another parameter (which
- * fulfills the ADC state condition) on the fly).
- */
-typedef struct {
- uint32_t
- Channel; /*!< Specify the channel to configure into ADC regular group.
- This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
- Note: Depending on devices and ADC instances, some channels
- may not be available on device package pins. Refer to device
- datasheet for channels availability. */
-
- uint32_t
- Rank; /*!< Specify the rank in the regular group sequencer.
- This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
- Note: to disable a channel or change order of conversion
- sequencer, rank containing a previous channel setting can be
- overwritten by the new channel setting (or parameter number of
- conversions adjusted) */
-
- uint32_t
- SamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and
- processing time (12.5 ADC clock cycles at ADC resolution
- 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8
- bits, 6.5 cycles at 6 bits). This parameter can be a
- value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME Caution:
- This parameter applies to a channel that can be used into
- regular and/or injected group. It overwrites the last
- setting. Note: In case of usage of internal measurement
- channels (VrefInt/Vbat/TempSensor), sampling time
- constraints must be respected (sampling time can be
- adjusted in function of ADC clock frequency and sampling
- time setting) Refer to device datasheet for timings
- values. */
-
- uint32_t
- SingleDiff; /*!< Select single-ended or differential input.
- In differential mode: Differential measurement is carried
- out between the selected channel 'i' (positive input) and
- channel 'i+1' (negative input). Only channel 'i' has to be
- configured, channel 'i+1' is configured automatically. This
- parameter must be a value of @ref
- ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Caution: This
- parameter applies to a channel that can be used in a
- regular and/or injected group. It overwrites the last
- setting. Note: Refer to Reference Manual to ensure the
- selected channel is available in differential mode. Note:
- When configuring a channel 'i' in differential mode, the
- channel 'i+1' is not usable separately. Note: This
- parameter must be modified when ADC is disabled (before ADC
- start conversion or after ADC stop conversion). If ADC is
- enabled, this parameter setting is bypassed without error
- reporting (as it can be the expected behavior in case of
- another parameter update on the fly) */
-
- uint32_t OffsetNumber; /*!< Select the offset number
- This parameter can be a value of @ref
- ADC_HAL_EC_OFFSET_NB Caution: Only one offset is
- allowed per channel. This parameter overwrites the
- last setting. */
-
- uint32_t
- Offset; /*!< Define the offset to be applied on the raw converted data.
- Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and
- Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This
- parameter must be modified when no conversion is on going on
- both regular and injected groups (ADC disabled, or ADC enabled
- without continuous mode or external trigger that could
- launch a conversion). */
-
- uint32_t
- OffsetSign; /*!< Define if the offset should be subtracted (negative sign)
- or added (positive sign) from or to the raw converted data.
- This parameter can be a value of @ref ADCEx_OffsetSign.
- Note: This parameter must be modified when no conversion is
- on going on both regular and injected groups (ADC disabled,
- or ADC enabled without continuous mode or external trigger
- that could launch a conversion). */
- FunctionalState
- OffsetSaturation; /*!< Define if the offset should be saturated upon under
- or over flow. This parameter value can be ENABLE or
- DISABLE. Note: This parameter must be modified when no
- conversion is on going on both regular and injected
- groups (ADC disabled, or ADC enabled without
- continuous mode or external trigger that could launch
- a conversion). */
-
-} ADC_ChannelConfTypeDef;
-
-/**
- * @brief Structure definition of ADC analog watchdog
- * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig()
- * is conditioned to ADC state. ADC state can be either:
- * - For all parameters except 'HighThreshold', 'LowThreshold': ADC
- * disabled or ADC enabled without conversion on going on ADC groups regular and
- * injected.
- * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with
- * conversion on going on regular and injected groups.
- */
-typedef struct {
- uint32_t
- WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the
- selected channel. For Analog Watchdog 1: Only 1 channel
- can be monitored (or overall group of channels by
- setting parameter 'WatchdogMode') For Analog Watchdog 2
- and 3: Several channels can be monitored (by successive
- calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
- This parameter can be a value of @ref
- ADC_HAL_EC_AWD_NUMBER. */
-
- uint32_t
- WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none
- channels. For Analog Watchdog 1: Configure the ADC analog
- watchdog mode: single channel or all channels, ADC groups
- regular and-or injected. For Analog Watchdog 2 and 3:
- Several channels can be monitored by applying
- successively the AWD init structure. Channels on ADC
- group regular and injected are not differentiated: Set
- value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
- channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor
- all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no
- channel. This parameter can be a value of @ref
- ADC_analog_watchdog_mode. */
-
- uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
- For Analog Watchdog 1: this parameter has an effect
- only if parameter 'WatchdogMode' is configured on single
- channel (only 1 channel can be monitored). For Analog
- Watchdog 2 and 3: Several channels can be monitored. To
- use this feature, call successively the function
- HAL_ADC_AnalogWDGConfig() for each channel to be added
- (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This
- parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
-
- FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured
- in interrupt or polling mode. This parameter can be
- set to ENABLE or DISABLE */
-
- uint32_t
- HighThreshold; /*!< Configure the ADC analog watchdog High threshold
- value. Depending of ADC resolution selected (12, 10, 8
- or 6 bits), this parameter must be a number between
- Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or
- 0x3F respectively. Note: Analog watchdog 2 and 3 are
- limited to a resolution of 8 bits: if ADC resolution is
- 12 bits the 4 LSB are ignored, if ADC resolution is 10
- bits the 2 LSB are ignored. Note: If ADC oversampling is
- enabled, ADC analog watchdog thresholds are impacted:
- the comparison of analog watchdog thresholds is done on
- oversampling final computation (after ratio and
- shift application): ADC data register bitfield [15:4]
- (12 most significant bits). */
-
- uint32_t
- LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6
- bits), this parameter must be a number between Min_Data =
- 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
- respectively. Note: Analog watchdog 2 and 3 are limited
- to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10
- bits the 2 LSB are ignored. Note: If ADC oversampling is
- enabled, ADC analog watchdog thresholds are impacted: the
- comparison of analog watchdog thresholds is done on
- oversampling final computation (after ratio and
- shift application): ADC data register bitfield [15:4] (12
- most significant bits). */
-
- uint32_t
- FilteringConfig; /*!< Specify whether filtering should be use and the
- number of samples to consider. Before setting flag or
- raising interrupt, analog watchdog can wait to have
- several consecutive out-of-window samples. This
- parameter allows to configure this number. This
- parameter only applies to Analog watchdog 1. For
- others, use value ADC_AWD_FILTERING_NONE. This
- parameter can be a value of @ref
- ADC_analog_watchdog_filtering_config. */
-} ADC_AnalogWDGConfTypeDef;
-
-/**
- * @brief ADC group injected contexts queue configuration
- * @note Structure intended to be used only through structure
- * "ADC_HandleTypeDef"
- */
-typedef struct {
- uint32_t ContextQueue; /*!< Injected channel configuration context: build-up
- over each HAL_ADCEx_InjectedConfigChannel() call to
- finally initialize JSQR register at
- HAL_ADCEx_InjectedConfigChannel() last call */
-
- uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
-} ADC_InjectionConfigTypeDef;
-
-/** @defgroup ADC_States ADC States
- * @{
- */
-
-/**
- * @brief HAL ADC state machine: ADC states definition (bitfields)
- * @note ADC state machine is managed by bitfields, state must be compared
- * with bit by bit.
- * For example:
- * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
- * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
- */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET \
- (0x00000000UL) /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY \
- (0x00000001UL) /*!< ADC peripheral ready for use \
- */
-#define HAL_ADC_STATE_BUSY_INTERNAL \
- (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, \
- calibration) */
-#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL \
- (0x00000010UL) /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG \
- (0x00000020UL) /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY \
- (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can \
- occur (either by continuous mode, external trigger, low \
- power auto power-on (if feature available), multimode ADC \
- master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC \
- (0x00000200UL) /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP \
- (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag \
- raised */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY \
- (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can \
- occur (either by auto-injection mode, external trigger, \
- low power auto power-on (if feature available), multimode \
- ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC \
- (0x00002000UL) /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF \
- (0x00004000UL) /*!< Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 \
- (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 \
- (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 \
- (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE \
- (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC \
- master (when feature available) */
-
-/**
- * @}
- */
-
-/**
- * @brief ADC handle Structure definition
- */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-typedef struct __ADC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-{
- ADC_TypeDef *Instance; /*!< Register base address */
- ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular
- conversions setting */
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
- HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
- __IO uint32_t ErrorCode; /*!< ADC Error code */
- ADC_InjectionConfigTypeDef
- InjectionConfig; /*!< ADC injected channel configuration build-up
- structure */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- void (*ConvCpltCallback)(struct __ADC_HandleTypeDef
- *hadc); /*!< ADC conversion complete callback */
- void (*ConvHalfCpltCallback)(
- struct __ADC_HandleTypeDef
- *hadc); /*!< ADC conversion DMA half-transfer callback */
- void (*LevelOutOfWindowCallback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
- void (*ErrorCallback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
- void (*InjectedConvCpltCallback)(
- struct __ADC_HandleTypeDef
- *hadc); /*!< ADC group injected conversion complete callback */
- void (*InjectedQueueOverflowCallback)(
- struct __ADC_HandleTypeDef
- *hadc); /*!< ADC group injected context queue overflow callback */
- void (*LevelOutOfWindow2Callback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
- void (*LevelOutOfWindow3Callback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
- void (*EndOfSamplingCallback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
- void (*MspInitCallback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
- void (*MspDeInitCallback)(
- struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-} ADC_HandleTypeDef;
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL ADC Callback ID enumeration definition
- */
-typedef enum {
- HAL_ADC_CONVERSION_COMPLETE_CB_ID =
- 0x00U, /*!< ADC conversion complete callback ID */
- HAL_ADC_CONVERSION_HALF_CB_ID =
- 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
- HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID =
- 0x02U, /*!< ADC analog watchdog 1 callback ID */
- HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
- HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID =
- 0x04U, /*!< ADC group injected conversion complete callback ID */
- HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID =
- 0x05U, /*!< ADC group injected context queue overflow callback ID */
- HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID =
- 0x06U, /*!< ADC analog watchdog 2 callback ID */
- HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID =
- 0x07U, /*!< ADC analog watchdog 3 callback ID */
- HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
- HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
- HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
-} HAL_ADC_CallbackIDTypeDef;
-
-/**
- * @brief HAL ADC Callback pointer definition
- */
-typedef void (*pADC_CallbackTypeDef)(
- ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_Error_Code ADC Error Code
- * @{
- */
-#define HAL_ADC_ERROR_NONE \
- (0x00U) /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL \
- (0x01U) /*!< ADC peripheral internal error (problem of clocking, \
- enable/disable, erroneous state, ...) */
-#define HAL_ADC_ERROR_OVR \
- (0x02U) /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA \
- (0x04U) /*!< DMA transfer error */
-#define HAL_ADC_ERROR_JQOVF \
- (0x08U) /*!< Injected context queue overflow error */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
- * @{
- */
-#define ADC_CLOCK_SYNC_PCLK_DIV1 \
- (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB \
- clock without prescaler */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 \
- (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB \
- clock with prescaler division by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 \
- (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB \
- clock with prescaler division by 4 */
-
-#define ADC_CLOCK_ASYNC_DIV1 \
- (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
-#define ADC_CLOCK_ASYNC_DIV2 \
- (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler \
- division by 2 */
-#define ADC_CLOCK_ASYNC_DIV4 \
- (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler \
- division by 4 */
-#define ADC_CLOCK_ASYNC_DIV6 \
- (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler \
- division by 6 */
-#define ADC_CLOCK_ASYNC_DIV8 \
- (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler \
- division by 8 */
-#define ADC_CLOCK_ASYNC_DIV10 \
- (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler \
- division by 10 */
-#define ADC_CLOCK_ASYNC_DIV12 \
- (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler \
- division by 12 */
-#define ADC_CLOCK_ASYNC_DIV16 \
- (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler \
- division by 16 */
-#define ADC_CLOCK_ASYNC_DIV32 \
- (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler \
- division by 32 */
-#define ADC_CLOCK_ASYNC_DIV64 \
- (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler \
- division by 64 */
-#define ADC_CLOCK_ASYNC_DIV128 \
- (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler \
- division by 128 */
-#define ADC_CLOCK_ASYNC_DIV256 \
- (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler \
- division by 256 */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
- * @{
- */
-#define ADC_RESOLUTION_12B \
- (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
-#define ADC_RESOLUTION_10B \
- (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
-#define ADC_RESOLUTION_8B \
- (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits \
- */
-#define ADC_RESOLUTION_6B \
- (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
- * @{
- */
-#define ADC_DATAALIGN_RIGHT \
- (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned \
- (alignment on data register LSB bit 0)*/
-#define ADC_DATAALIGN_LEFT \
- (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned \
- (alignment on data register MSB bit 15)*/
-/**
- * @}
- */
-
-/** @defgroup ADC_Scan_mode ADC sequencer scan mode
- * @{
- */
-#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
-#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger
- * source
- * @{
- */
-/* ADC group regular trigger sources for all ADC instances */
-#define ADC_SOFTWARE_START \
- (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger \
- internal: SW start. */
-#define ADC_EXTERNALTRIG_T1_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM1 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T1_TRGO2 \
- (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM1 TRGO2. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T1_CC1 \
- (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM1 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T1_CC2 \
- (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM1 channel 2 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T1_CC3 \
- (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM1 channel 3 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM2 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T2_CC1 \
- (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM2 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_CC2 \
- (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM2 channel 2 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_CC3 \
- (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM2 channel 3 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T3_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM3 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T3_CC1 \
- (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM3 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T3_CC4 \
- (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM3 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T4_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM4 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T4_CC1 \
- (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM4 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T4_CC4 \
- (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM4 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T6_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM6 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T7_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM7 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T8_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM8 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T8_TRGO2 \
- (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM8 TRGO2. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T8_CC1 \
- (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM8 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T15_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM15 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T20_TRGO \
- (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM20 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIG_T20_TRGO2 \
- (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM20 TRGO2. \
- Trigger edge set to rising edge \
- (default setting). */
-#define ADC_EXTERNALTRIG_T20_CC1 \
- (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM20 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T20_CC2 \
- (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM20 channel 2 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T20_CC3 \
- (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger \
- from external peripheral: TIM20 channel 3 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG1 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 1 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG2 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 2 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG3 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 3 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG4 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 4 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG5 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 5 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG6 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 6 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG7 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 7 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG8 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 8 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG9 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 9 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_HRTIM_TRG10 \
- (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 10 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_EXT_IT2 \
- (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger \
- from external peripheral: external \
- interrupt line 2. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_EXT_IT11 \
- (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger \
- from external peripheral: external \
- interrupt line 11. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIG_LPTIM_OUT \
- (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger \
- from external peripheral: LPTIMER OUT \
- event. Trigger edge set to rising edge \
- (default setting). */
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge
- * (when external trigger is selected)
- * @{
- */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE \
- (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled \
- */
-#define ADC_EXTERNALTRIGCONVEDGE_RISING \
- (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger \
- polarity set to rising edge */
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING \
- (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger \
- polarity set to falling edge */
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING \
- (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion \
- trigger polarity set to both rising \
- and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
- * @{
- */
-#define ADC_SAMPLING_MODE_NORMAL \
- (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using \
- @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
-#define ADC_SAMPLING_MODE_BULB \
- (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately \
- after end of conversion, and stops upon trigger event. \
- Note: First conversion is using minimal \
- sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) \
- */
-#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED \
- (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by \
- trigger events: Trigger rising edge = start sampling \
- Trigger falling edge = stop sampling and \
- start conversion */
-/**
- * @}
- */
-
-/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or
- * sequence conversions
- * @{
- */
-#define ADC_EOC_SINGLE_CONV \
- (ADC_ISR_EOC) /*!< End of unitary conversion flag */
-#define ADC_EOC_SEQ_CONV \
- (ADC_ISR_EOS) /*!< End of sequence conversions flag */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun
- * behavior on conversion data
- * @{
- */
-#define ADC_OVR_DATA_PRESERVED \
- (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of \
- overrun: data preserved */
-#define ADC_OVR_DATA_OVERWRITTEN \
- (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of \
- overrun: data overwritten */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
- * @{
- */
-#define ADC_REGULAR_RANK_1 \
- (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
-#define ADC_REGULAR_RANK_2 \
- (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
-#define ADC_REGULAR_RANK_3 \
- (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
-#define ADC_REGULAR_RANK_4 \
- (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
-#define ADC_REGULAR_RANK_5 \
- (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
-#define ADC_REGULAR_RANK_6 \
- (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
-#define ADC_REGULAR_RANK_7 \
- (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
-#define ADC_REGULAR_RANK_8 \
- (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
-#define ADC_REGULAR_RANK_9 \
- (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
-#define ADC_REGULAR_RANK_10 \
- (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
-#define ADC_REGULAR_RANK_11 \
- (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
-#define ADC_REGULAR_RANK_12 \
- (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
-#define ADC_REGULAR_RANK_13 \
- (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
-#define ADC_REGULAR_RANK_14 \
- (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
-#define ADC_REGULAR_RANK_15 \
- (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
-#define ADC_REGULAR_RANK_16 \
- (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
- * @{
- */
-#define ADC_SAMPLETIME_2CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
-#define ADC_SAMPLETIME_6CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
-#define ADC_SAMPLETIME_12CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
-#define ADC_SAMPLETIME_24CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
-#define ADC_SAMPLETIME_47CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
-#define ADC_SAMPLETIME_92CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
-#define ADC_SAMPLETIME_247CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles \
- */
-#define ADC_SAMPLETIME_640CYCLES_5 \
- (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles \
- */
-#define ADC_SAMPLETIME_3CYCLES_5 \
- (ADC_SMPR1_SMPPLUS | \
- LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If \
- selected, this sampling time replaces all \
- sampling time 2.5 ADC clock cycles. These \
- 2 sampling times cannot be used \
- simultaneously. */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
- * @{
- */
-/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
-/* all ADC instances (refer to Reference Manual). */
-#define ADC_CHANNEL_0 \
- (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN0 */
-#define ADC_CHANNEL_1 \
- (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN1 */
-#define ADC_CHANNEL_2 \
- (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN2 */
-#define ADC_CHANNEL_3 \
- (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN3 */
-#define ADC_CHANNEL_4 \
- (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN4 */
-#define ADC_CHANNEL_5 \
- (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN5 */
-#define ADC_CHANNEL_6 \
- (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN6 */
-#define ADC_CHANNEL_7 \
- (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN7 */
-#define ADC_CHANNEL_8 \
- (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN8 */
-#define ADC_CHANNEL_9 \
- (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) \
- ADCx_IN9 */
-#define ADC_CHANNEL_10 \
- (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN10 */
-#define ADC_CHANNEL_11 \
- (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN11 */
-#define ADC_CHANNEL_12 \
- (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN12 */
-#define ADC_CHANNEL_13 \
- (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN13 */
-#define ADC_CHANNEL_14 \
- (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN14 */
-#define ADC_CHANNEL_15 \
- (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN15 */
-#define ADC_CHANNEL_16 \
- (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN16 */
-#define ADC_CHANNEL_17 \
- (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN17 */
-#define ADC_CHANNEL_18 \
- (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO \
- pin) ADCx_IN18 */
-#define ADC_CHANNEL_VREFINT \
- (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: \
- Internal voltage reference. On this STM32 \
- series, ADC channel available on all instances \
- but ADC2. */
-#define ADC_CHANNEL_TEMPSENSOR_ADC1 \
- (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to \
- Temperature sensor. On this STM32 \
- series, ADC channel available only on \
- ADC1 instance. */
-#define ADC_CHANNEL_TEMPSENSOR_ADC5 \
- (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to \
- Temperature sensor. On this STM32 \
- series, ADC channel available only on \
- ADC5 instance. Refer to device datasheet \
- for ADC5 availaibility */
-#define ADC_CHANNEL_VBAT \
- (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat \
- voltage through a divider ladder of factor 1/3 to \
- have Vbat always below Vdda. On this STM32 series, \
- ADC channel available on all ADC instances but ADC2 \
- & ADC4. Refer to device datasheet for ADC4 \
- availaibility */
-#define ADC_CHANNEL_VOPAMP1 \
- (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 \
- output. On this STM32 series, ADC channel \
- available only on ADC1 instance. */
-#define ADC_CHANNEL_VOPAMP2 \
- (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 \
- output. On this STM32 series, ADC channel \
- available only on ADC2 instance. */
-#define ADC_CHANNEL_VOPAMP3_ADC2 \
- (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 \
- output. On this STM32 series, ADC channel \
- available only on ADC2 instance. */
-#define ADC_CHANNEL_VOPAMP3_ADC3 \
- (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 \
- output. On this STM32 series, ADC channel \
- available only on ADC3 instance. Refer to \
- device datasheet for ADC3 availability */
-#define ADC_CHANNEL_VOPAMP4 \
- (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 \
- output. On this STM32 series, ADC channel \
- available only on ADC5 instance. Refer to device \
- datasheet for ADC5 availability */
-#define ADC_CHANNEL_VOPAMP5 \
- (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 \
- output. On this STM32 series, ADC channel \
- available only on ADC5 instance. Refer to device \
- datasheet for ADC5 availability */
-#define ADC_CHANNEL_VOPAMP6 \
- (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 \
- output. On this STM32 series, ADC channel \
- available only on ADC4 instance. Refer to device \
- datasheet for ADC4 availability */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
- * @{
- */
-#define ADC_ANALOGWATCHDOG_1 \
- (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 \
- */
-#define ADC_ANALOGWATCHDOG_2 \
- (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 \
- */
-#define ADC_ANALOGWATCHDOG_3 \
- (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering
- * configuration
- * @{
- */
-#define ADC_AWD_FILTERING_NONE \
- (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window \
- sample is needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_2SAMPLES \
- ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_3SAMPLES \
- ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_4SAMPLES \
- ((ADC_TR1_AWDFILT_1 | \
- ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_5SAMPLES \
- ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_6SAMPLES \
- ((ADC_TR1_AWDFILT_2 | \
- ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_7SAMPLES \
- ((ADC_TR1_AWDFILT_2 | \
- ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define ADC_AWD_FILTERING_8SAMPLES \
- ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | \
- ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
- * @{
- */
-#define ADC_ANALOGWATCHDOG_NONE \
- (0x00000000UL) /*!< No analog watchdog selected */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG \
- (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a \
- regular group single channel */
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC \
- (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an \
- injected group single channel */
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC \
- (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | \
- ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected \
- groups single channel */
-#define ADC_ANALOGWATCHDOG_ALL_REG \
- (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels \
- */
-#define ADC_ANALOGWATCHDOG_ALL_INJEC \
- (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all \
- channels */
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC \
- (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular \
- and injected groups all channels */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
- * @{
- */
-#define ADC_OVERSAMPLING_RATIO_2 \
- (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_4 \
- (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_8 \
- (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_16 \
- (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions \
- are performed, sum of these conversions data is \
- computed to result as the ADC oversampling \
- conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_32 \
- (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions \
- are performed, sum of these conversions data is \
- computed to result as the ADC oversampling \
- conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_64 \
- (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions \
- are performed, sum of these conversions data is \
- computed to result as the ADC oversampling \
- conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_128 \
- (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC \
- conversions are performed, sum of these \
- conversions data is computed to result as the ADC \
- oversampling conversion data (before potential \
- shift) */
-#define ADC_OVERSAMPLING_RATIO_256 \
- (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC \
- conversions are performed, sum of these \
- conversions data is computed to result as the ADC \
- oversampling conversion data (before potential \
- shift) */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
- * @{
- */
-#define ADC_RIGHTBITSHIFT_NONE \
- (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC \
- conversions data is not divided to result as the \
- ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_1 \
- (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC \
- conversions data is divided by 2 to result as \
- the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_2 \
- (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC \
- conversions data is divided by 4 to result as \
- the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_3 \
- (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC \
- conversions data is divided by 8 to result as \
- the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_4 \
- (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC \
- conversions data is divided by 16 to result as \
- the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_5 \
- (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC \
- conversions data is divided by 32 to result as \
- the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_6 \
- (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC \
- conversions data is divided by 64 to result as \
- the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_7 \
- (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC \
- conversions data is divided by 128 to result \
- as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_8 \
- (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC \
- conversions data is divided by 256 to result \
- as the ADC oversampling conversion data) */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
- * @{
- */
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER \
- (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous \
- mode (all conversions of oversampling ratio are \
- done from 1 trigger) */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER \
- (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: \
- discontinuous mode (each conversion of \
- oversampling ratio needs a trigger) */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for
- * ADC group regular
- * @{
- */
-#define ADC_REGOVERSAMPLING_CONTINUED_MODE \
- (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained \
- during injection sequence */
-#define ADC_REGOVERSAMPLING_RESUMED_MODE \
- (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during \
- injection sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_Event_type ADC Event type
- * @{
- */
-#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
-#define ADC_AWD1_EVENT \
- (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, \
- present on all STM32 series) */
-#define ADC_AWD2_EVENT \
- (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog \
- watchdog, not present on all STM32 series) */
-#define ADC_AWD3_EVENT \
- (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog \
- watchdog, not present on all STM32 series) */
-#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
-#define ADC_JQOVF_EVENT \
- (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
-/**
- * @}
- */
-#define ADC_AWD_EVENT \
- ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility \
- with other STM32 devices having only one analog watchdog \
- */
-
-/** @defgroup ADC_interrupts_definition ADC interrupts definition
- * @{
- */
-#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
-#define ADC_IT_EOSMP \
- ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
-#define ADC_IT_EOC \
- ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
-#define ADC_IT_EOS \
- ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt \
- source */
-#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
-#define ADC_IT_JEOC \
- ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
-#define ADC_IT_JEOS \
- ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt \
- source */
-#define ADC_IT_AWD1 \
- ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog \
- watchdog) */
-#define ADC_IT_AWD2 \
- ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional \
- analog watchdog) */
-#define ADC_IT_AWD3 \
- ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional \
- analog watchdog) */
-#define ADC_IT_JQOVF \
- ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
-
-#define ADC_IT_AWD \
- ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for \
- compatibility with other STM32 devices having only one analog \
- watchdog */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition ADC flags definition
- * @{
- */
-#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
-#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS \
- ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
-#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
-#define ADC_FLAG_JEOS \
- ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_FLAG_AWD1 \
- ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
-#define ADC_FLAG_AWD2 \
- ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
-#define ADC_FLAG_AWD3 \
- ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
-#define ADC_FLAG_JQOVF \
- ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
- * @{
- */
-/* Macro reserved for internal HAL driver usage, not intended to be used in */
-/* code of final user. */
-
-/**
- * @brief Return resolution bits in CFGR register RES[1:0] field.
- * @param __HANDLE__ ADC handle
- * @retval Value of bitfield RES in CFGR register.
- */
-#define ADC_GET_RESOLUTION(__HANDLE__) \
- (LL_ADC_GetResolution((__HANDLE__)->Instance))
-
-/**
- * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
- ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
- * @brief Simultaneously clear and set specific bits of the handle State.
- * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro
- * MODIFY_REG(), the first parameter is the ADC handle State, the second
- * parameter is the bit field to clear, the third and last parameter is the bit
- * field to set.
- * @retval None
- */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
- * @brief Verify that a given value is aligned with the ADC resolution range.
- * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
- * @param __ADC_VALUE__ value checked against the resolution.
- * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET
- * (__ADC_VALUE__ not in line with __RESOLUTION__)
- */
-#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
- ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
-
-/**
- * @brief Verify the length of the scheduled regular conversions group.
- * @param __LENGTH__ number of programmed conversions.
- * @retval SET (__LENGTH__ is within the maximum number of possible programmable
- * regular conversions) or RESET (__LENGTH__ is null or too large)
- */
-#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) \
- (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
-
-/**
- * @brief Verify the number of scheduled regular conversions in discontinuous
- * mode.
- * @param NUMBER number of scheduled regular conversions in discontinuous mode.
- * @retval SET (NUMBER is within the maximum number of regular conversions in
- * discontinuous mode) or RESET (NUMBER is null or too large)
- */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) \
- (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
-
-/**
- * @brief Verify the ADC clock setting.
- * @param __ADC_CLOCK__ programmed ADC clock.
- * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is
- * invalid)
- */
-#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) \
- (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
- ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256))
-
-/**
- * @brief Verify the ADC resolution setting.
- * @param __RESOLUTION__ programmed ADC resolution.
- * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is
- * invalid)
- */
-#define IS_ADC_RESOLUTION(__RESOLUTION__) \
- (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
- ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
- ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
- ((__RESOLUTION__) == ADC_RESOLUTION_6B))
-
-/**
- * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
- * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
- * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is
- * invalid)
- */
-#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) \
- (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
- ((__RESOLUTION__) == ADC_RESOLUTION_6B))
-
-/**
- * @brief Verify the ADC converted data alignment.
- * @param __ALIGN__ programmed ADC converted data alignment.
- * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
- */
-#define IS_ADC_DATA_ALIGN(__ALIGN__) \
- (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || ((__ALIGN__) == ADC_DATAALIGN_LEFT))
-
-/**
- * @brief Verify the ADC gain compensation.
- * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
- * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET
- * (__GAIN_COMPENSATION__ is invalid)
- */
-#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) \
- ((__GAIN_COMPENSATION__) <= 16393UL)
-
-/**
- * @brief Verify the ADC scan mode.
- * @param __SCAN_MODE__ programmed ADC scan mode.
- * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
- */
-#define IS_ADC_SCAN_MODE(__SCAN_MODE__) \
- (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
- ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
-
-/**
- * @brief Verify the ADC edge trigger setting for regular group.
- * @param __EDGE__ programmed ADC edge trigger setting.
- * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
- */
-#define IS_ADC_EXTTRIG_EDGE(__EDGE__) \
- (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
-
-/**
- * @brief Verify the ADC regular conversions external trigger.
- * @param __HANDLE__ ADC handle
- * @param __REGTRIG__ programmed ADC regular conversions external trigger.
- * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
- */
-#if defined(STM32G474xx) || defined(STM32G484xx)
-#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
- ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
- ((__HANDLE__)->Instance == ADC5)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
- ((__REGTRIG__) == ADC_SOFTWARE_START))
-#elif defined(STM32G473xx) || defined(STM32G483xx)
-#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
- ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
- ((__HANDLE__)->Instance == ADC5)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
- ((__REGTRIG__) == ADC_SOFTWARE_START))
-#elif defined(STM32G471xx)
-#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
- ((((__HANDLE__)->Instance == ADC3)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
- ((__REGTRIG__) == ADC_SOFTWARE_START))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
- ((__REGTRIG__) == ADC_SOFTWARE_START))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
- (((__HANDLE__)->Instance == ADC3) && \
- (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
- ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
- ((__REGTRIG__) == ADC_SOFTWARE_START))
-#endif
-
-/**
- * @brief Verify the ADC regular conversions external trigger.
- * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
- * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is
- * invalid)
- */
-#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) \
- (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
- ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
- ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED))
-
-/**
- * @brief Verify the ADC regular conversions check for converted data
- * availability.
- * @param __EOC_SELECTION__ converted data availability check.
- * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__
- * is invalid)
- */
-#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) \
- (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
- ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV))
-
-/**
- * @brief Verify the ADC regular conversions overrun handling.
- * @param __OVR__ ADC regular conversions overrun handling.
- * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
- */
-#define IS_ADC_OVERRUN(__OVR__) \
- (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
- ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN))
-
-/**
- * @brief Verify the ADC conversions sampling time.
- * @param __TIME__ ADC conversions sampling time.
- * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
- */
-#define IS_ADC_SAMPLE_TIME(__TIME__) \
- (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
- ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5))
-
-/**
- * @brief Verify the ADC regular channel setting.
- * @param __CHANNEL__ programmed ADC regular channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC_REGULAR_RANK(__CHANNEL__) \
- (((__CHANNEL__) == ADC_REGULAR_RANK_1) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_2) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_3) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_4) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_5) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_6) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_7) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_8) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_9) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_16))
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-
-/* Fixed timeout values for ADC conversion (including sampling time) */
-/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
-/* Maximum conversion time is 12.5 + Maximum sampling time */
-/* or 12.5 + 640.5 = 653 ADC clock cycles */
-/* Minimum ADC Clock frequency is 0.14 MHz */
-/* Maximum conversion time is */
-/* 653 / 0.14 MHz = 4.66 ms */
-#define ADC_STOP_CONVERSION_TIMEOUT (5UL) /*!< ADC stop time-out value */
-
-/* Delay for temperature sensor stabilization time. */
-/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
-/* Unit: us */
-#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
- * @{
- */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user. */
-
-/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle,
- * IT and flags.
- * @{
- */
-
-/** @brief Reset ADC handle state.
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while (0)
-#else
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable ADC interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be one of the following values:
- * @arg @ref ADC_IT_RDY ADC Ready interrupt source
- * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
- * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt
- * source
- * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions
- * interrupt source
- * @arg @ref ADC_IT_OVR ADC overrun interrupt source
- * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt
- * source
- * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of
- * Conversions interrupt source
- * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source
- * (main analog watchdog)
- * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source
- * (additional analog watchdog)
- * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source
- * (additional analog watchdog)
- * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow
- * interrupt source.
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
- * @brief Disable ADC interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be one of the following values:
- * @arg @ref ADC_IT_RDY ADC Ready interrupt source
- * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
- * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt
- * source
- * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions
- * interrupt source
- * @arg @ref ADC_IT_OVR ADC overrun interrupt source
- * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt
- * source
- * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of
- * Conversions interrupt source
- * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source
- * (main analog watchdog)
- * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source
- * (additional analog watchdog)
- * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source
- * (additional analog watchdog)
- * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow
- * interrupt source.
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC interrupt source to check
- * This parameter can be one of the following values:
- * @arg @ref ADC_IT_RDY ADC Ready interrupt source
- * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
- * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt
- * source
- * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions
- * interrupt source
- * @arg @ref ADC_IT_OVR ADC overrun interrupt source
- * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt
- * source
- * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of
- * Conversions interrupt source
- * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source
- * (main analog watchdog)
- * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source
- * (additional analog watchdog)
- * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source
- * (additional analog watchdog)
- * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow
- * interrupt source.
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified ADC flag is set or not.
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be one of the following values:
- * @arg @ref ADC_FLAG_RDY ADC Ready flag
- * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
- * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
- * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of
- * Conversions flag
- * @arg @ref ADC_FLAG_OVR ADC overrun flag
- * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
- * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of
- * Conversions flag
- * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog
- * watchdog)
- * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional
- * analog watchdog)
- * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional
- * analog watchdog)
- * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow
- * flag.
- * @retval State of flag (TRUE or FALSE).
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the specified ADC flag.
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be one of the following values:
- * @arg @ref ADC_FLAG_RDY ADC Ready flag
- * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
- * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
- * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of
- * Conversions flag
- * @arg @ref ADC_FLAG_OVR ADC overrun flag
- * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
- * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of
- * Conversions flag
- * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog
- * watchdog)
- * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional
- * analog watchdog)
- * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional
- * analog watchdog)
- * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow
- * flag.
- * @retval None
- */
-/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of
- * register ISR) */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (((__HANDLE__)->Instance->ISR) = (__FLAG__))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get ADC channel number in decimal format
- * from literals ADC_CHANNEL_x.
- * @note Example:
- * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
- * will return decimal number "4".
- * @note The input can be a value from functions where a channel
- * number is returned, either defined with number
- * or with bitfield (only one bit must be set).
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref ADC_CHANNEL_0
- * @arg @ref ADC_CHANNEL_1 (8)
- * @arg @ref ADC_CHANNEL_2 (8)
- * @arg @ref ADC_CHANNEL_3 (8)
- * @arg @ref ADC_CHANNEL_4 (8)
- * @arg @ref ADC_CHANNEL_5 (8)
- * @arg @ref ADC_CHANNEL_6
- * @arg @ref ADC_CHANNEL_7
- * @arg @ref ADC_CHANNEL_8
- * @arg @ref ADC_CHANNEL_9
- * @arg @ref ADC_CHANNEL_10
- * @arg @ref ADC_CHANNEL_11
- * @arg @ref ADC_CHANNEL_12
- * @arg @ref ADC_CHANNEL_13
- * @arg @ref ADC_CHANNEL_14
- * @arg @ref ADC_CHANNEL_15
- * @arg @ref ADC_CHANNEL_16
- * @arg @ref ADC_CHANNEL_17
- * @arg @ref ADC_CHANNEL_18
- * @arg @ref ADC_CHANNEL_VREFINT (7)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref ADC_CHANNEL_VBAT (6)
- * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Value between Min_Data=0 and Max_Data=18
- */
-#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
-
-/**
- * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
- * from number in decimal format.
- * @note Example:
- * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
- * will return a data equivalent to "ADC_CHANNEL_4".
- * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
- * @retval Returned value can be one of the following values:
- * @arg @ref ADC_CHANNEL_0
- * @arg @ref ADC_CHANNEL_1 (8)
- * @arg @ref ADC_CHANNEL_2 (8)
- * @arg @ref ADC_CHANNEL_3 (8)
- * @arg @ref ADC_CHANNEL_4 (8)
- * @arg @ref ADC_CHANNEL_5 (8)
- * @arg @ref ADC_CHANNEL_6
- * @arg @ref ADC_CHANNEL_7
- * @arg @ref ADC_CHANNEL_8
- * @arg @ref ADC_CHANNEL_9
- * @arg @ref ADC_CHANNEL_10
- * @arg @ref ADC_CHANNEL_11
- * @arg @ref ADC_CHANNEL_12
- * @arg @ref ADC_CHANNEL_13
- * @arg @ref ADC_CHANNEL_14
- * @arg @ref ADC_CHANNEL_15
- * @arg @ref ADC_CHANNEL_16
- * @arg @ref ADC_CHANNEL_17
- * @arg @ref ADC_CHANNEL_18
- * @arg @ref ADC_CHANNEL_VREFINT (7)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref ADC_CHANNEL_VBAT (6)
- * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
- * register, comparison with internal channel parameter to be done using helper
- * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
-
-/**
- * @brief Helper macro to determine whether the selected channel
- * corresponds to literal definitions of driver.
- * @note The different literal definitions of ADC channels are:
- * - ADC internal channel:
- * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
- * - ADC external channel (channel connected to a GPIO pin):
- * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
- * @note The channel parameter must be a value defined from literal
- * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
- * ADC_CHANNEL_TEMPSENSOR, ...),
- * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
- * must not be a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref ADC_CHANNEL_0
- * @arg @ref ADC_CHANNEL_1 (8)
- * @arg @ref ADC_CHANNEL_2 (8)
- * @arg @ref ADC_CHANNEL_3 (8)
- * @arg @ref ADC_CHANNEL_4 (8)
- * @arg @ref ADC_CHANNEL_5 (8)
- * @arg @ref ADC_CHANNEL_6
- * @arg @ref ADC_CHANNEL_7
- * @arg @ref ADC_CHANNEL_8
- * @arg @ref ADC_CHANNEL_9
- * @arg @ref ADC_CHANNEL_10
- * @arg @ref ADC_CHANNEL_11
- * @arg @ref ADC_CHANNEL_12
- * @arg @ref ADC_CHANNEL_13
- * @arg @ref ADC_CHANNEL_14
- * @arg @ref ADC_CHANNEL_15
- * @arg @ref ADC_CHANNEL_16
- * @arg @ref ADC_CHANNEL_17
- * @arg @ref ADC_CHANNEL_18
- * @arg @ref ADC_CHANNEL_VREFINT (7)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref ADC_CHANNEL_VBAT (6)
- * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Value "0" if the channel corresponds to a parameter definition of a
- * ADC external channel (channel connected to a GPIO pin). Value "1" if the
- * channel corresponds to a parameter definition of a ADC internal channel.
- */
-#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
-
-/**
- * @brief Helper macro to convert a channel defined from parameter
- * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
- * ADC_CHANNEL_TEMPSENSOR, ...),
- * to its equivalent parameter definition of a ADC external channel
- * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
- * @note The channel parameter can be, additionally to a value
- * defined from parameter definition of a ADC internal channel
- * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
- * a value defined from parameter definition of
- * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is returned
- * from ADC registers.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref ADC_CHANNEL_0
- * @arg @ref ADC_CHANNEL_1 (8)
- * @arg @ref ADC_CHANNEL_2 (8)
- * @arg @ref ADC_CHANNEL_3 (8)
- * @arg @ref ADC_CHANNEL_4 (8)
- * @arg @ref ADC_CHANNEL_5 (8)
- * @arg @ref ADC_CHANNEL_6
- * @arg @ref ADC_CHANNEL_7
- * @arg @ref ADC_CHANNEL_8
- * @arg @ref ADC_CHANNEL_9
- * @arg @ref ADC_CHANNEL_10
- * @arg @ref ADC_CHANNEL_11
- * @arg @ref ADC_CHANNEL_12
- * @arg @ref ADC_CHANNEL_13
- * @arg @ref ADC_CHANNEL_14
- * @arg @ref ADC_CHANNEL_15
- * @arg @ref ADC_CHANNEL_16
- * @arg @ref ADC_CHANNEL_17
- * @arg @ref ADC_CHANNEL_18
- * @arg @ref ADC_CHANNEL_VREFINT (7)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref ADC_CHANNEL_VBAT (6)
- * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Returned value can be one of the following values:
- * @arg @ref ADC_CHANNEL_0
- * @arg @ref ADC_CHANNEL_1
- * @arg @ref ADC_CHANNEL_2
- * @arg @ref ADC_CHANNEL_3
- * @arg @ref ADC_CHANNEL_4
- * @arg @ref ADC_CHANNEL_5
- * @arg @ref ADC_CHANNEL_6
- * @arg @ref ADC_CHANNEL_7
- * @arg @ref ADC_CHANNEL_8
- * @arg @ref ADC_CHANNEL_9
- * @arg @ref ADC_CHANNEL_10
- * @arg @ref ADC_CHANNEL_11
- * @arg @ref ADC_CHANNEL_12
- * @arg @ref ADC_CHANNEL_13
- * @arg @ref ADC_CHANNEL_14
- * @arg @ref ADC_CHANNEL_15
- * @arg @ref ADC_CHANNEL_16
- * @arg @ref ADC_CHANNEL_17
- * @arg @ref ADC_CHANNEL_18
- */
-#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
-
-/**
- * @brief Helper macro to determine whether the internal channel
- * selected is available on the ADC instance selected.
- * @note The channel parameter must be a value defined from parameter
- * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
- * ADC_CHANNEL_TEMPSENSOR, ...),
- * must not be a value defined from parameter definition of
- * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __ADC_INSTANCE__ ADC instance
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref ADC_CHANNEL_VREFINT (7)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref ADC_CHANNEL_VBAT (6)
- * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details.
- * @retval Value "0" if the internal channel selected is not available on the
- * ADC instance selected. Value "1" if the internal channel selected is
- * available on the ADC instance selected.
- */
-#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Helper macro to get the ADC multimode conversion data of ADC master
- * or ADC slave from raw value with both ADC conversion data
- * concatenated.
- * @note This macro is intended to be used when multimode transfer by DMA
- * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
- * In this case the transferred data need to processed with this macro
- * to separate the conversion data of ADC master and ADC slave.
- * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_MULTI_MASTER
- * @arg @ref LL_ADC_MULTI_SLAVE
- * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and
- * Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, \
- __ADC_MULTI_CONV_DATA__) \
- __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), \
- (__ADC_MULTI_CONV_DATA__))
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @brief Helper macro to select the ADC common instance
- * to which is belonging the selected ADC instance.
- * @note ADC common register instance can be used for:
- * - Set parameters common to several ADC instances
- * - Multimode (for devices with several ADC instances)
- * Refer to functions having argument "ADCxy_COMMON" as parameter.
- * @param __ADCx__ ADC instance
- * @retval ADC common register instance
- */
-#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
-
-/**
- * @brief Helper macro to check if all ADC instances sharing the same
- * ADC common instance are disabled.
- * @note This check is required by functions with setting conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled.
- * Refer to functions having argument "ADCxy_COMMON" as parameter.
- * @note On devices with only 1 ADC common instance, parameter of this macro
- * is useless and can be ignored (parameter kept for compatibility
- * with devices featuring several ADC common instances).
- * @param __ADCXY_COMMON__ ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Value "0" if all ADC instances sharing the same ADC common instance
- * are disabled.
- * Value "1" if at least one ADC instance sharing the same ADC common
- * instance is enabled.
- */
-#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
-
-/**
- * @brief Helper macro to define the ADC conversion data full-scale digital
- * value corresponding to the selected ADC resolution.
- * @note ADC conversion data full-scale corresponds to voltage range
- * determined by analog voltage references Vref+ and Vref-
- * (refer to reference manual).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @retval ADC conversion data full-scale digital value
- */
-#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
-
-/**
- * @brief Helper macro to convert the ADC conversion data from
- * a resolution to another resolution.
- * @param __DATA__ ADC conversion data to be converted
- * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
- * This parameter can be one of the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
- * This parameter can be one of the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @retval ADC conversion data to the requested resolution
- */
-#define __HAL_ADC_CONVERT_DATA_RESOLUTION( \
- __DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
- __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), (__ADC_RESOLUTION_CURRENT__), \
- (__ADC_RESOLUTION_TARGET__))
-
-/**
- * @brief Helper macro to calculate the voltage (unit: mVolt)
- * corresponding to a ADC conversion data (unit: digital value).
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
- * (unit: digital value).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, \
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), (__ADC_DATA__), \
- (__ADC_RESOLUTION__))
-
-/**
- * @brief Helper macro to calculate analog reference voltage (Vref+)
- * (unit: mVolt) from ADC conversion data of internal voltage
- * reference VrefInt.
- * @note Computation is using VrefInt calibration value
- * stored in system memory for each device during production.
- * @note This voltage depends on user board environment: voltage level
- * connected to pin Vref+.
- * On devices with small package, the pin Vref+ is not present
- * and internally bonded to pin Vdda.
- * @note On this STM32 series, calibration data of internal voltage reference
- * VrefInt corresponds to a resolution of 12 bits,
- * this is the recommended ADC resolution to convert voltage of
- * internal voltage reference VrefInt.
- * Otherwise, this macro performs the processing to scale
- * ADC conversion data to 12 bits.
- * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
- * of internal voltage reference VrefInt (unit: digital value).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @retval Analog reference voltage (unit: mV)
- */
-#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, \
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), (__ADC_RESOLUTION__))
-
-/**
- * @brief Helper macro to calculate the temperature (unit: degree Celsius)
- * from ADC conversion data of internal temperature sensor.
- * @note Computation is using temperature sensor calibration values
- * stored in system memory for each device during production.
- * @note Calculation formula:
- * Temperature = ((TS_ADC_DATA - TS_CAL1)
- * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
- * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
- * with TS_ADC_DATA = temperature sensor raw data measured by ADC
- * Avg_Slope = (TS_CAL2 - TS_CAL1)
- * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
- * TS_CAL1 = equivalent TS_ADC_DATA at temperature
- * TEMP_DEGC_CAL1 (calibrated in factory)
- * TS_CAL2 = equivalent TS_ADC_DATA at temperature
- * TEMP_DEGC_CAL2 (calibrated in factory)
- * Caution: Calculation relevancy under reserve that calibration
- * parameters are correct (address and data).
- * To calculate temperature using temperature sensor
- * datasheet typical values (generic values less, therefore
- * less accurate than calibrated values),
- * use helper macro @ref
- * __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
- * @note As calculation input, the analog reference voltage (Vref+) must be
- * defined as it impacts the ADC LSB equivalent voltage.
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 series, calibration data of temperature sensor
- * corresponds to a resolution of 12 bits,
- * this is the recommended ADC resolution to convert voltage of
- * temperature sensor.
- * Otherwise, this macro performs the processing to scale
- * ADC conversion data to 12 bits.
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
- * temperature sensor (unit: digital value).
- * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
- * sensor voltage has been measured.
- * This parameter can be one of the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @retval Temperature (unit: degree Celsius)
- */
-#define __HAL_ADC_CALC_TEMPERATURE( \
- __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), (__ADC_RESOLUTION__))
-
-/**
- * @brief Helper macro to calculate the temperature (unit: degree Celsius)
- * from ADC conversion data of internal temperature sensor.
- * @note Computation is using temperature sensor typical values
- * (refer to device datasheet).
- * @note Calculation formula:
- * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
- * / Avg_Slope + CALx_TEMP
- * with TS_ADC_DATA = temperature sensor raw data measured by ADC
- * (unit: digital value)
- * Avg_Slope = temperature sensor slope
- * (unit: uV/Degree Celsius)
- * TS_TYP_CALx_VOLT = temperature sensor digital value at
- * temperature CALx_TEMP (unit: mV)
- * Caution: Calculation relevancy under reserve the temperature sensor
- * of the current device has characteristics in line with
- * datasheet typical values.
- * If temperature sensor calibration values are available on
- * on this device (presence of macro
- * __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate
- * using helper macro @ref __LL_ADC_CALC_TEMPERATURE().
- * @note As calculation input, the analog reference voltage (Vref+) must be
- * defined as it impacts the ADC LSB equivalent voltage.
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note ADC measurement data must correspond to a resolution of 12bits
- * (full scale digital value 4095). If not the case, the data must be
- * preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature
- * sensor slope typical value (unit: uV/DegCelsius). On STM32G4, refer to device
- * datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature
- * sensor voltage typical value (at temperature and Vref+ defined in parameters
- * below) (unit: mV). On STM32G4, refer to device datasheet parameter "V30"
- * (corresponding to TS_CAL1).
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at
- * which temperature sensor voltage (see parameter above) is corresponding
- * (unit: mV)
- * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+)
- * voltage (unit: mV)
- * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
- * temperature sensor (unit: digital value).
- * @param __ADC_RESOLUTION__ ADC resolution at which internal
- * temperature sensor voltage has been measured. This parameter can be one of
- * the following values:
- * @arg @ref ADC_RESOLUTION_12B
- * @arg @ref ADC_RESOLUTION_10B
- * @arg @ref ADC_RESOLUTION_8B
- * @arg @ref ADC_RESOLUTION_6B
- * @retval Temperature (unit: degree Celsius)
- */
-#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS( \
- __TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, \
- __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, \
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS( \
- (__TEMPSENSOR_TYP_AVGSLOPE__), (__TEMPSENSOR_TYP_CALX_V__), \
- (__TEMPSENSOR_CALX_TEMP__), (__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), (__ADC_RESOLUTION__))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include ADC HAL Extended module */
-#include "stm32g4xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc,
- HAL_ADC_CallbackIDTypeDef CallbackID,
- pADC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(
- ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group2
- * @brief IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc,
- uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData,
- uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or
- * interruption */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
-
-/* ADC sampling control */
-HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and
- * DMA) */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc,
- ADC_ChannelConfTypeDef *sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(
- ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
-
-/**
- * @}
- */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
- * @{
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions
- * -----------------------------------------------------------*/
-/** @addtogroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc,
- uint32_t ConversionGroup);
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAError(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_ADC_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_ADC_H
+#define STM32G4xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32g4xx_ll_adc.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC group regular oversampling structure definition
+ */
+typedef struct {
+ uint32_t
+ Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the
+ Oversampler. This parameter can be a value of @ref
+ ADC_HAL_EC_OVS_SHIFT */
+
+ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
+ This parameter can be a value of @ref
+ ADC_HAL_EC_OVS_DISCONT_MODE */
+
+ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
+ The oversampling is either temporary
+ stopped or reset upon an injected sequence
+ interruption. If oversampling is enabled on
+ both regular and injected groups, this
+ parameter is discarded and forced to
+ setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
+ (the oversampling buffer is zeroed during
+ injection sequence). This parameter can be
+ a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
+
+} ADC_OversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC instance and ADC group regular.
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects ADC groups regular and injected):
+ * ClockPrescaler, Resolution, DataAlign, GainCompensation, ScanConvMode,
+ * EOCSelection, LowPowerAutoWait.
+ * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion,
+ * DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConv,
+ * ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode,
+ * Oversampling, SamplingMode.
+ * @note The setting of these parameters by function HAL_ADC_Init() is
+ * conditioned to ADC state. ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'LowPowerAutoWait',
+ * 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on
+ * going on group regular.
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC
+ * enabled without conversion on going on groups regular and injected. If ADC is
+ * not in the appropriate state to modify some parameters, these parameters
+ * setting is bypassed without error reporting (as it can be the expected
+ * behavior in case of intended action to update another parameter (which
+ * fulfills the ADC state condition) on the fly).
+ */
+typedef struct {
+ uint32_t
+ ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived
+ from APB clock or asynchronous clock derived from
+ system clock or PLL (Refer to reference manual for list
+ of clocks available)) and clock prescaler. This
+ parameter can be a value of @ref
+ ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock
+ configuration is common to all ADC instances. Note: In
+ case of usage of channels on injected group, ADC
+ frequency should be lower than AHB clock frequency /4
+ for resolution 12 or 10 bits, AHB clock frequency /3
+ for resolution 8 bits, AHB clock frequency /2 for
+ resolution 6 bits. Note: In case of synchronous clock
+ mode based on HCLK/1, the configuration must be enabled
+ only if the system clock has a 50% duty clock cycle
+ (APB prescaler configured inside RCC must be bypassed
+ and PCLK clock must have 50% duty cycle). Refer to
+ reference manual for details. Note: In case of usage of
+ asynchronous clock, the selected clock must be
+ preliminarily enabled at RCC top level.
+ Note: This parameter can be modified only if all ADC
+ instances are disabled. */
+
+ uint32_t Resolution; /*!< Configure the ADC resolution.
+ This parameter can be a value of @ref
+ ADC_HAL_EC_RESOLUTION */
+
+ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data
+ register (right or left). Refer to reference manual for
+ alignments formats versus resolutions. This parameter
+ can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
+
+ uint32_t
+ GainCompensation; /*!< Specify the ADC gain compensation coefficient to be
+ applied to ADC raw conversion data, based on
+ following formula: DATA = DATA(raw) * (gain
+ compensation coef) / 4096 "2.12" bit format,
+ unsigned: 2 bits exponents / 12 bits mantissa Gain
+ step is 1/4096 = 0.000244 Gain range is 0.0000
+ to 3.999756 This parameter value can be 0 Gain
+ compensation will be disabled and coefficient set to
+ 0 1 -> 0x3FFF Gain compensation will be enabled and
+ coefficient set to specified value Note: Gain
+ compensation when enabled is applied to all channels.
+ */
+
+ uint32_t
+ ScanConvMode; /*!< Configure the sequencer of ADC groups regular and
+ injected. This parameter can be associated to parameter
+ 'DiscontinuousConvMode' to have main sequence subdivided
+ in successive parts. If disabled: Conversion is performed
+ in single mode (one channel converted, the one defined in
+ rank 1). Parameters 'NbrOfConversion' and
+ 'InjectedNbrOfConversion' are discarded
+ (equivalent to set to 1). If enabled: Conversions are
+ performed in sequence mode (multiple ranks defined by
+ 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank
+ of each channel in sequencer). Scan direction is upward:
+ from rank 1 to rank 'n'. This parameter can be a value of
+ @ref ADC_Scan_mode */
+
+ uint32_t
+ EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for
+ conversion by polling and interruption: end of unitary
+ conversion or end of sequence conversions. This parameter
+ can be a value of @ref ADC_EOCSelection. */
+
+ FunctionalState
+ LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new
+ conversion start only when the previous conversion
+ (for ADC group regular) or previous sequence (for ADC
+ group injected) has been retrieved by user software,
+ using function HAL_ADC_GetValue() or
+ HAL_ADCEx_InjectedGetValue(). This feature
+ automatically adapts the frequency of ADC conversions
+ triggers to the speed of the system that reads the
+ data. Moreover, this avoids risk of overrun for low
+ frequency applications. This parameter can be set to
+ ENABLE or DISABLE. Note: It is not recommended to use
+ with interruption or DMA (HAL_ADC_Start_IT(),
+ HAL_ADC_Start_DMA()) since these modes have to
+ clear immediately the EOC flag (by CPU to free the
+ IRQ pending event or by DMA). Auto wait will work but
+ fort a very short time, discarding its intended
+ benefit (except specific case of high load of
+ CPU or DMA transfers which can justify usage of auto
+ wait). Do use with polling: 1. Start conversion with
+ HAL_ADC_Start(), 2. Later on, when ADC conversion
+ data is needed: use HAL_ADC_PollForConversion() to
+ ensure that conversion is completed and
+ HAL_ADC_GetValue() to retrieve conversion
+ result and trig another conversion start. (in case of
+ usage of ADC group injected, use the equivalent
+ functions HAL_ADCExInjected_Start(),
+ HAL_ADCEx_InjectedGetValue(), ...). */
+
+ FunctionalState
+ ContinuousConvMode; /*!< Specify whether the conversion is performed in
+ single mode (one conversion) or continuous mode for
+ ADC group regular, after the first ADC conversion
+ start trigger occurred (software start or
+ external trigger). This parameter can be set to
+ ENABLE or DISABLE. */
+
+ uint32_t
+ NbrOfConversion; /*!< Specify the number of ranks that will be converted
+ within the regular group sequencer. This parameter is
+ dependent on ScanConvMode:
+ - sequencer configured to fully configurable:
+ Number of ranks in the scan sequence is
+ configurable using this parameter. Note: After the
+ first call of 'HAL_ADC_Init()', each rank
+ corresponding to parameter "NbrOfConversion" must be
+ set using 'HAL_ADC_ConfigChannel()'. Afterwards, when
+ all needed sequencer ranks are set, parameter
+ 'NbrOfConversion' can be updated without
+ modifying configuration of sequencer ranks (sequencer
+ ranks above 'NbrOfConversion' are discarded).
+ - sequencer configured to not fully configurable:
+ Number of ranks in the scan sequence is defined
+ by number of channels set in the sequence. This
+ parameter is discarded. This parameter must be a
+ number between Min_Data = 1 and Max_Data = 8. Note:
+ This parameter must be modified when no conversion is
+ on going on regular group (ADC disabled, or ADC
+ enabled without continuous mode or external trigger
+ that could launch a conversion). */
+
+ FunctionalState
+ DiscontinuousConvMode; /*!< Specify whether the conversions sequence of
+ ADC group regular is performed in
+ Complete-sequence/Discontinuous-sequence (main
+ sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer
+ is enabled (parameter 'ScanConvMode'). If
+ sequencer is disabled, this parameter is
+ discarded. Discontinuous mode can be enabled
+ only if continuous mode is disabled. If
+ continuous mode is enabled, this parameter
+ setting is discarded. This parameter can be set
+ to ENABLE or DISABLE. Note: On this STM32
+ series, ADC group regular number of
+ discontinuous ranks increment is fixed to
+ one-by-one. */
+
+ uint32_t
+ NbrOfDiscConversion; /*!< Specifies the number of discontinuous
+ conversions in which the main sequence of ADC
+ group regular (parameter NbrOfConversion) will be
+ subdivided. If parameter 'DiscontinuousConvMode'
+ is disabled, this parameter is discarded. This
+ parameter must be a number between Min_Data = 1
+ and Max_Data = 8. */
+
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to
+ trigger ADC group regular conversion start. If
+ set to ADC_SOFTWARE_START, external triggers are
+ disabled and software trigger is used instead.
+ This parameter can be a value of @ref
+ ADC_regular_external_trigger_source. Caution:
+ external trigger source is common to all ADC
+ instances. */
+
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to
+ trigger ADC group regular conversion start
+ If trigger source is set to
+ ADC_SOFTWARE_START, this parameter is
+ discarded. This parameter can be a value of
+ @ref ADC_regular_external_trigger_edge */
+
+ uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group
+ regular conversion. This parameter can be a value of
+ @ref ADC_regular_sampling_mode */
+
+ FunctionalState
+ DMAContinuousRequests; /*!< Specify whether the DMA requests are performed
+ in one shot mode (DMA transfer stops when number
+ of conversions is reached) or in continuous mode
+ (DMA transfer unlimited, whatever number of
+ conversions). This parameter can be set to
+ ENABLE or DISABLE. Note: In continuous mode, DMA
+ must be configured in circular mode. Otherwise
+ an overrun will be triggered when DMA buffer
+ maximum pointer is reached. */
+
+ uint32_t
+ Overrun; /*!< Select the behavior in case of overrun: data overwritten or
+ preserved (default). This parameter applies to ADC group
+ regular only. This parameter can be a value of @ref
+ ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. Note: In case of overrun set
+ to data preserved and usage with programming model with
+ interruption (HAL_Start_IT()): ADC IRQ handler has to clear
+ end of conversion flags, this induces the release of the
+ preserved data. If needed, this data can be saved in function
+ HAL_ADC_ConvCpltCallback(), placed in user program code
+ (called before end of conversion flags clear) Note: Error
+ reporting with respect to the conversion mode:
+ - Usage with ADC conversion by polling for event or
+ interruption: Error is reported only if overrun is set to data
+ preserved. If overrun is set to data overwritten, user can
+ willingly not read all the converted data, this is not
+ considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported
+ whatever overrun setting (DMA is expected to process all data
+ from data register). */
+
+ FunctionalState
+ OversamplingMode; /*!< Specify whether the oversampling feature is enabled
+ or disabled. This parameter can be set to ENABLE or
+ DISABLE. Note: This parameter can be modified only if
+ there is no conversion is ongoing on ADC groups
+ regular and injected */
+
+ ADC_OversamplingTypeDef
+ Oversampling; /*!< Specify the Oversampling parameters.
+ Caution: this setting overwrites the previous
+ oversampling configuration if oversampling is already
+ enabled. */
+
+} ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters by function HAL_ADC_ConfigChannel()
+ * is conditioned to ADC state. ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC
+ * state to modify parameter 'SingleDiff')
+ * - For all except parameters 'SamplingTime', 'Offset',
+ * 'OffsetNumber': ADC enabled without conversion on going on regular group.
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC
+ * enabled without conversion on going on regular and injected groups. If ADC is
+ * not in the appropriate state to modify some parameters, these parameters
+ * setting is bypassed without error reporting (as it can be the expected
+ * behavior in case of intended action to update another parameter (which
+ * fulfills the ADC state condition) on the fly).
+ */
+typedef struct {
+ uint32_t
+ Channel; /*!< Specify the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels
+ may not be available on device package pins. Refer to device
+ datasheet for channels availability. */
+
+ uint32_t
+ Rank; /*!< Specify the rank in the regular group sequencer.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
+ Note: to disable a channel or change order of conversion
+ sequencer, rank containing a previous channel setting can be
+ overwritten by the new channel setting (or parameter number of
+ conversions adjusted) */
+
+ uint32_t
+ SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and
+ processing time (12.5 ADC clock cycles at ADC resolution
+ 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8
+ bits, 6.5 cycles at 6 bits). This parameter can be a
+ value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME Caution:
+ This parameter applies to a channel that can be used into
+ regular and/or injected group. It overwrites the last
+ setting. Note: In case of usage of internal measurement
+ channels (VrefInt, Vbat, ...), sampling time constraints
+ must be respected (sampling time can be adjusted in
+ function of ADC clock frequency and sampling time
+ setting). Refer to device datasheet for timings values.
+ */
+
+ uint32_t SingleDiff; /*!< Select single-ended or differential input.
+ In differential mode: Differential measurement is
+ carried out between the selected channel 'i' (positive
+ input) and channel 'i+1' (negative input). Only
+ channel 'i' has to be configured, channel 'i+1' is
+ configured automatically This parameter must be a
+ value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+ Caution: This parameter applies to a channel that
+ can be used in a regular and/or injected group. It
+ overwrites the last setting. Note: Refer to Reference
+ Manual to ensure the selected channel is available in
+ differential mode.
+ Note: When configuring a channel 'i' in differential
+ mode, the channel 'i+1' is not usable separately.
+ Note: This parameter must be modified when ADC is
+ disabled (before ADC start conversion or after ADC
+ stop conversion). If ADC is enabled, this parameter
+ setting is bypassed without error reporting (as it can
+ be the expected behavior in case of another parameter
+ update on the fly) */
+
+ uint32_t OffsetNumber; /*!< Select the offset number
+ This parameter can be a value of @ref
+ ADC_HAL_EC_OFFSET_NB Caution: Only one offset is
+ allowed per channel. This parameter overwrites the
+ last setting. */
+
+ uint32_t
+ Offset; /*!< Define the offset to be applied on the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and
+ Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This
+ parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a
+ conversion). */
+
+ uint32_t
+ OffsetSign; /*!< Define if the offset should be subtracted (negative sign)
+ or added (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note: This parameter must be modified when no conversion
+ is on going on both regular and injected groups (ADC
+ disabled, or ADC enabled without continuous mode or
+ external trigger that could launch a conversion).*/
+ FunctionalState
+ OffsetSaturation; /*!< Define if the offset should be saturated upon under
+ or over flow. This parameter value can be ENABLE or
+ DISABLE. Note: This parameter must be modified when no
+ conversion is on going on both regular and injected
+ groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could
+ launch a conversion). */
+
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters by function
+ HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters except 'HighThreshold', 'LowThreshold': ADC
+ disabled or ADC enabled without conversion on going on ADC groups regular and
+ injected.
+ * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with
+ conversion on going on regular and injected groups.
+ */
+typedef struct {
+ uint32_t
+ WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the
+ selected channel. For Analog Watchdog 1: Only 1 channel
+ can be monitored (or overall group of channels by
+ setting parameter 'WatchdogMode') For Analog Watchdog 2
+ and 3: Several channels can be monitored (by successive
+ calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref
+ ADC_HAL_EC_AWD_NUMBER. */
+
+ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode:
+ single/all/none channels. For Analog Watchdog 1:
+ Configure the ADC analog watchdog mode: single
+ channel or all channels, ADC groups regular and-or
+ injected. For Analog Watchdog 2 and 3: Several
+ channels can be monitored by applying successively
+ the AWD init structure. Channels on ADC group
+ regular and injected are not differentiated: Set
+ value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
+ channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to
+ monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to
+ monitor no channel. This parameter can be a value of
+ @ref ADC_analog_watchdog_mode. */
+
+ uint32_t
+ Channel; /*!< Select which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if
+ parameter 'WatchdogMode' is configured on single channel (only
+ 1 channel can be monitored). For Analog Watchdog 2 and 3:
+ Several channels can be monitored. To use this feature, call
+ successively the function HAL_ADC_AnalogWDGConfig() for each
+ channel to be added (or removed with value
+ 'ADC_ANALOGWATCHDOG_NONE').
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured
+ in interrupt or polling mode. This parameter can be
+ set to ENABLE or DISABLE */
+
+ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold
+ value. Depending of ADC resolution selected (12,
+ 10, 8 or 6 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFF,
+ 0x3FF, 0xFF or 0x3F respectively. Note: Analog
+ watchdog 2 and 3 are limited to a resolution of 8
+ bits: if ADC resolution is 12 bits the 4 LSB are
+ ignored, if ADC resolution is 10 bits the 2 LSB are
+ ignored. Note: If ADC oversampling is enabled, ADC
+ analog watchdog thresholds are impacted: the
+ comparison of analog watchdog thresholds is done on
+ oversampling final computation (after ratio
+ and shift application): ADC data register bitfield
+ [15:4] (12 most significant bits). */
+
+ uint32_t
+ LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6
+ bits), this parameter must be a number between Min_Data =
+ 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+ respectively.
+ Note: Analog watchdog 2 and 3 are limited to a
+ resolution of 8 bits: if ADC resolution is 12 bits the 4
+ LSB are ignored, if ADC resolution is 10 bits the 2 LSB
+ are ignored. Note: If ADC oversampling is enabled, ADC
+ analog watchdog thresholds are impacted: the comparison
+ of analog watchdog thresholds is done on oversampling
+ final computation (after ratio and shift application):
+ ADC data register bitfield [15:4] (12 most
+ significant bits).*/
+
+ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the
+ number of samples to consider. Before setting
+ flag or raising interrupt, analog watchdog can
+ wait to have several consecutive out-of-window
+ samples. This parameter allows to configure this
+ number. This parameter only applies to Analog
+ watchdog 1. For others, use value
+ ADC_AWD_FILTERING_NONE.
+ This parameter can be a value of @ref
+ ADC_analog_watchdog_filtering_config. */
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief ADC group injected contexts queue configuration
+ * @note Structure intended to be used only through structure
+ * "ADC_HandleTypeDef"
+ */
+typedef struct {
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up
+ over each HAL_ADCEx_InjectedConfigChannel() call to
+ finally initialize JSQR register at
+ HAL_ADCEx_InjectedConfigChannel() last call */
+
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
+} ADC_InjectionConfigTypeDef;
+
+/** @defgroup ADC_States ADC States
+ * @{
+ */
+
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET \
+ (0x00000000UL) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY \
+ (0x00000001UL) /*!< ADC peripheral ready for use \
+ */
+#define HAL_ADC_STATE_BUSY_INTERNAL \
+ (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, \
+ calibration, ...) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL \
+ (0x00000010UL) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG \
+ (0x00000020UL) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY \
+ (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can \
+ occur (either by continuous mode, external trigger, low \
+ power auto power-on (if feature available), multimode ADC \
+ master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC \
+ (0x00000200UL) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP \
+ (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag \
+ raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY \
+ (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can \
+ occur (either by auto-injection mode, external trigger, \
+ low power auto power-on (if feature available), multimode \
+ ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC \
+ (0x00002000UL) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF \
+ (0x00004000UL) /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 \
+ (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 \
+ (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 \
+ (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE \
+ (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC \
+ master (when feature available) */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC handle Structure definition
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular
+ conversions setting */
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+ ADC_InjectionConfigTypeDef
+ InjectionConfig; /*!< ADC injected channel configuration build-up
+ structure */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (*ConvCpltCallback)(struct __ADC_HandleTypeDef
+ *hadc); /*!< ADC conversion complete callback */
+ void (*ConvHalfCpltCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
+ callback */
+ void (*LevelOutOfWindowCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (*ErrorCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (*InjectedConvCpltCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion
+ complete callback */
+ void (*InjectedQueueOverflowCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
+ overflow callback */
+ void (*LevelOutOfWindow2Callback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
+ void (*LevelOutOfWindow3Callback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
+ void (*EndOfSamplingCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
+ void (*MspInitCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (*MspDeInitCallback)(
+ struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum {
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID =
+ 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID =
+ 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID =
+ 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID =
+ 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID =
+ 0x05U, /*!< ADC group injected context queue overflow callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID =
+ 0x06U, /*!< ADC analog watchdog 2 callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID =
+ 0x07U, /*!< ADC analog watchdog 3 callback ID */
+ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(
+ ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE \
+ (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL \
+ (0x01U) /*!< ADC peripheral internal error (problem of clocking, \
+ enable/disable, erroneous state, ...) */
+#define HAL_ADC_ERROR_OVR \
+ (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA \
+ (0x04U) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF \
+ (0x08U) /*!< Injected context queue overflow error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+
+#define ADC_CLOCK_SYNC_PCLK_DIV1 \
+ (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock \
+ without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 \
+ (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock \
+ with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 \
+ (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock \
+ with prescaler division by 4 */
+#define ADC_CLOCK_ASYNC_DIV1 \
+ (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without \
+prescaler */
+#define ADC_CLOCK_ASYNC_DIV2 \
+ (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler \
+division by 2 */
+#define ADC_CLOCK_ASYNC_DIV4 \
+ (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler \
+division by 4 */
+#define ADC_CLOCK_ASYNC_DIV6 \
+ (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler \
+division by 6 */
+#define ADC_CLOCK_ASYNC_DIV8 \
+ (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler \
+division by 8 */
+#define ADC_CLOCK_ASYNC_DIV10 \
+ (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler \
+division by 10 */
+#define ADC_CLOCK_ASYNC_DIV12 \
+ (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler \
+division by 12 */
+#define ADC_CLOCK_ASYNC_DIV16 \
+ (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler \
+division by 16 */
+#define ADC_CLOCK_ASYNC_DIV32 \
+ (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler \
+division by 32 */
+#define ADC_CLOCK_ASYNC_DIV64 \
+ (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler \
+division by 64 */
+#define ADC_CLOCK_ASYNC_DIV128 \
+ (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler \
+division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256 \
+ (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler \
+division by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12B \
+ (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B \
+ (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B \
+ (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits \
+ */
+#define ADC_RESOLUTION_6B \
+ (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT \
+ (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned \
+ (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT \
+ (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned \
+ (alignment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger
+ * source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START \
+ (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion \
+trigger software start */
+#define ADC_EXTERNALTRIG_T1_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM1 TRGO. */
+#define ADC_EXTERNALTRIG_T1_TRGO2 \
+ (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM1 TRGO2. */
+#define ADC_EXTERNALTRIG_T1_CC1 \
+ (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM1 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC2 \
+ (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM1 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC3 \
+ (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM1 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM2 TRGO. */
+#define ADC_EXTERNALTRIG_T2_CC1 \
+ (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM2 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_CC2 \
+ (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM2 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_CC3 \
+ (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM2 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_T3_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM3 TRGO. */
+#define ADC_EXTERNALTRIG_T3_CC1 \
+ (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM3 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T3_CC4 \
+ (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_T4_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM4 TRGO. */
+#define ADC_EXTERNALTRIG_T4_CC1 \
+ (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM4 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T4_CC4 \
+ (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM4 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_T6_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM6 TRGO. */
+#define ADC_EXTERNALTRIG_T7_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM7 TRGO. */
+#define ADC_EXTERNALTRIG_T8_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM8 TRGO. */
+#define ADC_EXTERNALTRIG_T8_TRGO2 \
+ (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM8 TRGO2. */
+#define ADC_EXTERNALTRIG_T8_CC1 \
+ (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM8 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T15_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM15 TRGO. */
+#define ADC_EXTERNALTRIG_T20_TRGO \
+ (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM20 TRGO. */
+#define ADC_EXTERNALTRIG_T20_TRGO2 \
+ (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM20 TRGO2. */
+#define ADC_EXTERNALTRIG_T20_CC1 \
+ (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM20 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T20_CC2 \
+ (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM20 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T20_CC3 \
+ (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion \
+trigger from external peripheral: TIM20 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG1 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 1 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG2 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 2 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG3 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 3 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG4 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 4 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG5 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 5 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG6 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 6 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG7 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 7 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG8 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 8 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG9 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 9 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG10 \
+ (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion \
+trigger from external peripheral: HRTIMER ADC trigger 10 event. */
+#define ADC_EXTERNALTRIG_EXT_IT2 \
+ (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion \
+trigger from external peripheral: external interrupt line 2. */
+#define ADC_EXTERNALTRIG_EXT_IT11 \
+ (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion \
+trigger from external peripheral: external interrupt line 11. */
+#define ADC_EXTERNALTRIG_LPTIM_OUT \
+ (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion \
+trigger from external peripheral: LPTIMER OUT event. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge
+ * (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE \
+ (0x00000000UL) /*!< ADC group regular trigger \
+disabled (SW start)*/
+#define ADC_EXTERNALTRIGCONVEDGE_RISING \
+ (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion \
+trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING \
+ (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion \
+trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING \
+ (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion \
+ trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
+ * @{
+ */
+#define ADC_SAMPLING_MODE_NORMAL \
+ (0x00000000UL) /*!< ADC conversions sampling phase duration is \
+defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
+#define ADC_SAMPLING_MODE_BULB \
+ (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts \
+immediately after end of conversion, and stops upon trigger event. \
+Note: First conversion is using minimal sampling time \
+ (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
+#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED \
+ (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled \
+ by trigger events: \
+ Trigger rising edge = start sampling \
+ Trigger falling edge = stop sampling and start conversion */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or
+ * sequence conversions
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV \
+ (ADC_ISR_EOC) /*!< End of unitary conversion flag */
+#define ADC_EOC_SEQ_CONV \
+ (ADC_ISR_EOS) /*!< End of sequence conversions flag */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun
+ * behavior on conversion data
+ * @{
+ */
+#define ADC_OVR_DATA_PRESERVED \
+ (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case \
+of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN \
+ (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case \
+ of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 \
+ (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 \
+ (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 \
+ (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 \
+ (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 \
+ (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 \
+ (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 \
+ (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 \
+ (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9 \
+ (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10 \
+ (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11 \
+ (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12 \
+ (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13 \
+ (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14 \
+ (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15 \
+ (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16 \
+ (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC_SAMPLETIME_2CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_6CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_24CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
+#define ADC_SAMPLETIME_47CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
+#define ADC_SAMPLETIME_92CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
+#define ADC_SAMPLETIME_247CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles \
+ */
+#define ADC_SAMPLETIME_640CYCLES_5 \
+ (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles \
+ */
+#define ADC_SAMPLETIME_3CYCLES_5 \
+ (ADC_SMPR1_SMPPLUS | \
+ LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 \
+ADC clock cycles. If selected, this sampling time replaces sampling time \
+2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
+/* all ADC instances (refer to Reference Manual). */
+#define ADC_CHANNEL_0 \
+ (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 \
+ (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 \
+ (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 \
+ (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 \
+ (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 \
+ (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 \
+ (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 \
+ (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 \
+ (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 \
+ (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 \
+ (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 \
+ (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 \
+ (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 \
+ (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 \
+ (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 \
+ (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 \
+ (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 \
+ (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18 \
+ (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_VREFINT \
+ (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal \
+voltage reference. On this STM32 series, ADC channel available on all \
+instances but ADC2. */
+#define ADC_CHANNEL_TEMPSENSOR_ADC1 \
+ (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor. \
+ On this STM32 series, ADC channel available only on ADC1 instance. */
+#define ADC_CHANNEL_TEMPSENSOR_ADC5 \
+ (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor. \
+ On this STM32 series, ADC channel available only on ADC5 instance. \
+ Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VBAT \
+ (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage \
+through a divider ladder of factor 1/3 to have channel voltage always below \
+Vdda. \
+On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4. \
+Refer to device datasheet for ADC4 availability */
+#define ADC_CHANNEL_VOPAMP1 \
+ (LL_ADC_CHANNEL_VOPAMP1) /*!< Internal channel OPAMP1 output. \
+On this STM32 series, ADC channel available only on ADC1 instance. */
+#define ADC_CHANNEL_VOPAMP2 \
+ (LL_ADC_CHANNEL_VOPAMP2) /*!< Internal channel OPAMP2 output. \
+On this STM32 series, ADC channel available only on ADC2 instance. */
+#define ADC_CHANNEL_VOPAMP3_ADC2 \
+ (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< Internal channel OPAMP3 output. \
+On this STM32 series, ADC channel available only on ADC2 instance. */
+#define ADC_CHANNEL_VOPAMP3_ADC3 \
+ (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< Internal channel OPAMP3 output. \
+On this STM32 series, ADC channel available only on ADC3 instance. \
+Refer to device datasheet for ADC3 availability */
+#define ADC_CHANNEL_VOPAMP4 \
+ (LL_ADC_CHANNEL_VOPAMP4) /*!< Internal channel OPAMP4 output. \
+On this STM32 series, ADC channel available only on ADC5 instance. \
+Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VOPAMP5 \
+ (LL_ADC_CHANNEL_VOPAMP5) /*!< Internal channel OPAMP5 output. \
+On this STM32 series, ADC channel available only on ADC5 instance. \
+Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VOPAMP6 \
+ (LL_ADC_CHANNEL_VOPAMP6) /*!< Internal channel OPAMP6 output. \
+On this STM32 series, ADC channel available only on ADC4 instance. \
+Refer to device datasheet for ADC4 availability */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD)
+ * number
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 \
+ (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 \
+ */
+#define ADC_ANALOGWATCHDOG_2 \
+ (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 \
+ */
+#define ADC_ANALOGWATCHDOG_3 \
+ (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD)
+ * filtering configuration
+ * @{
+ */
+#define ADC_AWD_FILTERING_NONE \
+ (0x00000000UL) /*!< ADC AWD no filtering, one \
+out-of-window sample to raise flag or interrupt */
+#define ADC_AWD_FILTERING_2SAMPLES \
+ ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives \
+out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_3SAMPLES \
+ ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives \
+out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_4SAMPLES \
+ ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives \
+ out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_5SAMPLES \
+ ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives \
+out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_6SAMPLES \
+ ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives \
+ out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_7SAMPLES \
+ ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives \
+ out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_8SAMPLES \
+ ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | \
+ ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives \
+out-of-window samples to raise flag or interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG \
+ (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular \
+group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC \
+ (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an \
+ injected group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC \
+ (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied \
+ to a regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG \
+ (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular \
+group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC \
+ (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected \
+group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC \
+ (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular \
+and injected groups all channels */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+/**
+ * @note The oversampling ratio is the number of ADC conversions performed, sum
+ * of these conversions data is computed to result as the ADC oversampling
+ * conversion data (before potential shift)
+ */
+#define ADC_OVERSAMPLING_RATIO_2 \
+ (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */
+#define ADC_OVERSAMPLING_RATIO_4 \
+ (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */
+#define ADC_OVERSAMPLING_RATIO_8 \
+ (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */
+#define ADC_OVERSAMPLING_RATIO_16 \
+ (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */
+#define ADC_OVERSAMPLING_RATIO_32 \
+ (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */
+#define ADC_OVERSAMPLING_RATIO_64 \
+ (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */
+#define ADC_OVERSAMPLING_RATIO_128 \
+ (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */
+#define ADC_OVERSAMPLING_RATIO_256 \
+ (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+/**
+ * @note The sum of the ADC conversions data is divided by "Rightbitshift"
+ * number to result as the ADC oversampling conversion data)
+ */
+#define ADC_RIGHTBITSHIFT_NONE \
+ (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
+#define ADC_RIGHTBITSHIFT_1 \
+ (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2 \
+ (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3 \
+ (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4 \
+ (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5 \
+ (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6 \
+ (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7 \
+ (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8 \
+ (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER \
+ (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: \
+continuous mode (all conversions of OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER \
+ (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: \
+discontinuous mode (each conversion of OVS ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for
+ * ADC group regular
+ * @{
+ */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE \
+ (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained \
+ during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE \
+ (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during \
+injection sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+/**
+ * @note Analog watchdog 1 is available on all stm32 series
+ * Analog watchdog 2 and 3 are not available on all series
+ */
+#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT \
+ (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
+#define ADC_AWD2_EVENT \
+ (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog \
+ watchdog) */
+#define ADC_AWD3_EVENT \
+ (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog \
+ watchdog) */
+#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT \
+ (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+/**
+ * @}
+ */
+#define ADC_AWD_EVENT \
+ ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility \
+ with other STM32 devices having only one analog watchdog \
+ */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP \
+ ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC \
+ ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS \
+ ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt \
+ source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC \
+ ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS \
+ ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt \
+ source */
+#define ADC_IT_AWD1 \
+ ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog \
+ watchdog) */
+#define ADC_IT_AWD2 \
+ ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional \
+analog watchdog) */
+#define ADC_IT_AWD3 \
+ ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional \
+analog watchdog) */
+#define ADC_IT_JQOVF \
+ ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS \
+ ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS \
+ ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 \
+ ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2 \
+ ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3 \
+ ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF \
+ ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Return resolution bits in CFGR register RES[1:0] field.
+ * @param __HANDLE__ ADC handle
+ * @retval Value of bitfield RES in CFGR register.
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) \
+ (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+ * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Simultaneously clear and set specific bits of the handle State.
+ * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro
+ * MODIFY_REG(), the first parameter is the ADC handle State, the second
+ * parameter is the bit field to clear, the third and last parameter is the bit
+ * field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Verify that a given value is aligned with the ADC resolution range.
+ * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+ * @param __ADC_VALUE__ value checked against the resolution.
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET
+ * (__ADC_VALUE__ not in line with __RESOLUTION__)
+ */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/**
+ * @brief Verify the length of the scheduled regular conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable
+ * regular conversions) or RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) \
+ (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+/**
+ * @brief Verify the number of scheduled regular conversions in discontinuous
+ * mode.
+ * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+ * @retval SET (NUMBER is within the maximum number of regular conversions in
+ * discontinuous mode) or RESET (NUMBER is null or too large)
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) \
+ (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+/**
+ * @brief Verify the ADC clock setting.
+ * @param __ADC_CLOCK__ programmed ADC clock.
+ * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is
+ * invalid)
+ */
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) \
+ (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256))
+
+/**
+ * @brief Verify the ADC resolution setting.
+ * @param __RESOLUTION__ programmed ADC resolution.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is
+ * invalid)
+ */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) \
+ (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B))
+
+/**
+ * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+ * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is
+ * invalid)
+ */
+#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) \
+ (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B))
+
+/**
+ * @brief Verify the ADC converted data alignment.
+ * @param __ALIGN__ programmed ADC converted data alignment.
+ * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
+ */
+#define IS_ADC_DATA_ALIGN(__ALIGN__) \
+ (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || ((__ALIGN__) == ADC_DATAALIGN_LEFT))
+
+/**
+ * @brief Verify the ADC gain compensation.
+ * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
+ * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET
+ * (__GAIN_COMPENSATION__ is invalid)
+ */
+#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) \
+ ((__GAIN_COMPENSATION__) <= 16393UL)
+
+/**
+ * @brief Verify the ADC scan mode.
+ * @param __SCAN_MODE__ programmed ADC scan mode.
+ * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+ */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) \
+ (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+ ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
+
+/**
+ * @brief Verify the ADC edge trigger setting for regular group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) \
+ (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __HANDLE__ ADC handle
+ * @param __REGTRIG__ programmed ADC regular conversions external trigger.
+ * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
+ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
+ ((__HANDLE__)->Instance == ADC5)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START))
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
+ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
+ ((__HANDLE__)->Instance == ADC5)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START))
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
+ ((((__HANDLE__)->Instance == ADC3)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START))
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || \
+ defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
+ (((__HANDLE__)->Instance == ADC3) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START))
+#endif /* STM32G4xx */
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
+ * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is
+ * invalid)
+ */
+#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) \
+ (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
+ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
+ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED))
+
+/**
+ * @brief Verify the ADC regular conversions check for converted data
+ * availability.
+ * @param __EOC_SELECTION__ converted data availability check.
+ * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__
+ * is invalid)
+ */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) \
+ (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
+ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV))
+
+/**
+ * @brief Verify the ADC regular conversions overrun handling.
+ * @param __OVR__ ADC regular conversions overrun handling.
+ * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+ */
+#define IS_ADC_OVERRUN(__OVR__) \
+ (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
+ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN))
+
+/**
+ * @brief Verify the ADC conversions sampling time.
+ * @param __TIME__ ADC conversions sampling time.
+ * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
+ */
+#define IS_ADC_SAMPLE_TIME(__TIME__) \
+ (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5))
+
+/**
+ * @brief Verify the ADC regular channel setting.
+ * @param __CHANNEL__ programmed ADC regular channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) \
+ (((__CHANNEL__) == ADC_REGULAR_RANK_1) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_2) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_3) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_4) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_5) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_6) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_7) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_8) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_9) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_16))
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Fixed timeout values for ADC conversion (including sampling time) */
+/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
+/* Maximum conversion time is 12.5 + Maximum sampling time */
+/* or 12.5 + 640.5 = 653 ADC clock cycles */
+/* Minimum ADC Clock frequency is 0.14 MHz */
+/* Maximum conversion time is */
+/* 653 / 0.14 MHz = 4.66 ms */
+#define ADC_STOP_CONVERSION_TIMEOUT (5UL) /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle,
+ * IT and flags.
+ * @{
+ */
+
+/** @brief Reset ADC handle state.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while (0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt
+ * source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions
+ * interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt
+ * source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of
+ * Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source
+ * (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source
+ * (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source
+ * (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow
+ * interrupt source.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt
+ * source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions
+ * interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt
+ * source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of
+ * Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source
+ * (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source
+ * (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source
+ * (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow
+ * interrupt source.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt
+ * source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions
+ * interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt
+ * source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of
+ * Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source
+ * (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source
+ * (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source
+ * (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow
+ * interrupt source.
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified ADC flag is set or not.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of
+ * Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of
+ * Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog
+ * watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional
+ * analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional
+ * analog watchdog)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow
+ * flag.
+ * @retval State of flag (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified ADC flag.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of
+ * Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of
+ * Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog
+ * watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional
+ * analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional
+ * analog watchdog)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow
+ * flag.
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of
+ * register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals ADC_CHANNEL_x.
+ * @note Example:
+ * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1 (8)
+ * @arg @ref ADC_CHANNEL_2 (8)
+ * @arg @ref ADC_CHANNEL_3 (8)
+ * @arg @ref ADC_CHANNEL_4 (8)
+ * @arg @ref ADC_CHANNEL_5 (8)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (7)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref ADC_CHANNEL_VBAT (6)
+ * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+ * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1 (8)
+ * @arg @ref ADC_CHANNEL_2 (8)
+ * @arg @ref ADC_CHANNEL_3 (8)
+ * @arg @ref ADC_CHANNEL_4 (8)
+ * @arg @ref ADC_CHANNEL_5 (8)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (7)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref ADC_CHANNEL_VBAT (6)
+ * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n
+ * - On this STM32 series, all ADCx are not available on all devices.
+ * Refer to device datasheet for more details. (8) On STM32G4, fast channel
+ * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
+ * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
+ * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
+ * register, comparison with internal channel parameter to be done using helper
+ * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1 (8)
+ * @arg @ref ADC_CHANNEL_2 (8)
+ * @arg @ref ADC_CHANNEL_3 (8)
+ * @arg @ref ADC_CHANNEL_4 (8)
+ * @arg @ref ADC_CHANNEL_5 (8)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (7)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref ADC_CHANNEL_VBAT (6)
+ * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval Value "0" if the channel corresponds to a parameter definition of a
+ * ADC external channel (channel connected to a GPIO pin). Value "1" if the
+ * channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1 (8)
+ * @arg @ref ADC_CHANNEL_2 (8)
+ * @arg @ref ADC_CHANNEL_3 (8)
+ * @arg @ref ADC_CHANNEL_4 (8)
+ * @arg @ref ADC_CHANNEL_5 (8)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT (7)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref ADC_CHANNEL_VBAT (6)
+ * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_VREFINT (7)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref ADC_CHANNEL_VBAT (6)
+ * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details.
+ * @retval Value "0" if the internal channel selected is not available on the
+ * ADC instance selected. Value "1" if the internal channel selected is
+ * available on the ADC instance selected.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data
+ * concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and
+ * Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, \
+ __ADC_MULTI_CONV_DATA__) \
+ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), \
+ (__ADC_MULTI_CONV_DATA__))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common
+ * instance is enabled.
+ */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data full-scale digital value
+ */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION( \
+ __DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
+ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), (__ADC_RESOLUTION_CURRENT__), \
+ (__ADC_RESOLUTION_TARGET__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), (__ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value)
+ * in differential ended mode.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, \
+ __ADC_DATA__, __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), (__ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref
+ * __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 series, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE( \
+ __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
+ (__TEMPSENSOR_ADC_DATA__), (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by
+ ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro
+ __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature
+ sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32G4, refer to device datasheet
+ parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature
+ sensor voltage typical value (at temperature and Vref+ defined in parameters
+ below) (unit: mV).
+ * On STM32G4, refer to device datasheet
+ parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at
+ which temperature sensor voltage (see parameter above) is corresponding (unit:
+ mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+)
+ voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal
+ temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS( \
+ __TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, \
+ __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS( \
+ (__TEMPSENSOR_TYP_AVGSLOPE__), (__TEMPSENSOR_TYP_CALX_V__), \
+ (__TEMPSENSOR_CALX_TEMP__), (__VREFANALOG_VOLTAGE__), \
+ (__TEMPSENSOR_ADC_DATA__), (__ADC_RESOLUTION__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extended module */
+#include "stm32g4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc,
+ HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(
+ ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc,
+ uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData,
+ uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or
+ * interruption */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
+
+/* ADC sampling control */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and
+ * DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc,
+ const ADC_ChannelConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(
+ ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
+
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc,
+ uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_ADC_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
index 2daf315..aee04ac 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
@@ -1,1804 +1,1707 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_adc_ex.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_ADC_EX_H
-#define STM32G4xx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
- * @{
- */
-
-/**
- * @brief ADC Injected Conversion Oversampling structure definition
- */
-typedef struct {
- uint32_t
- Ratio; /*!< Configures the oversampling ratio.
- This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
-
- uint32_t RightBitShift; /*!< Configures the division coefficient for the
- Oversampler. This parameter can be a value of @ref
- ADC_HAL_EC_OVS_SHIFT */
-} ADC_InjOversamplingTypeDef;
-
-/**
- * @brief Structure definition of ADC group injected and ADC channel affected
- * to ADC group injected
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime
- * , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset,
- * InjectedOffsetSign, InjectedOffsetSaturation
- * - Scope ADC group injected (affects all channels of injected group):
- * InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv,
- * QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
- * InjecOversamplingMode, InjecOversampling.
- * @note The setting of these parameters by function
- * HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can
- * be either:
- * - For all parameters: ADC disabled (this is the only possible ADC
- * state to modify parameter 'InjectedSingleDiff')
- * - For parameters 'InjectedDiscontinuousConvMode',
- * 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion
- * on going on injected group.
- * - For parameters 'InjectedSamplingTime', 'InjectedOffset',
- * 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation',
- * 'AutoInjectedConv': ADC enabled without conversion on going on regular and
- * injected groups.
- * - For parameters 'InjectedChannel', 'InjectedRank',
- * 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
- * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC
- * groups regular and injected. If ADC is not in the appropriate state to modify
- * some parameters, these parameters setting is bypassed without error reporting
- * (as it can be the expected behavior in case of intended action to update
- * another parameter (which fulfills the ADC state condition) on the fly).
- */
-typedef struct {
- uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC
- group injected. This parameter can be a value of
- @ref ADC_HAL_EC_CHANNEL Note: Depending on
- devices and ADC instances, some channels may not
- be available on device package pins. Refer to
- device datasheet for channels availability. */
-
- uint32_t
- InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
- This parameter must be a value of @ref
- ADC_INJ_SEQ_RANKS. Note: to disable a channel or change
- order of conversion sequencer, rank containing a previous
- channel setting can be overwritten by the new channel
- setting (or parameter number of conversions adjusted) */
-
- uint32_t
- InjectedSamplingTime; /*!< Sampling time value to be set for the selected
- channel. Unit: ADC clock cycles. Conversion time
- is the addition of sampling time and processing
- time (12.5 ADC clock cycles at ADC resolution 12
- bits, 10.5 cycles at 10 bits, 8.5 cycles at 8
- bits, 6.5 cycles at 6 bits). This parameter can
- be a value of @ref
- ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution: This
- parameter applies to a channel that can be used
- in a regular and/or injected group. It overwrites
- the last setting. Note: In case of usage of
- internal measurement channels
- (VrefInt/Vbat/TempSensor), sampling time
- constraints must be respected (sampling time can
- be adjusted in function of ADC clock frequency
- and sampling time setting) Refer to device
- datasheet for timings values. */
-
- uint32_t
- InjectedSingleDiff; /*!< Selection of single-ended or differential input.
- In differential mode: Differential measurement is
- between the selected channel 'i' (positive input)
- and channel 'i+1' (negative input). Only channel
- 'i' has to be configured, channel 'i+1' is
- configured automatically. This parameter must be a
- value of @ref
- ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. Caution:
- This parameter applies to a channel that can be
- used in a regular and/or injected group. It
- overwrites the last setting. Note: Refer to
- Reference Manual to ensure the selected channel is
- available in differential mode. Note: When
- configuring a channel 'i' in differential mode, the
- channel 'i+1' is not usable separately. Note: This
- parameter must be modified when ADC is disabled
- (before ADC start conversion or after ADC stop
- conversion). If ADC is enabled, this parameter
- setting is bypassed without error reporting (as it
- can be the expected behavior in case of another
- parameter update on the fly) */
-
- uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
- This parameter can be a value of @ref
- ADC_HAL_EC_OFFSET_NB. Caution: Only one
- offset is allowed per channel. This
- parameter overwrites the last setting. */
-
- uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw
- converted data. Offset value must be a positive
- number. Depending of ADC resolution selected (12,
- 10, 8 or 6 bits), this parameter must be a number
- between Min_Data = 0x000 and Max_Data = 0xFFF,
- 0x3FF, 0xFF or 0x3F respectively. Note: This
- parameter must be modified when no conversion is
- on going on both regular and injected groups (ADC
- disabled, or ADC enabled without continuous mode
- or external trigger that could launch a
- conversion). */
-
- uint32_t
- InjectedOffsetSign; /*!< Define if the offset should be subtracted
- (negative sign) or added (positive sign) from or to
- the raw converted data. This parameter can be a value
- of @ref ADCEx_OffsetSign. Note: This parameter must
- be modified when no conversion is on going on both
- regular and injected groups (ADC disabled, or ADC
- enabled without continuous mode or external trigger
- that could launch a conversion). */
- FunctionalState
- InjectedOffsetSaturation; /*!< Define if the offset should be saturated
- upon under or over flow. This parameter value
- can be ENABLE or DISABLE. Note: This parameter
- must be modified when no conversion is on going
- on both regular and injected groups (ADC
- disabled, or ADC enabled without continuous
- mode or external trigger that could launch a
- conversion). */
-
- uint32_t
- InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be
- converted within the ADC group injected
- sequencer. To use the injected group sequencer
- and convert several ranks, parameter
- 'ScanConvMode' must be enabled. This parameter
- must be a number between Min_Data = 1 and
- Max_Data = 4. Caution: this setting impacts
- the entire injected group. Therefore, call of
- HAL_ADCEx_InjectedConfigChannel() to configure
- a channel on injected group can impact the
- configuration of other channels previously
- set. */
-
- FunctionalState
- InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions
- sequence of ADC group injected is performed
- in Complete-sequence/Discontinuous-sequence
- (main sequence subdivided in successive
- parts). Discontinuous mode is used only if
- sequencer is enabled (parameter
- 'ScanConvMode'). If sequencer is disabled,
- this parameter is discarded. Discontinuous
- mode can be enabled only if continuous mode
- is disabled. This parameter can be set to
- ENABLE or DISABLE. Note: This parameter must
- be modified when ADC is disabled (before ADC
- start conversion or after ADC stop
- conversion). Note: For injected group,
- discontinuous mode converts the sequence
- channel by channel (discontinuous length
- fixed to 1 rank). Caution: this setting
- impacts the entire injected group. Therefore,
- call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected
- group can impact the configuration of other
- channels previously set. */
-
- FunctionalState
- AutoInjectedConv; /*!< Enables or disables the selected ADC group injected
- automatic conversion after regular one This parameter
- can be set to ENABLE or DISABLE. Note: To use
- Automatic injected conversion, discontinuous mode
- must be disabled ('DiscontinuousConvMode' and
- 'InjectedDiscontinuousConvMode' set to DISABLE) Note:
- To use Automatic injected conversion, injected group
- external triggers must be disabled
- ('ExternalTrigInjecConv' set to
- ADC_INJECTED_SOFTWARE_START) Note: In case of DMA
- used with regular group: if DMA configured in normal
- mode (single shot) JAUTO will be stopped upon DMA
- transfer complete. To maintain JAUTO always enabled,
- DMA must be configured in circular mode. Caution:
- this setting impacts the entire injected group.
- Therefore, call of HAL_ADCEx_InjectedConfigChannel()
- to configure a channel on injected group can impact
- the configuration of other channels previously set.
- */
-
- FunctionalState
- QueueInjectedContext; /*!< Specifies whether the context queue feature is
- enabled. This parameter can be set to ENABLE or
- DISABLE. If context queue is enabled, injected
- sequencer&channels configurations are queued on
- up to 2 contexts. If a new injected context is
- set when queue is full, error is triggered by
- interruption and through function
- 'HAL_ADCEx_InjectedQueueOverflowCallback'.
- Caution: This feature request that the sequence
- is fully configured before injected conversion
- start. Therefore, configure channels with as many
- calls to HAL_ADCEx_InjectedConfigChannel() as the
- 'InjectedNbrOfConversion' parameter. Caution:
- this setting impacts the entire injected group.
- Therefore, call of
- HAL_ADCEx_InjectedConfigChannel() to configure a
- channel on injected group can impact the
- configuration of other channels previously set.
- Note: This parameter must be modified when ADC
- is disabled (before ADC start conversion or after
- ADC stop conversion). */
-
- uint32_t
- ExternalTrigInjecConv; /*!< Selects the external event used to trigger the
- conversion start of injected group. If set to
- ADC_INJECTED_SOFTWARE_START, external triggers
- are disabled and software trigger is used
- instead. This parameter can be a value of @ref
- ADC_injected_external_trigger_source. Caution:
- this setting impacts the entire injected group.
- Therefore, call of
- HAL_ADCEx_InjectedConfigChannel() to configure a
- channel on injected group can impact the
- configuration of other channels previously set.
- */
-
- uint32_t
- ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of
- injected group. This parameter can be a
- value of @ref
- ADC_injected_external_trigger_edge. If
- trigger source is set to
- ADC_INJECTED_SOFTWARE_START, this parameter
- is discarded. Caution: this setting impacts
- the entire injected group. Therefore, call
- of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected
- group can impact the configuration of other
- channels previously set. */
-
- FunctionalState
- InjecOversamplingMode; /*!< Specifies whether the oversampling feature is
- enabled or disabled. This parameter can be set
- to ENABLE or DISABLE. Note: This parameter can
- be modified only if there is no conversion is
- ongoing (both ADSTART and JADSTART cleared). */
-
- ADC_InjOversamplingTypeDef
- InjecOversampling; /*!< Specifies the Oversampling parameters.
- Caution: this setting overwrites the previous
- oversampling configuration if oversampling already
- enabled. Note: This parameter can be modified only
- if there is no conversion is ongoing (both ADSTART
- and JADSTART cleared). */
-} ADC_InjectionConfTypeDef;
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Structure definition of ADC multimode
- * @note The setting of these parameters by function
- * HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master
- * and Slave ADCs). Both Master and Slave ADCs must be disabled.
- */
-typedef struct {
- uint32_t
- Mode; /*!< Configures the ADC to operate in independent or multimode.
- This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
-
- uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
- selection whether 2 DMA channels (each ADC uses
- its own DMA channel) or 1 DMA channel (one DMA
- channel for both ADC, DMA of ADC master) This
- parameter can be a value of @ref
- ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
-
- uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling
- phases. This parameter can be a value of @ref
- ADC_HAL_EC_MULTI_TWOSMP_DELAY. Delay range
- depends on selected resolution: from 1 to 12
- clock cycles for 12 bits, from 1 to 10 clock
- cycles for 10 bits, from 1 to 8 clock cycles for
- 8 bits, from 1 to 6 clock cycles for 6 bits. */
-} ADC_MultiModeTypeDef;
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
- * @{
- */
-
-/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger
- * source
- * @{
- */
-/* ADC group regular trigger sources for all ADC instances */
-#define ADC_INJECTED_SOFTWARE_START \
- (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion \
- start */
-#define ADC_EXTERNALTRIGINJEC_T1_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM1 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 \
- (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM1 TRGO2. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T1_CC3 \
- (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM1 channel 3 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T1_CC4 \
- (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM1 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T2_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM2 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T2_CC1 \
- (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM2 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T3_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM3 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T3_CC1 \
- (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM3 channel 1 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T3_CC3 \
- (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM3 channel 3 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T3_CC4 \
- (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM3 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T4_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM4 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T4_CC3 \
- (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM4 channel 3 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T4_CC4 \
- (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM4 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T6_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM6 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T7_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM7 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T8_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM8 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 \
- (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM8 TRGO2. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T8_CC2 \
- (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM8 channel 2 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T8_CC4 \
- (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM8 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T15_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM15 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T16_CC1 \
- (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM8 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T20_TRGO \
- (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM20 TRGO. \
- Trigger edge set to rising edge (default \
- setting). */
-#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 \
- (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM20 TRGO2. \
- Trigger edge set to rising edge \
- (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T20_CC2 \
- (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM20 channel 2 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_T20_CC4 \
- (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger \
- from external peripheral: TIM20 channel 4 \
- event (capture compare: input capture or \
- output capture). Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 1 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 2 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 3 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 4 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 5 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 6 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 7 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 8 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 9 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 \
- (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger \
- from external peripheral: HRTIMER ADC \
- trigger 10 event. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_EXT_IT3 \
- (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger \
- from external peripheral: external \
- interrupt line 3. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_EXT_IT15 \
- (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger \
- from external peripheral: external \
- interrupt line 15. Trigger edge set to \
- rising edge (default setting). */
-#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT \
- (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger \
- from external peripheral: LPTIMER OUT \
- event. Trigger edge set to rising edge \
- (default setting). */
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge
- * (when external trigger is selected)
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE \
- (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled \
- */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING \
- (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on \
- the rising edge */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING \
- (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on \
- the falling edge */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING \
- (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on \
- both the rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or
- * differential ending
- * @{
- */
-#define ADC_SINGLE_ENDED \
- (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal \
- also used to set calibration mode) */
-#define ADC_DIFFERENTIAL_ENDED \
- (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential \
- (literal also used to set calibration mode) \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
- * @{
- */
-#define ADC_OFFSET_NONE \
- (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the \
- selected ADC channel */
-#define ADC_OFFSET_1 \
- (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-#define ADC_OFFSET_2 \
- (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-#define ADC_OFFSET_3 \
- (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-#define ADC_OFFSET_4 \
- (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
- * @{
- */
-#define ADC_OFFSET_SIGN_NEGATIVE \
- (0x00000000UL) /*!< Offset sign negative, offset is subtracted */
-#define ADC_OFFSET_SIGN_POSITIVE \
- (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */
-/**
- * @}
- */
-
-/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
- * @{
- */
-#define ADC_INJECTED_RANK_1 \
- (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
-#define ADC_INJECTED_RANK_2 \
- (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
-#define ADC_INJECTED_RANK_3 \
- (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
-#define ADC_INJECTED_RANK_4 \
- (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
-/**
- * @}
- */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
- * @{
- */
-#define ADC_MODE_INDEPENDENT \
- (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent \
- mode) */
-#define ADC_DUALMODE_REGSIMULT \
- (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular \
- simultaneous */
-#define ADC_DUALMODE_INTERL \
- (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group \
- regular interleaved */
-#define ADC_DUALMODE_INJECSIMULT \
- (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected \
- simultaneous */
-#define ADC_DUALMODE_ALTERTRIG \
- (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected \
- alternate trigger. Works only with \
- external triggers (not internal SW start) \
- */
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT \
- (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined \
- group regular simultaneous + group \
- injected simultaneous */
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG \
- (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined \
- group regular simultaneous + group \
- injected alternate trigger */
-#define ADC_DUALMODE_REGINTERL_INJECSIMULT \
- (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined \
- group regular interleaved + group \
- injected simultaneous */
-
-/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer
- * mode depending on ADC resolution
- * @{
- */
-#define ADC_DMAACCESSMODE_DISABLED \
- (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA \
- channel */
-#define ADC_DMAACCESSMODE_12_10_BITS \
- (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, \
- DMA of ADC master) for 12 and 10 bits resolution */
-#define ADC_DMAACCESSMODE_8_6_BITS \
- (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA \
- of ADC master) for 8 and 6 bits resolution */
-/**
- * @}
- */
-
-/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two
- * sampling phases
- * @{
- */
-#define ADC_TWOSAMPLINGDELAY_1CYCLE \
- (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two \
- sampling phases: 1 ADC clock cycle */
-#define ADC_TWOSAMPLINGDELAY_2CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 2 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_3CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 3 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_4CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 4 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_5CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 5 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_6CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 6 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_7CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 7 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_8CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 8 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_9CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 9 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_10CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 10 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_11CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 11 ADC clock cycles \
- */
-#define ADC_TWOSAMPLINGDELAY_12CYCLES \
- (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two \
- sampling phases: 12 ADC clock cycles \
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
- * @{
- */
-#define ADC_REGULAR_GROUP \
- (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 \
- devices) */
-#define ADC_INJECTED_GROUP \
- (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 \
- devices)*/
-#define ADC_REGULAR_INJECTED_GROUP \
- (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_CFGR_fields ADCx CFGR fields
- * @{
- */
-#define ADC_CFGR_FIELDS \
- (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | \
- ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | \
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES | \
- ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
-/**
- * @}
- */
-
-/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
- * @{
- */
-#if defined(ADC_SMPR1_SMPPLUS)
-#define ADC_SMPR1_FIELDS \
- (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | \
- ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | \
- ADC_SMPR1_SMP1 | ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
-#else
-#define ADC_SMPR1_FIELDS \
- (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | \
- ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | \
- ADC_SMPR1_SMP1 | ADC_SMPR1_SMP0)
-#endif /* ADC_SMPR1_SMPPLUS */
-/**
- * @}
- */
-
-/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
- * @{
- */
-/* ADC_CFGR fields of parameters that can be updated when no conversion
- (neither regular nor injected) is on-going */
-#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
- * @{
- */
-
-/** @brief Force ADC instance in multimode mode independent (multimode
- * disable).
- * @note This macro must be used only in case of transition from multimode
- * to mode independent and in case of unknown previous state,
- * to ensure ADC configuration is in mode independent.
- * @note Standard way of multimode configuration change is done from
- * HAL ADC handle of ADC master using function
- * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
- * Usage of this macro is not the Standard way of multimode
- * configuration and can lead to have HAL ADC handles status
- * misaligned. Usage of this macro must be limited to cases
- * mentioned above.
- * @param __HANDLE__ ADC handle.
- * @retval None
- */
-#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
- LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), \
- LL_ADC_MULTI_INDEPENDENT)
-
-/**
- * @}
- */
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private
- * Macros
- * @{
- */
-/* Macro reserved for internal HAL driver usage, not intended to be used in */
-/* code of final user. */
-
-/**
- * @brief Test if conversion trigger of injected group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle.
- * @retval SET (software start) or RESET (external trigger).
- */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
- (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
-
-/**
- * @brief Check whether or not ADC is independent.
- * @param __HANDLE__ ADC handle.
- * @note When multimode feature is not available, the macro always returns SET.
- * @retval SET (ADC is independent) or RESET (ADC is not).
- */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-#define ADC_IS_INDEPENDENT(__HANDLE__) \
- (((((__HANDLE__)->Instance) == ADC5)) ? SET : RESET)
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define ADC_IS_INDEPENDENT(__HANDLE__) \
- (((((__HANDLE__)->Instance) == ADC3)) ? SET : RESET)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
- defined(STM32G471xx)
-#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
-#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) \
- || defined(STM32G483xx) */
-
-/**
- * @brief Set the selected injected Channel rank.
- * @param __CHANNELNB__ Channel number.
- * @param __RANKNB__ Rank number.
- * @retval None
- */
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
- ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> \
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
- << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
-
-/**
- * @brief Configure ADC injected context queue
- * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
- * @retval None
- */
-#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
- ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
-
-/**
- * @brief Configure ADC discontinuous conversion mode for injected group
- * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
- * @retval None
- */
-#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
- ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
-
-/**
- * @brief Configure ADC discontinuous conversion mode for regular group
- * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
- * @retval None
- */
-#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
- ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
-
-/**
- * @brief Configure the number of discontinuous conversions for regular group.
- * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
- * @retval None
- */
-#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
- (((__NBR_DISCONTINUOUS_CONV__)-1UL) << ADC_CFGR_DISCNUM_Pos)
-
-/**
- * @brief Configure the ADC auto delay mode.
- * @param __AUTOWAIT__ Auto delay bit enable or disable.
- * @retval None
- */
-#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
-
-/**
- * @brief Configure ADC continuous conversion mode.
- * @param __CONTINUOUS_MODE__ Continuous mode.
- * @retval None
- */
-#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) \
- ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
-
-/**
- * @brief Configure the ADC DMA continuous request.
- * @param __DMACONTREQ_MODE__ DMA continuous request mode.
- * @retval None
- */
-#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) \
- ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Configure the ADC DMA continuous request for ADC multimode.
- * @param __DMACONTREQ_MODE__ DMA continuous request mode.
- * @retval None
- */
-#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) \
- ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @brief Shift the offset with respect to the selected ADC resolution.
- * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set
- * to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2
- * ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If
- * resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 -
- * resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
- * @param __HANDLE__ ADC handle
- * @param __OFFSET__ Value to be shifted
- * @retval None
- */
-#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
- ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * \
- 2UL))
-
-/**
- * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
- * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are
- * set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2
- * ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If
- * resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 -
- * resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
- * @param __HANDLE__ ADC handle
- * @param __THRESHOLD__ Value to be shifted
- * @retval None
- */
-#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
- ((__THRESHOLD__) \
- << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
-
-/**
- * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC
- * resolution.
- * @note Thresholds have to be left-aligned on bit 7.
- * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are
- * discarded). If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB
- * are discarded). If resolution 8 bits, no shift. If resolution 6 bits, shift
- * of 2 ranks on the left (the 2 LSB are set to 0).
- * @param __HANDLE__ ADC handle
- * @param __THRESHOLD__ Value to be shifted
- * @retval None
- */
-#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != \
- (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
- ? ((__THRESHOLD__) >> \
- ((4UL - \
- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & \
- 0x1FUL)) \
- : ((__THRESHOLD__) << 2UL))
-
-/**
- * @brief Clear Common Control Register.
- * @param __HANDLE__ ADC handle.
- * @retval None
- */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) \
- CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
- ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_VBATSEL | \
- ADC_CCR_VSENSESEL | ADC_CCR_VREFEN | ADC_CCR_MDMA | \
- ADC_CCR_DMACFG | ADC_CCR_DELAY | ADC_CCR_DUAL)
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-/**
- * @brief Set handle instance of the ADC slave associated to the ADC master.
- * @param __HANDLE_MASTER__ ADC master handle.
- * @param __HANDLE_SLAVE__ ADC slave handle.
- * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent
- * ADC, __HANDLE_SLAVE__ instance is set to NULL.
- * @retval None
- */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
- (((__HANDLE_MASTER__)->Instance == ADC1) \
- ? ((__HANDLE_SLAVE__)->Instance = ADC2) \
- : ((__HANDLE_MASTER__)->Instance == ADC3) \
- ? ((__HANDLE_SLAVE__)->Instance = ADC4) \
- : ((__HANDLE_SLAVE__)->Instance = NULL))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
- defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
-/**
- * @brief Set handle instance of the ADC slave associated to the ADC master.
- * @param __HANDLE_MASTER__ ADC master handle.
- * @param __HANDLE_SLAVE__ ADC slave handle.
- * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent
- * ADC, __HANDLE_SLAVE__ instance is set to NULL.
- * @retval None
- */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
- (((__HANDLE_MASTER__)->Instance == ADC1) \
- ? ((__HANDLE_SLAVE__)->Instance = ADC2) \
- : ((__HANDLE_SLAVE__)->Instance = NULL))
-#endif
-
-/**
- * @brief Verify the ADC instance connected to the temperature sensor.
- * @param __HANDLE__ ADC handle.
- * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
- */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
- ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
- defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
-#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
- (((__HANDLE__)->Instance) == ADC1)
-#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) \
- || defined(STM32G483xx) */
-
-/**
- * @brief Verify the ADC instance connected to the battery voltage VBAT.
- * @param __HANDLE__ ADC handle.
- * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
- */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
- ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
- defined(STM32G471xx)
-#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
- (((__HANDLE__)->Instance) != ADC2)
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
- (((__HANDLE__)->Instance) == ADC1)
-#endif
-
-/**
- * @brief Verify the ADC instance connected to the internal voltage reference
- * VREFINT.
- * @param __HANDLE__ ADC handle.
- * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
- */
-#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
-
-/**
- * @brief Verify the length of scheduled injected conversions group.
- * @param __LENGTH__ number of programmed conversions.
- * @retval SET (__LENGTH__ is within the maximum number of possible programmable
- * injected conversions) or RESET (__LENGTH__ is null or too large)
- */
-#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) \
- (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
-
-/**
- * @brief Calibration factor size verification (7 bits maximum).
- * @param __CALIBRATION_FACTOR__ Calibration factor value.
- * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET
- * (__CALIBRATION_FACTOR__ is too large)
- */
-#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) \
- ((__CALIBRATION_FACTOR__) <= (0x7FU))
-
-/**
- * @brief Verify the ADC channel setting.
- * @param __HANDLE__ ADC handle.
- * @param __CHANNEL__ programmed ADC channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_6) || ((__CHANNEL__) == ADC_CHANNEL_7) || \
- ((__CHANNEL__) == ADC_CHANNEL_8) || ((__CHANNEL__) == ADC_CHANNEL_9) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_14) || \
- ((__CHANNEL__) == ADC_CHANNEL_15)) || \
- ((((__HANDLE__)->Instance) == ADC1) && \
- (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
- ((((__HANDLE__)->Instance) == ADC3) && \
- (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
- ((((__HANDLE__)->Instance) == ADC4) && \
- (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
- ((((__HANDLE__)->Instance) == ADC5) && \
- (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \
- ((__CHANNEL__) == ADC_CHANNEL_13) || ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
-#elif defined(STM32G471xx)
-#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || ((__CHANNEL__) == ADC_CHANNEL_15)) || \
- ((((__HANDLE__)->Instance) == ADC1) && \
- (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
- ((((__HANDLE__)->Instance) == ADC3) && \
- (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || ((__CHANNEL__) == ADC_CHANNEL_15)) || \
- ((((__HANDLE__)->Instance) == ADC1) && \
- (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || ((__CHANNEL__) == ADC_CHANNEL_15)) || \
- ((((__HANDLE__)->Instance) == ADC1) && \
- (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
- ((((__HANDLE__)->Instance) == ADC3) && \
- (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
-#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) \
- || defined(STM32G483xx) */
-
-/**
- * @brief Verify the ADC channel setting in differential mode.
- * @param __HANDLE__ ADC handle.
- * @param __CHANNEL__ programmed ADC channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_14)) || \
- ((((__HANDLE__)->Instance) == ADC1) && \
- (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5))) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_13))) || \
- ((((__HANDLE__)->Instance) == ADC3) && \
- (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_15))) || \
- ((((__HANDLE__)->Instance) == ADC4) && \
- (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_15))) || \
- ((((__HANDLE__)->Instance) == ADC5) && \
- (((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_15))))
-#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || \
- (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_6) || ((__CHANNEL__) == ADC_CHANNEL_7) || \
- ((__CHANNEL__) == ADC_CHANNEL_8) || ((__CHANNEL__) == ADC_CHANNEL_9) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_14)) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_13))) || \
- ((((__HANDLE__)->Instance) == ADC3) && \
- ((__CHANNEL__) == ADC_CHANNEL_15))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
- ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_14)) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_13))))
-#endif
-
-/**
- * @brief Verify the ADC single-ended input or differential mode setting.
- * @param __SING_DIFF__ programmed channel setting.
- * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
- */
-#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) \
- (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
- ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED))
-
-/**
- * @brief Verify the ADC offset management setting.
- * @param __OFFSET_NUMBER__ ADC offset management.
- * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is
- * invalid)
- */
-#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) \
- (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
- ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
- ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
- ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
- ((__OFFSET_NUMBER__) == ADC_OFFSET_4))
-
-/**
- * @brief Verify the ADC offset sign setting.
- * @param __OFFSET_SIGN__ ADC offset sign.
- * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
- */
-#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) \
- (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
- ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE))
-
-/**
- * @brief Verify the ADC injected channel setting.
- * @param __CHANNEL__ programmed ADC injected channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC_INJECTED_RANK(__CHANNEL__) \
- (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
- ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
- ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
- ((__CHANNEL__) == ADC_INJECTED_RANK_4))
-
-/**
- * @brief Verify the ADC injected conversions external trigger.
- * @param __HANDLE__ ADC handle.
- * @param __INJTRIG__ programmed ADC injected conversions external trigger.
- * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
- */
-#if defined(STM32G474xx) || defined(STM32G484xx)
-#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
- ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
- ((__HANDLE__)->Instance == ADC5)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
- ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
-#elif defined(STM32G473xx) || defined(STM32G483xx)
-#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
- ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
- ((__HANDLE__)->Instance == ADC5)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
- ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
-#elif defined(STM32G471xx)
-#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
- ((((__HANDLE__)->Instance == ADC3)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
- ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
- ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
- ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
- (((__HANDLE__)->Instance == ADC3) && \
- (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
- ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
- ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
-#endif
-
-/**
- * @brief Verify the ADC edge trigger setting for injected group.
- * @param __EDGE__ programmed ADC edge trigger setting.
- * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
- */
-#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) \
- (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
- ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
- ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING))
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Verify the ADC multimode setting.
- * @param __MODE__ programmed ADC multimode setting.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_ADC_MULTIMODE(__MODE__) \
- (((__MODE__) == ADC_MODE_INDEPENDENT) || \
- ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_INTERL) || \
- ((__MODE__) == ADC_DUALMODE_ALTERTRIG))
-
-/**
- * @brief Verify the ADC multimode DMA access setting.
- * @param __MODE__ programmed ADC multimode DMA access setting.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) \
- (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
- ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
- ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS))
-
-/**
- * @brief Verify the ADC multimode delay setting.
- * @param __DELAY__ programmed ADC multimode delay setting.
- * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
- */
-#define IS_ADC_SAMPLING_DELAY(__DELAY__) \
- (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
- ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES))
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @brief Verify the ADC analog watchdog setting.
- * @param __WATCHDOG__ programmed ADC analog watchdog setting.
- * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
- */
-#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) \
- (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
- ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
- ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3))
-
-/**
- * @brief Verify the ADC analog watchdog mode setting.
- * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
- * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is
- * invalid)
- */
-#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) \
- (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
- ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
-
-/**
- * @brief Verify the ADC analog watchdog filtering setting.
- * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
- * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is
- * invalid)
- */
-#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
- (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \
- ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES))
-
-/**
- * @brief Verify the ADC conversion (regular or injected or both).
- * @param __CONVERSION__ ADC conversion group.
- * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
- */
-#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) \
- (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
- ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
- ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP))
-
-/**
- * @brief Verify the ADC event type.
- * @param __EVENT__ ADC event.
- * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
- */
-#define IS_ADC_EVENT_TYPE(__EVENT__) \
- (((__EVENT__) == ADC_EOSMP_EVENT) || ((__EVENT__) == ADC_AWD_EVENT) || \
- ((__EVENT__) == ADC_AWD2_EVENT) || ((__EVENT__) == ADC_AWD3_EVENT) || \
- ((__EVENT__) == ADC_OVR_EVENT) || ((__EVENT__) == ADC_JQOVF_EVENT))
-
-/**
- * @brief Verify the ADC oversampling ratio.
- * @param __RATIO__ programmed ADC oversampling ratio.
- * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
- */
-#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) \
- (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128) || \
- ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256))
-
-/**
- * @brief Verify the ADC oversampling shift.
- * @param __SHIFT__ programmed ADC oversampling shift.
- * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
- */
-#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) \
- (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_1) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_2) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_3) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_4) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_5) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_6) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_7) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_8))
-
-/**
- * @brief Verify the ADC oversampling triggered mode.
- * @param __MODE__ programmed ADC oversampling triggered mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) \
- (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
- ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER))
-
-/**
- * @brief Verify the ADC oversampling regular conversion resumed or continued
- * mode.
- * @param __MODE__ programmed ADC oversampling regular conversion resumed or
- * continued mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) \
- (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
- ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE))
-
-/**
- * @brief Verify the DFSDM mode configuration.
- * @param __HANDLE__ ADC handle.
- * @note When DMSDFM configuration is not supported, the macro systematically
- * reports SET. For this reason, the input parameter is the ADC handle and not
- * the configuration parameter directly.
- * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode
- * configuration is invalid)
- */
-#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
-
-/**
- * @brief Return the DFSDM configuration mode.
- * @param __HANDLE__ ADC handle.
- * @note When DMSDFM configuration is not supported, the macro systematically
- * reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC
- * handle and not the configuration parameter directly.
- * @retval DFSDM configuration mode
- */
-#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADCEx_Exported_Functions_Group1
- * @{
- */
-/* IO operation functions *****************************************************/
-
-/* ADC calibration */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc,
- uint32_t SingleDiff);
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc,
- uint32_t SingleDiff);
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc,
- uint32_t SingleDiff,
- uint32_t CalibrationFactor);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc,
- uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/* ADC multimode */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc,
- uint32_t *pData,
- uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/* ADC retrieve conversion value intended to be used with polling or
- * interruption */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc,
- uint32_t InjectedRank);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
-void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
-void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
-void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
-void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
-
-/* ADC group regular conversions stop */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
-#if defined(ADC_MULTIMODE_SUPPORT)
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @addtogroup ADCEx_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(
- ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
-#if defined(ADC_MULTIMODE_SUPPORT)
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(
- ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-#endif /* ADC_MULTIMODE_SUPPORT */
-HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_ADC_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_ADC_EX_H
+#define STM32G4xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC Injected Conversion Oversampling structure definition
+ */
+typedef struct {
+ uint32_t
+ Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the
+ Oversampler. This parameter can be a value of @ref
+ ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC group injected and ADC channel affected
+ * to ADC group injected
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime
+ * , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset,
+ * InjectedOffsetSign, InjectedOffsetSaturation
+ * - Scope ADC group injected (affects all channels of injected group):
+ * InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv,
+ * QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
+ * InjecOversamplingMode, InjecOversampling.
+ * @note The setting of these parameters by function
+ * HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can
+ * be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC
+ * state to modify parameter 'InjectedSingleDiff')
+ * - For parameters 'InjectedDiscontinuousConvMode',
+ * 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion
+ * on going on injected group.
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset',
+ * 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation',
+ * 'AutoInjectedConv': ADC enabled without conversion on going on regular and
+ * injected groups.
+ * - For parameters 'InjectedChannel', 'InjectedRank',
+ * 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
+ * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on
+ * going on ADC groups regular and injected. If ADC is not in the appropriate
+ * state to modify some parameters, these parameters setting is bypassed without
+ * error reporting (as it can be the expected behavior in case of intended
+ * action to update another parameter (which fulfills the ADC state condition)
+ * on the fly).
+ */
+typedef struct {
+ uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC
+ group injected. This parameter can be a value of
+ @ref ADC_HAL_EC_CHANNEL Note: Depending on
+ devices and ADC instances, some channels may not
+ be available on device package pins. Refer to
+ device datasheet for channels availability. */
+
+ uint32_t
+ InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
+ This parameter must be a value of @ref
+ ADC_INJ_SEQ_RANKS. Note: to disable a channel or change
+ order of conversion sequencer, rank containing a previous
+ channel setting can be overwritten by the new channel
+ setting (or parameter number of conversions adjusted) */
+
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the
+ selected channel. Unit: ADC clock cycles.
+ Conversion time is the addition of
+ sampling time and processing time (12.5 ADC
+ clock cycles at ADC resolution 12 bits, 10.5
+ cycles at 10 bits, 8.5 cycles at 8 bits, 6.5
+ cycles at 6 bits). This parameter can be a
+ value of @ref
+ ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution:
+ This parameter applies to a channel that can
+ be used in a regular and/or injected group.
+ It overwrites the last setting. Note: In
+ case of usage of internal measurement
+ channels (VrefInt, ...), sampling time
+ constraints must be respected (sampling time
+ can be adjusted in function of ADC clock
+ frequency and sampling time setting). Refer
+ to device datasheet for timings values. */
+
+ uint32_t
+ InjectedSingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is
+ between the selected channel 'i' (positive input)
+ and channel 'i+1' (negative input). Only channel
+ 'i' has to be configured, channel 'i+1' is
+ configured automatically. This parameter must be a
+ value of
+ @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+ Caution: This parameter applies to a channel that
+ can be used in a regular and/or injected group. It
+ overwrites the last setting. Note: Refer to
+ Reference Manual to ensure the selected channel is
+ available in differential mode.
+ Note: When configuring a channel 'i' in
+ differential mode, the channel 'i+1' is not usable
+ separately. Note: This parameter must be modified
+ when ADC is disabled (before ADC start conversion
+ or after ADC stop conversion). If ADC is enabled,
+ this parameter setting is bypassed without error
+ reporting (as it can be the expected behavior in
+ case of another parameter update on the fly) */
+
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
+ This parameter can be a value of @ref
+ ADC_HAL_EC_OFFSET_NB. Caution: Only one
+ offset is allowed per channel. This
+ parameter overwrites the last setting. */
+
+ uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw
+ converted data. Offset value must be a positive
+ number. Depending of ADC resolution selected (12,
+ 10, 8 or 6 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFF,
+ 0x3FF, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no
+ conversion is on going on both regular and
+ injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external
+ trigger that could launch a conversion). */
+
+ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted
+ (negative sign) or added (positive sign) from
+ or to the raw converted data. This parameter
+ can be a value of @ref ADCEx_OffsetSign. Note:
+ This parameter must be modified when no
+ conversion is on going on both regular and
+ injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger
+ that could launch a conversion). */
+ FunctionalState
+ InjectedOffsetSaturation; /*!< Define if the offset should be saturated
+ upon under or over flow. This parameter value
+ can be ENABLE or DISABLE. Note: This parameter
+ must be modified when no conversion is on going
+ on both regular and injected groups (ADC
+ disabled, or ADC enabled without continuous
+ mode or external trigger that could launch a
+ conversion). */
+
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will
+ be converted within the ADC group
+ injected sequencer. To use the injected
+ group sequencer and convert several
+ ranks, parameter 'ScanConvMode' must be
+ enabled. This parameter must be a number
+ between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire
+ injected group. Therefore, call of
+ HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can
+ impact the configuration of other
+ channels previously set. */
+
+ FunctionalState
+ InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions
+ sequence of ADC group injected is performed
+ in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive
+ parts). Discontinuous mode is used only if
+ sequencer is enabled (parameter
+ 'ScanConvMode'). If sequencer is disabled,
+ this parameter is discarded. Discontinuous
+ mode can be enabled only if continuous mode
+ is disabled. This parameter can be set to
+ ENABLE or DISABLE. Note: This parameter must
+ be modified when ADC is disabled (before ADC
+ start conversion or after ADC stop
+ conversion). Note: For injected group,
+ discontinuous mode converts the sequence
+ channel by channel (discontinuous length
+ fixed to 1 rank). Caution: this setting
+ impacts the entire injected group. Therefore,
+ call of
+ HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected
+ group can impact the configuration of other
+ channels previously set. */
+
+ FunctionalState
+ AutoInjectedConv; /*!< Enables or disables the selected ADC group injected
+ automatic conversion after regular one This parameter
+ can be set to ENABLE or DISABLE. Note: To use
+ Automatic injected conversion, discontinuous mode
+ must be disabled ('DiscontinuousConvMode' and
+ 'InjectedDiscontinuousConvMode' set to
+ DISABLE) Note: To use Automatic injected conversion,
+ injected group external triggers must be disabled
+ ('ExternalTrigInjecConv' set to
+ ADC_INJECTED_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if
+ DMA configured in normal mode (single shot) JAUTO
+ will be stopped upon DMA transfer complete. To
+ maintain JAUTO always enabled, DMA must be configured
+ in circular mode. Caution: this setting impacts the
+ entire injected group. Therefore, call of
+ HAL_ADCEx_InjectedConfigChannel() to configure a
+ channel on injected group can impact the
+ configuration of other channels previously set. */
+
+ FunctionalState
+ QueueInjectedContext; /*!< Specifies whether the context queue feature is
+ enabled. This parameter can be set to ENABLE or
+ DISABLE. If context queue is enabled, injected
+ sequencer&channels configurations are queued on
+ up to 2 contexts. If a new injected context is
+ set when queue is full, error is triggered by
+ interruption and through function
+ 'HAL_ADCEx_InjectedQueueOverflowCallback'.
+ Caution: This feature request that the sequence
+ is fully configured before injected conversion
+ start. Therefore, configure channels with as many
+ calls to HAL_ADCEx_InjectedConfigChannel() as the
+ 'InjectedNbrOfConversion' parameter.
+ Caution: this setting impacts the entire
+ injected group. Therefore, call of
+ HAL_ADCEx_InjectedConfigChannel() to configure a
+ channel on injected group can impact the
+ configuration of other channels
+ previously set. Note: This parameter must be
+ modified when ADC is disabled (before ADC start
+ conversion or after ADC stop conversion). */
+
+ uint32_t
+ ExternalTrigInjecConv; /*!< Selects the external event used to trigger the
+ conversion start of injected group. If set to
+ ADC_INJECTED_SOFTWARE_START, external triggers
+ are disabled and software trigger is used
+ instead. This parameter can be a value of
+ @ref ADC_injected_external_trigger_source.
+ Caution: this setting impacts the entire
+ injected group. Therefore, call of
+ HAL_ADCEx_InjectedConfigChannel() to configure a
+ channel on injected group can impact the
+ configuration of other channels previously set.
+ */
+
+ uint32_t
+ ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of
+ injected group. This parameter can be a
+ value of @ref
+ ADC_injected_external_trigger_edge. If
+ trigger source is set to
+ ADC_INJECTED_SOFTWARE_START, this parameter
+ is discarded.
+ Caution: this setting impacts the entire
+ injected group. Therefore, call of
+ HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected
+ group can impact the configuration of other
+ channels previously set. */
+
+ FunctionalState
+ InjecOversamplingMode; /*!< Specifies whether the oversampling feature is
+ enabled or disabled. This parameter can be set
+ to ENABLE or DISABLE. Note: This parameter can
+ be modified only if there is no conversion is
+ ongoing (both ADSTART and JADSTART cleared). */
+
+ ADC_InjOversamplingTypeDef
+ InjecOversampling; /*!< Specifies the Oversampling parameters.
+ Caution: this setting overwrites the previous
+ oversampling configuration if oversampling already
+ enabled. Note: This parameter can be modified only
+ if there is no conversion is ongoing (both ADSTART
+ and JADSTART cleared).*/
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters by function
+ * HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master
+ * and Slave ADCs). Both Master and Slave ADCs must be disabled.
+ */
+typedef struct {
+ uint32_t
+ Mode; /*!< Configures the ADC to operate in independent or multimode.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
+ selection whether 2 DMA channels (each ADC uses
+ its own DMA channel) or 1 DMA channel (one DMA
+ channel for both ADC, DMA of ADC master). This
+ parameter can be a value of @ref
+ ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
+
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling
+ phases. This parameter can be a value of @ref
+ ADC_HAL_EC_MULTI_TWOSMP_DELAY. Delay range
+ depends on selected resolution: from 1 to 12
+ clock cycles for 12 bits, from 1 to 10 clock
+ cycles for 10 bits, from 1 to 8 clock cycles for
+ 8 bits, from 1 to 6 clock cycles for 6 bits. */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger
+ * source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START \
+ (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion \
+trigger software start */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM1 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 \
+ (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM1 TRGO2. */
+#define ADC_EXTERNALTRIGINJEC_T1_CC3 \
+ (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM1 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4 \
+ (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM1 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM2 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 \
+ (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM2 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM3 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1 \
+ (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM3 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3 \
+ (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM3 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 \
+ (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM4 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T4_CC3 \
+ (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM4 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T4_CC4 \
+ (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM4 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM6 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T7_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM7 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM8 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 \
+ (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM8 TRGO2. */
+#define ADC_EXTERNALTRIGINJEC_T8_CC2 \
+ (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM8 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T8_CC4 \
+ (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM8 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM15 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T16_CC1 \
+ (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM8 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T20_TRGO \
+ (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM20 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 \
+ (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM20 TRGO2. */
+#define ADC_EXTERNALTRIGINJEC_T20_CC2 \
+ (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM20 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T20_CC4 \
+ (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion \
+trigger from external peripheral: TIM20 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 1 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 2 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 3 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 4 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 5 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 6 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 7 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 8 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 9 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 \
+ (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion \
+trigger from external peripheral: HRTIMER ADC trigger 10 event. */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT3 \
+ (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion \
+trigger from external peripheral: external interrupt line 3. */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 \
+ (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion \
+trigger from external peripheral: external interrupt line 15. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT \
+ (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion \
+trigger from external peripheral: LPTIMER OUT event. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge
+ * (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE \
+ (0x00000000UL) /*!< Injected conversions trigger \
+disabled (SW start)*/
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING \
+ (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger \
+polarity set to rising edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING \
+ (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger \
+polarity set to falling edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING \
+ (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger \
+polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or
+ * differential ending
+ * @{
+ */
+#define ADC_SINGLE_ENDED \
+ (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */
+#define ADC_DIFFERENTIAL_ENDED \
+ (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define ADC_OFFSET_NONE \
+ (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the \
+ selected ADC channel */
+#define ADC_OFFSET_1 \
+ (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to \
+ which the offset programmed will be applied (independently of channel mapped \
+ on ADC group regular or group injected) */
+#define ADC_OFFSET_2 \
+ (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to \
+ which the offset programmed will be applied (independently of channel mapped \
+ on ADC group regular or group injected) */
+#define ADC_OFFSET_3 \
+ (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to \
+ which the offset programmed will be applied (independently of channel mapped \
+ on ADC group regular or group injected) */
+#define ADC_OFFSET_4 \
+ (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to \
+ which the offset programmed will be applied (independently of channel mapped \
+ on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+ * @{
+ */
+#define ADC_OFFSET_SIGN_NEGATIVE \
+ (0x00000000UL) /*!< Offset sign negative, offset is subtracted */
+#define ADC_OFFSET_SIGN_POSITIVE \
+ (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 \
+ (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2 \
+ (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3 \
+ (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4 \
+ (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT \
+ (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled \
+(ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT \
+ (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular \
+simultaneous */
+#define ADC_DUALMODE_INTERL \
+ (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined \
+group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT \
+ (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group \
+injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG \
+ (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group \
+injected alternate trigger. Works only with external triggers (not internal \
+SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT \
+ (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined \
+ group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG \
+ (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined \
+ group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT \
+ (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined \
+ group regular interleaved + group injected simultaneous */
+
+/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer
+ * mode depending on ADC resolution
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED \
+ (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own \
+DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS \
+ (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, \
+DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS \
+ (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, \
+DMA of ADC master) for 8 and 6 bits resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two
+ * sampling phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE \
+ (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two \
+sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 8 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_9CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two \
+sampling phases: 9 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_10CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two \
+ sampling phases: 10 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_11CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two \
+ sampling phases: 11 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_12CYCLES \
+ (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two \
+ sampling phases: 12 ADC clock cycles */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define ADC_REGULAR_GROUP \
+ (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on \
+ all STM32 devices) */
+#define ADC_INJECTED_GROUP \
+ (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on \
+ all STM32 devices) */
+#define ADC_REGULAR_INJECTED_GROUP \
+ (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields
+ * @{
+ */
+#define ADC_CFGR_FIELDS \
+ (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | \
+ ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | \
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES | \
+ ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+ * @{
+ */
+#if defined(ADC_SMPR1_SMPPLUS)
+#define ADC_SMPR1_FIELDS \
+ (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | \
+ ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | \
+ ADC_SMPR1_SMP1 | ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
+#else
+#define ADC_SMPR1_FIELDS \
+ (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | \
+ ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | \
+ ADC_SMPR1_SMP1 | ADC_SMPR1_SMP0)
+#endif /* ADC_SMPR1_SMPPLUS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
+ * @{
+ */
+/* ADC_CFGR fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+ * @{
+ */
+
+/** @brief Force ADC instance in multimode mode independent (multimode
+ * disable).
+ * @note This macro must be used only in case of transition from multimode
+ * to mode independent and in case of unknown previous state,
+ * to ensure ADC configuration is in mode independent.
+ * @note Standard way of multimode configuration change is done from
+ * HAL ADC handle of ADC master using function
+ * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+ * Usage of this macro is not the Standard way of multimode
+ * configuration and can lead to have HAL ADC handles status
+ * misaligned. Usage of this macro must be limited to cases
+ * mentioned above.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
+ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), \
+ LL_ADC_MULTI_INDEPENDENT)
+
+/**
+ * @}
+ */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private
+ * Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (software start) or RESET (external trigger).
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+ * @brief Check whether or not ADC is independent.
+ * @param __HANDLE__ ADC handle.
+ * @note When multimode feature is not available, the macro always returns SET.
+ * @retval SET (ADC is independent) or RESET (ADC is not).
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__) \
+ (((((__HANDLE__)->Instance) == ADC5)) ? SET : RESET)
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define ADC_IS_INDEPENDENT(__HANDLE__) \
+ (((((__HANDLE__)->Instance) == ADC3)) ? SET : RESET)
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || \
+ defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) \
+ || defined(STM32G483xx) */
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param __CHANNELNB__ Channel number.
+ * @param __RANKNB__ Rank number.
+ * @retval None
+ */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
+ ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> \
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+
+/**
+ * @brief Configure ADC injected context queue
+ * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
+ ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for injected group
+ * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
+ ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for regular group
+ * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
+ ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
+
+/**
+ * @brief Configure the number of discontinuous conversions for regular group.
+ * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
+ (((__NBR_DISCONTINUOUS_CONV__)-1UL) << ADC_CFGR_DISCNUM_Pos)
+
+/**
+ * @brief Configure the ADC auto delay mode.
+ * @param __AUTOWAIT__ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
+
+/**
+ * @brief Configure ADC continuous conversion mode.
+ * @param __CONTINUOUS_MODE__ Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) \
+ ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
+
+/**
+ * @brief Configure the ADC DMA continuous request.
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) \
+ ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Configure the ADC DMA continuous request for ADC multimode.
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) \
+ ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Shift the offset with respect to the selected ADC resolution.
+ * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set
+ * to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2
+ * ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If
+ * resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 -
+ * resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+ * @param __HANDLE__ ADC handle
+ * @param __OFFSET__ Value to be shifted
+ * @retval None
+ */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+ ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * \
+ 2UL))
+
+/**
+ * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
+ * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are
+ * set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2
+ * ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If
+ * resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 -
+ * resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+ * @param __HANDLE__ ADC handle
+ * @param __THRESHOLD__ Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ((__THRESHOLD__) \
+ << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
+
+/**
+ * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC
+ * resolution.
+ * @note Thresholds have to be left-aligned on bit 7.
+ * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are
+ * discarded). If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB
+ * are discarded). If resolution 8 bits, no shift. If resolution 6 bits, shift
+ * of 2 ranks on the left (the 2 LSB are set to 0).
+ * @param __HANDLE__ ADC handle
+ * @param __THRESHOLD__ Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != \
+ (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
+ ? ((__THRESHOLD__) >> \
+ ((4UL - \
+ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & \
+ 0x1FUL)) \
+ : ((__THRESHOLD__) << 2UL))
+
+/**
+ * @brief Clear Common Control Register.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) \
+ CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
+ ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_VBATSEL | \
+ ADC_CCR_VSENSESEL | ADC_CCR_VREFEN | ADC_CCR_MDMA | \
+ ADC_CCR_DMACFG | ADC_CCR_DELAY | ADC_CCR_DUAL)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+/**
+ * @brief Set handle instance of the ADC slave associated to the ADC master.
+ * @param __HANDLE_MASTER__ ADC master handle.
+ * @param __HANDLE_SLAVE__ ADC slave handle.
+ * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent
+ * ADC, __HANDLE_SLAVE__ instance is set to NULL.
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ (((__HANDLE_MASTER__)->Instance == ADC1) \
+ ? ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : ((__HANDLE_MASTER__)->Instance == ADC3) \
+ ? ((__HANDLE_SLAVE__)->Instance = ADC4) \
+ : ((__HANDLE_SLAVE__)->Instance = NULL))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || \
+ defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
+ defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+/**
+ * @brief Set handle instance of the ADC slave associated to the ADC master.
+ * @param __HANDLE_MASTER__ ADC master handle.
+ * @param __HANDLE_SLAVE__ ADC slave handle.
+ * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent
+ * ADC, __HANDLE_SLAVE__ instance is set to NULL.
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ (((__HANDLE_MASTER__)->Instance == ADC1) \
+ ? ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : ((__HANDLE_SLAVE__)->Instance = NULL))
+#endif /* STM32G4xx */
+
+/**
+ * @brief Verify the ADC instance connected to the temperature sensor.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
+ ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || \
+ defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
+ defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
+ (((__HANDLE__)->Instance) == ADC1)
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) \
+ || defined(STM32G483xx) */
+
+/**
+ * @brief Verify the ADC instance connected to the battery voltage VBAT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
+ ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || \
+ defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || \
+ defined(STM32G471xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
+ (((__HANDLE__)->Instance) != ADC2)
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
+ (((__HANDLE__)->Instance) == ADC1)
+#endif /* STM32G4xx */
+
+/**
+ * @brief Verify the ADC instance connected to the internal voltage reference
+ * VREFINT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
+
+/**
+ * @brief Verify the length of scheduled injected conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable
+ * injected conversions) or RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) \
+ (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+ * @brief Calibration factor size verification (7 bits maximum).
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET
+ * (__CALIBRATION_FACTOR__ is too large)
+ */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) \
+ ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+/**
+ * @brief Verify the ADC channel setting.
+ * @param __HANDLE__ ADC handle.
+ * @param __CHANNEL__ programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_0) || ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || ((__CHANNEL__) == ADC_CHANNEL_15)) || \
+ ((((__HANDLE__)->Instance) == ADC1) && \
+ (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC4) && \
+ (((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC5) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13) || ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G471xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_0) || ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15)) || \
+ ((((__HANDLE__)->Instance) == ADC1) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || \
+ defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_0) || ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15)) || \
+ ((((__HANDLE__)->Instance) == ADC1) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_0) || ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15)) || \
+ ((((__HANDLE__)->Instance) == ADC1) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) \
+ || defined(STM32G483xx) */
+
+/**
+ * @brief Verify the ADC channel setting in differential mode.
+ * @param __HANDLE__ ADC handle.
+ * @param __CHANNEL__ programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_14)) || \
+ ((((__HANDLE__)->Instance) == ADC1) && \
+ (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15))) || \
+ ((((__HANDLE__)->Instance) == ADC4) && \
+ (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15))) || \
+ ((((__HANDLE__)->Instance) == ADC5) && \
+ (((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15))))
+#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) || \
+ defined(STM32G411xC)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_1) || \
+ (((__CHANNEL__) == ADC_CHANNEL_2) || ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14)) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ ((__CHANNEL__) == ADC_CHANNEL_15))))
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || \
+ defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
+ ((((__CHANNEL__) == ADC_CHANNEL_1) || ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || ((__CHANNEL__) == ADC_CHANNEL_14)) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_12) || ((__CHANNEL__) == ADC_CHANNEL_13))))
+#endif /* STM32G4xx */
+
+/**
+ * @brief Verify the ADC single-ended input or differential mode setting.
+ * @param __SING_DIFF__ programmed channel setting.
+ * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+ */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) \
+ (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
+ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED))
+
+/**
+ * @brief Verify the ADC offset management setting.
+ * @param __OFFSET_NUMBER__ ADC offset management.
+ * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is
+ * invalid)
+ */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) \
+ (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_4))
+
+/**
+ * @brief Verify the ADC offset sign setting.
+ * @param __OFFSET_SIGN__ ADC offset sign.
+ * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+ */
+#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) \
+ (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
+ ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE))
+
+/**
+ * @brief Verify the ADC injected channel setting.
+ * @param __CHANNEL__ programmed ADC injected channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) \
+ (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_4))
+
+/**
+ * @brief Verify the ADC injected conversions external trigger.
+ * @param __HANDLE__ ADC handle.
+ * @param __INJTRIG__ programmed ADC injected conversions external trigger.
+ * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
+ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
+ ((__HANDLE__)->Instance == ADC5)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
+ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
+ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || \
+ ((__HANDLE__)->Instance == ADC5)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
+ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
+ ((((__HANDLE__)->Instance == ADC3)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
+ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || \
+ defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
+ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
+ (((__HANDLE__)->Instance == ADC3) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
+ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#endif /* STM32G4xx */
+
+/**
+ * @brief Verify the ADC edge trigger setting for injected group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) \
+ (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Verify the ADC multimode setting.
+ * @param __MODE__ programmed ADC multimode setting.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_MULTIMODE(__MODE__) \
+ (((__MODE__) == ADC_MODE_INDEPENDENT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG))
+
+/**
+ * @brief Verify the ADC multimode DMA access setting.
+ * @param __MODE__ programmed ADC multimode DMA access setting.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) \
+ (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
+ ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS))
+
+/**
+ * @brief Verify the ADC multimode delay setting.
+ * @param __DELAY__ programmed ADC multimode delay setting.
+ * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+ */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) \
+ (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Verify the ADC analog watchdog setting.
+ * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+ * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) \
+ (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3))
+
+/**
+ * @brief Verify the ADC analog watchdog mode setting.
+ * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is
+ * invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) \
+ (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
+
+/**
+ * @brief Verify the ADC analog watchdog filtering setting.
+ * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is
+ * invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
+ (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES))
+
+/**
+ * @brief Verify the ADC conversion (regular or injected or both).
+ * @param __CONVERSION__ ADC conversion group.
+ * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+ */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) \
+ (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
+ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
+ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP))
+
+/**
+ * @brief Verify the ADC event type.
+ * @param __EVENT__ ADC event.
+ * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+ */
+#define IS_ADC_EVENT_TYPE(__EVENT__) \
+ (((__EVENT__) == ADC_EOSMP_EVENT) || ((__EVENT__) == ADC_AWD_EVENT) || \
+ ((__EVENT__) == ADC_AWD2_EVENT) || ((__EVENT__) == ADC_AWD3_EVENT) || \
+ ((__EVENT__) == ADC_OVR_EVENT) || ((__EVENT__) == ADC_JQOVF_EVENT))
+
+/**
+ * @brief Verify the ADC oversampling ratio.
+ * @param __RATIO__ programmed ADC oversampling ratio.
+ * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+ */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) \
+ (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256))
+
+/**
+ * @brief Verify the ADC oversampling shift.
+ * @param __SHIFT__ programmed ADC oversampling shift.
+ * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+ */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) \
+ (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8))
+
+/**
+ * @brief Verify the ADC oversampling triggered mode.
+ * @param __MODE__ programmed ADC oversampling triggered mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) \
+ (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER))
+
+/**
+ * @brief Verify the ADC oversampling regular conversion resumed or continued
+ * mode.
+ * @param __MODE__ programmed ADC oversampling regular conversion resumed or
+ * continued mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) \
+ (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE))
+
+/**
+ * @brief Verify the DFSDM mode configuration.
+ * @param __HANDLE__ ADC handle.
+ * @note When DMSDFM configuration is not supported, the macro systematically
+ * reports SET. For this reason, the input parameter is the ADC handle and not
+ * the configuration parameter directly.
+ * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode
+ * configuration is invalid)
+ */
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
+
+/**
+ * @brief Return the DFSDM configuration mode.
+ * @param __HANDLE__ ADC handle.
+ * @note When DMSDFM configuration is not supported, the macro systematically
+ * reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC
+ * handle and not the configuration parameter directly.
+ * @retval DFSDM configuration mode
+ */
+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc,
+ uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc,
+ uint32_t SingleDiff);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc,
+ uint32_t SingleDiff,
+ uint32_t CalibrationFactor);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc,
+ uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc,
+ uint32_t *pData,
+ uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC retrieve conversion value intended to be used with polling or
+ * interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc,
+ uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(
+ ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(
+ ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_ADC_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
index d2af42a..8199a66 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
@@ -1,424 +1,426 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_HAL_CORTEX_H
-#define __STM32G4xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CORTEX CORTEX
- * @brief CORTEX HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region
- * Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct {
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref
- CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref
- CORTEX_MPU_Region_Number */
- uint32_t
- BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t
- Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t
- SubRegionDisable; /*!< Specifies the number of the subregion protection to
- disable. This parameter must be a number between
- Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref
- CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref
- CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref
- CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected
- region. This parameter can be a value of @ref
- CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region
- protected. This parameter can be a value of @ref
- CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected
- region. This parameter can be a value of @ref
- CORTEX_MPU_Access_Bufferable */
-} MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 \
- 0x00000007U /*!< 0 bit for pre-emption priority, \
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 \
- 0x00000006U /*!< 1 bit for pre-emption priority, \
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 \
- 0x00000005U /*!< 2 bits for pre-emption priority, \
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 \
- 0x00000004U /*!< 3 bits for pre-emption priority, \
- 1 bit for subpriority */
-#define NVIC_PRIORITYGROUP_4 \
- 0x00000003U /*!< 4 bits for pre-emption priority, \
- 0 bit for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
-
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED
- * Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
-#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
-#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
-#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access
- * Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access
- * Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access
- * Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region
- * Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration
- * functions
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and Configuration functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority,
- uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup,
- uint32_t *pPreemptPriority, uint32_t *pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) \
- (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
- (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) \
- (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) \
- (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) \
- (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) \
- (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) \
- (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) \
- (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2) || ((TYPE) == MPU_TEX_LEVEL4))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \
- (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) \
- (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE) \
- (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_HAL_CORTEX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_CORTEX_H
+#define __STM32G4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region
+ * Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct {
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref
+ CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref
+ CORTEX_MPU_Region_Number */
+ uint32_t
+ BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t
+ Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t
+ SubRegionDisable; /*!< Specifies the number of the subregion protection to
+ disable. This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref
+ CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref
+ CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref
+ CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected
+ region. This parameter can be a value of @ref
+ CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region
+ protected. This parameter can be a value of @ref
+ CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected
+ region. This parameter can be a value of @ref
+ CORTEX_MPU_Access_Bufferable */
+} MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 \
+ 0x00000007U /*!< 0 bit for pre-emption priority, \
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 \
+ 0x00000006U /*!< 1 bit for pre-emption priority, \
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 \
+ 0x00000005U /*!< 2 bits for pre-emption priority, \
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 \
+ 0x00000004U /*!< 3 bits for pre-emption priority, \
+ 1 bit for subpriority */
+#define NVIC_PRIORITYGROUP_4 \
+ 0x00000003U /*!< 4 bits for pre-emption priority, \
+ 0 bit for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
+
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED
+ * Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
+#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
+#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access
+ * Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access
+ * Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access
+ * Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region
+ * Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration
+ * functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority,
+ uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup,
+ uint32_t *pPreemptPriority, uint32_t *pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+ (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
+ (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) \
+ (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) \
+ (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) \
+ (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) \
+ (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) \
+ (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) \
+ (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2) || ((TYPE) == MPU_TEX_LEVEL4))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \
+ (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) \
+ (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) \
+ (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_HAL_CORTEX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
index df7122a..78df670 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
@@ -1,206 +1,208 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_HAL_DEF
-#define __STM32G4xx_HAL_DEF
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include <stddef.h>
-
-#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
-#include "stm32g4xx.h"
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL Status structures definition
- */
-typedef enum {
- HAL_OK = 0x00U,
- HAL_ERROR = 0x01U,
- HAL_BUSY = 0x02U,
- HAL_TIMEOUT = 0x03U
-} HAL_StatusTypeDef;
-
-/**
- * @brief HAL Lock structures definition
- */
-typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-
-#define HAL_MAX_DELAY 0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do { \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while (0)
-
-#define UNUSED(X) (void)X
-
-/** @brief Reset the Handle's State field.
- * @param __HANDLE__: specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
- * - When the Handle is declared as local variable; before passing it
- * as parameter to HAL_PPP_Init() for the first time, it is mandatory to use
- * this macro to set to 0 the Handle's "State" field. Otherwise, "State" field
- * may have any random value and the first time the function HAL_PPP_Init() is
- * called, the low level hardware initialization will be missed (i.e.
- * HAL_PPP_MspInit() will not be executed).
- * - When there is a need to reconfigure the low level hardware:
- * instead of calling HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call
- * to this macro then HAL_PPP_Init(). In this later function, when the Handle's
- * "State" field is set to 0, it will execute the function HAL_PPP_MspInit()
- * which will reconfigure the low level hardware.
- * @retval None
- */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1U)
-/* Reserved for future use */
-#error " USE_RTOS should be 0 in the current HAL release "
-#else
-#define __HAL_LOCK(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Lock == HAL_LOCKED) { \
- return HAL_BUSY; \
- } else { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- } while (0U)
-
-#define __HAL_UNLOCK(__HANDLE__) \
- do { \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- } while (0U)
-#endif /* USE_RTOS */
-
-#if defined(__ARMCC_VERSION) && \
- (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-#ifndef __weak
-#define __weak __attribute__((weak))
-#endif
-#ifndef __packed
-#define __packed __attribute__((packed))
-#endif
-#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
-#ifndef __weak
-#define __weak __attribute__((weak))
-#endif /* __weak */
-#ifndef __packed
-#define __packed __attribute__((__packed__))
-#endif /* __packed */
-#endif /* __GNUC__ */
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
- * "#pragma data_alignment=4" must be used instead */
-#if defined(__ARMCC_VERSION) && \
- (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-#ifndef __ALIGN_BEGIN
-#define __ALIGN_BEGIN
-#endif
-#ifndef __ALIGN_END
-#define __ALIGN_END __attribute__((aligned(4)))
-#endif
-#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
-#ifndef __ALIGN_END
-#define __ALIGN_END __attribute__((aligned(4U)))
-#endif /* __ALIGN_END */
-#ifndef __ALIGN_BEGIN
-#define __ALIGN_BEGIN
-#endif /* __ALIGN_BEGIN */
-#else
-#ifndef __ALIGN_END
-#define __ALIGN_END
-#endif /* __ALIGN_END */
-#ifndef __ALIGN_BEGIN
-#if defined(__CC_ARM) /* ARM Compiler V5*/
-#define __ALIGN_BEGIN __align(4U)
-#elif defined(__ICCARM__) /* IAR Compiler */
-#define __ALIGN_BEGIN
-#endif /* __CC_ARM */
-#endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/**
- * @brief __RAM_FUNC definition
- */
-#if defined(__CC_ARM) || \
- (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-/* ARM Compiler V4/V5 and V6
- --------------------------
- RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
- area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the 'Options for
- Target' dialog.
-*/
-#define __RAM_FUNC
-
-#elif defined(__ICCARM__)
-/* ICCARM Compiler
- ---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined(__GNUC__)
-/* GNU Compiler
- ------------
- RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC __attribute__((section(".RamFunc")))
-
-#endif /* __CC_ARM */
-
-/**
- * @brief __NOINLINE definition
- */
-#if defined(__CC_ARM) || \
- (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
- defined(__GNUC__)
-/* ARM V4/V5 and V6 & GNU Compiler
- -------------------------------
-*/
-#define __NOINLINE __attribute__((noinline))
-
-#elif defined(__ICCARM__)
-/* ICCARM Compiler
- ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif /* __CC_ARM || __GNUC__ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32G4xx_HAL_DEF */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_def.h
+ * @author MCD Application Team
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_DEF
+#define __STM32G4xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stddef.h>
+
+#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
+#include "stm32g4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum {
+ HAL_OK = 0x00U,
+ HAL_ERROR = 0x01U,
+ HAL_BUSY = 0x02U,
+ HAL_TIMEOUT = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do { \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while (0)
+
+#if !defined(UNUSED)
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it
+ * as parameter to HAL_PPP_Init() for the first time, it is mandatory to use
+ * this macro to set to 0 the Handle's "State" field. Otherwise, "State" field
+ * may have any random value and the first time the function HAL_PPP_Init() is
+ * called, the low level hardware initialization will be missed (i.e.
+ * HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware:
+ * instead of calling HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call
+ * to this macro then HAL_PPP_Init(). In this later function, when the Handle's
+ * "State" field is set to 0, it will execute the function HAL_PPP_MspInit()
+ * which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
+#else
+#define __HAL_LOCK(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Lock == HAL_LOCKED) { \
+ return HAL_BUSY; \
+ } else { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ } while (0U)
+
+#define __HAL_UNLOCK(__HANDLE__) \
+ do { \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ } while (0U)
+#endif /* USE_RTOS */
+
+#if defined(__ARMCC_VERSION) && \
+ (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
+ * "#pragma data_alignment=4" must be used instead */
+#if defined(__ARMCC_VERSION) && \
+ (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned(4)))
+#endif
+#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned(4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined(__CC_ARM) /* ARM Compiler V5*/
+#define __ALIGN_BEGIN __align(4U)
+#elif defined(__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined(__CC_ARM) || \
+ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+ --------------------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for
+ Target' dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined(__ICCARM__)
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined(__GNUC__)
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif /* __CC_ARM */
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined(__CC_ARM) || \
+ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
+ defined(__GNUC__)
+/* ARM V4/V5 and V6 & GNU Compiler
+ -------------------------------
+*/
+#define __NOINLINE __attribute__((noinline))
+
+#elif defined(__ICCARM__)
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif /* __CC_ARM || __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32G4xx_HAL_DEF */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
index d7d202d..317f851 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
@@ -1,993 +1,993 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_HAL_DMA_H
-#define __STM32G4xx_HAL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct {
- uint32_t
- Request; /*!< Specifies the request selected for the specified channel.
- This parameter can be a value of @ref DMA_request */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory
- to peripheral, from memory to memory or from peripheral
- to memory. This parameter can be a value of @ref
- DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register
- should be incremented or not. This parameter can be a
- value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be
- incremented or not. This parameter can be a value of @ref
- DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref
- DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref
- DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the
- memory-to-memory data transfer is configured on the selected
- Channel */
-
- uint32_t
- Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum {
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
-} HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum {
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
-} HAL_DMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL DMA Callback ID structure definition
- */
-typedef enum {
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
-
-} HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef {
- DMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (*XferCpltCallback)(
- struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
-
- void (*XferHalfCpltCallback)(
- struct __DMA_HandleTypeDef
- *hdma); /*!< DMA Half transfer complete callback */
-
- void (*XferErrorCallback)(
- struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
-
- void (*XferAbortCallback)(
- struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
-
- uint32_t ChannelIndex; /*!< DMA Channel Index */
-
- DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
-
- DMAMUX_ChannelStatus_TypeDef
- *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
-
- uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
-
- DMAMUX_RequestGen_TypeDef
- *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
-
- DMAMUX_RequestGenStatus_TypeDef
- *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
-
- uint32_t
- DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
-
-} DMA_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE \
- 0x00000000U /*!< No error */
-#define HAL_DMA_ERROR_TE \
- 0x00000001U /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER \
- 0x00000004U /*!< Abort requested with no Xfer ongoing */
-#define HAL_DMA_ERROR_TIMEOUT \
- 0x00000020U /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED \
- 0x00000100U /*!< Not supported mode */
-#define HAL_DMA_ERROR_SYNC \
- 0x00000200U /*!< DMAMUX sync overrun error */
-#define HAL_DMA_ERROR_REQGEN \
- 0x00000400U /*!< DMAMUX request generator overrun error */
-/**
- * @}
- */
-
-/** @defgroup DMA_request DMA request
- * @{
- */
-#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
-
-#define DMA_REQUEST_GENERATOR0 1U
-#define DMA_REQUEST_GENERATOR1 2U
-#define DMA_REQUEST_GENERATOR2 3U
-#define DMA_REQUEST_GENERATOR3 4U
-
-#define DMA_REQUEST_ADC1 5U
-
-#define DMA_REQUEST_DAC1_CHANNEL1 6U
-#define DMA_REQUEST_DAC1_CHANNEL2 7U
-
-#define DMA_REQUEST_TIM6_UP 8U
-#define DMA_REQUEST_TIM7_UP 9U
-
-#define DMA_REQUEST_SPI1_RX 10U
-#define DMA_REQUEST_SPI1_TX 11U
-#define DMA_REQUEST_SPI2_RX 12U
-#define DMA_REQUEST_SPI2_TX 13U
-#define DMA_REQUEST_SPI3_RX 14U
-#define DMA_REQUEST_SPI3_TX 15U
-
-#define DMA_REQUEST_I2C1_RX 16U
-#define DMA_REQUEST_I2C1_TX 17U
-#define DMA_REQUEST_I2C2_RX 18U
-#define DMA_REQUEST_I2C2_TX 19U
-#define DMA_REQUEST_I2C3_RX 20U
-#define DMA_REQUEST_I2C3_TX 21U
-#if defined(I2C4)
-#define DMA_REQUEST_I2C4_RX 22U
-#define DMA_REQUEST_I2C4_TX 23U
-#endif /* I2C4 */
-
-#define DMA_REQUEST_USART1_RX 24U
-#define DMA_REQUEST_USART1_TX 25U
-#define DMA_REQUEST_USART2_RX 26U
-#define DMA_REQUEST_USART2_TX 27U
-#define DMA_REQUEST_USART3_RX 28U
-#define DMA_REQUEST_USART3_TX 29U
-
-#define DMA_REQUEST_UART4_RX 30U
-#define DMA_REQUEST_UART4_TX 31U
-#if defined(UART5)
-#define DMA_REQUEST_UART5_RX 32U
-#define DMA_REQUEST_UART5_TX 33U
-#endif /* UART5 */
-
-#define DMA_REQUEST_LPUART1_RX 34U
-#define DMA_REQUEST_LPUART1_TX 35U
-
-#define DMA_REQUEST_ADC2 36U
-#if defined(ADC3)
-#define DMA_REQUEST_ADC3 37U
-#endif /* ADC3 */
-#if defined(ADC4)
-#define DMA_REQUEST_ADC4 38U
-#endif /* ADC4 */
-#if defined(ADC5)
-#define DMA_REQUEST_ADC5 39U
-#endif /* ADC5 */
-
-#if defined(QUADSPI)
-#define DMA_REQUEST_QUADSPI 40U
-#endif /* QUADSPI */
-
-#if defined(DAC2)
-#define DMA_REQUEST_DAC2_CHANNEL1 41U
-#endif /* DAC2 */
-
-#define DMA_REQUEST_TIM1_CH1 42U
-#define DMA_REQUEST_TIM1_CH2 43U
-#define DMA_REQUEST_TIM1_CH3 44U
-#define DMA_REQUEST_TIM1_CH4 45U
-#define DMA_REQUEST_TIM1_UP 46U
-#define DMA_REQUEST_TIM1_TRIG 47U
-#define DMA_REQUEST_TIM1_COM 48U
-
-#define DMA_REQUEST_TIM8_CH1 49U
-#define DMA_REQUEST_TIM8_CH2 50U
-#define DMA_REQUEST_TIM8_CH3 51U
-#define DMA_REQUEST_TIM8_CH4 52U
-#define DMA_REQUEST_TIM8_UP 53U
-#define DMA_REQUEST_TIM8_TRIG 54U
-#define DMA_REQUEST_TIM8_COM 55U
-
-#define DMA_REQUEST_TIM2_CH1 56U
-#define DMA_REQUEST_TIM2_CH2 57U
-#define DMA_REQUEST_TIM2_CH3 58U
-#define DMA_REQUEST_TIM2_CH4 59U
-#define DMA_REQUEST_TIM2_UP 60U
-
-#define DMA_REQUEST_TIM3_CH1 61U
-#define DMA_REQUEST_TIM3_CH2 62U
-#define DMA_REQUEST_TIM3_CH3 63U
-#define DMA_REQUEST_TIM3_CH4 64U
-#define DMA_REQUEST_TIM3_UP 65U
-#define DMA_REQUEST_TIM3_TRIG 66U
-
-#define DMA_REQUEST_TIM4_CH1 67U
-#define DMA_REQUEST_TIM4_CH2 68U
-#define DMA_REQUEST_TIM4_CH3 69U
-#define DMA_REQUEST_TIM4_CH4 70U
-#define DMA_REQUEST_TIM4_UP 71U
-
-#if defined(TIM5)
-#define DMA_REQUEST_TIM5_CH1 72U
-#define DMA_REQUEST_TIM5_CH2 73U
-#define DMA_REQUEST_TIM5_CH3 74U
-#define DMA_REQUEST_TIM5_CH4 75U
-#define DMA_REQUEST_TIM5_UP 76U
-#define DMA_REQUEST_TIM5_TRIG 77U
-#endif /* TIM5 */
-
-#define DMA_REQUEST_TIM15_CH1 78U
-#define DMA_REQUEST_TIM15_UP 79U
-#define DMA_REQUEST_TIM15_TRIG 80U
-#define DMA_REQUEST_TIM15_COM 81U
-
-#define DMA_REQUEST_TIM16_CH1 82U
-#define DMA_REQUEST_TIM16_UP 83U
-#define DMA_REQUEST_TIM17_CH1 84U
-#define DMA_REQUEST_TIM17_UP 85U
-
-#if defined(TIM20)
-#define DMA_REQUEST_TIM20_CH1 86U
-#define DMA_REQUEST_TIM20_CH2 87U
-#define DMA_REQUEST_TIM20_CH3 88U
-#define DMA_REQUEST_TIM20_CH4 89U
-#define DMA_REQUEST_TIM20_UP 90U
-#endif /* TIM20 */
-
-#define DMA_REQUEST_AES_IN 91U
-#define DMA_REQUEST_AES_OUT 92U
-
-#if defined(TIM20)
-#define DMA_REQUEST_TIM20_TRIG 93U
-#define DMA_REQUEST_TIM20_COM 94U
-#endif /* TIM20 */
-
-#if defined(HRTIM1)
-#define DMA_REQUEST_HRTIM1_M 95U
-#define DMA_REQUEST_HRTIM1_A 96U
-#define DMA_REQUEST_HRTIM1_B 97U
-#define DMA_REQUEST_HRTIM1_C 98U
-#define DMA_REQUEST_HRTIM1_D 99U
-#define DMA_REQUEST_HRTIM1_E 100U
-#define DMA_REQUEST_HRTIM1_F 101U
-#endif /* HRTIM1 */
-
-#define DMA_REQUEST_DAC3_CHANNEL1 102U
-#define DMA_REQUEST_DAC3_CHANNEL2 103U
-#if defined(DAC4)
-#define DMA_REQUEST_DAC4_CHANNEL1 104U
-#define DMA_REQUEST_DAC4_CHANNEL2 105U
-#endif /* DAC4 */
-
-#if defined(SPI4)
-#define DMA_REQUEST_SPI4_RX 106U
-#define DMA_REQUEST_SPI4_TX 107U
-#endif /* SPI4 */
-
-#define DMA_REQUEST_SAI1_A 108U
-#define DMA_REQUEST_SAI1_B 109U
-
-#define DMA_REQUEST_FMAC_READ 110U
-#define DMA_REQUEST_FMAC_WRITE 111U
-
-#define DMA_REQUEST_CORDIC_READ 112U
-#define DMA_REQUEST_CORDIC_WRITE 113U
-
-#define DMA_REQUEST_UCPD1_RX 114U
-#define DMA_REQUEST_UCPD1_TX 115U
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY \
- 0x00000000U /*!< Peripheral to memory direction \
- */
-#define DMA_MEMORY_TO_PERIPH \
- DMA_CCR_DIR /*!< Memory to peripheral direction \
- */
-#define DMA_MEMORY_TO_MEMORY \
- DMA_CCR_MEM2MEM /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE \
- 0x00000000U /*!< Peripheral data alignment : Byte */
-#define DMA_PDATAALIGN_HALFWORD \
- DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD \
- DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
-#define DMA_MDATAALIGN_HALFWORD \
- DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD \
- DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @{
- */
-#define DMA_NORMAL 0x00000000U /*!< Normal mode */
-#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @{
- */
-#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
-#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
-#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @{
- */
-#define DMA_IT_TC DMA_CCR_TCIE
-#define DMA_IT_HT DMA_CCR_HTIE
-#define DMA_IT_TE DMA_CCR_TEIE
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @{
- */
-#define DMA_FLAG_GL1 0x00000001U
-#define DMA_FLAG_TC1 0x00000002U
-#define DMA_FLAG_HT1 0x00000004U
-#define DMA_FLAG_TE1 0x00000008U
-#define DMA_FLAG_GL2 0x00000010U
-#define DMA_FLAG_TC2 0x00000020U
-#define DMA_FLAG_HT2 0x00000040U
-#define DMA_FLAG_TE2 0x00000080U
-#define DMA_FLAG_GL3 0x00000100U
-#define DMA_FLAG_TC3 0x00000200U
-#define DMA_FLAG_HT3 0x00000400U
-#define DMA_FLAG_TE3 0x00000800U
-#define DMA_FLAG_GL4 0x00001000U
-#define DMA_FLAG_TC4 0x00002000U
-#define DMA_FLAG_HT4 0x00004000U
-#define DMA_FLAG_TE4 0x00008000U
-#define DMA_FLAG_GL5 0x00010000U
-#define DMA_FLAG_TC5 0x00020000U
-#define DMA_FLAG_HT5 0x00040000U
-#define DMA_FLAG_TE5 0x00080000U
-#define DMA_FLAG_GL6 0x00100000U
-#define DMA_FLAG_TC6 0x00200000U
-#define DMA_FLAG_HT6 0x00400000U
-#define DMA_FLAG_TE6 0x00800000U
-#if defined(DMA1_Channel7)
-#define DMA_FLAG_GL7 0x01000000U
-#define DMA_FLAG_TC7 0x02000000U
-#define DMA_FLAG_HT7 0x04000000U
-#define DMA_FLAG_TE7 0x08000000U
-#endif /* DMA1_Channel7 */
-#if defined(DMA1_Channel8)
-#define DMA_FLAG_GL8 0x10000000U
-#define DMA_FLAG_TC8 0x20000000U
-#define DMA_FLAG_HT8 0x40000000U
-#define DMA_FLAG_TE8 0x80000000U
-#endif /* DMA1_Channel8 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @brief Reset DMA handle state.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Enable the specified DMA Channel.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
-
-/**
- * @brief Disable the specified DMA Channel.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Return the current DMA Channel transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer complete flag index.
- */
-
-#if defined(DMA1_Channel8)
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_FLAG_TC1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_FLAG_TC1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_FLAG_TC2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_FLAG_TC2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_FLAG_TC3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_FLAG_TC3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_FLAG_TC4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_FLAG_TC4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_FLAG_TC5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_FLAG_TC5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
- ? DMA_FLAG_TC6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
- ? DMA_FLAG_TC6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
- ? DMA_FLAG_TC7 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
- ? DMA_FLAG_TC7 \
- : DMA_FLAG_TC8)
-#elif defined(DMA1_Channel6)
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_FLAG_TC1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_FLAG_TC1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_FLAG_TC2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_FLAG_TC2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_FLAG_TC3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_FLAG_TC3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_FLAG_TC4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_FLAG_TC4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_FLAG_TC5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_FLAG_TC5 \
- : DMA_FLAG_TC6)
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Return the current DMA Channel half transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#if defined(DMA1_Channel8)
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_FLAG_HT1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_FLAG_HT1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_FLAG_HT2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_FLAG_HT2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_FLAG_HT3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_FLAG_HT3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_FLAG_HT4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_FLAG_HT4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_FLAG_HT5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_FLAG_HT5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
- ? DMA_FLAG_HT6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
- ? DMA_FLAG_HT6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
- ? DMA_FLAG_HT7 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
- ? DMA_FLAG_HT7 \
- : DMA_FLAG_HT8)
-#elif defined(DMA1_Channel6)
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_FLAG_HT1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_FLAG_HT1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_FLAG_HT2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_FLAG_HT2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_FLAG_HT3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_FLAG_HT3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_FLAG_HT4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_FLAG_HT4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_FLAG_HT5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_FLAG_HT5 \
- : DMA_FLAG_HT6)
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Return the current DMA Channel transfer error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#if defined(DMA1_Channel8)
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_FLAG_TE1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_FLAG_TE1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_FLAG_TE2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_FLAG_TE2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_FLAG_TE3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_FLAG_TE3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_FLAG_TE4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_FLAG_TE4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_FLAG_TE5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_FLAG_TE5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
- ? DMA_FLAG_TE6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
- ? DMA_FLAG_TE6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
- ? DMA_FLAG_TE7 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
- ? DMA_FLAG_TE7 \
- : DMA_FLAG_TE8)
-#elif defined(DMA1_Channel6)
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_FLAG_TE1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_FLAG_TE1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_FLAG_TE2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_FLAG_TE2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_FLAG_TE3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_FLAG_TE3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_FLAG_TE4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_FLAG_TE4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_FLAG_TE5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_FLAG_TE5 \
- : DMA_FLAG_TE6)
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#if defined(DMA1_Channel8)
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_ISR_GIF1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_ISR_GIF1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_ISR_GIF2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_ISR_GIF2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_ISR_GIF3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_ISR_GIF3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_ISR_GIF4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_ISR_GIF4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_ISR_GIF5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_ISR_GIF5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
- ? DMA_ISR_GIF6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
- ? DMA_ISR_GIF6 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
- ? DMA_ISR_GIF7 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
- ? DMA_ISR_GIF7 \
- : DMA_ISR_GIF8)
-#elif defined(DMA1_Channel6)
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
- (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
- ? DMA_ISR_GIF1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
- ? DMA_ISR_GIF1 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
- ? DMA_ISR_GIF2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
- ? DMA_ISR_GIF2 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
- ? DMA_ISR_GIF3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
- ? DMA_ISR_GIF3 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
- ? DMA_ISR_GIF4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
- ? DMA_ISR_GIF4 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
- ? DMA_ISR_GIF5 \
- : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
- ? DMA_ISR_GIF5 \
- : DMA_ISR_GIF6)
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx Transfer complete flag
- * @arg DMA_FLAG_HTx Half transfer complete flag
- * @arg DMA_FLAG_TEx Transfer error flag
- * @arg DMA_FLAG_GLx Global interrupt flag
- * Where x can be from 1 to 8 to select the DMA Channel x flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#if defined(DMA1_Channel8)
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
- (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8)) \
- ? (DMA2->ISR & (__FLAG__)) \
- : (DMA1->ISR & (__FLAG__)))
-#elif defined(DMA1_Channel6)
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
- (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6)) \
- ? (DMA2->ISR & (__FLAG__)) \
- : (DMA1->ISR & (__FLAG__)))
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Clear the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx Transfer complete flag
- * @arg DMA_FLAG_HTx Half transfer complete flag
- * @arg DMA_FLAG_TEx Transfer error flag
- * @arg DMA_FLAG_GLx Global interrupt flag
- * Where x can be from 1 to 8 to select the DMA Channel x flag.
- * @retval None
- */
-#if defined(DMA1_Channel8)
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8)) \
- ? (DMA2->IFCR = (__FLAG__)) \
- : (DMA1->IFCR = (__FLAG__)))
-#else
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6)) \
- ? (DMA2->IFCR = (__FLAG__)) \
- : (DMA1->IFCR = (__FLAG__)))
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Enable the specified DMA Channel interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or
- * disabled. This parameter can be any combination of the following values:
- * @arg DMA_IT_TC Transfer complete interrupt mask
- * @arg DMA_IT_HT Half transfer complete interrupt mask
- * @arg DMA_IT_TE Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified DMA Channel interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or
- * disabled. This parameter can be any combination of the following values:
- * @arg DMA_IT_TC Transfer complete interrupt mask
- * @arg DMA_IT_HT Half transfer complete interrupt mask
- * @arg DMA_IT_TE Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified DMA Channel interrupt is enabled or not.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC Transfer complete interrupt mask
- * @arg DMA_IT_HT Half transfer complete interrupt mask
- * @arg DMA_IT_TE Transfer error interrupt mask
- * @retval The state of DMA_IT (SET or RESET).
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
- * @brief Return the number of remaining data units in the current DMA Channel
- * transfer.
- * @param __HANDLE__ DMA handle
- * @retval The number of remaining data units in the current DMA Channel
- * transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
- * @}
- */
-
-/* Include DMA HAL Extension module */
-#include "stm32g4xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DMA_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(
- DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
- uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(
- DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID,
- void (*pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(
- DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @{
- */
-
-#define IS_DMA_DIRECTION(DIRECTION) \
- (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) \
- (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) \
- (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) \
- (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
- (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) \
- (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_HAL_DMA_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_DMA_H
+#define __STM32G4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct {
+ uint32_t
+ Request; /*!< Specifies the request selected for the specified channel.
+ This parameter can be a value of @ref DMA_request */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory
+ to peripheral, from memory to memory or from peripheral
+ to memory. This parameter can be a value of @ref
+ DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register
+ should be incremented or not. This parameter can be a
+ value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be
+ incremented or not. This parameter can be a value of @ref
+ DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref
+ DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref
+ DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the
+ memory-to-memory data transfer is configured on the selected
+ Channel */
+
+ uint32_t
+ Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum {
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
+} HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum {
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Callback ID structure definition
+ */
+typedef enum {
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef {
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (*XferCpltCallback)(
+ struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
+
+ void (*XferHalfCpltCallback)(
+ struct __DMA_HandleTypeDef
+ *hdma); /*!< DMA Half transfer complete callback */
+
+ void (*XferErrorCallback)(
+ struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
+
+ void (*XferAbortCallback)(
+ struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
+
+ uint32_t ChannelIndex; /*!< DMA Channel Index */
+
+ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
+
+ DMAMUX_ChannelStatus_TypeDef
+ *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
+
+ uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
+
+ DMAMUX_RequestGen_TypeDef
+ *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
+
+ DMAMUX_RequestGenStatus_TypeDef
+ *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
+
+ uint32_t
+ DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
+
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE \
+ 0x00000000U /*!< No error */
+#define HAL_DMA_ERROR_TE \
+ 0x00000001U /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER \
+ 0x00000004U /*!< Abort requested with no Xfer ongoing */
+#define HAL_DMA_ERROR_TIMEOUT \
+ 0x00000020U /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED \
+ 0x00000100U /*!< Not supported mode */
+#define HAL_DMA_ERROR_SYNC \
+ 0x00000200U /*!< DMAMUX sync overrun error */
+#define HAL_DMA_ERROR_REQGEN \
+ 0x00000400U /*!< DMAMUX request generator overrun error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_request DMA request
+ * @{
+ */
+#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
+
+#define DMA_REQUEST_GENERATOR0 1U
+#define DMA_REQUEST_GENERATOR1 2U
+#define DMA_REQUEST_GENERATOR2 3U
+#define DMA_REQUEST_GENERATOR3 4U
+
+#define DMA_REQUEST_ADC1 5U
+
+#define DMA_REQUEST_DAC1_CHANNEL1 6U
+#define DMA_REQUEST_DAC1_CHANNEL2 7U
+
+#define DMA_REQUEST_TIM6_UP 8U
+#define DMA_REQUEST_TIM7_UP 9U
+
+#define DMA_REQUEST_SPI1_RX 10U
+#define DMA_REQUEST_SPI1_TX 11U
+#define DMA_REQUEST_SPI2_RX 12U
+#define DMA_REQUEST_SPI2_TX 13U
+#define DMA_REQUEST_SPI3_RX 14U
+#define DMA_REQUEST_SPI3_TX 15U
+
+#define DMA_REQUEST_I2C1_RX 16U
+#define DMA_REQUEST_I2C1_TX 17U
+#define DMA_REQUEST_I2C2_RX 18U
+#define DMA_REQUEST_I2C2_TX 19U
+#define DMA_REQUEST_I2C3_RX 20U
+#define DMA_REQUEST_I2C3_TX 21U
+#if defined(I2C4)
+#define DMA_REQUEST_I2C4_RX 22U
+#define DMA_REQUEST_I2C4_TX 23U
+#endif /* I2C4 */
+
+#define DMA_REQUEST_USART1_RX 24U
+#define DMA_REQUEST_USART1_TX 25U
+#define DMA_REQUEST_USART2_RX 26U
+#define DMA_REQUEST_USART2_TX 27U
+#define DMA_REQUEST_USART3_RX 28U
+#define DMA_REQUEST_USART3_TX 29U
+
+#define DMA_REQUEST_UART4_RX 30U
+#define DMA_REQUEST_UART4_TX 31U
+#if defined(UART5)
+#define DMA_REQUEST_UART5_RX 32U
+#define DMA_REQUEST_UART5_TX 33U
+#endif /* UART5 */
+
+#define DMA_REQUEST_LPUART1_RX 34U
+#define DMA_REQUEST_LPUART1_TX 35U
+
+#define DMA_REQUEST_ADC2 36U
+#if defined(ADC3)
+#define DMA_REQUEST_ADC3 37U
+#endif /* ADC3 */
+#if defined(ADC4)
+#define DMA_REQUEST_ADC4 38U
+#endif /* ADC4 */
+#if defined(ADC5)
+#define DMA_REQUEST_ADC5 39U
+#endif /* ADC5 */
+
+#if defined(QUADSPI)
+#define DMA_REQUEST_QUADSPI 40U
+#endif /* QUADSPI */
+
+#if defined(DAC2)
+#define DMA_REQUEST_DAC2_CHANNEL1 41U
+#endif /* DAC2 */
+
+#define DMA_REQUEST_TIM1_CH1 42U
+#define DMA_REQUEST_TIM1_CH2 43U
+#define DMA_REQUEST_TIM1_CH3 44U
+#define DMA_REQUEST_TIM1_CH4 45U
+#define DMA_REQUEST_TIM1_UP 46U
+#define DMA_REQUEST_TIM1_TRIG 47U
+#define DMA_REQUEST_TIM1_COM 48U
+
+#define DMA_REQUEST_TIM8_CH1 49U
+#define DMA_REQUEST_TIM8_CH2 50U
+#define DMA_REQUEST_TIM8_CH3 51U
+#define DMA_REQUEST_TIM8_CH4 52U
+#define DMA_REQUEST_TIM8_UP 53U
+#define DMA_REQUEST_TIM8_TRIG 54U
+#define DMA_REQUEST_TIM8_COM 55U
+
+#define DMA_REQUEST_TIM2_CH1 56U
+#define DMA_REQUEST_TIM2_CH2 57U
+#define DMA_REQUEST_TIM2_CH3 58U
+#define DMA_REQUEST_TIM2_CH4 59U
+#define DMA_REQUEST_TIM2_UP 60U
+
+#define DMA_REQUEST_TIM3_CH1 61U
+#define DMA_REQUEST_TIM3_CH2 62U
+#define DMA_REQUEST_TIM3_CH3 63U
+#define DMA_REQUEST_TIM3_CH4 64U
+#define DMA_REQUEST_TIM3_UP 65U
+#define DMA_REQUEST_TIM3_TRIG 66U
+
+#define DMA_REQUEST_TIM4_CH1 67U
+#define DMA_REQUEST_TIM4_CH2 68U
+#define DMA_REQUEST_TIM4_CH3 69U
+#define DMA_REQUEST_TIM4_CH4 70U
+#define DMA_REQUEST_TIM4_UP 71U
+
+#if defined(TIM5)
+#define DMA_REQUEST_TIM5_CH1 72U
+#define DMA_REQUEST_TIM5_CH2 73U
+#define DMA_REQUEST_TIM5_CH3 74U
+#define DMA_REQUEST_TIM5_CH4 75U
+#define DMA_REQUEST_TIM5_UP 76U
+#define DMA_REQUEST_TIM5_TRIG 77U
+#endif /* TIM5 */
+
+#define DMA_REQUEST_TIM15_CH1 78U
+#define DMA_REQUEST_TIM15_UP 79U
+#define DMA_REQUEST_TIM15_TRIG 80U
+#define DMA_REQUEST_TIM15_COM 81U
+
+#define DMA_REQUEST_TIM16_CH1 82U
+#define DMA_REQUEST_TIM16_UP 83U
+#define DMA_REQUEST_TIM17_CH1 84U
+#define DMA_REQUEST_TIM17_UP 85U
+
+#if defined(TIM20)
+#define DMA_REQUEST_TIM20_CH1 86U
+#define DMA_REQUEST_TIM20_CH2 87U
+#define DMA_REQUEST_TIM20_CH3 88U
+#define DMA_REQUEST_TIM20_CH4 89U
+#define DMA_REQUEST_TIM20_UP 90U
+#endif /* TIM20 */
+
+#define DMA_REQUEST_AES_IN 91U
+#define DMA_REQUEST_AES_OUT 92U
+
+#if defined(TIM20)
+#define DMA_REQUEST_TIM20_TRIG 93U
+#define DMA_REQUEST_TIM20_COM 94U
+#endif /* TIM20 */
+
+#if defined(HRTIM1)
+#define DMA_REQUEST_HRTIM1_M 95U
+#define DMA_REQUEST_HRTIM1_A 96U
+#define DMA_REQUEST_HRTIM1_B 97U
+#define DMA_REQUEST_HRTIM1_C 98U
+#define DMA_REQUEST_HRTIM1_D 99U
+#define DMA_REQUEST_HRTIM1_E 100U
+#define DMA_REQUEST_HRTIM1_F 101U
+#endif /* HRTIM1 */
+
+#define DMA_REQUEST_DAC3_CHANNEL1 102U
+#define DMA_REQUEST_DAC3_CHANNEL2 103U
+#if defined(DAC4)
+#define DMA_REQUEST_DAC4_CHANNEL1 104U
+#define DMA_REQUEST_DAC4_CHANNEL2 105U
+#endif /* DAC4 */
+
+#if defined(SPI4)
+#define DMA_REQUEST_SPI4_RX 106U
+#define DMA_REQUEST_SPI4_TX 107U
+#endif /* SPI4 */
+
+#define DMA_REQUEST_SAI1_A 108U
+#define DMA_REQUEST_SAI1_B 109U
+
+#define DMA_REQUEST_FMAC_READ 110U
+#define DMA_REQUEST_FMAC_WRITE 111U
+
+#define DMA_REQUEST_CORDIC_READ 112U
+#define DMA_REQUEST_CORDIC_WRITE 113U
+
+#define DMA_REQUEST_UCPD1_RX 114U
+#define DMA_REQUEST_UCPD1_TX 115U
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY \
+ 0x00000000U /*!< Peripheral to memory direction \
+ */
+#define DMA_MEMORY_TO_PERIPH \
+ DMA_CCR_DIR /*!< Memory to peripheral direction \
+ */
+#define DMA_MEMORY_TO_MEMORY \
+ DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE \
+ 0x00000000U /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_HALFWORD \
+ DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD \
+ DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_HALFWORD \
+ DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD \
+ DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */
+#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+#define DMA_IT_TC DMA_CCR_TCIE
+#define DMA_IT_HT DMA_CCR_HTIE
+#define DMA_IT_TE DMA_CCR_TEIE
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_GL1 0x00000001U
+#define DMA_FLAG_TC1 0x00000002U
+#define DMA_FLAG_HT1 0x00000004U
+#define DMA_FLAG_TE1 0x00000008U
+#define DMA_FLAG_GL2 0x00000010U
+#define DMA_FLAG_TC2 0x00000020U
+#define DMA_FLAG_HT2 0x00000040U
+#define DMA_FLAG_TE2 0x00000080U
+#define DMA_FLAG_GL3 0x00000100U
+#define DMA_FLAG_TC3 0x00000200U
+#define DMA_FLAG_HT3 0x00000400U
+#define DMA_FLAG_TE3 0x00000800U
+#define DMA_FLAG_GL4 0x00001000U
+#define DMA_FLAG_TC4 0x00002000U
+#define DMA_FLAG_HT4 0x00004000U
+#define DMA_FLAG_TE4 0x00008000U
+#define DMA_FLAG_GL5 0x00010000U
+#define DMA_FLAG_TC5 0x00020000U
+#define DMA_FLAG_HT5 0x00040000U
+#define DMA_FLAG_TE5 0x00080000U
+#define DMA_FLAG_GL6 0x00100000U
+#define DMA_FLAG_TC6 0x00200000U
+#define DMA_FLAG_HT6 0x00400000U
+#define DMA_FLAG_TE6 0x00800000U
+#if defined(DMA1_Channel7)
+#define DMA_FLAG_GL7 0x01000000U
+#define DMA_FLAG_TC7 0x02000000U
+#define DMA_FLAG_HT7 0x04000000U
+#define DMA_FLAG_TE7 0x08000000U
+#endif /* DMA1_Channel7 */
+#if defined(DMA1_Channel8)
+#define DMA_FLAG_GL8 0x10000000U
+#define DMA_FLAG_TC8 0x20000000U
+#define DMA_FLAG_HT8 0x40000000U
+#define DMA_FLAG_TE8 0x80000000U
+#endif /* DMA1_Channel8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Return the current DMA Channel transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+
+#if defined(DMA1_Channel8)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_FLAG_TC1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_FLAG_TC1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_FLAG_TC2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_FLAG_TC2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_FLAG_TC3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_FLAG_TC3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_FLAG_TC4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_FLAG_TC4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_FLAG_TC5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_FLAG_TC5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
+ ? DMA_FLAG_TC6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
+ ? DMA_FLAG_TC6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
+ ? DMA_FLAG_TC7 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
+ ? DMA_FLAG_TC7 \
+ : DMA_FLAG_TC8)
+#elif defined(DMA1_Channel6)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_FLAG_TC1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_FLAG_TC1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_FLAG_TC2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_FLAG_TC2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_FLAG_TC3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_FLAG_TC3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_FLAG_TC4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_FLAG_TC4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_FLAG_TC5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_FLAG_TC5 \
+ : DMA_FLAG_TC6)
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Return the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#if defined(DMA1_Channel8)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_FLAG_HT1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_FLAG_HT1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_FLAG_HT2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_FLAG_HT2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_FLAG_HT3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_FLAG_HT3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_FLAG_HT4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_FLAG_HT4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_FLAG_HT5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_FLAG_HT5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
+ ? DMA_FLAG_HT6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
+ ? DMA_FLAG_HT6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
+ ? DMA_FLAG_HT7 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
+ ? DMA_FLAG_HT7 \
+ : DMA_FLAG_HT8)
+#elif defined(DMA1_Channel6)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_FLAG_HT1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_FLAG_HT1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_FLAG_HT2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_FLAG_HT2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_FLAG_HT3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_FLAG_HT3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_FLAG_HT4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_FLAG_HT4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_FLAG_HT5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_FLAG_HT5 \
+ : DMA_FLAG_HT6)
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Return the current DMA Channel transfer error flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#if defined(DMA1_Channel8)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_FLAG_TE1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_FLAG_TE1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_FLAG_TE2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_FLAG_TE2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_FLAG_TE3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_FLAG_TE3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_FLAG_TE4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_FLAG_TE4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_FLAG_TE5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_FLAG_TE5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
+ ? DMA_FLAG_TE6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
+ ? DMA_FLAG_TE6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
+ ? DMA_FLAG_TE7 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
+ ? DMA_FLAG_TE7 \
+ : DMA_FLAG_TE8)
+#elif defined(DMA1_Channel6)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_FLAG_TE1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_FLAG_TE1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_FLAG_TE2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_FLAG_TE2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_FLAG_TE3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_FLAG_TE3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_FLAG_TE4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_FLAG_TE4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_FLAG_TE5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_FLAG_TE5 \
+ : DMA_FLAG_TE6)
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Return the current DMA Channel Global interrupt flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#if defined(DMA1_Channel8)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_ISR_GIF1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_ISR_GIF1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_ISR_GIF2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_ISR_GIF2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_ISR_GIF3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_ISR_GIF3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_ISR_GIF4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_ISR_GIF4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_ISR_GIF5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_ISR_GIF5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
+ ? DMA_ISR_GIF6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6)) \
+ ? DMA_ISR_GIF6 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
+ ? DMA_ISR_GIF7 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7)) \
+ ? DMA_ISR_GIF7 \
+ : DMA_ISR_GIF8)
+#elif defined(DMA1_Channel6)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
+ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
+ ? DMA_ISR_GIF1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
+ ? DMA_ISR_GIF1 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
+ ? DMA_ISR_GIF2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
+ ? DMA_ISR_GIF2 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
+ ? DMA_ISR_GIF3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+ ? DMA_ISR_GIF3 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
+ ? DMA_ISR_GIF4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) \
+ ? DMA_ISR_GIF4 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
+ ? DMA_ISR_GIF5 \
+ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5)) \
+ ? DMA_ISR_GIF5 \
+ : DMA_ISR_GIF6)
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx Transfer complete flag
+ * @arg DMA_FLAG_HTx Half transfer complete flag
+ * @arg DMA_FLAG_TEx Transfer error flag
+ * @arg DMA_FLAG_GLx Global interrupt flag
+ * Where x can be from 1 to 8 to select the DMA Channel x flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#if defined(DMA1_Channel8)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8)) \
+ ? (DMA2->ISR & (__FLAG__)) \
+ : (DMA1->ISR & (__FLAG__)))
+#elif defined(DMA1_Channel6)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6)) \
+ ? (DMA2->ISR & (__FLAG__)) \
+ : (DMA1->ISR & (__FLAG__)))
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Clear the DMA Channel pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx Transfer complete flag
+ * @arg DMA_FLAG_HTx Half transfer complete flag
+ * @arg DMA_FLAG_TEx Transfer error flag
+ * @arg DMA_FLAG_GLx Global interrupt flag
+ * Where x can be from 1 to 8 to select the DMA Channel x flag.
+ * @retval None
+ */
+#if defined(DMA1_Channel8)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8)) \
+ ? (DMA2->IFCR = (__FLAG__)) \
+ : (DMA1->IFCR = (__FLAG__)))
+#else
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6)) \
+ ? (DMA2->IFCR = (__FLAG__)) \
+ : (DMA1->IFCR = (__FLAG__)))
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Enable the specified DMA Channel interrupts.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or
+ * disabled. This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC Transfer complete interrupt mask
+ * @arg DMA_IT_HT Half transfer complete interrupt mask
+ * @arg DMA_IT_TE Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DMA Channel interrupts.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or
+ * disabled. This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC Transfer complete interrupt mask
+ * @arg DMA_IT_HT Half transfer complete interrupt mask
+ * @arg DMA_IT_TE Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DMA Channel interrupt is enabled or not.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC Transfer complete interrupt mask
+ * @arg DMA_IT_HT Half transfer complete interrupt mask
+ * @arg DMA_IT_TE Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+ * @brief Return the number of remaining data units in the current DMA Channel
+ * transfer.
+ * @param __HANDLE__ DMA handle
+ * @retval The number of remaining data units in the current DMA Channel
+ * transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32g4xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(
+ DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+ uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(
+ DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID,
+ void (*pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(
+ DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @{
+ */
+
+#define IS_DMA_DIRECTION(DIRECTION) \
+ (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) \
+ (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) \
+ (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) \
+ (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_HAL_DMA_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
index 420e3d0..6cabfda 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
@@ -1,318 +1,318 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_HAL_DMA_EX_H
-#define __STM32G4xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
- * @{
- */
-
-/**
- * @brief HAL DMA Synchro definition
- */
-
-/**
- * @brief HAL DMAMUX Synchronization configuration structure definition
- */
-typedef struct {
- uint32_t
- SyncSignalID; /*!< Specifies the synchronization signal gating the DMA
- request in periodic mode. This parameter can be a value
- of @ref DMAEx_DMAMUX_SyncSignalID_selection */
-
- uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the
- DMA request is synchronized. This parameter can be a
- value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
-
- FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be
- enabled or disabled This parameter can take the
- value ENABLE or DISABLE*/
-
- FunctionalState
- EventEnable; /*!< Specifies if an event shall be generated once the
- RequestNumber is reached. This parameter can take the
- value ENABLE or DISABLE */
-
- uint32_t
- RequestNumber; /*!< Specifies the number of DMA request that will be
- authorized after a sync event This parameter must be a
- number between Min_Data = 1 and Max_Data = 32 */
-
-} HAL_DMA_MuxSyncConfigTypeDef;
-
-/**
- * @brief HAL DMAMUX request generator parameters structure definition
- */
-typedef struct {
- uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request
- generator This parameter can be a value of @ref
- DMAEx_DMAMUX_SignalGeneratorID_selection */
-
- uint32_t Polarity; /*!< Specifies the polarity of the signal on which the
- request is generated. This parameter can be a value of
- @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
-
- uint32_t
- RequestNumber; /*!< Specifies the number of DMA request that will be
- generated after a signal event This parameter must be a
- number between Min_Data = 1 and Max_Data = 32 */
-
-} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
- * @{
- */
-
-/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
- * @{
- */
-#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
-#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
-#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
-#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
-#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
-#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
-#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
-#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
-#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
-#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
-#define HAL_DMAMUX1_SYNC_EXTI10 \
- 10U /*!< Synchronization Signal is EXTI10 IT */
-#define HAL_DMAMUX1_SYNC_EXTI11 \
- 11U /*!< Synchronization Signal is EXTI11 IT */
-#define HAL_DMAMUX1_SYNC_EXTI12 \
- 12U /*!< Synchronization Signal is EXTI12 IT */
-#define HAL_DMAMUX1_SYNC_EXTI13 \
- 13U /*!< Synchronization Signal is EXTI13 IT */
-#define HAL_DMAMUX1_SYNC_EXTI14 \
- 14U /*!< Synchronization Signal is EXTI14 IT */
-#define HAL_DMAMUX1_SYNC_EXTI15 \
- 15U /*!< Synchronization Signal is EXTI15 IT */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT \
- 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT \
- 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT \
- 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT \
- 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
-#define HAL_DMAMUX1_SYNC_LPTIM1_OUT \
- 20U /*!< Synchronization Signal is LPTIM1 OUT */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
- * @{
- */
-#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
-#define HAL_DMAMUX_SYNC_RISING \
- ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */
-#define HAL_DMAMUX_SYNC_FALLING \
- ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */
-#define HAL_DMAMUX_SYNC_RISING_FALLING \
- ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge \
- events */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID
- * selection
- * @{
- */
-#define HAL_DMAMUX1_REQ_GEN_EXTI0 \
- 0U /*!< Request generator Signal is EXTI0 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI1 \
- 1U /*!< Request generator Signal is EXTI1 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI2 \
- 2U /*!< Request generator Signal is EXTI2 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI3 \
- 3U /*!< Request generator Signal is EXTI3 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI4 \
- 4U /*!< Request generator Signal is EXTI4 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI5 \
- 5U /*!< Request generator Signal is EXTI5 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI6 \
- 6U /*!< Request generator Signal is EXTI6 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI7 \
- 7U /*!< Request generator Signal is EXTI7 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI8 \
- 8U /*!< Request generator Signal is EXTI8 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI9 \
- 9U /*!< Request generator Signal is EXTI9 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI10 \
- 10U /*!< Request generator Signal is EXTI10 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI11 \
- 11U /*!< Request generator Signal is EXTI11 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI12 \
- 12U /*!< Request generator Signal is EXTI12 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI13 \
- 13U /*!< Request generator Signal is EXTI13 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI14 \
- 14U /*!< Request generator Signal is EXTI14 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI15 \
- 15U /*!< Request generator Signal is EXTI15 IT */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT \
- 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT \
- 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT \
- 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT \
- 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT \
- 20U /*!< Request generator Signal is LPTIM1 OUT */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX
- * RequestGeneneratorPolarity selection
- * @{
- */
-#define HAL_DMAMUX_REQ_GEN_NO_EVENT \
- 0x00000000U /*!< block request generator events */
-#define HAL_DMAMUX_REQ_GEN_RISING \
- DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
-#define HAL_DMAMUX_REQ_GEN_FALLING \
- DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
-#define HAL_DMAMUX_REQ_GEN_RISING_FALLING \
- DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMAEx_Exported_Functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup DMAEx_Exported_Functions_Group1
- * @{
- */
-
-/* ------------------------- REQUEST -----------------------------------------*/
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(
- DMA_HandleTypeDef *hdma,
- HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
-/* -------------------------------------------------------------------------- */
-
-/* ------------------------- SYNCHRO -----------------------------------------*/
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(
- DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
-/* -------------------------------------------------------------------------- */
-
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
- * @brief DMAEx private macros
- * @{
- */
-
-#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) \
- ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
-
-#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) \
- (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
-
-#define IS_DMAMUX_SYNC_POLARITY(POLARITY) \
- (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
-
-#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
-
-#define IS_DMAMUX_SYNC_EVENT(EVENT) \
- (((EVENT) == DISABLE) || ((EVENT) == ENABLE))
-
-#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) \
- ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
-
-#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) \
- (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
-
-#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) \
- (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_HAL_DMA_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_DMA_EX_H
+#define __STM32G4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL DMA Synchro definition
+ */
+
+/**
+ * @brief HAL DMAMUX Synchronization configuration structure definition
+ */
+typedef struct {
+ uint32_t
+ SyncSignalID; /*!< Specifies the synchronization signal gating the DMA
+ request in periodic mode. This parameter can be a value
+ of @ref DMAEx_DMAMUX_SyncSignalID_selection */
+
+ uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the
+ DMA request is synchronized. This parameter can be a
+ value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
+
+ FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be
+ enabled or disabled This parameter can take the
+ value ENABLE or DISABLE*/
+
+ FunctionalState
+ EventEnable; /*!< Specifies if an event shall be generated once the
+ RequestNumber is reached. This parameter can take the
+ value ENABLE or DISABLE */
+
+ uint32_t
+ RequestNumber; /*!< Specifies the number of DMA request that will be
+ authorized after a sync event This parameter must be a
+ number between Min_Data = 1 and Max_Data = 32 */
+
+} HAL_DMA_MuxSyncConfigTypeDef;
+
+/**
+ * @brief HAL DMAMUX request generator parameters structure definition
+ */
+typedef struct {
+ uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request
+ generator This parameter can be a value of @ref
+ DMAEx_DMAMUX_SignalGeneratorID_selection */
+
+ uint32_t Polarity; /*!< Specifies the polarity of the signal on which the
+ request is generated. This parameter can be a value of
+ @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
+
+ uint32_t
+ RequestNumber; /*!< Specifies the number of DMA request that will be
+ generated after a signal event This parameter must be a
+ number between Min_Data = 1 and Max_Data = 32 */
+
+} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+ * @{
+ */
+
+/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
+ * @{
+ */
+#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
+#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
+#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
+#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
+#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
+#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
+#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
+#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
+#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
+#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
+#define HAL_DMAMUX1_SYNC_EXTI10 \
+ 10U /*!< Synchronization Signal is EXTI10 IT */
+#define HAL_DMAMUX1_SYNC_EXTI11 \
+ 11U /*!< Synchronization Signal is EXTI11 IT */
+#define HAL_DMAMUX1_SYNC_EXTI12 \
+ 12U /*!< Synchronization Signal is EXTI12 IT */
+#define HAL_DMAMUX1_SYNC_EXTI13 \
+ 13U /*!< Synchronization Signal is EXTI13 IT */
+#define HAL_DMAMUX1_SYNC_EXTI14 \
+ 14U /*!< Synchronization Signal is EXTI14 IT */
+#define HAL_DMAMUX1_SYNC_EXTI15 \
+ 15U /*!< Synchronization Signal is EXTI15 IT */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT \
+ 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT \
+ 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT \
+ 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT \
+ 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT \
+ 20U /*!< Synchronization Signal is LPTIM1 OUT */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
+ * @{
+ */
+#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
+#define HAL_DMAMUX_SYNC_RISING \
+ ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */
+#define HAL_DMAMUX_SYNC_FALLING \
+ ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */
+#define HAL_DMAMUX_SYNC_RISING_FALLING \
+ ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge \
+ events */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID
+ * selection
+ * @{
+ */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0 \
+ 0U /*!< Request generator Signal is EXTI0 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI1 \
+ 1U /*!< Request generator Signal is EXTI1 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI2 \
+ 2U /*!< Request generator Signal is EXTI2 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI3 \
+ 3U /*!< Request generator Signal is EXTI3 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI4 \
+ 4U /*!< Request generator Signal is EXTI4 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI5 \
+ 5U /*!< Request generator Signal is EXTI5 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI6 \
+ 6U /*!< Request generator Signal is EXTI6 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI7 \
+ 7U /*!< Request generator Signal is EXTI7 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI8 \
+ 8U /*!< Request generator Signal is EXTI8 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI9 \
+ 9U /*!< Request generator Signal is EXTI9 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI10 \
+ 10U /*!< Request generator Signal is EXTI10 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI11 \
+ 11U /*!< Request generator Signal is EXTI11 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI12 \
+ 12U /*!< Request generator Signal is EXTI12 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI13 \
+ 13U /*!< Request generator Signal is EXTI13 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI14 \
+ 14U /*!< Request generator Signal is EXTI14 IT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI15 \
+ 15U /*!< Request generator Signal is EXTI15 IT */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT \
+ 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT \
+ 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT \
+ 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT \
+ 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT \
+ 20U /*!< Request generator Signal is LPTIM1 OUT */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX
+ * RequestGeneneratorPolarity selection
+ * @{
+ */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT \
+ 0x00000000U /*!< block request generator events */
+#define HAL_DMAMUX_REQ_GEN_RISING \
+ DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
+#define HAL_DMAMUX_REQ_GEN_FALLING \
+ DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING \
+ DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMAEx_Exported_Functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup DMAEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* ------------------------- REQUEST -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(
+ DMA_HandleTypeDef *hdma,
+ HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+/* -------------------------------------------------------------------------- */
+
+/* ------------------------- SYNCHRO -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(
+ DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+/* -------------------------------------------------------------------------- */
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
+ * @brief DMAEx private macros
+ * @{
+ */
+
+#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) \
+ ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) \
+ (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) \
+ (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
+ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
+ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
+ ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) \
+ (((EVENT) == DISABLE) || ((EVENT) == ENABLE))
+
+#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) \
+ ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) \
+ (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) \
+ (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_HAL_DMA_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
index d3a4dc1..8608126 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
@@ -1,316 +1,316 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_EXTI_H
-#define STM32G4xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup EXTI EXTI
- * @brief EXTI HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
- * @{
- */
-typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00UL } EXTI_CallbackIDTypeDef;
-
-/**
- * @brief EXTI Handle structure definition
- */
-typedef struct {
- uint32_t Line; /*!< Exti line number */
- void (*PendingCallback)(void); /*!< Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
- * @brief EXTI Configuration structure definition
- */
-typedef struct {
- uint32_t Line; /*!< The Exti line to be configured. This parameter
- can be a value of @ref EXTI_Line */
- uint32_t Mode; /*!< The Exit Mode to be configured for a core.
- This parameter can be a combination of @ref EXTI_Mode */
- uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
- uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
- This parameter is only possible for line 0 to 15. It
- can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_Line EXTI Line
- * @{
- */
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
-#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
-#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
-#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
-#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
-#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
-#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
-#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
-#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
-#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
-#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
-#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
-/**
- * @}
- */
-
-/** @defgroup EXTI_Mode EXTI Mode
- * @{
- */
-#define EXTI_MODE_NONE 0x00000000U
-#define EXTI_MODE_INTERRUPT 0x00000001U
-#define EXTI_MODE_EVENT 0x00000002U
-/**
- * @}
- */
-
-/** @defgroup EXTI_Trigger EXTI Trigger
- * @{
- */
-#define EXTI_TRIGGER_NONE 0x00000000U
-#define EXTI_TRIGGER_RISING 0x00000001U
-#define EXTI_TRIGGER_FALLING 0x00000002U
-#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
- * @}
- */
-
-/** @defgroup EXTI_GPIOSel EXTI GPIOSel
- * @brief
- * @{
- */
-#define EXTI_GPIOA 0x00000000U
-#define EXTI_GPIOB 0x00000001U
-#define EXTI_GPIOC 0x00000002U
-#define EXTI_GPIOD 0x00000003U
-#define EXTI_GPIOE 0x00000004U
-#define EXTI_GPIOF 0x00000005U
-#define EXTI_GPIOG 0x00000006U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-/**
- * @brief EXTI Line property definition
- */
-#define EXTI_PROPERTY_SHIFT 24U
-#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
-
-/**
- * @brief EXTI Register and bit usage
- */
-#define EXTI_REG_SHIFT 16U
-#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
-#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
-#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
-#define EXTI_PIN_MASK 0x0000001FU
-
-/**
- * @brief EXTI Mask for interrupt & event mode
- */
-#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
- * @brief EXTI Mask for trigger possibilities
- */
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
- * @brief EXTI Line number
- */
-#define EXTI_LINE_NB 44UL
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
- * @{
- */
-#define IS_EXTI_LINE(__EXTI_LINE__) \
- ((((__EXTI_LINE__) & \
- ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
- ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
- (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
-
-#define IS_EXTI_MODE(__EXTI_LINE__) \
- ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
- (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__) \
- (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) \
- (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) \
- (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) || \
- ((__PORT__) == EXTI_GPIOG))
-
-#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
-
-#define IS_EXTI_PENDING_EDGE(__EDGE__) \
- (((__EDGE__) == EXTI_TRIGGER_RISING) || \
- ((__EDGE__) == EXTI_TRIGGER_FALLING) || \
- ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
-
-#define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
- * @brief EXTI Exported Functions
- * @{
- */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
- * @brief Configuration functions
- * @{
- */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti,
- EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti,
- EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti,
- EXTI_CallbackIDTypeDef CallbackID,
- void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti,
- uint32_t ExtiLine);
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_EXTI_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_EXTI_H
+#define STM32G4xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00UL } EXTI_CallbackIDTypeDef;
+
+/**
+ * @brief EXTI Handle structure definition
+ */
+typedef struct {
+ uint32_t Line; /*!< Exti line number */
+ void (*PendingCallback)(void); /*!< Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief EXTI Configuration structure definition
+ */
+typedef struct {
+ uint32_t Line; /*!< The Exti line to be configured. This parameter
+ can be a value of @ref EXTI_Line */
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.
+ This parameter can be a combination of @ref EXTI_Mode */
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
+#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
+#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
+#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
+#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
+#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
+#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
+#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
+#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
+#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
+#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
+#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
+#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
+#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
+#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
+#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
+#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
+#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
+#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
+#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
+#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
+#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
+#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
+#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
+#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
+#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
+#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
+#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
+#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
+#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
+#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
+#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
+#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
+#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
+#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
+#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
+#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
+#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
+#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
+#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
+#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
+#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
+#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
+#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_NONE 0x00000000U
+#define EXTI_MODE_INTERRUPT 0x00000001U
+#define EXTI_MODE_EVENT 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger EXTI Trigger
+ * @{
+ */
+#define EXTI_TRIGGER_NONE 0x00000000U
+#define EXTI_TRIGGER_RISING 0x00000001U
+#define EXTI_TRIGGER_FALLING 0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000U
+#define EXTI_GPIOB 0x00000001U
+#define EXTI_GPIOC 0x00000002U
+#define EXTI_GPIOD 0x00000003U
+#define EXTI_GPIOE 0x00000004U
+#define EXTI_GPIOF 0x00000005U
+#define EXTI_GPIOG 0x00000006U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24U
+#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI Register and bit usage
+ */
+#define EXTI_REG_SHIFT 16U
+#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
+#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
+#define EXTI_PIN_MASK 0x0000001FU
+
+/**
+ * @brief EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+ * @brief EXTI Line number
+ */
+#define EXTI_LINE_NB 44UL
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__EXTI_LINE__) \
+ ((((__EXTI_LINE__) & \
+ ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+
+#define IS_EXTI_MODE(__EXTI_LINE__) \
+ ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) \
+ (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) \
+ (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
+
+#define IS_EXTI_GPIO_PORT(__PORT__) \
+ (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG))
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
+
+#define IS_EXTI_PENDING_EDGE(__EDGE__) \
+ (((__EDGE__) == EXTI_TRIGGER_RISING) || \
+ ((__EDGE__) == EXTI_TRIGGER_FALLING) || \
+ ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti,
+ EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti,
+ EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti,
+ EXTI_CallbackIDTypeDef CallbackID,
+ void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti,
+ uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_EXTI_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
index aa88dfb..59b283a 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
@@ -1,1755 +1,1766 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_fdcan.h
- * @author MCD Application Team
- * @brief Header file of FDCAN HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_FDCAN_H
-#define STM32G4xx_HAL_FDCAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-#if defined(FDCAN1)
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FDCAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum {
- HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
- HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
- HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
- HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
-} HAL_FDCAN_StateTypeDef;
-
-/**
- * @brief FDCAN Init structure definition
- */
-typedef struct {
- uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider.
- The clock is common to all FDCAN instances.
- This parameter is applied only at initialisation
- of first FDCAN instance. This parameter can be a
- value of @ref FDCAN_clock_divider. */
-
- uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
- This parameter can be a value of @ref
- FDCAN_frame_format */
-
- uint32_t
- Mode; /*!< Specifies the FDCAN mode.
- This parameter can be a value of @ref FDCAN_operating_mode */
-
- FunctionalState AutoRetransmission; /*!< Enable or disable the automatic
- retransmission mode. This parameter can
- be set to ENABLE or DISABLE */
-
- FunctionalState
- TransmitPause; /*!< Enable or disable the Transmit Pause feature.
- This parameter can be set to ENABLE or DISABLE */
-
- FunctionalState
- ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator
- frequency is divided for generating the nominal
- bit time quanta. This parameter must be a number
- between 1 and 512 */
-
- uint32_t
- NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the
- FDCAN hardware is allowed to lengthen or shorten
- a bit to perform resynchronization. This
- parameter must be a number between 1 and 128 */
-
- uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit
- Segment 1. This parameter must be a number
- between 2 and 256 */
-
- uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit
- Segment 2. This parameter must be a number
- between 2 and 128 */
-
- uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator
- frequency is divided for generating the data bit
- time quanta. This parameter must be a number
- between 1 and 32 */
-
- uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta
- the FDCAN hardware is allowed to lengthen or
- shorten a data bit to perform
- resynchronization. This parameter must be a
- number between 1 and 16 */
-
- uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit
- Segment 1. This parameter must be a number between 1
- and 32 */
-
- uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit
- Segment 2. This parameter must be a number between 1
- and 16 */
-
- uint32_t
- StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
- This parameter must be a number between 0 and 28 */
-
- uint32_t
- ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
- This parameter must be a number between 0 and 8 */
-
- uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
- This parameter can be a value of @ref
- FDCAN_txFifoQueue_Mode */
-
-} FDCAN_InitTypeDef;
-
-/**
- * @brief FDCAN filter structure definition
- */
-typedef struct {
- uint32_t IdType; /*!< Specifies the identifier type.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between:
- - 0 and (SRAMCAN_FLS_NBR-1), if IdType is
- FDCAN_STANDARD_ID
- - 0 and (SRAMCAN_FLE_NBR-1), if IdType is
- FDCAN_EXTENDED_ID */
-
- uint32_t
- FilterType; /*!< Specifies the filter type.
- This parameter can be a value of @ref FDCAN_filter_type.
- The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
- only when IdType is FDCAN_EXTENDED_ID. */
-
- uint32_t FilterConfig; /*!< Specifies the filter configuration.
- This parameter can be a value of @ref
- FDCAN_filter_config */
-
- uint32_t
- FilterID1; /*!< Specifies the filter identification 1.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t
- FilterID2; /*!< Specifies the filter identification 2.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
-} FDCAN_FilterTypeDef;
-
-/**
- * @brief FDCAN Tx header structure definition
- */
-typedef struct {
- uint32_t
- Identifier; /*!< Specifies the identifier.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t
- IdType; /*!< Specifies the identifier type for the message that will be
- transmitted.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t TxFrameType; /*!< Specifies the frame type of the message that will
- be transmitted. This parameter can be a value of @ref
- FDCAN_frame_type */
-
- uint32_t DataLength; /*!< Specifies the length of the frame that will be
- transmitted. This parameter can be a value of @ref
- FDCAN_data_length_code */
-
- uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
- This parameter can be a value of @ref
- FDCAN_error_state_indicator */
-
- uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be
- transmitted with or without bit rate switching.
- This parameter can be a value of @ref
- FDCAN_bit_rate_switching */
-
- uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in
- classic or FD format. This parameter can be a value of
- @ref FDCAN_format */
-
- uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
- This parameter can be a value of @ref
- FDCAN_EFC */
-
- uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx
- Event FIFO element for identification of Tx message
- status. This parameter must be a number between 0
- and 0xFF */
-
-} FDCAN_TxHeaderTypeDef;
-
-/**
- * @brief FDCAN Rx header structure definition
- */
-typedef struct {
- uint32_t
- Identifier; /*!< Specifies the identifier.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t IdType; /*!< Specifies the identifier type of the received message.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t RxFrameType; /*!< Specifies the the received message frame type.
- This parameter can be a value of @ref
- FDCAN_frame_type */
-
- uint32_t DataLength; /*!< Specifies the received frame length.
- This parameter can be a value of @ref
- FDCAN_data_length_code */
-
- uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
- This parameter can be a value of @ref
- FDCAN_error_state_indicator */
-
- uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with
- or without bit rate switching. This parameter can
- be a value of @ref FDCAN_bit_rate_switching */
-
- uint32_t
- FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
- format.
- This parameter can be a value of @ref FDCAN_format */
-
- uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on
- start of frame reception. This parameter must be a
- number between 0 and 0xFFFF */
-
- uint32_t
- FilterIndex; /*!< Specifies the index of matching Rx acceptance filter
- element. This parameter must be a number between:
- - 0 and (SRAMCAN_FLS_NBR-1), if IdType is
- FDCAN_STANDARD_ID
- - 0 and (SRAMCAN_FLE_NBR-1), if IdType is
- FDCAN_EXTENDED_ID */
-
- uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did
- not match any Rx filter. Acceptance of
- non-matching frames may be enabled via
- HAL_FDCAN_ConfigGlobalFilter().
- This parameter can be 0 or 1 */
-
-} FDCAN_RxHeaderTypeDef;
-
-/**
- * @brief FDCAN Tx event FIFO structure definition
- */
-typedef struct {
- uint32_t
- Identifier; /*!< Specifies the identifier.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t
- IdType; /*!< Specifies the identifier type for the transmitted message.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted
- message. This parameter can be a value of @ref
- FDCAN_frame_type */
-
- uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
- This parameter can be a value of @ref
- FDCAN_data_length_code */
-
- uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
- This parameter can be a value of @ref
- FDCAN_error_state_indicator */
-
- uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted
- with or without bit rate switching. This parameter
- can be a value of @ref FDCAN_bit_rate_switching */
-
- uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in
- classic or FD format. This parameter can be a value of
- @ref FDCAN_format */
-
- uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on
- start of frame transmission. This parameter must be a
- number between 0 and 0xFFFF */
-
- uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event
- FIFO element for identification of Tx message
- status. This parameter must be a number between 0
- and 0xFF */
-
- uint32_t
- EventType; /*!< Specifies the event type.
- This parameter can be a value of @ref FDCAN_event_type */
-
-} FDCAN_TxEventFifoTypeDef;
-
-/**
- * @brief FDCAN High Priority Message Status structure definition
- */
-typedef struct {
- uint32_t FilterList; /*!< Specifies the filter list of the matching filter
- element. This parameter can be:
- - 0 : Standard Filter List
- - 1 : Extended Filter List */
-
- uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
- This parameter can be a number between:
- - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0
- (Standard)
- - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1
- (Extended) */
-
- uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
- This parameter can be a value of @ref
- FDCAN_hp_msg_storage */
-
- uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which
- the message was stored. This parameter is valid only
- when MessageStorage is: FDCAN_HP_STORAGE_RXFIFO0 or
- FDCAN_HP_STORAGE_RXFIFO1 */
-
-} FDCAN_HpMsgStatusTypeDef;
-
-/**
- * @brief FDCAN Protocol Status structure definition
- */
-typedef struct {
- uint32_t LastErrorCode; /*!< Specifies the type of the last error that
- occurred on the FDCAN bus. This parameter can be a
- value of @ref FDCAN_protocol_error_code */
-
- uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that
- occurred in the data phase of a CAN FD format
- frame with its BRS flag set. This parameter can
- be a value of @ref FDCAN_protocol_error_code */
-
- uint32_t Activity; /*!< Specifies the FDCAN module communication state.
- This parameter can be a value of @ref
- FDCAN_communication_state */
-
- uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
- This parameter can be:
- - 0 : The FDCAN is in Error_Active state
- - 1 : The FDCAN is in Error_Passive state */
-
- uint32_t Warning; /*!< Specifies the FDCAN module warning status.
- This parameter can be:
- - 0 : error counters (RxErrorCnt and TxErrorCnt)
- are below the Error_Warning limit of 96
- - 1 : at least one of error counters has reached the
- Error_Warning limit of 96 */
-
- uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
- This parameter can be:
- - 0 : The FDCAN is not in Bus_Off state
- - 1 : The FDCAN is in Bus_Off state */
-
- uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
- This parameter can be:
- - 0 : Last received CAN FD message did not have its
- ESI flag set
- - 1 : Last received CAN FD message had its ESI flag
- set */
-
- uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
- This parameter can be:
- - 0 : Last received CAN FD message did not have its
- BRS flag set
- - 1 : Last received CAN FD message had its BRS flag
- set */
-
- uint32_t
- RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been
- received since last protocol status.This parameter can be:
- - 0 : No CAN FD message received
- - 1 : CAN FD message received */
-
- uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception
- status. This parameter can be:
- - 0 : No protocol exception event occurred
- since last read access
- - 1 : Protocol exception event occurred */
-
- uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
- This parameter can be a number between 0 and 127 */
-
-} FDCAN_ProtocolStatusTypeDef;
-
-/**
- * @brief FDCAN Error Counters structure definition
- */
-typedef struct {
- uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
- This parameter can be a number between 0 and 255 */
-
- uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
- This parameter can be a number between 0 and 127 */
-
- uint32_t
- RxErrorPassive; /*!< Specifies the Receive Error Passive status.
- This parameter can be:
- - 0 : The Receive Error Counter (RxErrorCnt) is
- below the error passive level of 128
- - 1 : The Receive Error Counter (RxErrorCnt)
- has reached the error passive level of 128 */
-
- uint32_t
- ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter
- value. This parameter can be a number between 0 and 255.
- This counter is incremented each time when a FDCAN
- protocol error causes the TxErrorCnt or the RxErrorCnt to
- be incremented. The counter stops at 255; the next
- increment of TxErrorCnt or RxErrorCnt sets interrupt flag
- FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
-
-} FDCAN_ErrorCountersTypeDef;
-
-/**
- * @brief FDCAN Message RAM blocks
- */
-typedef struct {
- uint32_t
- StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t
- ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
- This parameter must be a 32-bit word address */
-
-} FDCAN_MsgRamAddressTypeDef;
-
-/**
- * @brief FDCAN handle structure definition
- */
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-typedef struct __FDCAN_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-{
- FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
-
- FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
-
- FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
-
- uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
- of latest Tx FIFO/Queue request */
-
- __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
-
- HAL_LockTypeDef Lock; /*!< FDCAN locking object */
-
- __IO uint32_t ErrorCode; /*!< FDCAN Error code */
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- void (*TxEventFifoCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan,
- uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */
- void (*RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */
- void (*RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */
- void (*TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef
- *hfdcan); /*!< FDCAN Tx Fifo Empty callback */
- void (*TxBufferCompleteCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
- void (*TxBufferAbortCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */
- void (*HighPriorityMessageCallback)(
- struct __FDCAN_HandleTypeDef
- *hfdcan); /*!< FDCAN High priority message callback */
- void (*TimestampWraparoundCallback)(
- struct __FDCAN_HandleTypeDef
- *hfdcan); /*!< FDCAN Timestamp wraparound callback */
- void (*TimeoutOccurredCallback)(
- struct __FDCAN_HandleTypeDef
- *hfdcan); /*!< FDCAN Timeout occurred callback */
- void (*ErrorCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */
- void (*ErrorStatusCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan,
- uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */
-
- void (*MspInitCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */
- void (*MspDeInitCallback)(
- struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */
-
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-
-} FDCAN_HandleTypeDef;
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-/**
- * @brief HAL FDCAN common Callback ID enumeration definition
- */
-typedef enum {
- HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
- HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID =
- 0x01U, /*!< FDCAN High priority message callback ID */
- HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID =
- 0x02U, /*!< FDCAN Timestamp wraparound callback ID */
- HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID =
- 0x03U, /*!< FDCAN Timeout occurred callback ID */
- HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */
-
- HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */
- HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */
-
-} HAL_FDCAN_CallbackIDTypeDef;
-
-/**
- * @brief HAL FDCAN Callback pointer definition
- */
-typedef void (*pFDCAN_CallbackTypeDef)(
- FDCAN_HandleTypeDef
- *hfdcan); /*!< pointer to a common FDCAN callback function */
-typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(
- FDCAN_HandleTypeDef *hfdcan,
- uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback
- function */
-typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(
- FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */
-typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(
- FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */
-typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(
- FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback
- function */
-typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(
- FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback
- function */
-typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(
- FDCAN_HandleTypeDef *hfdcan,
- uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */
-
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
- * @{
- */
-
-/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
- * @{
- */
-#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_FDCAN_ERROR_NOT_INITIALIZED \
- ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
-#define HAL_FDCAN_ERROR_NOT_READY \
- ((uint32_t)0x00000004U) /*!< Peripheral not ready */
-#define HAL_FDCAN_ERROR_NOT_STARTED \
- ((uint32_t)0x00000008U) /*!< Peripheral not started */
-#define HAL_FDCAN_ERROR_NOT_SUPPORTED \
- ((uint32_t)0x00000010U) /*!< Mode not supported */
-#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
-#define HAL_FDCAN_ERROR_PENDING \
- ((uint32_t)0x00000040U) /*!< Pending operation */
-#define HAL_FDCAN_ERROR_RAM_ACCESS \
- ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
-#define HAL_FDCAN_ERROR_FIFO_EMPTY \
- ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
-#define HAL_FDCAN_ERROR_FIFO_FULL \
- ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
-#define HAL_FDCAN_ERROR_LOG_OVERFLOW \
- FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
-#define HAL_FDCAN_ERROR_RAM_WDG \
- FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
-#define HAL_FDCAN_ERROR_PROTOCOL_ARBT \
- FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is \
- used) */
-#define HAL_FDCAN_ERROR_PROTOCOL_DATA \
- FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
-#define HAL_FDCAN_ERROR_RESERVED_AREA \
- FDCAN_IR_ARA /*!< Access to Reserved Address */
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-#define HAL_FDCAN_ERROR_INVALID_CALLBACK \
- ((uint32_t)0x00000100U) /*!< Invalid Callback error */
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_frame_format FDCAN Frame Format
- * @{
- */
-#define FDCAN_FRAME_CLASSIC \
- ((uint32_t)0x00000000U) /*!< Classic mode */
-#define FDCAN_FRAME_FD_NO_BRS \
- ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
-#define FDCAN_FRAME_FD_BRS \
- ((uint32_t)(FDCAN_CCCR_FDOE | \
- FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
- * @{
- */
-#define FDCAN_MODE_NORMAL \
- ((uint32_t)0x00000000U) /*!< Normal mode */
-#define FDCAN_MODE_RESTRICTED_OPERATION \
- ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
-#define FDCAN_MODE_BUS_MONITORING \
- ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
-#define FDCAN_MODE_INTERNAL_LOOPBACK \
- ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
-#define FDCAN_MODE_EXTERNAL_LOOPBACK \
- ((uint32_t)0x00000004U) /*!< External LoopBack mode */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
- * @{
- */
-#define FDCAN_CLOCK_DIV1 \
- ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
-#define FDCAN_CLOCK_DIV2 \
- ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
-#define FDCAN_CLOCK_DIV4 \
- ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
-#define FDCAN_CLOCK_DIV6 \
- ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
-#define FDCAN_CLOCK_DIV8 \
- ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
-#define FDCAN_CLOCK_DIV10 \
- ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
-#define FDCAN_CLOCK_DIV12 \
- ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
-#define FDCAN_CLOCK_DIV14 \
- ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
-#define FDCAN_CLOCK_DIV16 \
- ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
-#define FDCAN_CLOCK_DIV18 \
- ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
-#define FDCAN_CLOCK_DIV20 \
- ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
-#define FDCAN_CLOCK_DIV22 \
- ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
-#define FDCAN_CLOCK_DIV24 \
- ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
-#define FDCAN_CLOCK_DIV26 \
- ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
-#define FDCAN_CLOCK_DIV28 \
- ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
-#define FDCAN_CLOCK_DIV30 \
- ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
- * @{
- */
-#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
-#define FDCAN_TX_QUEUE_OPERATION \
- ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode \
- */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_id_type FDCAN ID Type
- * @{
- */
-#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
-#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_frame_type FDCAN Frame Type
- * @{
- */
-#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
-#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
- * @{
- */
-#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
-#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
-#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
-#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
-#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
-#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
-#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
-#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
-#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
-#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
-#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
-#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
-#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
-#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
-#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
-#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
- * @{
- */
-#define FDCAN_ESI_ACTIVE \
- ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
-#define FDCAN_ESI_PASSIVE \
- ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
- * @{
- */
-#define FDCAN_BRS_OFF \
- ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit \
- rate switching */
-#define FDCAN_BRS_ON \
- ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate \
- switching */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_format FDCAN format
- * @{
- */
-#define FDCAN_CLASSIC_CAN \
- ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN \
- format */
-#define FDCAN_FD_CAN \
- ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_EFC FDCAN Event FIFO control
- * @{
- */
-#define FDCAN_NO_TX_EVENTS \
- ((uint32_t)0x00000000U) /*!< Do not store Tx events */
-#define FDCAN_STORE_TX_EVENTS \
- ((uint32_t)0x00800000U) /*!< Store Tx events */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_filter_type FDCAN Filter Type
- * @{
- */
-#define FDCAN_FILTER_RANGE \
- ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
-#define FDCAN_FILTER_DUAL \
- ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
-#define FDCAN_FILTER_MASK \
- ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = \
- mask */
-#define FDCAN_FILTER_RANGE_NO_EIDM \
- ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM \
- mask not applied */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
- * @{
- */
-#define FDCAN_FILTER_DISABLE \
- ((uint32_t)0x00000000U) /*!< Disable filter element */
-#define FDCAN_FILTER_TO_RXFIFO0 \
- ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
-#define FDCAN_FILTER_TO_RXFIFO1 \
- ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
-#define FDCAN_FILTER_REJECT \
- ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
-#define FDCAN_FILTER_HP \
- ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
-#define FDCAN_FILTER_TO_RXFIFO0_HP \
- ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter \
- matches */
-#define FDCAN_FILTER_TO_RXFIFO1_HP \
- ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter \
- matches */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Tx_location FDCAN Tx Location
- * @{
- */
-#define FDCAN_TX_BUFFER0 \
- ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
-#define FDCAN_TX_BUFFER1 \
- ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
-#define FDCAN_TX_BUFFER2 \
- ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_location FDCAN Rx Location
- * @{
- */
-#define FDCAN_RX_FIFO0 \
- ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
-#define FDCAN_RX_FIFO1 \
- ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_event_type FDCAN Event Type
- * @{
- */
-#define FDCAN_TX_EVENT \
- ((uint32_t)0x00400000U) /*!< Tx event */
-#define FDCAN_TX_IN_SPITE_OF_ABORT \
- ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
- * @{
- */
-#define FDCAN_HP_STORAGE_NO_FIFO \
- ((uint32_t)0x00000000U) /*!< No FIFO selected */
-#define FDCAN_HP_STORAGE_MSG_LOST \
- ((uint32_t)0x00000040U) /*!< FIFO message lost */
-#define FDCAN_HP_STORAGE_RXFIFO0 \
- ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
-#define FDCAN_HP_STORAGE_RXFIFO1 \
- ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
- * @{
- */
-#define FDCAN_PROTOCOL_ERROR_NONE \
- ((uint32_t)0x00000000U) /*!< No error occurred */
-#define FDCAN_PROTOCOL_ERROR_STUFF \
- ((uint32_t)0x00000001U) /*!< Stuff error */
-#define FDCAN_PROTOCOL_ERROR_FORM \
- ((uint32_t)0x00000002U) /*!< Form error */
-#define FDCAN_PROTOCOL_ERROR_ACK \
- ((uint32_t)0x00000003U) /*!< Acknowledge error */
-#define FDCAN_PROTOCOL_ERROR_BIT1 \
- ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
-#define FDCAN_PROTOCOL_ERROR_BIT0 \
- ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
-#define FDCAN_PROTOCOL_ERROR_CRC \
- ((uint32_t)0x00000006U) /*!< CRC check sum error */
-#define FDCAN_PROTOCOL_ERROR_NO_CHANGE \
- ((uint32_t)0x00000007U) /*!< No change since last read */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_communication_state FDCAN communication state
- * @{
- */
-#define FDCAN_COM_STATE_SYNC \
- ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
-#define FDCAN_COM_STATE_IDLE \
- ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
-#define FDCAN_COM_STATE_RX \
- ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
-#define FDCAN_COM_STATE_TX \
- ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
- * @{
- */
-#define FDCAN_RX_FIFO_BLOCKING \
- ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
-#define FDCAN_RX_FIFO_OVERWRITE \
- ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
- * @{
- */
-#define FDCAN_ACCEPT_IN_RX_FIFO0 \
- ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
-#define FDCAN_ACCEPT_IN_RX_FIFO1 \
- ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
-#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
- * @{
- */
-#define FDCAN_FILTER_REMOTE \
- ((uint32_t)0x00000000U) /*!< Filter remote frames \
- */
-#define FDCAN_REJECT_REMOTE \
- ((uint32_t)0x00000001U) /*!< Reject all remote frames */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
- * @{
- */
-#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
-#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Timestamp FDCAN timestamp
- * @{
- */
-#define FDCAN_TIMESTAMP_INTERNAL \
- ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according \
- to TCP */
-#define FDCAN_TIMESTAMP_EXTERNAL \
- ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
- * @{
- */
-#define FDCAN_TIMESTAMP_PRESC_1 \
- ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time */
-#define FDCAN_TIMESTAMP_PRESC_2 \
- ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 2 */
-#define FDCAN_TIMESTAMP_PRESC_3 \
- ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 3 */
-#define FDCAN_TIMESTAMP_PRESC_4 \
- ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 4 */
-#define FDCAN_TIMESTAMP_PRESC_5 \
- ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 5 */
-#define FDCAN_TIMESTAMP_PRESC_6 \
- ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 6 */
-#define FDCAN_TIMESTAMP_PRESC_7 \
- ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 7 */
-#define FDCAN_TIMESTAMP_PRESC_8 \
- ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 8 */
-#define FDCAN_TIMESTAMP_PRESC_9 \
- ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 9 */
-#define FDCAN_TIMESTAMP_PRESC_10 \
- ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 10 */
-#define FDCAN_TIMESTAMP_PRESC_11 \
- ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 11 */
-#define FDCAN_TIMESTAMP_PRESC_12 \
- ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 12 */
-#define FDCAN_TIMESTAMP_PRESC_13 \
- ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 13 */
-#define FDCAN_TIMESTAMP_PRESC_14 \
- ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 14 */
-#define FDCAN_TIMESTAMP_PRESC_15 \
- ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 15 */
-#define FDCAN_TIMESTAMP_PRESC_16 \
- ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit \
- time multiplied by 16 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
- * @{
- */
-#define FDCAN_TIMEOUT_CONTINUOUS \
- ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
-#define FDCAN_TIMEOUT_TX_EVENT_FIFO \
- ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
-#define FDCAN_TIMEOUT_RX_FIFO0 \
- ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
-#define FDCAN_TIMEOUT_RX_FIFO1 \
- ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup Interrupt_Masks Interrupt masks
- * @{
- */
-#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
-#define FDCAN_ILS_MASK \
- ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_flags FDCAN Flags
- * @{
- */
-#define FDCAN_FLAG_TX_COMPLETE \
- FDCAN_IR_TC /*!< Transmission Completed */
-#define FDCAN_FLAG_TX_ABORT_COMPLETE \
- FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
-#define FDCAN_FLAG_TX_FIFO_EMPTY \
- FDCAN_IR_TFE /*!< Tx FIFO Empty */
-#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG \
- FDCAN_IR_HPM /*!< High priority message received */
-#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST \
- FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
-#define FDCAN_FLAG_TX_EVT_FIFO_FULL \
- FDCAN_IR_TEFF /*!< Tx Event FIFO full */
-#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA \
- FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
-#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST \
- FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
-#define FDCAN_FLAG_RX_FIFO0_FULL \
- FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
-#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE \
- FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
-#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST \
- FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
-#define FDCAN_FLAG_RX_FIFO1_FULL \
- FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
-#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE \
- FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
-#define FDCAN_FLAG_RAM_ACCESS_FAILURE \
- FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
-#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW \
- FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
-#define FDCAN_FLAG_ERROR_PASSIVE \
- FDCAN_IR_EP /*!< Error_Passive status changed */
-#define FDCAN_FLAG_ERROR_WARNING \
- FDCAN_IR_EW /*!< Error_Warning status changed */
-#define FDCAN_FLAG_BUS_OFF \
- FDCAN_IR_BO /*!< Bus_Off status changed */
-#define FDCAN_FLAG_RAM_WATCHDOG \
- FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
-#define FDCAN_FLAG_ARB_PROTOCOL_ERROR \
- FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
-#define FDCAN_FLAG_DATA_PROTOCOL_ERROR \
- FDCAN_IR_PED /*!< Protocol error in data phase detected */
-#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS \
- FDCAN_IR_ARA /*!< Access to reserved address occurred */
-#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND \
- FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
-#define FDCAN_FLAG_TIMEOUT_OCCURRED \
- FDCAN_IR_TOO /*!< Timeout reached */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Interrupts FDCAN Interrupts
- * @{
- */
-
-/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
- * @{
- */
-#define FDCAN_IT_TX_COMPLETE \
- FDCAN_IE_TCE /*!< Transmission Completed */
-#define FDCAN_IT_TX_ABORT_COMPLETE \
- FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
-#define FDCAN_IT_TX_FIFO_EMPTY \
- FDCAN_IE_TFEE /*!< Tx FIFO Empty */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
- * @{
- */
-#define FDCAN_IT_RX_HIGH_PRIORITY_MSG \
- FDCAN_IE_HPME /*!< High priority message received */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
- * @{
- */
-#define FDCAN_IT_TIMESTAMP_WRAPAROUND \
- FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
-#define FDCAN_IT_TIMEOUT_OCCURRED \
- FDCAN_IE_TOOE /*!< Timeout reached */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
- * @{
- */
-#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST \
- FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
-#define FDCAN_IT_TX_EVT_FIFO_FULL \
- FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
-#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA \
- FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
- * @{
- */
-#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST \
- FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
-#define FDCAN_IT_RX_FIFO0_FULL \
- FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
-#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE \
- FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
- * @{
- */
-#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST \
- FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
-#define FDCAN_IT_RX_FIFO1_FULL \
- FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
-#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE \
- FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
- * @{
- */
-#define FDCAN_IT_RAM_ACCESS_FAILURE \
- FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
-#define FDCAN_IT_ERROR_LOGGING_OVERFLOW \
- FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
-#define FDCAN_IT_RAM_WATCHDOG \
- FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
-#define FDCAN_IT_ARB_PROTOCOL_ERROR \
- FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
-#define FDCAN_IT_DATA_PROTOCOL_ERROR \
- FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
-#define FDCAN_IT_RESERVED_ADDRESS_ACCESS \
- FDCAN_IE_ARAE /*!< Access to reserved address occurred */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
- * @{
- */
-#define FDCAN_IT_ERROR_PASSIVE \
- FDCAN_IE_EPE /*!< Error_Passive status changed */
-#define FDCAN_IT_ERROR_WARNING \
- FDCAN_IE_EWE /*!< Error_Warning status changed */
-#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
- * @{
- */
-#define FDCAN_IT_LIST_RX_FIFO0 \
- (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | FDCAN_IT_RX_FIFO0_FULL | \
- FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */
-#define FDCAN_IT_LIST_RX_FIFO1 \
- (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | FDCAN_IT_RX_FIFO1_FULL | \
- FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */
-#define FDCAN_IT_LIST_SMSG \
- (FDCAN_IT_TX_ABORT_COMPLETE | FDCAN_IT_TX_COMPLETE | \
- FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */
-#define FDCAN_IT_LIST_TX_FIFO_ERROR \
- (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | FDCAN_IT_TX_EVT_FIFO_FULL | \
- FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
- FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */
-#define FDCAN_IT_LIST_MISC \
- (FDCAN_IT_TIMEOUT_OCCURRED | FDCAN_IT_RAM_ACCESS_FAILURE | \
- FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */
-#define FDCAN_IT_LIST_BIT_LINE_ERROR \
- (FDCAN_IT_ERROR_PASSIVE | \
- FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */
-#define FDCAN_IT_LIST_PROTOCOL_ERROR \
- (FDCAN_IT_RESERVED_ADDRESS_ACCESS | FDCAN_IT_DATA_PROTOCOL_ERROR | \
- FDCAN_IT_ARB_PROTOCOL_ERROR | FDCAN_IT_RAM_WATCHDOG | FDCAN_IT_BUS_OFF | \
- FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
- * @{
- */
-#define FDCAN_IT_GROUP_RX_FIFO0 \
- FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: \
- RF0LL: Rx FIFO 0 Message Lost \
- RF0FL: Rx FIFO 0 is Full \
- RF0NL: Rx FIFO 0 Has New Message */
-#define FDCAN_IT_GROUP_RX_FIFO1 \
- FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: \
- RF1LL: Rx FIFO 1 Message Lost \
- RF1FL: Rx FIFO 1 is Full \
- RF1NL: Rx FIFO 1 Has New Message */
-#define FDCAN_IT_GROUP_SMSG \
- FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: \
- TCFL: Transmission Cancellation Finished \
- TCL: Transmission Completed \
- HPML: High Priority Message */
-#define FDCAN_IT_GROUP_TX_FIFO_ERROR \
- FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: \
- TEFLL: Tx Event FIFO Element Lost \
- TEFFL: Tx Event FIFO Full \
- TEFNL: Tx Event FIFO New Entry \
- TFEL: Tx FIFO Empty Interrupt Line */
-#define FDCAN_IT_GROUP_MISC \
- FDCAN_ILS_MISC /*!< Misc. Interrupts Group: \
- TOOL: Timeout Occurred \
- MRAFL: Message RAM Access Failure \
- TSWL: Timestamp Wraparound */
-#define FDCAN_IT_GROUP_BIT_LINE_ERROR \
- FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: \
- EPL: Error Passive \
- ELOL: Error Logging Overflow */
-#define FDCAN_IT_GROUP_PROTOCOL_ERROR \
- FDCAN_ILS_PERR /*!< Protocol Error Group: \
- ARAL: Access to Reserved Address Line \
- PEDL: Protocol Error in Data Phase Line \
- PEAL: Protocol Error in Arbitration Phase Line \
- WDIL: Watchdog Interrupt Line \
- BOL: Bus_Off Status \
- EWL: Warning Status */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
- * @{
- */
-
-/** @brief Reset FDCAN handle state.
- * @param __HANDLE__ FDCAN handle.
- * @retval None
- */
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while (0)
-#else
-#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the specified FDCAN interrupts.
- * @param __HANDLE__ FDCAN handle.
- * @param __INTERRUPT__ FDCAN interrupt.
- * This parameter can be any combination of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
-
-/**
- * @brief Disable the specified FDCAN interrupts.
- * @param __HANDLE__ FDCAN handle.
- * @param __INTERRUPT__ FDCAN interrupt.
- * This parameter can be any combination of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
-
-/**
- * @brief Check whether the specified FDCAN interrupt is set or not.
- * @param __HANDLE__ FDCAN handle.
- * @param __INTERRUPT__ FDCAN interrupt.
- * This parameter can be one of @arg FDCAN_Interrupts
- * @retval ITStatus
- */
-#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
-
-/**
- * @brief Clear the specified FDCAN interrupts.
- * @param __HANDLE__ FDCAN handle.
- * @param __INTERRUPT__ specifies the interrupts to clear.
- * This parameter can be any combination of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
-
-/**
- * @brief Check whether the specified FDCAN flag is set or not.
- * @param __HANDLE__ FDCAN handle.
- * @param __FLAG__ FDCAN flag.
- * This parameter can be one of @arg FDCAN_flags
- * @retval FlagStatus
- */
-#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) \
- ((__HANDLE__)->Instance->IR & (__FLAG__))
-
-/**
- * @brief Clear the specified FDCAN flags.
- * @param __HANDLE__ FDCAN handle.
- * @param __FLAG__ specifies the flags to clear.
- * This parameter can be any combination of @arg FDCAN_flags
- * @retval None
- */
-#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- ((__HANDLE__)->Instance->IR) = (__FLAG__)
-
-/** @brief Check if the specified FDCAN interrupt source is enabled or
- * disabled.
- * @param __HANDLE__ FDCAN handle.
- * @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
- * This parameter can be a value of @arg FDCAN_Interrupts
- * @retval ITStatus
- */
-#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FDCAN_Exported_Functions
- * @{
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(
- FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
- pFDCAN_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(
- FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(
- FDCAN_HandleTypeDef *hfdcan,
- pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(
- FDCAN_HandleTypeDef *hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group2
- * @{
- */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan,
- FDCAN_FilterTypeDef *sFilterConfig);
-HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t NonMatchingStd,
- uint32_t NonMatchingExt,
- uint32_t RejectRemoteStd,
- uint32_t RejectRemoteExt);
-HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan,
- uint32_t Mask);
-HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo,
- uint32_t OperationMode);
-HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan,
- uint32_t CounterStartValue);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TimestampPrescaler);
-HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TimestampOperation);
-HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(
- FDCAN_HandleTypeDef *hfdcan);
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TimeoutOperation,
- uint32_t TimeoutPeriod);
-HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(
- FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
-HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(
- FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group3
- * @{
- */
-/* Control functions **********************************************************/
-HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
- uint8_t *pTxData);
-uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndex);
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxLocation,
- FDCAN_RxHeaderTypeDef *pRxHeader,
- uint8_t *pRxData);
-HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan,
- FDCAN_TxEventFifoTypeDef *pTxEvent);
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TxBufferIndex);
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo);
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(
- FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group4
- * @{
- */
-/* Interrupts management ******************************************************/
-HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan,
- uint32_t ITList,
- uint32_t InterruptLine);
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan,
- uint32_t ActiveITs,
- uint32_t BufferIndexes);
-HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan,
- uint32_t InactiveITs);
-void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group5
- * @{
- */
-/* Callback functions *********************************************************/
-void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TxEventFifoITs);
-void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo0ITs);
-void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo1ITs);
-void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes);
-void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes);
-void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t ErrorStatusITs);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group6
- * @{
- */
-/* Peripheral State functions *************************************************/
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
- * @{
- */
-#define IS_FDCAN_FRAME_FORMAT(FORMAT) \
- (((FORMAT) == FDCAN_FRAME_CLASSIC) || ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
- ((FORMAT) == FDCAN_FRAME_FD_BRS))
-#define IS_FDCAN_MODE(MODE) \
- (((MODE) == FDCAN_MODE_NORMAL) || \
- ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
- ((MODE) == FDCAN_MODE_BUS_MONITORING) || \
- ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK) || \
- ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK))
-#define IS_FDCAN_CKDIV(CKDIV) \
- (((CKDIV) == FDCAN_CLOCK_DIV1) || ((CKDIV) == FDCAN_CLOCK_DIV2) || \
- ((CKDIV) == FDCAN_CLOCK_DIV4) || ((CKDIV) == FDCAN_CLOCK_DIV6) || \
- ((CKDIV) == FDCAN_CLOCK_DIV8) || ((CKDIV) == FDCAN_CLOCK_DIV10) || \
- ((CKDIV) == FDCAN_CLOCK_DIV12) || ((CKDIV) == FDCAN_CLOCK_DIV14) || \
- ((CKDIV) == FDCAN_CLOCK_DIV16) || ((CKDIV) == FDCAN_CLOCK_DIV18) || \
- ((CKDIV) == FDCAN_CLOCK_DIV20) || ((CKDIV) == FDCAN_CLOCK_DIV22) || \
- ((CKDIV) == FDCAN_CLOCK_DIV24) || ((CKDIV) == FDCAN_CLOCK_DIV26) || \
- ((CKDIV) == FDCAN_CLOCK_DIV28) || ((CKDIV) == FDCAN_CLOCK_DIV30))
-#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) \
- (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
-#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
-#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
-#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
-#define IS_FDCAN_DATA_PRESCALER(PRESCALER) \
- (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
-#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
-#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
-#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
-#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
-#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
-#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) \
- (((MODE) == FDCAN_TX_FIFO_OPERATION) || ((MODE) == FDCAN_TX_QUEUE_OPERATION))
-#define IS_FDCAN_ID_TYPE(ID_TYPE) \
- (((ID_TYPE) == FDCAN_STANDARD_ID) || ((ID_TYPE) == FDCAN_EXTENDED_ID))
-#define IS_FDCAN_FILTER_CFG(CONFIG) \
- (((CONFIG) == FDCAN_FILTER_DISABLE) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1) || \
- ((CONFIG) == FDCAN_FILTER_REJECT) || ((CONFIG) == FDCAN_FILTER_HP) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
-#define IS_FDCAN_TX_LOCATION(LOCATION) \
- (((LOCATION) == FDCAN_TX_BUFFER0) || ((LOCATION) == FDCAN_TX_BUFFER1) || \
- ((LOCATION) == FDCAN_TX_BUFFER2))
-#define IS_FDCAN_TX_LOCATION_LIST(LOCATION) \
- (((LOCATION) >= FDCAN_TX_BUFFER0) && \
- ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
-#define IS_FDCAN_RX_FIFO(FIFO) \
- (((FIFO) == FDCAN_RX_FIFO0) || ((FIFO) == FDCAN_RX_FIFO1))
-#define IS_FDCAN_RX_FIFO_MODE(MODE) \
- (((MODE) == FDCAN_RX_FIFO_BLOCKING) || ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
-#define IS_FDCAN_STD_FILTER_TYPE(TYPE) \
- (((TYPE) == FDCAN_FILTER_RANGE) || ((TYPE) == FDCAN_FILTER_DUAL) || \
- ((TYPE) == FDCAN_FILTER_MASK))
-#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) \
- (((TYPE) == FDCAN_FILTER_RANGE) || ((TYPE) == FDCAN_FILTER_DUAL) || \
- ((TYPE) == FDCAN_FILTER_MASK) || ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
-#define IS_FDCAN_FRAME_TYPE(TYPE) \
- (((TYPE) == FDCAN_DATA_FRAME) || ((TYPE) == FDCAN_REMOTE_FRAME))
-#define IS_FDCAN_DLC(DLC) \
- (((DLC) == FDCAN_DLC_BYTES_0) || ((DLC) == FDCAN_DLC_BYTES_1) || \
- ((DLC) == FDCAN_DLC_BYTES_2) || ((DLC) == FDCAN_DLC_BYTES_3) || \
- ((DLC) == FDCAN_DLC_BYTES_4) || ((DLC) == FDCAN_DLC_BYTES_5) || \
- ((DLC) == FDCAN_DLC_BYTES_6) || ((DLC) == FDCAN_DLC_BYTES_7) || \
- ((DLC) == FDCAN_DLC_BYTES_8) || ((DLC) == FDCAN_DLC_BYTES_12) || \
- ((DLC) == FDCAN_DLC_BYTES_16) || ((DLC) == FDCAN_DLC_BYTES_20) || \
- ((DLC) == FDCAN_DLC_BYTES_24) || ((DLC) == FDCAN_DLC_BYTES_32) || \
- ((DLC) == FDCAN_DLC_BYTES_48) || ((DLC) == FDCAN_DLC_BYTES_64))
-#define IS_FDCAN_ESI(ESI) \
- (((ESI) == FDCAN_ESI_ACTIVE) || ((ESI) == FDCAN_ESI_PASSIVE))
-#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || ((BRS) == FDCAN_BRS_ON))
-#define IS_FDCAN_FDF(FDF) \
- (((FDF) == FDCAN_CLASSIC_CAN) || ((FDF) == FDCAN_FD_CAN))
-#define IS_FDCAN_EFC(EFC) \
- (((EFC) == FDCAN_NO_TX_EVENTS) || ((EFC) == FDCAN_STORE_TX_EVENTS))
-#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
-#define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
-#define IS_FDCAN_NON_MATCHING(DESTINATION) \
- (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
- ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
- ((DESTINATION) == FDCAN_REJECT))
-#define IS_FDCAN_REJECT_REMOTE(DESTINATION) \
- (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
- ((DESTINATION) == FDCAN_REJECT_REMOTE))
-#define IS_FDCAN_IT_LINE(IT_LINE) \
- (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
-#define IS_FDCAN_TIMESTAMP(OPERATION) \
- (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
- ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
-#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) \
- (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
-#define IS_FDCAN_TIMEOUT(OPERATION) \
- (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS) || \
- ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
- ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0) || \
- ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1))
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* FDCAN1 */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_FDCAN_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_fdcan.h
+ * @author MCD Application Team
+ * @brief Header file of FDCAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_FDCAN_H
+#define STM32G4xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FDCAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum {
+ HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
+ HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
+ HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
+ HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+ * @brief FDCAN Init structure definition
+ */
+typedef struct {
+ uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider.
+ The clock is common to all FDCAN instances.
+ This parameter is applied only at initialisation
+ of first FDCAN instance. This parameter can be a
+ value of @ref FDCAN_clock_divider. */
+
+ uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
+ This parameter can be a value of @ref
+ FDCAN_frame_format */
+
+ uint32_t
+ Mode; /*!< Specifies the FDCAN mode.
+ This parameter can be a value of @ref FDCAN_operating_mode */
+
+ FunctionalState AutoRetransmission; /*!< Enable or disable the automatic
+ retransmission mode. This parameter can
+ be set to ENABLE or DISABLE */
+
+ FunctionalState
+ TransmitPause; /*!< Enable or disable the Transmit Pause feature.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState
+ ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator
+ frequency is divided for generating the nominal
+ bit time quanta. This parameter must be a number
+ between 1 and 512 */
+
+ uint32_t
+ NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the
+ FDCAN hardware is allowed to lengthen or shorten
+ a bit to perform resynchronization. This
+ parameter must be a number between 1 and 128 */
+
+ uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter must be a number
+ between 2 and 256 */
+
+ uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit
+ Segment 2. This parameter must be a number
+ between 2 and 128 */
+
+ uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator
+ frequency is divided for generating the data bit
+ time quanta. This parameter must be a number
+ between 1 and 32 */
+
+ uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta
+ the FDCAN hardware is allowed to lengthen or
+ shorten a data bit to perform
+ resynchronization. This parameter must be a
+ number between 1 and 16 */
+
+ uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit
+ Segment 1. This parameter must be a number between 1
+ and 32 */
+
+ uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit
+ Segment 2. This parameter must be a number between 1
+ and 16 */
+
+ uint32_t
+ StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
+ This parameter must be a number between 0 and 28 */
+
+ uint32_t
+ ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
+ This parameter must be a number between 0 and 8 */
+
+ uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
+ This parameter can be a value of @ref
+ FDCAN_txFifoQueue_Mode */
+
+} FDCAN_InitTypeDef;
+
+/**
+ * @brief FDCAN filter structure definition
+ */
+typedef struct {
+ uint32_t IdType; /*!< Specifies the identifier type.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between:
+ - 0 and (SRAMCAN_FLS_NBR-1), if IdType is
+ FDCAN_STANDARD_ID
+ - 0 and (SRAMCAN_FLE_NBR-1), if IdType is
+ FDCAN_EXTENDED_ID */
+
+ uint32_t
+ FilterType; /*!< Specifies the filter type.
+ This parameter can be a value of @ref FDCAN_filter_type.
+ The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
+ only when IdType is FDCAN_EXTENDED_ID. */
+
+ uint32_t FilterConfig; /*!< Specifies the filter configuration.
+ This parameter can be a value of @ref
+ FDCAN_filter_config */
+
+ uint32_t
+ FilterID1; /*!< Specifies the filter identification 1.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t
+ FilterID2; /*!< Specifies the filter identification 2.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+} FDCAN_FilterTypeDef;
+
+/**
+ * @brief FDCAN Tx header structure definition
+ */
+typedef struct {
+ uint32_t
+ Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t
+ IdType; /*!< Specifies the identifier type for the message that will be
+ transmitted.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxFrameType; /*!< Specifies the frame type of the message that will
+ be transmitted. This parameter can be a value of @ref
+ FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value of @ref
+ FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref
+ FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be
+ transmitted with or without bit rate switching.
+ This parameter can be a value of @ref
+ FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in
+ classic or FD format. This parameter can be a value of
+ @ref FDCAN_format */
+
+ uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
+ This parameter can be a value of @ref
+ FDCAN_EFC */
+
+ uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx
+ Event FIFO element for identification of Tx message
+ status. This parameter must be a number between 0
+ and 0xFF */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+ * @brief FDCAN Rx header structure definition
+ */
+typedef struct {
+ uint32_t
+ Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type of the received message.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t RxFrameType; /*!< Specifies the the received message frame type.
+ This parameter can be a value of @ref
+ FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the received frame length.
+ This parameter can be a value of @ref
+ FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref
+ FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with
+ or without bit rate switching. This parameter can
+ be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t
+ FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
+ format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on
+ start of frame reception. This parameter must be a
+ number between 0 and 0xFFFF */
+
+ uint32_t
+ FilterIndex; /*!< Specifies the index of matching Rx acceptance filter
+ element. This parameter must be a number between:
+ - 0 and (SRAMCAN_FLS_NBR-1), if IdType is
+ FDCAN_STANDARD_ID
+ - 0 and (SRAMCAN_FLE_NBR-1), if IdType is
+ FDCAN_EXTENDED_ID When the frame is a Non-Filter matching
+ frame, this parameter is unused. */
+
+ uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did
+ not match any Rx filter. Acceptance of
+ non-matching frames may be enabled via
+ HAL_FDCAN_ConfigGlobalFilter().
+ This parameter takes 0 if the frame
+ matched an Rx filter or 1 if it did not
+ match any Rx filter */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+ * @brief FDCAN Tx event FIFO structure definition
+ */
+typedef struct {
+ uint32_t
+ Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t
+ IdType; /*!< Specifies the identifier type for the transmitted message.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted
+ message. This parameter can be a value of @ref
+ FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
+ This parameter can be a value of @ref
+ FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref
+ FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted
+ with or without bit rate switching. This parameter
+ can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in
+ classic or FD format. This parameter can be a value of
+ @ref FDCAN_format */
+
+ uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on
+ start of frame transmission. This parameter must be a
+ number between 0 and 0xFFFF */
+
+ uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event
+ FIFO element for identification of Tx message
+ status. This parameter must be a number between 0
+ and 0xFF */
+
+ uint32_t
+ EventType; /*!< Specifies the event type.
+ This parameter can be a value of @ref FDCAN_event_type */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+ * @brief FDCAN High Priority Message Status structure definition
+ */
+typedef struct {
+ uint32_t FilterList; /*!< Specifies the filter list of the matching filter
+ element. This parameter can be:
+ - 0 : Standard Filter List
+ - 1 : Extended Filter List */
+
+ uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
+ This parameter can be a number between:
+ - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0
+ (Standard)
+ - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1
+ (Extended) */
+
+ uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+ This parameter can be a value of @ref
+ FDCAN_hp_msg_storage */
+
+ uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which
+ the message was stored. This parameter is valid only
+ when MessageStorage is: FDCAN_HP_STORAGE_RXFIFO0 or
+ FDCAN_HP_STORAGE_RXFIFO1 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+ * @brief FDCAN Protocol Status structure definition
+ */
+typedef struct {
+ uint32_t LastErrorCode; /*!< Specifies the type of the last error that
+ occurred on the FDCAN bus. This parameter can be a
+ value of @ref FDCAN_protocol_error_code */
+
+ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that
+ occurred in the data phase of a CAN FD format
+ frame with its BRS flag set. This parameter can
+ be a value of @ref FDCAN_protocol_error_code */
+
+ uint32_t Activity; /*!< Specifies the FDCAN module communication state.
+ This parameter can be a value of @ref
+ FDCAN_communication_state */
+
+ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
+ This parameter can be:
+ - 0 : The FDCAN is in Error_Active state
+ - 1 : The FDCAN is in Error_Passive state */
+
+ uint32_t Warning; /*!< Specifies the FDCAN module warning status.
+ This parameter can be:
+ - 0 : error counters (RxErrorCnt and TxErrorCnt) are
+ below the Error_Warning limit of 96
+ - 1 : at least one of error counters has reached the
+ Error_Warning limit of 96 */
+
+ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
+ This parameter can be:
+ - 0 : The FDCAN is not in Bus_Off state
+ - 1 : The FDCAN is in Bus_Off state */
+
+ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
+ This parameter can be:
+ - 0 : Last received CAN FD message did not have its
+ ESI flag set
+ - 1 : Last received CAN FD message had its ESI flag
+ set */
+
+ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
+ This parameter can be:
+ - 0 : Last received CAN FD message did not have its
+ BRS flag set
+ - 1 : Last received CAN FD message had its BRS flag
+ set */
+
+ uint32_t
+ RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been
+ received since last protocol status. This parameter can be:
+ - 0 : No CAN FD message received
+ - 1 : CAN FD message received */
+
+ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception
+ status. This parameter can be:
+ - 0 : No protocol exception event occurred
+ since last read access
+ - 1 : Protocol exception event occurred */
+
+ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
+ This parameter can be a number between 0 and 127 */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+ * @brief FDCAN Error Counters structure definition
+ */
+typedef struct {
+ uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
+ This parameter can be a number between 0 and 127 */
+
+ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+ This parameter can be:
+ - 0 : The Receive Error Counter (RxErrorCnt) is
+ below the error passive level of 128
+ - 1 : The Receive Error Counter (RxErrorCnt)
+ has reached the error passive level of 128 */
+
+ uint32_t
+ ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter
+ value. This parameter can be a number between 0 and 255.
+ This counter is incremented each time when a FDCAN
+ protocol error causes the TxErrorCnt or the RxErrorCnt to
+ be incremented. The counter stops at 255; the next
+ increment of TxErrorCnt or RxErrorCnt sets interrupt flag
+ FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+ * @brief FDCAN Message RAM blocks
+ */
+typedef struct {
+ uint32_t
+ StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t
+ ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
+ This parameter must be a 32-bit word address */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+ * @brief FDCAN handle structure definition
+ */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+ FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
+
+ FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
+
+ FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
+
+ uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+ of latest Tx FIFO/Queue request */
+
+ __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< FDCAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< FDCAN Error code */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ void (*TxEventFifoCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */
+ void (*RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */
+ void (*RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */
+ void (*TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef
+ *hfdcan); /*!< FDCAN Tx Fifo Empty callback */
+ void (*TxBufferCompleteCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
+ void (*TxBufferAbortCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */
+ void (*HighPriorityMessageCallback)(
+ struct __FDCAN_HandleTypeDef
+ *hfdcan); /*!< FDCAN High priority message callback */
+ void (*TimestampWraparoundCallback)(
+ struct __FDCAN_HandleTypeDef
+ *hfdcan); /*!< FDCAN Timestamp wraparound callback */
+ void (*TimeoutOccurredCallback)(
+ struct __FDCAN_HandleTypeDef
+ *hfdcan); /*!< FDCAN Timeout occurred callback */
+ void (*ErrorCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */
+ void (*ErrorStatusCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */
+
+ void (*MspInitCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */
+ void (*MspDeInitCallback)(
+ struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL FDCAN common Callback ID enumeration definition
+ */
+typedef enum {
+ HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
+ HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID =
+ 0x01U, /*!< FDCAN High priority message callback ID */
+ HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID =
+ 0x02U, /*!< FDCAN Timestamp wraparound callback ID */
+ HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID =
+ 0x03U, /*!< FDCAN Timeout occurred callback ID */
+ HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */
+
+ HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */
+ HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FDCAN Callback pointer definition
+ */
+typedef void (*pFDCAN_CallbackTypeDef)(
+ FDCAN_HandleTypeDef
+ *hfdcan); /*!< pointer to a common FDCAN callback function */
+typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(
+ FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback
+ function */
+typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(
+ FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */
+typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(
+ FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */
+typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(
+ FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback
+ function */
+typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(
+ FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback
+ function */
+typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(
+ FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+ * @{
+ */
+#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED \
+ ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
+#define HAL_FDCAN_ERROR_NOT_READY \
+ ((uint32_t)0x00000004U) /*!< Peripheral not ready */
+#define HAL_FDCAN_ERROR_NOT_STARTED \
+ ((uint32_t)0x00000008U) /*!< Peripheral not started */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED \
+ ((uint32_t)0x00000010U) /*!< Mode not supported */
+#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
+#define HAL_FDCAN_ERROR_PENDING \
+ ((uint32_t)0x00000040U) /*!< Pending operation */
+#define HAL_FDCAN_ERROR_RAM_ACCESS \
+ ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY \
+ ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */
+#define HAL_FDCAN_ERROR_FIFO_FULL \
+ ((uint32_t)0x00000200U) /*!< Put element in full FIFO */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW \
+ FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
+#define HAL_FDCAN_ERROR_RAM_WDG \
+ FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT \
+ FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is \
+ used) */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA \
+ FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
+#define HAL_FDCAN_ERROR_RESERVED_AREA \
+ FDCAN_IR_ARA /*!< Access to Reserved Address */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK \
+ ((uint32_t)0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+ * @{
+ */
+#define FDCAN_FRAME_CLASSIC \
+ ((uint32_t)0x00000000U) /*!< Classic mode */
+#define FDCAN_FRAME_FD_NO_BRS \
+ ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS \
+ ((uint32_t)(FDCAN_CCCR_FDOE | \
+ FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+ * @{
+ */
+#define FDCAN_MODE_NORMAL \
+ ((uint32_t)0x00000000U) /*!< Normal mode */
+#define FDCAN_MODE_RESTRICTED_OPERATION \
+ ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING \
+ ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
+#define FDCAN_MODE_INTERNAL_LOOPBACK \
+ ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK \
+ ((uint32_t)0x00000004U) /*!< External LoopBack mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+ * @{
+ */
+#define FDCAN_CLOCK_DIV1 \
+ ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
+#define FDCAN_CLOCK_DIV2 \
+ ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
+#define FDCAN_CLOCK_DIV4 \
+ ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
+#define FDCAN_CLOCK_DIV6 \
+ ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
+#define FDCAN_CLOCK_DIV8 \
+ ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
+#define FDCAN_CLOCK_DIV10 \
+ ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 \
+ ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 \
+ ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 \
+ ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 \
+ ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 \
+ ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 \
+ ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 \
+ ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 \
+ ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 \
+ ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 \
+ ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+ * @{
+ */
+#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
+#define FDCAN_TX_QUEUE_OPERATION \
+ ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+ * @{
+ */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+ * @{
+ */
+#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+ * @{
+ */
+#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
+#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
+#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
+#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
+#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
+#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
+#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
+#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
+#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+ * @{
+ */
+#define FDCAN_ESI_ACTIVE \
+ ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
+#define FDCAN_ESI_PASSIVE \
+ ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+ * @{
+ */
+#define FDCAN_BRS_OFF \
+ ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit \
+ rate switching */
+#define FDCAN_BRS_ON \
+ ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate \
+ switching */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_format FDCAN format
+ * @{
+ */
+#define FDCAN_CLASSIC_CAN \
+ ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN \
+ format */
+#define FDCAN_FD_CAN \
+ ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+ * @{
+ */
+#define FDCAN_NO_TX_EVENTS \
+ ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS \
+ ((uint32_t)0x00800000U) /*!< Store Tx events */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+ * @{
+ */
+#define FDCAN_FILTER_RANGE \
+ ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
+#define FDCAN_FILTER_DUAL \
+ ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
+#define FDCAN_FILTER_MASK \
+ ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = \
+ mask */
+#define FDCAN_FILTER_RANGE_NO_EIDM \
+ ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM \
+ mask not applied */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+ * @{
+ */
+#define FDCAN_FILTER_DISABLE \
+ ((uint32_t)0x00000000U) /*!< Disable filter element */
+#define FDCAN_FILTER_TO_RXFIFO0 \
+ ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO1 \
+ ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
+#define FDCAN_FILTER_REJECT \
+ ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
+#define FDCAN_FILTER_HP \
+ ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO0_HP \
+ ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter \
+ matches */
+#define FDCAN_FILTER_TO_RXFIFO1_HP \
+ ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter \
+ matches */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+ * @{
+ */
+#define FDCAN_TX_BUFFER0 \
+ ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
+#define FDCAN_TX_BUFFER1 \
+ ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
+#define FDCAN_TX_BUFFER2 \
+ ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+ * @{
+ */
+#define FDCAN_RX_FIFO0 \
+ ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
+#define FDCAN_RX_FIFO1 \
+ ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+ * @{
+ */
+#define FDCAN_TX_EVENT \
+ ((uint32_t)0x00400000U) /*!< Tx event */
+#define FDCAN_TX_IN_SPITE_OF_ABORT \
+ ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+ * @{
+ */
+#define FDCAN_HP_STORAGE_NO_FIFO \
+ ((uint32_t)0x00000000U) /*!< No FIFO selected */
+#define FDCAN_HP_STORAGE_MSG_LOST \
+ ((uint32_t)0x00000040U) /*!< FIFO message lost */
+#define FDCAN_HP_STORAGE_RXFIFO0 \
+ ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1 \
+ ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+ * @{
+ */
+#define FDCAN_PROTOCOL_ERROR_NONE \
+ ((uint32_t)0x00000000U) /*!< No error occurred */
+#define FDCAN_PROTOCOL_ERROR_STUFF \
+ ((uint32_t)0x00000001U) /*!< Stuff error */
+#define FDCAN_PROTOCOL_ERROR_FORM \
+ ((uint32_t)0x00000002U) /*!< Form error */
+#define FDCAN_PROTOCOL_ERROR_ACK \
+ ((uint32_t)0x00000003U) /*!< Acknowledge error */
+#define FDCAN_PROTOCOL_ERROR_BIT1 \
+ ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
+#define FDCAN_PROTOCOL_ERROR_BIT0 \
+ ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
+#define FDCAN_PROTOCOL_ERROR_CRC \
+ ((uint32_t)0x00000006U) /*!< CRC check sum error */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE \
+ ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+ * @{
+ */
+#define FDCAN_COM_STATE_SYNC \
+ ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE \
+ ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
+#define FDCAN_COM_STATE_RX \
+ ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
+#define FDCAN_COM_STATE_TX \
+ ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+ * @{
+ */
+#define FDCAN_RX_FIFO_BLOCKING \
+ ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
+#define FDCAN_RX_FIFO_OVERWRITE \
+ ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+ * @{
+ */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 \
+ ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 \
+ ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+ * @{
+ */
+#define FDCAN_FILTER_REMOTE \
+ ((uint32_t)0x00000000U) /*!< Filter remote frames \
+ */
+#define FDCAN_REJECT_REMOTE \
+ ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+ * @{
+ */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+ * @{
+ */
+#define FDCAN_TIMESTAMP_INTERNAL \
+ ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according \
+ to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL \
+ ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+ * @{
+ */
+#define FDCAN_TIMESTAMP_PRESC_1 \
+ ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time */
+#define FDCAN_TIMESTAMP_PRESC_2 \
+ ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 2 */
+#define FDCAN_TIMESTAMP_PRESC_3 \
+ ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 3 */
+#define FDCAN_TIMESTAMP_PRESC_4 \
+ ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 4 */
+#define FDCAN_TIMESTAMP_PRESC_5 \
+ ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 5 */
+#define FDCAN_TIMESTAMP_PRESC_6 \
+ ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 6 */
+#define FDCAN_TIMESTAMP_PRESC_7 \
+ ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 7 */
+#define FDCAN_TIMESTAMP_PRESC_8 \
+ ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 8 */
+#define FDCAN_TIMESTAMP_PRESC_9 \
+ ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 9 */
+#define FDCAN_TIMESTAMP_PRESC_10 \
+ ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 \
+ ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 \
+ ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 \
+ ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 \
+ ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 \
+ ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 \
+ ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit \
+ time multiplied by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+ * @{
+ */
+#define FDCAN_TIMEOUT_CONTINUOUS \
+ ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO \
+ ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0 \
+ ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
+#define FDCAN_TIMEOUT_RX_FIFO1 \
+ ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+ * @{
+ */
+#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
+#define FDCAN_ILS_MASK \
+ ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+ * @{
+ */
+#define FDCAN_FLAG_TX_COMPLETE \
+ FDCAN_IR_TC /*!< Transmission Completed */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE \
+ FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
+#define FDCAN_FLAG_TX_FIFO_EMPTY \
+ FDCAN_IR_TFE /*!< Tx FIFO Empty */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG \
+ FDCAN_IR_HPM /*!< High priority message received */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST \
+ FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL \
+ FDCAN_IR_TEFF /*!< Tx Event FIFO full */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA \
+ FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST \
+ FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
+#define FDCAN_FLAG_RX_FIFO0_FULL \
+ FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE \
+ FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST \
+ FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
+#define FDCAN_FLAG_RX_FIFO1_FULL \
+ FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE \
+ FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE \
+ FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW \
+ FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_FLAG_ERROR_PASSIVE \
+ FDCAN_IR_EP /*!< Error_Passive status changed */
+#define FDCAN_FLAG_ERROR_WARNING \
+ FDCAN_IR_EW /*!< Error_Warning status changed */
+#define FDCAN_FLAG_BUS_OFF \
+ FDCAN_IR_BO /*!< Bus_Off status changed */
+#define FDCAN_FLAG_RAM_WATCHDOG \
+ FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR \
+ FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR \
+ FDCAN_IR_PED /*!< Protocol error in data phase detected */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS \
+ FDCAN_IR_ARA /*!< Access to reserved address occurred */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND \
+ FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED \
+ FDCAN_IR_TOO /*!< Timeout reached */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+ * @{
+ */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+ * @{
+ */
+#define FDCAN_IT_TX_COMPLETE \
+ FDCAN_IE_TCE /*!< Transmission Completed */
+#define FDCAN_IT_TX_ABORT_COMPLETE \
+ FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
+#define FDCAN_IT_TX_FIFO_EMPTY \
+ FDCAN_IE_TFEE /*!< Tx FIFO Empty */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG \
+ FDCAN_IE_HPME /*!< High priority message received */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+ * @{
+ */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND \
+ FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
+#define FDCAN_IT_TIMEOUT_OCCURRED \
+ FDCAN_IE_TOOE /*!< Timeout reached */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+ * @{
+ */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST \
+ FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
+#define FDCAN_IT_TX_EVT_FIFO_FULL \
+ FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA \
+ FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST \
+ FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
+#define FDCAN_IT_RX_FIFO0_FULL \
+ FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE \
+ FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST \
+ FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
+#define FDCAN_IT_RX_FIFO1_FULL \
+ FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE \
+ FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+ * @{
+ */
+#define FDCAN_IT_RAM_ACCESS_FAILURE \
+ FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW \
+ FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG \
+ FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR \
+ FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR \
+ FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS \
+ FDCAN_IE_ARAE /*!< Access to reserved address occurred */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+ * @{
+ */
+#define FDCAN_IT_ERROR_PASSIVE \
+ FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING \
+ FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
+ * @{
+ */
+#define FDCAN_IT_LIST_RX_FIFO0 \
+ (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | FDCAN_IT_RX_FIFO0_FULL | \
+ FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */
+#define FDCAN_IT_LIST_RX_FIFO1 \
+ (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | FDCAN_IT_RX_FIFO1_FULL | \
+ FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */
+#define FDCAN_IT_LIST_SMSG \
+ (FDCAN_IT_TX_ABORT_COMPLETE | FDCAN_IT_TX_COMPLETE | \
+ FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */
+#define FDCAN_IT_LIST_TX_FIFO_ERROR \
+ (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | FDCAN_IT_TX_EVT_FIFO_FULL | \
+ FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
+ FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */
+#define FDCAN_IT_LIST_MISC \
+ (FDCAN_IT_TIMEOUT_OCCURRED | FDCAN_IT_RAM_ACCESS_FAILURE | \
+ FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */
+#define FDCAN_IT_LIST_BIT_LINE_ERROR \
+ (FDCAN_IT_ERROR_PASSIVE | \
+ FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */
+#define FDCAN_IT_LIST_PROTOCOL_ERROR \
+ (FDCAN_IT_RESERVED_ADDRESS_ACCESS | FDCAN_IT_DATA_PROTOCOL_ERROR | \
+ FDCAN_IT_ARB_PROTOCOL_ERROR | FDCAN_IT_RAM_WATCHDOG | FDCAN_IT_BUS_OFF | \
+ FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
+ * @{
+ */
+#define FDCAN_IT_GROUP_RX_FIFO0 \
+ FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: \
+ RF0LL: Rx FIFO 0 Message Lost \
+ RF0FL: Rx FIFO 0 is Full \
+ RF0NL: Rx FIFO 0 Has New Message */
+#define FDCAN_IT_GROUP_RX_FIFO1 \
+ FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: \
+ RF1LL: Rx FIFO 1 Message Lost \
+ RF1FL: Rx FIFO 1 is Full \
+ RF1NL: Rx FIFO 1 Has New Message */
+#define FDCAN_IT_GROUP_SMSG \
+ FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: \
+ TCFL: Transmission Cancellation Finished \
+ TCL: Transmission Completed \
+ HPML: High Priority Message */
+#define FDCAN_IT_GROUP_TX_FIFO_ERROR \
+ FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: \
+ TEFLL: Tx Event FIFO Element Lost \
+ TEFFL: Tx Event FIFO Full \
+ TEFNL: Tx Event FIFO New Entry \
+ TFEL: Tx FIFO Empty Interrupt Line */
+#define FDCAN_IT_GROUP_MISC \
+ FDCAN_ILS_MISC /*!< Misc. Interrupts Group: \
+ TOOL: Timeout Occurred \
+ MRAFL: Message RAM Access Failure \
+ TSWL: Timestamp Wraparound */
+#define FDCAN_IT_GROUP_BIT_LINE_ERROR \
+ FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: \
+ EPL: Error Passive \
+ ELOL: Error Logging Overflow */
+#define FDCAN_IT_GROUP_PROTOCOL_ERROR \
+ FDCAN_ILS_PERR /*!< Protocol Error Group: \
+ ARAL: Access to Reserved Address Line \
+ PEDL: Protocol Error in Data Phase Line \
+ PEAL: Protocol Error in Arbitration Phase Line \
+ WDIL: Watchdog Interrupt Line \
+ BOL: Bus_Off Status \
+ EWL: Warning Status */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset FDCAN handle state.
+ * @param __HANDLE__ FDCAN handle.
+ * @retval None
+ */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while (0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
+
+/**
+ * @brief Disable the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
+
+/**
+ * @brief Check whether the specified FDCAN interrupt is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be one of @arg FDCAN_Interrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
+
+/**
+ * @brief Clear the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the interrupts to clear.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
+
+/**
+ * @brief Check whether the specified FDCAN flag is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ FDCAN flag.
+ * This parameter can be one of @arg FDCAN_flags
+ * @retval FlagStatus
+ */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->IR & (__FLAG__))
+
+/**
+ * @brief Clear the specified FDCAN flags.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ specifies the flags to clear.
+ * This parameter can be any combination of @arg FDCAN_flags
+ * @retval None
+ */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->IR) = (__FLAG__)
+
+/** @brief Check if the specified FDCAN interrupt source is enabled or
+ * disabled.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
+ * This parameter can be a value of @arg FDCAN_Interrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(
+ FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+ pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(
+ FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(
+ FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(
+ FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(
+ FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t NonMatchingStd,
+ uint32_t NonMatchingExt,
+ uint32_t RejectRemoteStd,
+ uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo,
+ uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(
+ FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TimeoutOperation,
+ uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(
+ FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(
+ FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+ * @{
+ */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(
+ FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(
+ const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxLocation,
+ FDCAN_RxHeaderTypeDef *pRxHeader,
+ uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(
+ const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(
+ const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(
+ const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(
+ FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ITList,
+ uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ActiveITs,
+ uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t InactiveITs);
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ErrorStatusITs);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+ * @{
+ */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) \
+ (((FORMAT) == FDCAN_FRAME_CLASSIC) || ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+ ((FORMAT) == FDCAN_FRAME_FD_BRS))
+#define IS_FDCAN_MODE(MODE) \
+ (((MODE) == FDCAN_MODE_NORMAL) || \
+ ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+ ((MODE) == FDCAN_MODE_BUS_MONITORING) || \
+ ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK) || \
+ ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK))
+#define IS_FDCAN_CKDIV(CKDIV) \
+ (((CKDIV) == FDCAN_CLOCK_DIV1) || ((CKDIV) == FDCAN_CLOCK_DIV2) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV4) || ((CKDIV) == FDCAN_CLOCK_DIV6) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV8) || ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV12) || ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV16) || ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV20) || ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV24) || ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV28) || ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) \
+ (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) \
+ (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
+#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) \
+ (((MODE) == FDCAN_TX_FIFO_OPERATION) || ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) \
+ (((ID_TYPE) == FDCAN_STANDARD_ID) || ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) \
+ (((CONFIG) == FDCAN_FILTER_DISABLE) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1) || \
+ ((CONFIG) == FDCAN_FILTER_REJECT) || ((CONFIG) == FDCAN_FILTER_HP) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
+#define IS_FDCAN_TX_LOCATION(LOCATION) \
+ (((LOCATION) == FDCAN_TX_BUFFER0) || ((LOCATION) == FDCAN_TX_BUFFER1) || \
+ ((LOCATION) == FDCAN_TX_BUFFER2))
+#define IS_FDCAN_TX_LOCATION_LIST(LOCATION) \
+ (((LOCATION) >= FDCAN_TX_BUFFER0) && \
+ ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
+#define IS_FDCAN_RX_FIFO(FIFO) \
+ (((FIFO) == FDCAN_RX_FIFO0) || ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) \
+ (((MODE) == FDCAN_RX_FIFO_BLOCKING) || ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) \
+ (((TYPE) == FDCAN_FILTER_RANGE) || ((TYPE) == FDCAN_FILTER_DUAL) || \
+ ((TYPE) == FDCAN_FILTER_MASK))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) \
+ (((TYPE) == FDCAN_FILTER_RANGE) || ((TYPE) == FDCAN_FILTER_DUAL) || \
+ ((TYPE) == FDCAN_FILTER_MASK) || ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) \
+ (((TYPE) == FDCAN_DATA_FRAME) || ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) \
+ (((DLC) == FDCAN_DLC_BYTES_0) || ((DLC) == FDCAN_DLC_BYTES_1) || \
+ ((DLC) == FDCAN_DLC_BYTES_2) || ((DLC) == FDCAN_DLC_BYTES_3) || \
+ ((DLC) == FDCAN_DLC_BYTES_4) || ((DLC) == FDCAN_DLC_BYTES_5) || \
+ ((DLC) == FDCAN_DLC_BYTES_6) || ((DLC) == FDCAN_DLC_BYTES_7) || \
+ ((DLC) == FDCAN_DLC_BYTES_8) || ((DLC) == FDCAN_DLC_BYTES_12) || \
+ ((DLC) == FDCAN_DLC_BYTES_16) || ((DLC) == FDCAN_DLC_BYTES_20) || \
+ ((DLC) == FDCAN_DLC_BYTES_24) || ((DLC) == FDCAN_DLC_BYTES_32) || \
+ ((DLC) == FDCAN_DLC_BYTES_48) || ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) \
+ (((ESI) == FDCAN_ESI_ACTIVE) || ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || ((BRS) == FDCAN_BRS_ON))
+#define IS_FDCAN_FDF(FDF) \
+ (((FDF) == FDCAN_CLASSIC_CAN) || ((FDF) == FDCAN_FD_CAN))
+#define IS_FDCAN_EFC(EFC) \
+ (((EFC) == FDCAN_NO_TX_EVENTS) || ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
+#define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
+#define IS_FDCAN_NON_MATCHING(DESTINATION) \
+ (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+ ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+ ((DESTINATION) == FDCAN_REJECT))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) \
+ (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+ ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) \
+ (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) \
+ (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+ ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) \
+ (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) \
+ (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS) || \
+ ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0) || \
+ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1))
+
+#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) \
+ ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) \
+ ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* FDCAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_FDCAN_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
index d5d64c4..4f5d7e3 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
@@ -1,1217 +1,1217 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_FLASH_H
-#define STM32G4xx_HAL_FLASH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct {
- uint32_t
- TypeErase; /*!< Mass erase or page erase.
- This parameter can be a value of @ref FLASH_Type_Erase */
- uint32_t Banks; /*!< Select bank to erase.
- This parameter must be a value of @ref FLASH_Banks
- (FLASH_BANK_BOTH should be used only for mass erase) */
- uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled.
- This parameter must be a value between 0 and (max number
- of pages in the bank - 1) (eg : 127 for 512KB dual bank) */
- uint32_t NbPages; /*!< Number of pages to be erased.
- This parameter must be a value between 1 and (max
- number of pages in the bank - value of initial page)*/
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Option Bytes Program structure definition
- */
-typedef struct {
- uint32_t OptionType; /*!< Option byte to be configured.
- This parameter can be a combination of the values of
- @ref FLASH_OB_Type */
- uint32_t WRPArea; /*!< Write protection area to be programmed (used for
- OPTIONBYTE_WRP). Only one WRP area could be programmed
- at the same time. This parameter can be value of
- @ref FLASH_OB_WRP_Area */
- uint32_t
- WRPStartOffset; /*!< Write protection start offset (used for
- OPTIONBYTE_WRP). This parameter must be a value between
- 0 and (max number of pages in the bank - 1) */
- uint32_t
- WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
- This parameter must be a value between WRPStartOffset
- and (max number of pages in the bank - 1) */
- uint32_t RDPLevel; /*!< Set the read protection level.. (used for
- OPTIONBYTE_RDP). This parameter can be a value of @ref
- FLASH_OB_Read_Protection */
- uint32_t USERType; /*!< User option byte(s) to be configured (used for
- OPTIONBYTE_USER). This parameter can be a combination of
- @ref FLASH_OB_USER_Type */
- uint32_t
- USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
- This parameter can be a combination of @ref
- FLASH_OB_USER_BOR_LEVEL,
- @ref FLASH_OB_USER_nRST_STOP, @ref
- FLASH_OB_USER_nRST_STANDBY,
- @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref
- FLASH_OB_USER_IWDG_SW,
- @ref FLASH_OB_USER_IWDG_STOP, @ref
- FLASH_OB_USER_IWDG_STANDBY,
- @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
- @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
- @ref FLASH_OB_USER_CCMSRAM_RST
- @note (*) availability depends on devices */
- uint32_t
- PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
- This parameter must be a combination of @ref FLASH_Banks
- (except FLASH_BANK_BOTH) and @ref FLASH_OB_PCROP_RDP */
- uint32_t
- PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
- This parameter must be a value between begin and end
- of bank
- => Be careful of the bank swapping for the address */
- uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
- This parameter must be a value between PCROP Start
- address and end of bank */
- uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for
- OPTIONBYTE_BOOT_LOCK). This parameter can be a
- value of @ref FLASH_OB_Boot_Lock */
- uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used
- for OPTIONBYTE_SEC). Only one securable memory area could
- be programmed at the same time. This parameter can be one
- of the following values: FLASH_BANK_1: Securable memory
- area to be programmed in bank 1 FLASH_BANK_2: Securable
- memory area to be programmed in bank 2 (*)
- @note (*) availability depends on devices */
- uint32_t SecSize; /*!< Size of securable memory area to be programmed (used
- for OPTIONBYTE_SEC), in number of pages. Securable memory
- area is starting from first page of the bank. Only one
- securable memory could be programmed at the same time.
- This parameter must be a value between 0 and (max
- number of pages in the bank - 1) */
-} FLASH_OBProgramInitTypeDef;
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum {
- FLASH_PROC_NONE = 0,
- FLASH_PROC_PAGE_ERASE,
- FLASH_PROC_MASS_ERASE,
- FLASH_PROC_PROGRAM,
- FLASH_PROC_PROGRAM_LAST
-} FLASH_ProcedureTypeDef;
-
-/**
- * @brief FLASH Cache structure definition
- */
-typedef enum {
- FLASH_CACHE_DISABLED = 0,
- FLASH_CACHE_ICACHE_ENABLED,
- FLASH_CACHE_DCACHE_ENABLED,
- FLASH_CACHE_ICACHE_DCACHE_ENABLED
-} FLASH_CacheTypeDef;
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct {
- HAL_LockTypeDef Lock; /* FLASH locking object */
- __IO uint32_t ErrorCode; /* FLASH error code */
- __IO FLASH_ProcedureTypeDef
- ProcedureOnGoing; /* Internal variable to indicate which procedure is
- ongoing or not in IT context */
- __IO uint32_t Address; /* Internal variable to save address selected for
- program in IT context */
- __IO uint32_t Bank; /* Internal variable to save current bank selected during
- erase in IT context */
- __IO uint32_t Page; /* Internal variable to define the current page which is
- erasing in IT context */
- __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages
- to erase in IT context */
- __IO FLASH_CacheTypeDef
- CacheToReactivate; /* Internal variable to indicate which caches should be
- reactivated */
-} FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASH_Error FLASH Error
- * @{
- */
-#define HAL_FLASH_ERROR_NONE 0x00000000U
-#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
-#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
-#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
-#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
-#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
-#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
-#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
-#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
-#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
-#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
-#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
-#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
-#if defined(FLASH_OPTR_DBANK)
-#define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2
-#define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2
-#endif
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Erase FLASH Erase Type
- * @{
- */
-#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE 0x01U /*!<Flash mass erase activation*/
-/**
- * @}
- */
-
-/** @defgroup FLASH_Banks FLASH Banks
- * @{
- */
-#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
-#if defined(FLASH_OPTR_DBANK)
-#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
-#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
-#else
-#define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */
-#endif
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Program FLASH Program Type
- * @{
- */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD \
- 0x00U /*!< Program a double-word (64-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_FAST \
- 0x01U /*!< Fast program a 32 row double-word (64-bit) at a specified \
- address. And another 32 row double-word (64-bit) will be programmed \
- */
-#define FLASH_TYPEPROGRAM_FAST_AND_LAST \
- 0x02U /*!< Fast program a 32 row double-word (64-bit) at a specified \
- address. And this is the last 32 row double-word (64-bit) \
- programmed */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
- * @{
- */
-#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
-#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
-#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
-#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
-#define OPTIONBYTE_BOOT_LOCK 0x10U /*!< Boot lock option byte configuration */
-#define OPTIONBYTE_SEC \
- 0x20U /*!< Securable memory option byte configuration \
- */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
- * @{
- */
-#define OB_WRPAREA_BANK1_AREAA 0x00U /*!< Flash Bank 1 Area A */
-#define OB_WRPAREA_BANK1_AREAB 0x01U /*!< Flash Bank 1 Area B */
-#if defined(FLASH_OPTR_DBANK)
-#define OB_WRPAREA_BANK2_AREAA 0x02U /*!< Flash Bank 2 Area A */
-#define OB_WRPAREA_BANK2_AREAB 0x04U /*!< Flash Bank 2 Area B */
-#endif
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
- * @{
- */
-#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot Lock Disable */
-#define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK /*!< Boot Lock Enable */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
- * @{
- */
-#define OB_RDP_LEVEL_0 0xAAU
-#define OB_RDP_LEVEL_1 0xBBU
-#define OB_RDP_LEVEL_2 \
- 0xCCU /*!< Warning: When enabling read protection level 2 \
- it's no more possible to go back to level 1 or 0 */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
- * @{
- */
-#define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */
-#define OB_USER_nRST_STOP \
- 0x00000002U /*!< Reset generated when entering the stop mode */
-#define OB_USER_nRST_STDBY \
- 0x00000004U /*!< Reset generated when entering the standby mode */
-#define OB_USER_IWDG_SW 0x00000008U /*!< Independent watchdog selection */
-#define OB_USER_IWDG_STOP \
- 0x00000010U /*!< Independent watchdog counter freeze in stop mode */
-#define OB_USER_IWDG_STDBY \
- 0x00000020U /*!< Independent watchdog counter freeze in standby mode */
-#define OB_USER_WWDG_SW 0x00000040U /*!< Window watchdog selection */
-#if defined(FLASH_OPTR_DBANK)
-#define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */
-#define OB_USER_DBANK \
- 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits \
- data */
-#endif
-#if defined(FLASH_OPTR_PB4_PUPEN)
-#define OB_USER_PB4_PUPEN \
- 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */
-#endif
-#define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */
-#define OB_USER_SRAM_PE \
- 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) \
- */
-#define OB_USER_CCMSRAM_RST \
- 0x00000800U /*!< CCMSRAM Erase when system reset \
- */
-#define OB_USER_nRST_SHDW \
- 0x00001000U /*!< Reset generated when entering the shutdown mode */
-#define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */
-#define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */
-#define OB_USER_NRST_MODE 0x00008000U /*!< Reset pin configuration */
-#define OB_USER_IRHEN 0x00010000U /*!< Internal Reset Holder enable */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
- * @{
- */
-#define OB_BOR_LEVEL_0 \
- FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */
-#define OB_BOR_LEVEL_1 \
- FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */
-#define OB_BOR_LEVEL_2 \
- FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */
-#define OB_BOR_LEVEL_3 \
- FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */
-#define OB_BOR_LEVEL_4 \
- FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
- * @{
- */
-#define OB_STOP_RST \
- 0x00000000U /*!< Reset generated when entering the stop mode */
-#define OB_STOP_NORST \
- FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On
- * Standby
- * @{
- */
-#define OB_STANDBY_RST \
- 0x00000000U /*!< Reset generated when entering the standby mode */
-#define OB_STANDBY_NORST \
- FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode \
- */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On
- * Shutdown
- * @{
- */
-#define OB_SHUTDOWN_RST \
- 0x00000000U /*!< Reset generated when entering the shutdown mode */
-#define OB_SHUTDOWN_NORST \
- FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode \
- */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
- * @{
- */
-#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
-#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
- * @{
- */
-#define OB_IWDG_STOP_FREEZE \
- 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
-#define OB_IWDG_STOP_RUN \
- FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop \
- mode */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On
- * Standby
- * @{
- */
-#define OB_IWDG_STDBY_FREEZE \
- 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
-#define OB_IWDG_STDBY_RUN \
- FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in \
- Standby mode */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
- * @{
- */
-#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
-#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
-/**
- * @}
- */
-
-#if defined(FLASH_OPTR_DBANK)
-/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
- * @{
- */
-#define OB_BFB2_DISABLE 0x00000000U /*!< Dual-bank boot disable */
-#define OB_BFB2_ENABLE FLASH_OPTR_BFB2 /*!< Dual-bank boot enable */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
- * @{
- */
-#define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */
-#define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */
-/**
- * @}
- */
-#endif
-
-#if defined(FLASH_OPTR_PB4_PUPEN)
-/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
- * @{
- */
-#define OB_PB4_PUPEN_DISABLE \
- 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up \
- deactivated */
-#define OB_PB4_PUPEN_ENABLE \
- FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI \
- pull-up activated */
-/**
- * @}
- */
-#endif
-
-/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
- * @{
- */
-#define OB_BOOT1_SRAM \
- 0x00000000U /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
-#define OB_BOOT1_SYSTEM \
- FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) \
- */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check
- * Type
- * @{
- */
-#define OB_SRAM_PARITY_ENABLE \
- 0x00000000U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) \
- */
-#define OB_SRAM_PARITY_DISABLE \
- FLASH_OPTR_SRAM_PE /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM \
- SRAM) */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On
- * Reset Type
- * @{
- */
-#define OB_CCMSRAM_RST_ERASE \
- 0x00000000U /*!< CCMSRAM erased when a system reset occurs */
-#define OB_CCMSRAM_RST_NOT_ERASE \
- FLASH_OPTR_CCMSRAM_RST /*!< CCMSRAM is not erased when a system reset occurs \
- */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
- * @{
- */
-#define OB_BOOT0_FROM_OB \
- 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
-#define OB_BOOT0_FROM_PIN \
- FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PB8/BOOT0 pin */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
- * @{
- */
-#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
-#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
- * @{
- */
-#define OB_NRST_MODE_INPUT_ONLY \
- FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */
-#define OB_NRST_MODE_GPIO \
- FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode only */
-#define OB_NRST_MODE_INPUT_OUTPUT \
- FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User
- * internal reset holder bit
- * @{
- */
-#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset holder disable */
-#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset holder enable */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
- * @{
- */
-#define OB_PCROP_RDP_NOT_ERASE \
- 0x00000000U /*!< PCROP area is not erased when the RDP level \
- is decreased from Level 1 to Level 0 */
-#define OB_PCROP_RDP_ERASE \
- FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is \
- decreased from Level 1 to Level 0 (full mass \
- erase) */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Latency FLASH Latency
- * @{
- */
-#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
-#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
-#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
-#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
-#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
-#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */
-#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */
-#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
-#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
-#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */
-#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */
-#define FLASH_LATENCY_11 \
- FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state \
- */
-#define FLASH_LATENCY_12 \
- FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states \
- */
-#define FLASH_LATENCY_13 \
- FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */
-#define FLASH_LATENCY_14 \
- FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */
-#define FLASH_LATENCY_15 \
- FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Keys FLASH Keys
- * @{
- */
-#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
-#define FLASH_KEY2 \
- 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 \
- to unlock the FLASH registers access */
-
-#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
-#define FLASH_PDKEY2 \
- 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 \
- to unlock the RUN_PD bit in FLASH_ACR */
-
-#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
-#define FLASH_OPTKEY2 \
- 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 \
- to allow option bytes operations */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags FLASH Flags Definition
- * @{
- */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
-#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
-#define FLASH_FLAG_PROGERR \
- FLASH_SR_PROGERR /*!< FLASH Programming error flag \
- */
-#define FLASH_FLAG_WRPERR \
- FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
-#define FLASH_FLAG_PGAERR \
- FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
-#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
-#define FLASH_FLAG_PGSERR \
- FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
-#define FLASH_FLAG_MISERR \
- FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
-#define FLASH_FLAG_FASTERR \
- FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
-#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
-#define FLASH_FLAG_OPTVERR \
- FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-#define FLASH_FLAG_ECCC \
- FLASH_ECCR_ECCC /*!< FLASH ECC correction in 64 LSB bits */
-#define FLASH_FLAG_ECCD \
- FLASH_ECCR_ECCD /*!< FLASH ECC detection in 64 LSB bits */
-#if defined(FLASH_OPTR_DBANK)
-#define FLASH_FLAG_ECCC2 \
- FLASH_ECCR_ECCC2 /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits \
- only) */
-#define FLASH_FLAG_ECCD2 \
- FLASH_ECCR_ECCD2 /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits \
- only) */
-#endif
-
-#define FLASH_FLAG_SR_ERRORS \
- (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
- FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
- FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
- FLASH_FLAG_OPTVERR)
-#if defined(FLASH_OPTR_DBANK)
-#define FLASH_FLAG_ECCR_ERRORS \
- (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD | FLASH_FLAG_ECCC2 | FLASH_FLAG_ECCD2)
-#else
-#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
-#endif
-#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
- * @brief FLASH Interrupt definition
- * @{
- */
-#define FLASH_IT_EOP \
- FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
-#define FLASH_IT_RDERR \
- FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt \
- source*/
-#define FLASH_IT_ECCC \
- (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- * @brief macros to control FLASH features
- * @{
- */
-
-/**
- * @brief Set the FLASH Latency.
- * @param __LATENCY__ FLASH Latency.
- * This parameter can be one of the following values :
- * @arg FLASH_LATENCY_0: FLASH Zero wait state
- * @arg FLASH_LATENCY_1: FLASH One wait state
- * @arg FLASH_LATENCY_2: FLASH Two wait states
- * @arg FLASH_LATENCY_3: FLASH Three wait states
- * @arg FLASH_LATENCY_4: FLASH Four wait states
- * @arg FLASH_LATENCY_5: FLASH Five wait states
- * @arg FLASH_LATENCY_6: FLASH Six wait states
- * @arg FLASH_LATENCY_7: FLASH Seven wait states
- * @arg FLASH_LATENCY_8: FLASH Eight wait states
- * @arg FLASH_LATENCY_9: FLASH Nine wait states
- * @arg FLASH_LATENCY_10: FLASH Ten wait state
- * @arg FLASH_LATENCY_11: FLASH Eleven wait state
- * @arg FLASH_LATENCY_12: FLASH Twelve wait states
- * @arg FLASH_LATENCY_13: FLASH Thirteen wait states
- * @arg FLASH_LATENCY_14: FLASH Fourteen wait states
- * @arg FLASH_LATENCY_15: FLASH Fifteen wait states
- * @retval None
- */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
-
-/**
- * @brief Get the FLASH Latency.
- * @retval FLASH_Latency.
- * This parameter can be one of the following values :
- * @arg FLASH_LATENCY_0: FLASH Zero wait state
- * @arg FLASH_LATENCY_1: FLASH One wait state
- * @arg FLASH_LATENCY_2: FLASH Two wait states
- * @arg FLASH_LATENCY_3: FLASH Three wait states
- * @arg FLASH_LATENCY_4: FLASH Four wait states
- * @arg FLASH_LATENCY_5: FLASH Five wait states
- * @arg FLASH_LATENCY_6: FLASH Six wait states
- * @arg FLASH_LATENCY_7: FLASH Seven wait states
- * @arg FLASH_LATENCY_8: FLASH Eight wait states
- * @arg FLASH_LATENCY_9: FLASH Nine wait states
- * @arg FLASH_LATENCY_10: FLASH Ten wait state
- * @arg FLASH_LATENCY_11: FLASH Eleven wait state
- * @arg FLASH_LATENCY_12: FLASH Twelve wait states
- * @arg FLASH_LATENCY_13: FLASH Thirteen wait states
- * @arg FLASH_LATENCY_14: FLASH Fourteen wait states
- * @arg FLASH_LATENCY_15: FLASH Fifteen wait states
- */
-#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
-
-/**
- * @brief Enable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() \
- SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-
-/**
- * @brief Disable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-
-/**
- * @brief Enable the FLASH instruction cache.
- * @retval none
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() \
- SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-
-/**
- * @brief Disable the FLASH instruction cache.
- * @retval none
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-
-/**
- * @brief Enable the FLASH data cache.
- * @retval none
- */
-#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-
-/**
- * @brief Disable the FLASH data cache.
- * @retval none
- */
-#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-
-/**
- * @brief Reset the FLASH instruction Cache.
- * @note This function must be used only when the Instruction Cache is
- * disabled.
- * @retval None
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() \
- do { \
- SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
- } while (0)
-
-/**
- * @brief Reset the FLASH data Cache.
- * @note This function must be used only when the data Cache is disabled.
- * @retval None
- */
-#define __HAL_FLASH_DATA_CACHE_RESET() \
- do { \
- SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
- } while (0)
-
-/**
- * @brief Enable the FLASH power down during Low-power run mode.
- * @note Writing this bit to 1, automatically the keys are
- * lost and a new unlock sequence is necessary to re-write it to 0.
- */
-#define __HAL_FLASH_POWER_DOWN_ENABLE() \
- do { \
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
- SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
- } while (0)
-
-/**
- * @brief Disable the FLASH power down during Low-power run mode.
- * @note Writing this bit to 0, automatically the keys are
- * lost and a new unlock sequence is necessary to re-write it to 1.
- */
-#define __HAL_FLASH_POWER_DOWN_DISABLE() \
- do { \
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
- } while (0)
-
-/**
- * @brief Enable the FLASH power down during Low-Power sleep mode
- * @retval none
- */
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() \
- SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
- * @brief Disable the FLASH power down during Low-Power sleep mode
- * @retval none
- */
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
- * @brief macros to handle FLASH interrupts
- * @{
- */
-
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
- * @arg FLASH_IT_OPERR: Error Interrupt
- * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
- * @arg FLASH_IT_ECCC: ECC Correction Interrupt
- * @retval none
- */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) \
- do { \
- if (((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { \
- SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); \
- } \
- if (((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { \
- SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); \
- } \
- } while (0)
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
- * @arg FLASH_IT_OPERR: Error Interrupt
- * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
- * @arg FLASH_IT_ECCC: ECC Correction Interrupt
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) \
- do { \
- if (((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { \
- CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); \
- } \
- if (((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { \
- CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); \
- } \
- } while (0)
-
-/**
- * @brief Check whether the specified FLASH flag is set or not.
- * @param __FLAG__ specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
- * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
- * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
- * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
- * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
- * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
- * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
- * in 64 LSB bits
- * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB
- * bits
- * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and
- * corrected in 64 MSB bits (mode 128 bits only)
- * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64
- * MSB bits (mode 128 bits only)
- * @note (*) availability depends on devices
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) \
- ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \
- ? (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) \
- : (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
-
-/**
- * @brief Clear the FLASH's pending flags.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
- * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
- * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
- * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
- * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
- * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
- * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
- * in 64 LSB bits
- * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB
- * bits
- * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and
- * corrected in 64 MSB bits (mode 128 bits only)
- * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64
- * MSB bits (mode 128 bits only)
- * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
- * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
- * @note (*) availability depends on devices
- * @retval None
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \
- do { \
- if (((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { \
- SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); \
- } \
- if (((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { \
- WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); \
- } \
- } while (0)
-/**
- * @}
- */
-
-/* Include FLASH HAL Extended module */
-#include "stm32g4xx_hal_flash_ex.h"
-#include "stm32g4xx_hal_flash_ramfunc.h"
-
-/* Exported variables --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
- * @{
- */
-extern FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
- * @{
- */
-
-/* Program operation functions ***********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address,
- uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address,
- uint64_t Data);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
-uint32_t HAL_FLASH_GetError(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
- * @}
- */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
-
-#if defined(FLASH_OPTR_DBANK)
-#define FLASH_SIZE \
- ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) \
- ? (0x200UL << 10U) \
- : (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
-#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
-#define FLASH_PAGE_NB 128U
-#define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */
-#else
-#define FLASH_SIZE \
- ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) \
- ? (0x80UL << 10U) \
- : (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
-#define FLASH_BANK_SIZE (FLASH_SIZE)
-#define FLASH_PAGE_NB \
- ((FLASH_SIZE == 0x00080000U) ? 256U \
- : ((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
-#endif
-
-#define FLASH_PAGE_SIZE 0x800U /* 2 KB */
-
-#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE) \
- (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#if defined(FLASH_OPTR_DBANK)
-#define IS_FLASH_BANK(BANK) \
- (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK) \
- (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2))
-#else
-#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
-#endif
-
-#define IS_FLASH_TYPEPROGRAM(VALUE) \
- (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
- ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
-
-#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) \
- (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
-
-#define IS_FLASH_OTP_ADDRESS(ADDRESS) \
- (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
-
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
- (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
-
-#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
-
-#define IS_OPTIONBYTE(VALUE) \
- (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
- OPTIONBYTE_PCROP | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
-
-#if defined(FLASH_OPTR_DBANK)
-#define IS_OB_WRPAREA(VALUE) \
- (((VALUE) == OB_WRPAREA_BANK1_AREAA) || \
- ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
- ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
-#else
-#define IS_OB_WRPAREA(VALUE) \
- (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
-#endif
-
-#define IS_OB_BOOT_LOCK(VALUE) \
- (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
-
-#define IS_OB_RDP_LEVEL(LEVEL) \
- (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1) || \
- ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
-
-#define IS_OB_USER_BOR_LEVEL(LEVEL) \
- (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
- ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
- ((LEVEL) == OB_BOR_LEVEL_4))
-
-#define IS_OB_USER_STOP(VALUE) \
- (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
-
-#define IS_OB_USER_STANDBY(VALUE) \
- (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
-
-#define IS_OB_USER_SHUTDOWN(VALUE) \
- (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
-
-#define IS_OB_USER_IWDG(VALUE) \
- (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
-
-#define IS_OB_USER_IWDG_STOP(VALUE) \
- (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
-
-#define IS_OB_USER_IWDG_STDBY(VALUE) \
- (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
-
-#define IS_OB_USER_WWDG(VALUE) \
- (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
-
-#if defined(FLASH_OPTR_DBANK)
-#define IS_OB_USER_BFB2(VALUE) \
- (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
-
-#define IS_OB_USER_DBANK(VALUE) \
- (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
-#endif
-
-#if defined(FLASH_OPTR_PB4_PUPEN)
-#define IS_OB_USER_PB4_PUPEN(VALUE) \
- (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
-#endif
-
-#define IS_OB_USER_BOOT1(VALUE) \
- (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
-
-#define IS_OB_USER_SRAM_PARITY(VALUE) \
- (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
-
-#define IS_OB_USER_CCMSRAM_RST(VALUE) \
- (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
-
-#define IS_OB_USER_SWBOOT0(VALUE) \
- (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
-
-#define IS_OB_USER_BOOT0(VALUE) \
- (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
-
-#define IS_OB_USER_NRST_MODE(VALUE) \
- (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
- ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
-
-#define IS_OB_USER_IRHEN(VALUE) \
- (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
-
-#define IS_OB_PCROP_RDP(VALUE) \
- (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
-
-#define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
-
-#define IS_FLASH_LATENCY(LATENCY) \
- (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
- ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
- ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
- ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
- ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_FLASH_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_flash.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_FLASH_H
+#define STM32G4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct {
+ uint32_t
+ TypeErase; /*!< Mass erase or page erase.
+ This parameter can be a value of @ref FLASH_Type_Erase */
+ uint32_t Banks; /*!< Select bank to erase.
+ This parameter must be a value of @ref FLASH_Banks
+ (FLASH_BANK_BOTH should be used only for mass erase) */
+ uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled.
+ This parameter must be a value between 0 and (max number
+ of pages in the bank - 1) (eg : 127 for 512KB dual bank) */
+ uint32_t NbPages; /*!< Number of pages to be erased.
+ This parameter must be a value between 1 and (max
+ number of pages in the bank - value of initial page)*/
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Option Bytes Program structure definition
+ */
+typedef struct {
+ uint32_t OptionType; /*!< Option byte to be configured.
+ This parameter can be a combination of the values of
+ @ref FLASH_OB_Type */
+ uint32_t WRPArea; /*!< Write protection area to be programmed (used for
+ OPTIONBYTE_WRP). Only one WRP area could be programmed
+ at the same time. This parameter can be value of
+ @ref FLASH_OB_WRP_Area */
+ uint32_t
+ WRPStartOffset; /*!< Write protection start offset (used for
+ OPTIONBYTE_WRP). This parameter must be a value between
+ 0 and (max number of pages in the bank - 1) */
+ uint32_t
+ WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
+ This parameter must be a value between WRPStartOffset
+ and (max number of pages in the bank - 1) */
+ uint32_t RDPLevel; /*!< Set the read protection level.. (used for
+ OPTIONBYTE_RDP). This parameter can be a value of @ref
+ FLASH_OB_Read_Protection */
+ uint32_t USERType; /*!< User option byte(s) to be configured (used for
+ OPTIONBYTE_USER). This parameter can be a combination of
+ @ref FLASH_OB_USER_Type */
+ uint32_t
+ USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
+ This parameter can be a combination of @ref
+ FLASH_OB_USER_BOR_LEVEL,
+ @ref FLASH_OB_USER_nRST_STOP, @ref
+ FLASH_OB_USER_nRST_STANDBY,
+ @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref
+ FLASH_OB_USER_IWDG_SW,
+ @ref FLASH_OB_USER_IWDG_STOP, @ref
+ FLASH_OB_USER_IWDG_STANDBY,
+ @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
+ @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
+ @ref FLASH_OB_USER_CCMSRAM_RST
+ @note (*) availability depends on devices */
+ uint32_t
+ PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
+ This parameter must be a combination of @ref FLASH_Banks
+ (except FLASH_BANK_BOTH) and @ref FLASH_OB_PCROP_RDP */
+ uint32_t
+ PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+ This parameter must be a value between begin and end
+ of bank
+ => Be careful of the bank swapping for the address */
+ uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+ This parameter must be a value between PCROP Start
+ address and end of bank */
+ uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for
+ OPTIONBYTE_BOOT_LOCK). This parameter can be a
+ value of @ref FLASH_OB_Boot_Lock */
+ uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used
+ for OPTIONBYTE_SEC). Only one securable memory area could
+ be programmed at the same time. This parameter can be one
+ of the following values: FLASH_BANK_1: Securable memory
+ area to be programmed in bank 1 FLASH_BANK_2: Securable
+ memory area to be programmed in bank 2 (*)
+ @note (*) availability depends on devices */
+ uint32_t SecSize; /*!< Size of securable memory area to be programmed (used
+ for OPTIONBYTE_SEC), in number of pages. Securable memory
+ area is starting from first page of the bank. Only one
+ securable memory could be programmed at the same time.
+ This parameter must be a value between 0 and (max
+ number of pages in the bank - 1) */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum {
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_PAGE_ERASE,
+ FLASH_PROC_MASS_ERASE,
+ FLASH_PROC_PROGRAM,
+ FLASH_PROC_PROGRAM_LAST
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH Cache structure definition
+ */
+typedef enum {
+ FLASH_CACHE_DISABLED = 0,
+ FLASH_CACHE_ICACHE_ENABLED,
+ FLASH_CACHE_DCACHE_ENABLED,
+ FLASH_CACHE_ICACHE_DCACHE_ENABLED
+} FLASH_CacheTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct {
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+ __IO uint32_t ErrorCode; /* FLASH error code */
+ __IO FLASH_ProcedureTypeDef
+ ProcedureOnGoing; /* Internal variable to indicate which procedure is
+ ongoing or not in IT context */
+ __IO uint32_t Address; /* Internal variable to save address selected for
+ program in IT context */
+ __IO uint32_t Bank; /* Internal variable to save current bank selected during
+ erase in IT context */
+ __IO uint32_t Page; /* Internal variable to define the current page which is
+ erasing in IT context */
+ __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages
+ to erase in IT context */
+ __IO FLASH_CacheTypeDef
+ CacheToReactivate; /* Internal variable to indicate which caches should be
+ reactivated */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error FLASH Error
+ * @{
+ */
+#define HAL_FLASH_ERROR_NONE 0x00000000U
+#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
+#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
+#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
+#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
+#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
+#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
+#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
+#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
+#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
+#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
+#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
+#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
+#if defined(FLASH_OPTR_DBANK)
+#define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2
+#define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Erase FLASH Erase Type
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE 0x01U /*!<Flash mass erase activation*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Banks FLASH Banks
+ * @{
+ */
+#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
+#if defined(FLASH_OPTR_DBANK)
+#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
+#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+#else
+#define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Program Type
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD \
+ 0x00U /*!< Program a double-word (64-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_FAST \
+ 0x01U /*!< Fast program a 32 row double-word (64-bit) at a specified \
+ address. And another 32 row double-word (64-bit) will be programmed \
+ */
+#define FLASH_TYPEPROGRAM_FAST_AND_LAST \
+ 0x02U /*!< Fast program a 32 row double-word (64-bit) at a specified \
+ address. And this is the last 32 row double-word (64-bit) \
+ programmed */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOOT_LOCK 0x10U /*!< Boot lock option byte configuration */
+#define OPTIONBYTE_SEC \
+ 0x20U /*!< Securable memory option byte configuration \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
+ * @{
+ */
+#define OB_WRPAREA_BANK1_AREAA 0x00U /*!< Flash Bank 1 Area A */
+#define OB_WRPAREA_BANK1_AREAB 0x01U /*!< Flash Bank 1 Area B */
+#if defined(FLASH_OPTR_DBANK)
+#define OB_WRPAREA_BANK2_AREAA 0x02U /*!< Flash Bank 2 Area A */
+#define OB_WRPAREA_BANK2_AREAB 0x04U /*!< Flash Bank 2 Area B */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
+ * @{
+ */
+#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot Lock Disable */
+#define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK /*!< Boot Lock Enable */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 0xAAU
+#define OB_RDP_LEVEL_1 0xBBU
+#define OB_RDP_LEVEL_2 \
+ 0xCCU /*!< Warning: When enabling read protection level 2 \
+ it's no more possible to go back to level 1 or 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
+ * @{
+ */
+#define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */
+#define OB_USER_nRST_STOP \
+ 0x00000002U /*!< Reset generated when entering the stop mode */
+#define OB_USER_nRST_STDBY \
+ 0x00000004U /*!< Reset generated when entering the standby mode */
+#define OB_USER_IWDG_SW 0x00000008U /*!< Independent watchdog selection */
+#define OB_USER_IWDG_STOP \
+ 0x00000010U /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY \
+ 0x00000020U /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_WWDG_SW 0x00000040U /*!< Window watchdog selection */
+#if defined(FLASH_OPTR_DBANK)
+#define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */
+#define OB_USER_DBANK \
+ 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits \
+ data */
+#endif
+#if defined(FLASH_OPTR_PB4_PUPEN)
+#define OB_USER_PB4_PUPEN \
+ 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */
+#endif
+#define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */
+#define OB_USER_SRAM_PE \
+ 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) \
+ */
+#define OB_USER_CCMSRAM_RST \
+ 0x00000800U /*!< CCMSRAM Erase when system reset \
+ */
+#define OB_USER_nRST_SHDW \
+ 0x00001000U /*!< Reset generated when entering the shutdown mode */
+#define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */
+#define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */
+#define OB_USER_NRST_MODE 0x00008000U /*!< Reset pin configuration */
+#define OB_USER_IRHEN 0x00010000U /*!< Internal Reset Holder enable */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
+ * @{
+ */
+#define OB_BOR_LEVEL_0 \
+ FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */
+#define OB_BOR_LEVEL_1 \
+ FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */
+#define OB_BOR_LEVEL_2 \
+ FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */
+#define OB_BOR_LEVEL_3 \
+ FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */
+#define OB_BOR_LEVEL_4 \
+ FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
+ * @{
+ */
+#define OB_STOP_RST \
+ 0x00000000U /*!< Reset generated when entering the stop mode */
+#define OB_STOP_NORST \
+ FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On
+ * Standby
+ * @{
+ */
+#define OB_STANDBY_RST \
+ 0x00000000U /*!< Reset generated when entering the standby mode */
+#define OB_STANDBY_NORST \
+ FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On
+ * Shutdown
+ * @{
+ */
+#define OB_SHUTDOWN_RST \
+ 0x00000000U /*!< Reset generated when entering the shutdown mode */
+#define OB_SHUTDOWN_NORST \
+ FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
+ * @{
+ */
+#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
+#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
+ * @{
+ */
+#define OB_IWDG_STOP_FREEZE \
+ 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
+#define OB_IWDG_STOP_RUN \
+ FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop \
+ mode */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On
+ * Standby
+ * @{
+ */
+#define OB_IWDG_STDBY_FREEZE \
+ 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
+#define OB_IWDG_STDBY_RUN \
+ FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in \
+ Standby mode */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
+ * @{
+ */
+#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
+#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
+/**
+ * @}
+ */
+
+#if defined(FLASH_OPTR_DBANK)
+/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
+ * @{
+ */
+#define OB_BFB2_DISABLE 0x00000000U /*!< Dual-bank boot disable */
+#define OB_BFB2_ENABLE FLASH_OPTR_BFB2 /*!< Dual-bank boot enable */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
+ * @{
+ */
+#define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */
+#define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */
+/**
+ * @}
+ */
+#endif
+
+#if defined(FLASH_OPTR_PB4_PUPEN)
+/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
+ * @{
+ */
+#define OB_PB4_PUPEN_DISABLE \
+ 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up \
+ deactivated */
+#define OB_PB4_PUPEN_ENABLE \
+ FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI \
+ pull-up activated */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
+ * @{
+ */
+#define OB_BOOT1_SRAM \
+ 0x00000000U /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
+#define OB_BOOT1_SYSTEM \
+ FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check
+ * Type
+ * @{
+ */
+#define OB_SRAM_PARITY_ENABLE \
+ 0x00000000U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) \
+ */
+#define OB_SRAM_PARITY_DISABLE \
+ FLASH_OPTR_SRAM_PE /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM \
+ SRAM) */
+/**
+ * @}
+ */
+/** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On
+ * Reset Type
+ * @{
+ */
+#define OB_CCMSRAM_RST_ERASE \
+ 0x00000000U /*!< CCMSRAM erased when a system reset occurs */
+#define OB_CCMSRAM_RST_NOT_ERASE \
+ FLASH_OPTR_CCMSRAM_RST /*!< CCMSRAM is not erased when a system reset occurs \
+ */
+/**
+ * @}
+ */
+/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
+ * @{
+ */
+#define OB_BOOT0_FROM_OB \
+ 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
+#define OB_BOOT0_FROM_PIN \
+ FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PB8/BOOT0 pin */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
+ * @{
+ */
+#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
+#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
+ * @{
+ */
+#define OB_NRST_MODE_INPUT_ONLY \
+ FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */
+#define OB_NRST_MODE_GPIO \
+ FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode only */
+#define OB_NRST_MODE_INPUT_OUTPUT \
+ FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User
+ * internal reset holder bit
+ * @{
+ */
+#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset holder disable */
+#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset holder enable */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
+ * @{
+ */
+#define OB_PCROP_RDP_NOT_ERASE \
+ 0x00000000U /*!< PCROP area is not erased when the RDP level \
+ is decreased from Level 1 to Level 0 */
+#define OB_PCROP_RDP_ERASE \
+ FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is \
+ decreased from Level 1 to Level 0 (full mass \
+ erase) */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */
+#define FLASH_LATENCY_11 \
+ FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state \
+ */
+#define FLASH_LATENCY_12 \
+ FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states \
+ */
+#define FLASH_LATENCY_13 \
+ FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */
+#define FLASH_LATENCY_14 \
+ FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */
+#define FLASH_LATENCY_15 \
+ FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Keys FLASH Keys
+ * @{
+ */
+#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
+#define FLASH_KEY2 \
+ 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 \
+ to unlock the FLASH registers access */
+
+#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
+#define FLASH_PDKEY2 \
+ 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 \
+ to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
+#define FLASH_OPTKEY2 \
+ 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 \
+ to allow option bytes operations */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags FLASH Flags Definition
+ * @{
+ */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
+#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
+#define FLASH_FLAG_PROGERR \
+ FLASH_SR_PROGERR /*!< FLASH Programming error flag \
+ */
+#define FLASH_FLAG_WRPERR \
+ FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
+#define FLASH_FLAG_PGAERR \
+ FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
+#define FLASH_FLAG_PGSERR \
+ FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
+#define FLASH_FLAG_MISERR \
+ FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
+#define FLASH_FLAG_FASTERR \
+ FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
+#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
+#define FLASH_FLAG_OPTVERR \
+ FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_ECCC \
+ FLASH_ECCR_ECCC /*!< FLASH ECC correction in 64 LSB bits */
+#define FLASH_FLAG_ECCD \
+ FLASH_ECCR_ECCD /*!< FLASH ECC detection in 64 LSB bits */
+#if defined(FLASH_OPTR_DBANK)
+#define FLASH_FLAG_ECCC2 \
+ FLASH_ECCR_ECCC2 /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits \
+ only) */
+#define FLASH_FLAG_ECCD2 \
+ FLASH_ECCR_ECCD2 /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits \
+ only) */
+#endif
+
+#define FLASH_FLAG_SR_ERRORS \
+ (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
+ FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
+ FLASH_FLAG_OPTVERR)
+#if defined(FLASH_OPTR_DBANK)
+#define FLASH_FLAG_ECCR_ERRORS \
+ (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD | FLASH_FLAG_ECCC2 | FLASH_FLAG_ECCD2)
+#else
+#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
+#endif
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#define FLASH_IT_EOP \
+ FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
+#define FLASH_IT_RDERR \
+ FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt \
+ source*/
+#define FLASH_IT_ECCC \
+ (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @brief macros to control FLASH features
+ * @{
+ */
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__ FLASH Latency.
+ * This parameter can be one of the following values :
+ * @arg FLASH_LATENCY_0: FLASH Zero wait state
+ * @arg FLASH_LATENCY_1: FLASH One wait state
+ * @arg FLASH_LATENCY_2: FLASH Two wait states
+ * @arg FLASH_LATENCY_3: FLASH Three wait states
+ * @arg FLASH_LATENCY_4: FLASH Four wait states
+ * @arg FLASH_LATENCY_5: FLASH Five wait states
+ * @arg FLASH_LATENCY_6: FLASH Six wait states
+ * @arg FLASH_LATENCY_7: FLASH Seven wait states
+ * @arg FLASH_LATENCY_8: FLASH Eight wait states
+ * @arg FLASH_LATENCY_9: FLASH Nine wait states
+ * @arg FLASH_LATENCY_10: FLASH Ten wait state
+ * @arg FLASH_LATENCY_11: FLASH Eleven wait state
+ * @arg FLASH_LATENCY_12: FLASH Twelve wait states
+ * @arg FLASH_LATENCY_13: FLASH Thirteen wait states
+ * @arg FLASH_LATENCY_14: FLASH Fourteen wait states
+ * @arg FLASH_LATENCY_15: FLASH Fifteen wait states
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH_Latency.
+ * This parameter can be one of the following values :
+ * @arg FLASH_LATENCY_0: FLASH Zero wait state
+ * @arg FLASH_LATENCY_1: FLASH One wait state
+ * @arg FLASH_LATENCY_2: FLASH Two wait states
+ * @arg FLASH_LATENCY_3: FLASH Three wait states
+ * @arg FLASH_LATENCY_4: FLASH Four wait states
+ * @arg FLASH_LATENCY_5: FLASH Five wait states
+ * @arg FLASH_LATENCY_6: FLASH Six wait states
+ * @arg FLASH_LATENCY_7: FLASH Seven wait states
+ * @arg FLASH_LATENCY_8: FLASH Eight wait states
+ * @arg FLASH_LATENCY_9: FLASH Nine wait states
+ * @arg FLASH_LATENCY_10: FLASH Ten wait state
+ * @arg FLASH_LATENCY_11: FLASH Eleven wait state
+ * @arg FLASH_LATENCY_12: FLASH Twelve wait states
+ * @arg FLASH_LATENCY_13: FLASH Thirteen wait states
+ * @arg FLASH_LATENCY_14: FLASH Fourteen wait states
+ * @arg FLASH_LATENCY_15: FLASH Fifteen wait states
+ */
+#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() \
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Enable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() \
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+ * @brief Disable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+ * @brief Enable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+ * @brief Disable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+ * @brief Reset the FLASH instruction Cache.
+ * @note This function must be used only when the Instruction Cache is
+ * disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() \
+ do { \
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
+ } while (0)
+
+/**
+ * @brief Reset the FLASH data Cache.
+ * @note This function must be used only when the data Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_DATA_CACHE_RESET() \
+ do { \
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
+ } while (0)
+
+/**
+ * @brief Enable the FLASH power down during Low-power run mode.
+ * @note Writing this bit to 1, automatically the keys are
+ * lost and a new unlock sequence is necessary to re-write it to 0.
+ */
+#define __HAL_FLASH_POWER_DOWN_ENABLE() \
+ do { \
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+ SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+ } while (0)
+
+/**
+ * @brief Disable the FLASH power down during Low-power run mode.
+ * @note Writing this bit to 0, automatically the keys are
+ * lost and a new unlock sequence is necessary to re-write it to 1.
+ */
+#define __HAL_FLASH_POWER_DOWN_DISABLE() \
+ do { \
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+ } while (0)
+
+/**
+ * @brief Enable the FLASH power down during Low-Power sleep mode
+ * @retval none
+ */
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() \
+ SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+ * @brief Disable the FLASH power down during Low-Power sleep mode
+ * @retval none
+ */
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) \
+ do { \
+ if (((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { \
+ SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); \
+ } \
+ if (((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { \
+ SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); \
+ } \
+ } while (0)
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) \
+ do { \
+ if (((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { \
+ CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); \
+ } \
+ if (((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { \
+ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); \
+ } \
+ } while (0)
+
+/**
+ * @brief Check whether the specified FLASH flag is set or not.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+ * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+ * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * in 64 LSB bits
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB
+ * bits
+ * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and
+ * corrected in 64 MSB bits (mode 128 bits only)
+ * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64
+ * MSB bits (mode 128 bits only)
+ * @note (*) availability depends on devices
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) \
+ ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \
+ ? (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) \
+ : (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
+
+/**
+ * @brief Clear the FLASH's pending flags.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+ * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+ * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * in 64 LSB bits
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB
+ * bits
+ * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and
+ * corrected in 64 MSB bits (mode 128 bits only)
+ * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64
+ * MSB bits (mode 128 bits only)
+ * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
+ * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
+ * @note (*) availability depends on devices
+ * @retval None
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \
+ do { \
+ if (((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { \
+ SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); \
+ } \
+ if (((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { \
+ WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); \
+ } \
+ } while (0)
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32g4xx_hal_flash_ex.h"
+#include "stm32g4xx_hal_flash_ramfunc.h"
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
+ * @{
+ */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/* Program operation functions ***********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address,
+ uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address,
+ uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+uint32_t HAL_FLASH_GetError(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
+
+#if defined(FLASH_OPTR_DBANK)
+#define FLASH_SIZE \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) \
+ ? (0x200UL << 10U) \
+ : (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
+#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
+#define FLASH_PAGE_NB \
+ ((FLASH_SIZE == 0x00080000U) ? 128U \
+ : ((FLASH_SIZE == 0x00040000U) ? 64U : 32U))
+#define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */
+#else
+#define FLASH_SIZE \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) \
+ ? (0x80UL << 10U) \
+ : (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
+#define FLASH_BANK_SIZE (FLASH_SIZE)
+#define FLASH_PAGE_NB \
+ ((FLASH_SIZE == 0x00080000U) ? 256U \
+ : ((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
+#endif
+
+#define FLASH_PAGE_SIZE 0x800U /* 2 KB */
+
+#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE) \
+ (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#if defined(FLASH_OPTR_DBANK)
+#define IS_FLASH_BANK(BANK) \
+ (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK) \
+ (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2))
+#else
+#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
+#endif
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) \
+ (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) \
+ (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
+
+#define IS_FLASH_OTP_ADDRESS(ADDRESS) \
+ (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
+ (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
+
+#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
+
+#define IS_OPTIONBYTE(VALUE) \
+ (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
+ OPTIONBYTE_PCROP | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
+
+#if defined(FLASH_OPTR_DBANK)
+#define IS_OB_WRPAREA(VALUE) \
+ (((VALUE) == OB_WRPAREA_BANK1_AREAA) || \
+ ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
+ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
+#else
+#define IS_OB_WRPAREA(VALUE) \
+ (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
+#endif
+
+#define IS_OB_BOOT_LOCK(VALUE) \
+ (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL) \
+ (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1) || \
+ ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
+
+#define IS_OB_USER_BOR_LEVEL(LEVEL) \
+ (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
+ ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
+ ((LEVEL) == OB_BOR_LEVEL_4))
+
+#define IS_OB_USER_STOP(VALUE) \
+ (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
+
+#define IS_OB_USER_STANDBY(VALUE) \
+ (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
+
+#define IS_OB_USER_SHUTDOWN(VALUE) \
+ (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
+
+#define IS_OB_USER_IWDG(VALUE) \
+ (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
+
+#define IS_OB_USER_IWDG_STOP(VALUE) \
+ (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE) \
+ (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
+
+#define IS_OB_USER_WWDG(VALUE) \
+ (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
+
+#if defined(FLASH_OPTR_DBANK)
+#define IS_OB_USER_BFB2(VALUE) \
+ (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
+
+#define IS_OB_USER_DBANK(VALUE) \
+ (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
+#endif
+
+#if defined(FLASH_OPTR_PB4_PUPEN)
+#define IS_OB_USER_PB4_PUPEN(VALUE) \
+ (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
+#endif
+
+#define IS_OB_USER_BOOT1(VALUE) \
+ (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
+
+#define IS_OB_USER_SRAM_PARITY(VALUE) \
+ (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
+
+#define IS_OB_USER_CCMSRAM_RST(VALUE) \
+ (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
+
+#define IS_OB_USER_SWBOOT0(VALUE) \
+ (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
+
+#define IS_OB_USER_BOOT0(VALUE) \
+ (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
+
+#define IS_OB_USER_NRST_MODE(VALUE) \
+ (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
+ ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
+
+#define IS_OB_USER_IRHEN(VALUE) \
+ (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
+
+#define IS_OB_PCROP_RDP(VALUE) \
+ (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
+
+#define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
+
+#define IS_FLASH_LATENCY(LATENCY) \
+ (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
+ ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
+ ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
+ ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
+ ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_FLASH_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
index 063010a..15a5e9d 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
@@ -1,89 +1,89 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_flash_ex.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_FLASH_EX_H
-#define STM32G4xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
- * @{
- */
-
-/* Extended Program operation functions *************************************/
-/** @addtogroup FLASHEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit,
- uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
-void HAL_FLASHEx_EnableDebugger(void);
-void HAL_FLASHEx_DisableDebugger(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-void FLASH_PageErase(uint32_t Page, uint32_t Banks);
-void FLASH_FlushCaches(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_FLASH_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_FLASH_EX_H
+#define STM32G4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/* Extended Program operation functions *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit,
+ uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
+void HAL_FLASHEx_EnableDebugger(void);
+void HAL_FLASHEx_DisableDebugger(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks);
+void FLASH_FlushCaches(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_FLASH_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
index bc4aba0..db75f10 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
@@ -1,74 +1,74 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_flash_ramfunc.h
- * @author MCD Application Team
- * @brief Header file of FLASH RAMFUNC driver.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_FLASH_RAMFUNC_H
-#define STM32G4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH_RAMFUNC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
- * @{
- */
-/* Peripheral Control functions
- * ************************************************/
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
-#if defined(FLASH_OPTR_DBANK)
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_FLASH_RAMFUNC_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_flash_ramfunc.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH RAMFUNC driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_FLASH_RAMFUNC_H
+#define STM32G4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH_RAMFUNC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+ * @{
+ */
+/* Peripheral Control functions
+ * ************************************************/
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
+#if defined(FLASH_OPTR_DBANK)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_FLASH_RAMFUNC_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
index ec6b29c..34a2a5d 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
@@ -1,356 +1,356 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_GPIO_H
-#define STM32G4xx_HAL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIO GPIO
- * @brief GPIO HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
- * @{
- */
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct {
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_mode */
-
- uint32_t
- Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected
- pins. This parameter can be a value of @ref GPIO_pull */
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_speed */
-
- uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
- This parameter can be a value of @ref
- GPIOEx_Alternate_function_selection */
-} GPIO_InitTypeDef;
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
- * @{
- */
-/** @defgroup GPIO_pins GPIO pins
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
-/**
- * @}
- */
-
-/** @defgroup GPIO_mode GPIO mode
- * @brief GPIO Configuration Mode
- * Elements values convention: 0x00WX00YZ
- * - W : EXTI trigger detection on 3 bits
- * - X : EXTI mode (IT or Event) on 2 bits
- * - Y : Output type (Push Pull or Open Drain) on 1 bit
- * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
- * @{
- */
-#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP \
- (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD \
- (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP \
- (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD \
- (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
-
-#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING \
- (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with \
- Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING \
- (MODE_INPUT | EXTI_IT | \
- TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger \
- detection */
-#define GPIO_MODE_IT_RISING_FALLING \
- (MODE_INPUT | EXTI_IT | TRIGGER_RISING | \
- TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge \
- trigger detection */
-
-#define GPIO_MODE_EVT_RISING \
- (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with \
- Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING \
- (MODE_INPUT | EXTI_EVT | \
- TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger \
- detection */
-#define GPIO_MODE_EVT_RISING_FALLING \
- (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | \
- TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger \
- detection */
-/**
- * @}
- */
-
-/** @defgroup GPIO_speed GPIO speed
- * @brief GPIO Output Maximum frequency
- * @{
- */
-#define GPIO_SPEED_FREQ_LOW \
- (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet \
- */
-#define GPIO_SPEED_FREQ_MEDIUM \
- (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product \
- datasheet */
-#define GPIO_SPEED_FREQ_HIGH \
- (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product \
- datasheet */
-#define GPIO_SPEED_FREQ_VERY_HIGH \
- (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product \
- datasheet */
-/**
- * @}
- */
-
-/** @defgroup GPIO_pull GPIO pull
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
-#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/**
- * @brief Check whether the specified EXTI line flag is set or not.
- * @param __EXTI_LINE__ specifies the EXTI line flag to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
- * @brief Clear the EXTI's line pending flags.
- * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be
- * (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
- * @brief Check whether the specified EXTI line is asserted or not.
- * @param __EXTI_LINE__ specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
- * @brief Clear the EXTI's line pending bits.
- * @param __EXTI_LINE__ specifies the EXTI lines to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be
- * (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__ specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
- (EXTI->SWIER1 |= (__EXTI_LINE__))
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_MODE_Pos 0U
-#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
-#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
-#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
-#define MODE_AF (0x2UL << GPIO_MODE_Pos)
-#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos 4U
-#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos 16U
-#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
-#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
-#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos 20U
-#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) \
- (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(__PIN__) \
- ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) && \
- (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
-
-#define IS_GPIO_MODE(__MODE__) \
- (((__MODE__) == GPIO_MODE_INPUT) || ((__MODE__) == GPIO_MODE_OUTPUT_PP) || \
- ((__MODE__) == GPIO_MODE_OUTPUT_OD) || ((__MODE__) == GPIO_MODE_AF_PP) || \
- ((__MODE__) == GPIO_MODE_AF_OD) || ((__MODE__) == GPIO_MODE_IT_RISING) || \
- ((__MODE__) == GPIO_MODE_IT_FALLING) || \
- ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) || \
- ((__MODE__) == GPIO_MODE_EVT_RISING) || \
- ((__MODE__) == GPIO_MODE_EVT_FALLING) || \
- ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) || \
- ((__MODE__) == GPIO_MODE_ANALOG))
-
-#define IS_GPIO_SPEED(__SPEED__) \
- (((__SPEED__) == GPIO_SPEED_FREQ_LOW) || \
- ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) || \
- ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) || \
- ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_GPIO_PULL(__PULL__) \
- (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || \
- ((__PULL__) == GPIO_PULLDOWN))
-/**
- * @}
- */
-
-/* Include GPIO HAL Extended module */
-#include "stm32g4xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
- * @brief GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization
- * functions
- * @brief Initialization and Configuration functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
- GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_GPIO_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_GPIO_H
+#define STM32G4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct {
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode */
+
+ uint32_t
+ Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected
+ pins. This parameter can be a value of @ref GPIO_pull */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref
+ GPIOEx_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+/** @defgroup GPIO_pins GPIO pins
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode GPIO mode
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0x00WX00YZ
+ * - W : EXTI trigger detection on 3 bits
+ * - X : EXTI mode (IT or Event) on 2 bits
+ * - Y : Output type (Push Pull or Open Drain) on 1 bit
+ * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
+ * @{
+ */
+#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP \
+ (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD \
+ (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP \
+ (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD \
+ (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING \
+ (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with \
+ Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING \
+ (MODE_INPUT | EXTI_IT | \
+ TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger \
+ detection */
+#define GPIO_MODE_IT_RISING_FALLING \
+ (MODE_INPUT | EXTI_IT | TRIGGER_RISING | \
+ TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge \
+ trigger detection */
+
+#define GPIO_MODE_EVT_RISING \
+ (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with \
+ Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING \
+ (MODE_INPUT | EXTI_EVT | \
+ TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger \
+ detection */
+#define GPIO_MODE_EVT_RISING_FALLING \
+ (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | \
+ TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger \
+ detection */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed GPIO speed
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW \
+ (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet \
+ */
+#define GPIO_SPEED_FREQ_MEDIUM \
+ (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product \
+ datasheet */
+#define GPIO_SPEED_FREQ_HIGH \
+ (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product \
+ datasheet */
+#define GPIO_SPEED_FREQ_VERY_HIGH \
+ (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product \
+ datasheet */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_pull GPIO pull
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
+#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending flags.
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__ specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending bits.
+ * @param __EXTI_LINE__ specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__ specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
+ (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+#define GPIO_MODE_Pos 0U
+#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
+#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
+#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
+#define MODE_AF (0x2UL << GPIO_MODE_Pos)
+#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos 4U
+#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos 16U
+#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
+#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
+#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos 20U
+#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) \
+ (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__) \
+ ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) && \
+ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+
+#define IS_GPIO_MODE(__MODE__) \
+ (((__MODE__) == GPIO_MODE_INPUT) || ((__MODE__) == GPIO_MODE_OUTPUT_PP) || \
+ ((__MODE__) == GPIO_MODE_OUTPUT_OD) || ((__MODE__) == GPIO_MODE_AF_PP) || \
+ ((__MODE__) == GPIO_MODE_AF_OD) || ((__MODE__) == GPIO_MODE_IT_RISING) || \
+ ((__MODE__) == GPIO_MODE_IT_FALLING) || \
+ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) || \
+ ((__MODE__) == GPIO_MODE_EVT_RISING) || \
+ ((__MODE__) == GPIO_MODE_EVT_FALLING) || \
+ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) || \
+ ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__) \
+ (((__SPEED__) == GPIO_SPEED_FREQ_LOW) || \
+ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) || \
+ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) || \
+ ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__) \
+ (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || \
+ ((__PULL__) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extended module */
+#include "stm32g4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @brief GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization
+ * functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
+ GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_GPIO_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
index 6ddbdfa..0764638 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
@@ -1,403 +1,403 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_gpio_ex.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_GPIO_EX_H
-#define STM32G4xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @brief GPIO Extended HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
- * @{
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function
- * selection
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz \
- ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO \
- ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ \
- ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#if defined(TIM5)
-#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
-#endif /* TIM5 */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_TIM17_COMP1 \
- ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 \
- ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping \
- */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#if defined(TIM5)
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-#endif /* TIM5 */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
-#if defined(TIM20)
-#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
-#endif /* TIM20 */
-#define GPIO_AF2_TIM1_COMP1 \
- ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF2_TIM15_COMP1 \
- ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF2_TIM16_COMP1 \
- ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
-#if defined(TIM20)
-#define GPIO_AF2_TIM20_COMP1 \
- ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF2_TIM20_COMP2 \
- ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */
-#endif /* TIM20 */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
-#if defined(TIM20)
-#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
-#endif /* TIM20 */
-#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
-#if defined(I2C4)
-#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
-#endif /* I2C4 */
-#if defined(HRTIM1)
-#define GPIO_AF3_HRTIM1 \
- ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping \
- */
-#endif /* HRTIM1 */
-#if defined(QUADSPI)
-#define GPIO_AF3_QUADSPI \
- ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
-#endif /* QUADSPI */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
-#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_TIM8_COMP1 \
- ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#if defined(I2C4)
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#endif /* I2C4 */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 \
- ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 \
- ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#if defined(SPI4)
-#define GPIO_AF5_SPI4 \
- ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
-#endif /* SPI4 */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_TIM8 \
- ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_TIM8_COMP1 \
- ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF5_UART4 \
- ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#if defined(UART5)
-#define GPIO_AF5_UART5 \
- ((uint8_t)0x05) /* UART5 Alternate Function mapping */
-#endif /* UART5 */
-#define GPIO_AF5_I2S2ext \
- ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 \
- ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 \
- ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-#define GPIO_AF6_TIM1 \
- ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#if defined(TIM5)
-#define GPIO_AF6_TIM5 \
- ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
-#endif /* TIM5 */
-#define GPIO_AF6_TIM8 \
- ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
-#if defined(TIM20)
-#define GPIO_AF6_TIM20 \
- ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
-#endif /* TIM20 */
-#define GPIO_AF6_TIM1_COMP1 \
- ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF6_TIM1_COMP2 \
- ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF6_TIM8_COMP2 \
- ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_I2S3ext \
- ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 \
- ((uint8_t)0x07) /* USART1 Alternate Function mapping \
- */
-#define GPIO_AF7_USART2 \
- ((uint8_t)0x07) /* USART2 Alternate Function mapping \
- */
-#define GPIO_AF7_USART3 \
- ((uint8_t)0x07) /* USART3 Alternate Function mapping \
- */
-#if defined(COMP5)
-#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */
-#endif /* COMP7 */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#if defined(COMP5)
-#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */
-#endif /* COMP7 */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
-#if defined(I2C4)
-#define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */
-#endif /* I2C4 */
-#define GPIO_AF8_LPUART1 \
- ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#if defined(UART5)
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#endif /* UART5 */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
-#define GPIO_AF9_TIM1_COMP1 \
- ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF9_TIM8_COMP1 \
- ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF9_TIM15_COMP1 \
- ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF9_FDCAN1 \
- ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping \
- */
-#if defined(FDCAN2)
-#define GPIO_AF9_FDCAN2 \
- ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping \
- */
-#endif /* FDCAN2 */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
-#define GPIO_AF10_TIM8_COMP2 \
- ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF10_TIM17_COMP1 \
- ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
-#if defined(QUADSPI)
-#define GPIO_AF10_QUADSPI \
- ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#endif /* QUADSPI */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_FDCAN1 \
- ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
-#if defined(FDCAN3)
-#define GPIO_AF11_FDCAN3 \
- ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
-#endif /* FDCAN3 */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
-#define GPIO_AF11_TIM8_COMP1 \
- ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF11_LPTIM1 \
- ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_LPUART1 \
- ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP1 \
- ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP2 \
- ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
-#if defined(HRTIM1)
-#define GPIO_AF12_HRTIM1 \
- ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
-#endif /* HRTIM1 */
-#if defined(FMC_BANK1)
-#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
-#endif /* FMC_BANK1 */
-#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#if defined(HRTIM1)
-#define GPIO_AF13_HRTIM1 \
- ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
-#endif /* HRTIM1 */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
-#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
-#define GPIO_AF14_UART4 \
- ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
-#if defined(UART5)
-#define GPIO_AF14_UART5 \
- ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
-#endif /* UART5 */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT \
- ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
- * @{
- */
-
-/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
- * @{
- */
-#define GPIO_GET_INDEX(__GPIOx__) \
- (((__GPIOx__) == (GPIOA)) ? 0UL \
- : ((__GPIOx__) == (GPIOB)) ? 1UL \
- : ((__GPIOx__) == (GPIOC)) ? 2UL \
- : ((__GPIOx__) == (GPIOD)) ? 3UL \
- : ((__GPIOx__) == (GPIOE)) ? 4UL \
- : ((__GPIOx__) == (GPIOF)) ? 5UL \
- : 6UL)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_GPIO_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_GPIO_EX_H
+#define STM32G4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function
+ * selection
+ * @{
+ */
+
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz \
+ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO \
+ ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_SWJ \
+ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#if defined(TIM5)
+#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
+#endif /* TIM5 */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_TIM17_COMP1 \
+ ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 \
+ ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping \
+ */
+#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#if defined(TIM5)
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+#endif /* TIM5 */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
+#if defined(TIM20)
+#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
+#endif /* TIM20 */
+#define GPIO_AF2_TIM1_COMP1 \
+ ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF2_TIM15_COMP1 \
+ ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF2_TIM16_COMP1 \
+ ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
+#if defined(TIM20)
+#define GPIO_AF2_TIM20_COMP1 \
+ ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF2_TIM20_COMP2 \
+ ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */
+#endif /* TIM20 */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#if defined(TIM20)
+#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
+#endif /* TIM20 */
+#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+#if defined(I2C4)
+#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
+#endif /* I2C4 */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1 \
+ ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping \
+ */
+#endif /* HRTIM1 */
+#if defined(QUADSPI)
+#define GPIO_AF3_QUADSPI \
+ ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
+#endif /* QUADSPI */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
+#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_TIM8_COMP1 \
+ ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#if defined(I2C4)
+#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
+#endif /* I2C4 */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 \
+ ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 \
+ ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
+#if defined(SPI4)
+#define GPIO_AF5_SPI4 \
+ ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#endif /* SPI4 */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_TIM8 \
+ ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_TIM8_COMP1 \
+ ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF5_UART4 \
+ ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#if defined(UART5)
+#define GPIO_AF5_UART5 \
+ ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#endif /* UART5 */
+#define GPIO_AF5_I2S2ext \
+ ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 \
+ ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 \
+ ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
+#define GPIO_AF6_TIM1 \
+ ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#if defined(TIM5)
+#define GPIO_AF6_TIM5 \
+ ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
+#endif /* TIM5 */
+#define GPIO_AF6_TIM8 \
+ ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#if defined(TIM20)
+#define GPIO_AF6_TIM20 \
+ ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
+#endif /* TIM20 */
+#define GPIO_AF6_TIM1_COMP1 \
+ ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF6_TIM1_COMP2 \
+ ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF6_TIM8_COMP2 \
+ ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_I2S3ext \
+ ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 \
+ ((uint8_t)0x07) /* USART1 Alternate Function mapping \
+ */
+#define GPIO_AF7_USART2 \
+ ((uint8_t)0x07) /* USART2 Alternate Function mapping \
+ */
+#define GPIO_AF7_USART3 \
+ ((uint8_t)0x07) /* USART3 Alternate Function mapping \
+ */
+#if defined(COMP5)
+#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */
+#endif /* COMP7 */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#if defined(COMP5)
+#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */
+#endif /* COMP7 */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+#if defined(I2C4)
+#define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */
+#endif /* I2C4 */
+#define GPIO_AF8_LPUART1 \
+ ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#if defined(UART5)
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#endif /* UART5 */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_TIM1_COMP1 \
+ ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF9_TIM8_COMP1 \
+ ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF9_TIM15_COMP1 \
+ ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF9_FDCAN1 \
+ ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping \
+ */
+#if defined(FDCAN2)
+#define GPIO_AF9_FDCAN2 \
+ ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping \
+ */
+#endif /* FDCAN2 */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM8_COMP2 \
+ ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF10_TIM17_COMP1 \
+ ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI \
+ ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
+#endif /* QUADSPI */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_FDCAN1 \
+ ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
+#if defined(FDCAN3)
+#define GPIO_AF11_FDCAN3 \
+ ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
+#endif /* FDCAN3 */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+#define GPIO_AF11_TIM8_COMP1 \
+ ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF11_LPTIM1 \
+ ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_LPUART1 \
+ ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1_COMP1 \
+ ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
+#define GPIO_AF12_TIM1_COMP2 \
+ ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
+#if defined(HRTIM1)
+#define GPIO_AF12_HRTIM1 \
+ ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#if defined(FMC_BANK1)
+#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#endif /* FMC_BANK1 */
+#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#if defined(HRTIM1)
+#define GPIO_AF13_HRTIM1 \
+ ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
+#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
+#define GPIO_AF14_UART4 \
+ ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
+#if defined(UART5)
+#define GPIO_AF14_UART5 \
+ ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
+#endif /* UART5 */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT \
+ ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
+ * @{
+ */
+#define GPIO_GET_INDEX(__GPIOx__) \
+ (((__GPIOx__) == (GPIOA)) ? 0UL \
+ : ((__GPIOx__) == (GPIOB)) ? 1UL \
+ : ((__GPIOx__) == (GPIOC)) ? 2UL \
+ : ((__GPIOx__) == (GPIOD)) ? 3UL \
+ : ((__GPIOx__) == (GPIOE)) ? 4UL \
+ : ((__GPIOx__) == (GPIOF)) ? 5UL \
+ : 6UL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_GPIO_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h
new file mode 100644
index 0000000..22983ae
--- /dev/null
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h
@@ -0,0 +1,245 @@
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_IWDG_H
+#define STM32G4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct {
+ uint32_t
+ Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and
+ Max_Data = 0x0FFF */
+
+ uint32_t Window; /*!< Specifies the window value to be compared to the
+ down-counter. This parameter must be a number between
+ Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+typedef struct {
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+} IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 \
+ (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 \
+ (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 \
+ (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+ * @{
+ */
+#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) \
+ WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Reload IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) \
+ WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE \
+ 0x00005555u /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE \
+ 0x00000000u /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) \
+ WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) \
+ WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__ IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__ IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+ * @brief Check IWDG window value.
+ * @param __WINDOW__ IWDG window value
+ * @retval None
+ */
+#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_IWDG_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
index dd4d7ee..0e90dcc 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
@@ -1,1049 +1,1041 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pcd.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_PCD_H
-#define STM32G4xx_HAL_PCD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_ll_usb.h"
-
-#if defined(USB)
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
- * @{
- */
-
-/**
- * @brief PCD State structure definition
- */
-typedef enum {
- HAL_PCD_STATE_RESET = 0x00,
- HAL_PCD_STATE_READY = 0x01,
- HAL_PCD_STATE_ERROR = 0x02,
- HAL_PCD_STATE_BUSY = 0x03,
- HAL_PCD_STATE_TIMEOUT = 0x04
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum {
- LPM_L0 = 0x00, /* on */
- LPM_L1 = 0x01, /* LPM L1 sleep */
- LPM_L2 = 0x02, /* suspend */
- LPM_L3 = 0x03, /* off */
-} PCD_LPM_StateTypeDef;
-
-typedef enum {
- PCD_LPM_L0_ACTIVE = 0x00, /* on */
- PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-} PCD_LPM_MsgTypeDef;
-
-typedef enum {
- PCD_BCD_ERROR = 0xFF,
- PCD_BCD_CONTACT_DETECTION = 0xFE,
- PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
- PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
- PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
- PCD_BCD_DISCOVERY_COMPLETED = 0x00,
-
-} PCD_BCD_MsgTypeDef;
-
-typedef USB_TypeDef PCD_TypeDef;
-typedef USB_CfgTypeDef PCD_InitTypeDef;
-typedef USB_EPTypeDef PCD_EPTypeDef;
-
-/**
- * @brief PCD Handle Structure definition
- */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-typedef struct __PCD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
- uint32_t BESL;
-
- uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t
- battery_charging_active; /*!< Enable or disable Battery charging.
- This parameter can be set to ENABLE or DISABLE */
- void *pData; /*!< Pointer to upper stack Handler */
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- void (*SOFCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
- void (*SetupStageCallback)(struct __PCD_HandleTypeDef *
- hpcd); /*!< USB OTG PCD Setup Stage callback */
- void (*ResetCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
- void (*SuspendCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
- void (*ResumeCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
- void (*ConnectCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
- void (*DisconnectCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
-
- void (*DataOutStageCallback)(
- struct __PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
- void (*DataInStageCallback)(
- struct __PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
- void (*ISOOUTIncompleteCallback)(
- struct __PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
- void (*ISOINIncompleteCallback)(
- struct __PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
- void (*BCDCallback)(struct __PCD_HandleTypeDef *hpcd,
- PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
- void (*LPMCallback)(struct __PCD_HandleTypeDef *hpcd,
- PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
-
- void (*MspInitCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
- void (*MspDeInitCallback)(
- struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-} PCD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Include PCD HAL Extended module */
-#include "stm32g4xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup PCD_Speed PCD Speed
- * @{
- */
-#define PCD_SPEED_FULL USBD_FS_SPEED
-/**
- * @}
- */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
- * @{
- */
-#define PCD_PHY_ULPI 1U
-#define PCD_PHY_EMBEDDED 2U
-#define PCD_PHY_UTMI 3U
-/**
- * @}
- */
-
-/** @defgroup PCD_Error_Code_definition PCD Error Code definition
- * @brief PCD Error Code definition
- * @{
- */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-#define HAL_PCD_ERROR_INVALID_CALLBACK \
- (0x00000010U) /*!< Invalid Callback error */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-#define __HAL_PCD_ENABLE(__HANDLE__) \
- (void)USB_EnableGlobalInt((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) \
- (void)USB_DisableGlobalInt((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
- ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == \
- (__INTERRUPT__))
-
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and
- * de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD
- * Callback ID enumeration definition
- * @brief HAL USB OTG PCD Callback ID enumeration definition
- * @{
- */
-typedef enum {
- HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
- HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
- HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
- HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
- HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
- HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
-
- HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
- HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
-
-} HAL_PCD_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback
- * pointer definition
- * @brief HAL USB OTG PCD Callback pointer definition
- * @{
- */
-
-typedef void (*pPCD_CallbackTypeDef)(
- PCD_HandleTypeDef
- *hpcd); /*!< pointer to a common USB OTG PCD callback function */
-typedef void (*pPCD_DataOutStageCallbackTypeDef)(
- PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
-typedef void (*pPCD_DataInStageCallbackTypeDef)(
- PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
-typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(
- PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
-typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(
- PCD_HandleTypeDef *hpcd,
- uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
-typedef void (*pPCD_LpmCallbackTypeDef)(
- PCD_HandleTypeDef *hpcd,
- PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
-typedef void (*pPCD_BcdCallbackTypeDef)(
- PCD_HandleTypeDef *hpcd,
- PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
-
-/**
- * @}
- */
-
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
- pPCD_CallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(
- PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(
- PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(
- PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(
- PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(
- PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(
- PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(
- PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(
- PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(
- PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(
- PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(
- PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation
- * functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type);
-
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
- * @{
- */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
- * @{
- */
-
-#define USB_WAKEUP_EXTI_LINE \
- (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS
- * @{
- */
-#define PCD_EP0MPS_64 EP_MPS_64
-#define PCD_EP0MPS_32 EP_MPS_32
-#define PCD_EP0MPS_16 EP_MPS_16
-#define PCD_EP0MPS_08 EP_MPS_8
-/**
- * @}
- */
-
-/** @defgroup PCD_ENDP PCD ENDP
- * @{
- */
-#define PCD_ENDP0 0U
-#define PCD_ENDP1 1U
-#define PCD_ENDP2 2U
-#define PCD_ENDP3 3U
-#define PCD_ENDP4 4U
-#define PCD_ENDP5 5U
-#define PCD_ENDP6 6U
-#define PCD_ENDP7 7U
-/**
- * @}
- */
-
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
- * @{
- */
-#define PCD_SNG_BUF 0U
-#define PCD_DBL_BUF 1U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-
-/******************** Bit definition for USB_COUNTn_RX register *************/
-#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
-#define USB_CNTRX_BLSIZE (0x1U << 15)
-
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
- (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) \
- (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
-
-/**
- * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wType Endpoint Type.
- * @retval None
- */
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
- (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | \
- (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
-
-/**
- * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval Endpoint Type
- */
-#define PCD_GET_EPTYPE(USBx, bEpNum) \
- (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
-
-/**
- * @brief free buffer used from the application realizing it to the line
- * toggles bit SW_BUF in the double buffered endpoint register
- * @param USBx USB device.
- * @param bEpNum, bDir
- * @retval None
- */
-#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
- do { \
- if ((bDir) == 0U) { \
- /* OUT double buffered endpoint */ \
- PCD_TX_DTOG((USBx), (bEpNum)); \
- } else if ((bDir) == 1U) { \
- /* IN double buffered endpoint */ \
- PCD_RX_DTOG((USBx), (bEpNum)); \
- } \
- } while (0)
-
-/**
- * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wState new state
- * @retval None
- */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
- /* toggle first bit ? */ \
- if ((USB_EPTX_DTOG1 & (wState)) != 0U) { \
- _wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if ((USB_EPTX_DTOG2 & (wState)) != 0U) { \
- _wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
- } while (0) /* PCD_SET_EP_TX_STATUS */
-
-/**
- * @brief sets the status for rx transfer (bits STAT_TX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wState new state
- * @retval None
- */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
- /* toggle first bit ? */ \
- if ((USB_EPRX_DTOG1 & (wState)) != 0U) { \
- _wRegVal ^= USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if ((USB_EPRX_DTOG2 & (wState)) != 0U) { \
- _wRegVal ^= USB_EPRX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
- } while (0) /* PCD_SET_EP_RX_STATUS */
-
-/**
- * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wStaterx new state.
- * @param wStatetx new state.
- * @retval None
- */
-#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & \
- (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
- /* toggle first bit ? */ \
- if ((USB_EPRX_DTOG1 & (wStaterx)) != 0U) { \
- _wRegVal ^= USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if ((USB_EPRX_DTOG2 & (wStaterx)) != 0U) { \
- _wRegVal ^= USB_EPRX_DTOG2; \
- } \
- /* toggle first bit ? */ \
- if ((USB_EPTX_DTOG1 & (wStatetx)) != 0U) { \
- _wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if ((USB_EPTX_DTOG2 & (wStatetx)) != 0U) { \
- _wRegVal ^= USB_EPTX_DTOG2; \
- } \
- \
- PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
- } while (0) /* PCD_SET_EP_TXRX_STATUS */
-
-/**
- * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
- * /STAT_RX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval status
- */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) \
- ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) \
- ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
-
-/**
- * @brief sets directly the VALID tx/rx-status into the endpoint register
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum) \
- (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum) \
- (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
- * @brief checks stall condition in an endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval TRUE = endpoint in stall condition.
- */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) \
- (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) \
- (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
-
-/**
- * @brief set & clear EP_KIND bit.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_KIND(USBx, bEpNum) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
- \
- PCD_SET_ENDPOINT( \
- (USBx), (bEpNum), \
- (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
- } while (0) /* PCD_SET_EP_KIND */
-
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
- \
- PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
- } while (0) /* PCD_CLEAR_EP_KIND */
-
-/**
- * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
- * @brief Sets/clears directly EP_KIND bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
- * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = \
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
- \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
- } while (0) /* PCD_CLEAR_RX_EP_CTR */
-
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = \
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
- \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
- } while (0) /* PCD_CLEAR_TX_EP_CTR */
-
-/**
- * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_RX_DTOG(USBx, bEpNum) \
- do { \
- uint16_t _wEPVal; \
- \
- _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
- \
- PCD_SET_ENDPOINT( \
- (USBx), (bEpNum), \
- (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
- } while (0) /* PCD_RX_DTOG */
-
-#define PCD_TX_DTOG(USBx, bEpNum) \
- do { \
- uint16_t _wEPVal; \
- \
- _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
- \
- PCD_SET_ENDPOINT( \
- (USBx), (bEpNum), \
- (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
- } while (0) /* PCD_TX_DTOG */
-/**
- * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
- \
- if ((_wRegVal & USB_EP_DTOG_RX) != 0U) { \
- PCD_RX_DTOG((USBx), (bEpNum)); \
- } \
- } while (0) /* PCD_CLEAR_RX_DTOG */
-
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
- \
- if ((_wRegVal & USB_EP_DTOG_TX) != 0U) { \
- PCD_TX_DTOG((USBx), (bEpNum)); \
- } \
- } while (0) /* PCD_CLEAR_TX_DTOG */
-
-/**
- * @brief Sets address in an endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param bAddr Address.
- * @retval None
- */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
- do { \
- uint16_t _wRegVal; \
- \
- _wRegVal = \
- (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
- \
- PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
- } while (0) /* PCD_SET_EP_ADDRESS */
-
-/**
- * @brief Gets address in an endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) \
- ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-#define PCD_EP_TX_CNT(USBx, bEpNum) \
- ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * \
- PMA_ACCESS) + \
- ((uint32_t)(USBx) + 0x400U)))
-
-#define PCD_EP_RX_CNT(USBx, bEpNum) \
- ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * \
- PMA_ACCESS) + \
- ((uint32_t)(USBx) + 0x400U)))
-
-/**
- * @brief sets address of the tx/rx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wAddr address to be set (must be word aligned).
- * @retval None
- */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
- do { \
- __IO uint16_t *_wRegVal; \
- uint32_t _wRegBase = (uint32_t)USBx; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + \
- (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
- *_wRegVal = ((wAddr) >> 1) << 1; \
- } while (0) /* PCD_SET_EP_TX_ADDRESS */
-
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
- do { \
- __IO uint16_t *_wRegVal; \
- uint32_t _wRegBase = (uint32_t)USBx; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = \
- (__IO uint16_t *)(_wRegBase + 0x400U + \
- ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
- *_wRegVal = ((wAddr) >> 1) << 1; \
- } while (0) /* PCD_SET_EP_RX_ADDRESS */
-
-/**
- * @brief Gets address of the tx/rx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval address of the buffer.
- */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) \
- ((uint16_t) * PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) \
- ((uint16_t) * PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
- * @brief Sets counter of rx buffer with no. of blocks.
- * @param pdwReg Register pointer
- * @param wCount Counter.
- * @param wNBlocks no. of Blocks.
- * @retval None
- */
-#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
- do { \
- (wNBlocks) = (wCount) >> 5; \
- if (((wCount) & 0x1fU) == 0U) { \
- (wNBlocks)--; \
- } \
- *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
- } while (0) /* PCD_CALC_BLK32 */
-
-#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
- do { \
- (wNBlocks) = (wCount) >> 1; \
- if (((wCount) & 0x1U) != 0U) { \
- (wNBlocks)++; \
- } \
- *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
- } while (0) /* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
- do { \
- uint32_t wNBlocks; \
- \
- if ((wCount) > 62U) { \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
- } else { \
- if ((wCount) == 0U) { \
- *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } else { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
- } \
- } \
- } while (0) /* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
- do { \
- uint32_t _wRegBase = (uint32_t)(USBx); \
- __IO uint16_t *pdwReg; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- pdwReg = \
- (__IO uint16_t *)(_wRegBase + 0x400U + \
- ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
- } while (0)
-
-/**
- * @brief sets counter for the tx/rx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wCount Counter value.
- * @retval None
- */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
- do { \
- uint32_t _wRegBase = (uint32_t)(USBx); \
- __IO uint16_t *_wRegVal; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = \
- (__IO uint16_t *)(_wRegBase + 0x400U + \
- ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
- *_wRegVal = (uint16_t)(wCount); \
- } while (0)
-
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
- do { \
- uint32_t _wRegBase = (uint32_t)(USBx); \
- __IO uint16_t *_wRegVal; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = \
- (__IO uint16_t *)(_wRegBase + 0x400U + \
- ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
- PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
- } while (0)
-
-/**
- * @brief gets counter of the tx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval Counter value
- */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum) \
- ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum) \
- ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
-
-/**
- * @brief Sets buffer 0/1 address in a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wBuf0Addr buffer 0 address.
- * @retval Counter value
- */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
- do { \
- PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
- } while (0) /* PCD_SET_EP_DBUF0_ADDR */
-
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
- do { \
- PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
- } while (0) /* PCD_SET_EP_DBUF1_ADDR */
-
-/**
- * @brief Sets addresses in a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @param wBuf1Addr = buffer 1 address.
- * @retval None
- */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
- do { \
- PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
- PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
- } while (0) /* PCD_SET_EP_DBUF_ADDR */
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) \
- (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) \
- (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param bDir endpoint dir EP_DBUF_OUT = OUT
- * EP_DBUF_IN = IN
- * @param wCount: Counter value
- * @retval None
- */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
- do { \
- if ((bDir) == 0U) /* OUT endpoint */ \
- { \
- PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
- } else { \
- if ((bDir) == 1U) { \
- /* IN endpoint */ \
- PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
- } \
- } \
- } while (0) /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
- do { \
- uint32_t _wBase = (uint32_t)(USBx); \
- __IO uint16_t *_wEPRegVal; \
- \
- if ((bDir) == 0U) { \
- /* OUT endpoint */ \
- PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
- } else { \
- if ((bDir) == 1U) { \
- /* IN endpoint */ \
- _wBase += (uint32_t)(USBx)->BTABLE; \
- _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + \
- ((((uint32_t)(bEpNum) * 8U) + 6U) * \
- PMA_ACCESS)); \
- *_wEPRegVal = (uint16_t)(wCount); \
- } \
- } \
- } while (0) /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
- do { \
- PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- } while (0) /* PCD_SET_EP_DBUF_CNT */
-
-/**
- * @brief Gets buffer 0/1 rx/tx counter for double buffering.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_PCD_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pcd.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PCD_H
+#define STM32G4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_ll_usb.h"
+
+#if defined(USB)
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
+typedef enum {
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum {
+ LPM_L0 = 0x00, /* on */
+ LPM_L1 = 0x01, /* LPM L1 sleep */
+ LPM_L2 = 0x02, /* suspend */
+ LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum {
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum {
+ PCD_BCD_ERROR = 0xFF,
+ PCD_BCD_CONTACT_DETECTION = 0xFE,
+ PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
+ PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
+ PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
+ PCD_BCD_DISCOVERY_COMPLETED = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+typedef USB_TypeDef PCD_TypeDef;
+typedef USB_CfgTypeDef PCD_InitTypeDef;
+typedef USB_EPTypeDef PCD_EPTypeDef;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ uint32_t BESL;
+
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t
+ battery_charging_active; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ void (*SOFCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
+ void (*SetupStageCallback)(struct __PCD_HandleTypeDef *
+ hpcd); /*!< USB OTG PCD Setup Stage callback */
+ void (*ResetCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
+ void (*SuspendCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
+ void (*ResumeCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
+ void (*ConnectCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
+ void (*DisconnectCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
+
+ void (*DataOutStageCallback)(
+ struct __PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
+ void (*DataInStageCallback)(
+ struct __PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
+ void (*ISOOUTIncompleteCallback)(
+ struct __PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
+ void (*ISOINIncompleteCallback)(
+ struct __PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
+ void (*BCDCallback)(struct __PCD_HandleTypeDef *hpcd,
+ PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
+ void (*LPMCallback)(struct __PCD_HandleTypeDef *hpcd,
+ PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
+
+ void (*MspInitCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
+ void (*MspDeInitCallback)(
+ struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extended module */
+#include "stm32g4xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Speed PCD Speed
+ * @{
+ */
+#define PCD_SPEED_FULL USBD_FS_SPEED
+/**
+ * @}
+ */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+ * @{
+ */
+#define PCD_PHY_ULPI 1U
+#define PCD_PHY_EMBEDDED 2U
+#define PCD_PHY_UTMI 3U
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+ * @brief PCD Error Code definition
+ * @{
+ */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define HAL_PCD_ERROR_INVALID_CALLBACK \
+ (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_ENABLE(__HANDLE__) \
+ (void)USB_EnableGlobalInt((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) \
+ (void)USB_DisableGlobalInt((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == \
+ (__INTERRUPT__))
+
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and
+ * de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD
+ * Callback ID enumeration definition
+ * @brief HAL USB OTG PCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum {
+ HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
+ HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
+ HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
+ HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
+ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
+ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+
+ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
+ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback
+ * pointer definition
+ * @brief HAL USB OTG PCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pPCD_CallbackTypeDef)(
+ PCD_HandleTypeDef
+ *hpcd); /*!< pointer to a common USB OTG PCD callback function */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(
+ PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(
+ PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(
+ PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(
+ PCD_HandleTypeDef *hpcd,
+ uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
+typedef void (*pPCD_LpmCallbackTypeDef)(
+ PCD_HandleTypeDef *hpcd,
+ PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
+typedef void (*pPCD_BcdCallbackTypeDef)(
+ PCD_HandleTypeDef *hpcd,
+ PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
+
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(
+ PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(
+ PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(
+ PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(
+ PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(
+ PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation
+ * functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+ * @{
+ */
+
+#define USB_WAKEUP_EXTI_LINE \
+ (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+ * @{
+ */
+#define PCD_EP0MPS_64 EP_MPS_64
+#define PCD_EP0MPS_32 EP_MPS_32
+#define PCD_EP0MPS_16 EP_MPS_16
+#define PCD_EP0MPS_08 EP_MPS_8
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP PCD ENDP
+ * @{
+ */
+#define PCD_ENDP0 0U
+#define PCD_ENDP1 1U
+#define PCD_ENDP2 2U
+#define PCD_ENDP3 3U
+#define PCD_ENDP4 4U
+#define PCD_ENDP5 5U
+#define PCD_ENDP6 6U
+#define PCD_ENDP7 7U
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+ * @{
+ */
+#define PCD_SNG_BUF 0U
+#define PCD_DBL_BUF 1U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/******************** Bit definition for USB_COUNTn_RX register *************/
+#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
+#define USB_CNTRX_BLSIZE (0x1U << 15)
+
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
+ (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum) \
+ (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
+
+/**
+ * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wType Endpoint Type.
+ * @retval None
+ */
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
+ (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | \
+ (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+
+/**
+ * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval Endpoint Type
+ */
+#define PCD_GET_EPTYPE(USBx, bEpNum) \
+ (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+/**
+ * @brief free buffer used from the application realizing it to the line
+ * toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx USB device.
+ * @param bEpNum, bDir
+ * @retval None
+ */
+#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
+ do { \
+ if ((bDir) == 0U) { \
+ /* OUT double buffered endpoint */ \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ } else if ((bDir) == 1U) { \
+ /* IN double buffered endpoint */ \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while (0)
+
+/**
+ * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state
+ * @retval None
+ */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((USB_EPTX_DTOG1 & (wState)) != 0U) { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPTX_DTOG2 & (wState)) != 0U) { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while (0) /* PCD_SET_EP_TX_STATUS */
+
+/**
+ * @brief sets the status for rx transfer (bits STAT_TX[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state
+ * @retval None
+ */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((USB_EPRX_DTOG1 & (wState)) != 0U) { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPRX_DTOG2 & (wState)) != 0U) { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while (0) /* PCD_SET_EP_RX_STATUS */
+
+/**
+ * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wStaterx new state.
+ * @param wStatetx new state.
+ * @retval None
+ */
+#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & \
+ (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
+ /* toggle first bit ? */ \
+ if ((USB_EPRX_DTOG1 & (wStaterx)) != 0U) { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPRX_DTOG2 & (wStaterx)) != 0U) { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ /* toggle first bit ? */ \
+ if ((USB_EPTX_DTOG1 & (wStatetx)) != 0U) { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPTX_DTOG2 & (wStatetx)) != 0U) { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while (0) /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+ * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval status
+ */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) \
+ ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) \
+ ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+ * @brief sets directly the VALID tx/rx-status into the endpoint register
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum) \
+ (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum) \
+ (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+ * @brief checks stall condition in an endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval TRUE = endpoint in stall condition.
+ */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) \
+ (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) \
+ (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
+
+/**
+ * @brief set & clear EP_KIND bit.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_KIND(USBx, bEpNum) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+ \
+ PCD_SET_ENDPOINT( \
+ (USBx), (bEpNum), \
+ (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
+ } while (0) /* PCD_SET_EP_KIND */
+
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while (0) /* PCD_CLEAR_EP_KIND */
+
+/**
+ * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Sets/clears directly EP_KIND bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = \
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
+ } while (0) /* PCD_CLEAR_RX_EP_CTR */
+
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = \
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
+ } while (0) /* PCD_CLEAR_TX_EP_CTR */
+
+/**
+ * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_RX_DTOG(USBx, bEpNum) \
+ do { \
+ uint16_t _wEPVal; \
+ \
+ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+ \
+ PCD_SET_ENDPOINT( \
+ (USBx), (bEpNum), \
+ (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
+ } while (0) /* PCD_RX_DTOG */
+
+#define PCD_TX_DTOG(USBx, bEpNum) \
+ do { \
+ uint16_t _wEPVal; \
+ \
+ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+ \
+ PCD_SET_ENDPOINT( \
+ (USBx), (bEpNum), \
+ (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
+ } while (0) /* PCD_TX_DTOG */
+/**
+ * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
+ \
+ if ((_wRegVal & USB_EP_DTOG_RX) != 0U) { \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while (0) /* PCD_CLEAR_RX_DTOG */
+
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
+ \
+ if ((_wRegVal & USB_EP_DTOG_TX) != 0U) { \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while (0) /* PCD_CLEAR_TX_DTOG */
+
+/**
+ * @brief Sets address in an endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr Address.
+ * @retval None
+ */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
+ do { \
+ uint16_t _wRegVal; \
+ \
+ _wRegVal = \
+ (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while (0) /* PCD_SET_EP_ADDRESS */
+
+/**
+ * @brief Gets address in an endpoint register.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) \
+ ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+#define PCD_EP_TX_CNT(USBx, bEpNum) \
+ ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * \
+ PMA_ACCESS) + \
+ ((uint32_t)(USBx) + 0x400U)))
+
+#define PCD_EP_RX_CNT(USBx, bEpNum) \
+ ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * \
+ PMA_ACCESS) + \
+ ((uint32_t)(USBx) + 0x400U)))
+
+/**
+ * @brief sets address of the tx/rx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr address to be set (must be word aligned).
+ * @retval None
+ */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
+ do { \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + \
+ (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+ } while (0) /* PCD_SET_EP_TX_ADDRESS */
+
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
+ do { \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = \
+ (__IO uint16_t *)(_wRegBase + 0x400U + \
+ ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+ } while (0) /* PCD_SET_EP_RX_ADDRESS */
+
+/**
+ * @brief Gets address of the tx/rx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval address of the buffer.
+ */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) \
+ ((uint16_t) * PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) \
+ ((uint16_t) * PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Sets counter of rx buffer with no. of blocks.
+ * @param pdwReg Register pointer
+ * @param wCount Counter.
+ * @param wNBlocks no. of Blocks.
+ * @retval None
+ */
+#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
+ do { \
+ (wNBlocks) = (wCount) >> 5; \
+ if (((wCount) & 0x1fU) == 0U) { \
+ (wNBlocks)--; \
+ } \
+ *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
+ } while (0) /* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
+ do { \
+ (wNBlocks) = (wCount) >> 1; \
+ if (((wCount) & 0x1U) != 0U) { \
+ (wNBlocks)++; \
+ } \
+ *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
+ } while (0) /* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
+ do { \
+ uint32_t wNBlocks; \
+ \
+ *(pdwReg) &= 0x3FFU; \
+ \
+ if ((wCount) == 0U) { \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } else if ((wCount) <= 62U) { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ } else { \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ } \
+ } while (0) /* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
+ do { \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *pdwReg; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ pdwReg = \
+ (__IO uint16_t *)(_wRegBase + 0x400U + \
+ ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
+ } while (0)
+
+/**
+ * @brief sets counter for the tx/rx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wCount Counter value.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
+ do { \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *_wRegVal; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = \
+ (__IO uint16_t *)(_wRegBase + 0x400U + \
+ ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+ *_wRegVal = (uint16_t)(wCount); \
+ } while (0)
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
+ do { \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *_wRegVal; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = \
+ (__IO uint16_t *)(_wRegBase + 0x400U + \
+ ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+ PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
+ } while (0)
+
+/**
+ * @brief gets counter of the tx buffer.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval Counter value
+ */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum) \
+ ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum) \
+ ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
+
+/**
+ * @brief Sets buffer 0/1 address in a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr buffer 0 address.
+ * @retval Counter value
+ */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
+ do { \
+ PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
+ } while (0) /* PCD_SET_EP_DBUF0_ADDR */
+
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
+ do { \
+ PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
+ } while (0) /* PCD_SET_EP_DBUF1_ADDR */
+
+/**
+ * @brief Sets addresses in a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @param wBuf1Addr = buffer 1 address.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
+ do { \
+ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
+ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
+ } while (0) /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) \
+ (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) \
+ (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @param bDir endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * @param wCount: Counter value
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
+ if ((bDir) == 0U) /* OUT endpoint */ \
+ { \
+ PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
+ } else { \
+ if ((bDir) == 1U) { \
+ /* IN endpoint */ \
+ PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
+ } \
+ } \
+ } while (0) /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
+ uint32_t _wBase = (uint32_t)(USBx); \
+ __IO uint16_t *_wEPRegVal; \
+ \
+ if ((bDir) == 0U) { \
+ /* OUT endpoint */ \
+ PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
+ } else { \
+ if ((bDir) == 1U) { \
+ /* IN endpoint */ \
+ _wBase += (uint32_t)(USBx)->BTABLE; \
+ _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + \
+ ((((uint32_t)(bEpNum) * 8U) + 6U) * \
+ PMA_ACCESS)); \
+ *_wEPRegVal = (uint16_t)(wCount); \
+ } \
+ } \
+ } while (0) /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ } while (0) /* PCD_SET_EP_DBUF_CNT */
+
+/**
+ * @brief Gets buffer 0/1 rx/tx counter for double buffering.
+ * @param USBx USB peripheral instance register address.
+ * @param bEpNum Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_PCD_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
index 078e3ba..067d3a5 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
@@ -1,83 +1,83 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pcd_ex.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_PCD_EX_H
-#define STM32G4xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-#if defined(USB)
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCDEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
- uint16_t ep_kind, uint32_t pmaadress);
-
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* STM32G4xx_HAL_PCD_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PCD_EX_H
+#define STM32G4xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined(USB)
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+ uint16_t ep_kind, uint32_t pmaadress);
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32G4xx_HAL_PCD_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
index d80e49e..d06efc7 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
@@ -1,455 +1,455 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_PWR_H
-#define STM32G4xx_HAL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct {
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
- This parameter can be a value of @ref
- PWR_PVD_detection_level. */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWR_PVD_Mode. */
-} PWR_PVDTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
-#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
-#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
-#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
-#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
-#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
-#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
-#define PWR_PVDLEVEL_7 \
- PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to \
- VREFINT) */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
-#define PWR_PVD_MODE_IT_RISING \
- ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger \
- detection */
-#define PWR_PVD_MODE_IT_FALLING \
- ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge \
- trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING \
- ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge \
- trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING \
- ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING \
- ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection \
- */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING \
- ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger \
- detection */
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON \
- ((uint32_t)0x00000000) /*!< Regulator in main mode */
-#define PWR_LOWPOWERREGULATOR_ON \
- PWR_CR1_LPR /*!< Regulator in low-power mode \
- */
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI \
- ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode \
- */
-#define PWR_SLEEPENTRY_WFE \
- ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI \
- ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
-#define PWR_STOPENTRY_WFE \
- ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
- * @{
- */
-#define PWR_EXTI_LINE_PVD \
- ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD \
- EXTI Line */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
- * @{
- */
-#define PWR_EVENT_LINE_PVD \
- ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @brief Check whether or not a specific PWR flag is set.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup
-event
- * was received from the WKUP pin 1.
- * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup
-event
- * was received from the WKUP pin 2.
- * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup
-event
- * was received from the WKUP pin 3.
- * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup
-event
- * was received from the WKUP pin 4.
- * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup
-event
- * was received from the WKUP pin 5.
- * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
- * entered StandBy mode.
- * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup
-is detected on
- * the internal wakeup line.
- * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates
-whether or not the
- * low-power regulator is ready.
- * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates
-whether the
- * regulator is ready in main mode or is in low-power mode.
- * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether
-the regulator is ready
- * in the selected voltage range or is still changing to the
-required voltage level.
- * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates
-whether VDD voltage is
- * below or above the selected PVD threshold.
-@if PWR_CR2_PVME1
- * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1.
-Indicates whether VDDUSB voltage is
- * is below or above PVM1 threshold (applicable when USB
-feature is supported).
-@endif
-@if PWR_CR2_PVME2
- * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2.
-Indicates whether VDDIO2 voltage is
- * is below or above PVM2 threshold (applicable when VDDIO2 is
-present on device).
-@endif
- * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3.
-Indicates whether VDDA voltage is
- * is below or above PVM3 threshold.
- * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4.
-Indicates whether VDDA voltage is
- * is below or above PVM4 threshold.
- *
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) \
- (((((uint8_t)(__FLAG__)) >> 5U) == 1) \
- ? (PWR->SR1 & (1U << ((__FLAG__) & 31U))) \
- : (PWR->SR2 & (1U << ((__FLAG__) & 31U))))
-
-/** @brief Clear a specific PWR flag.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup
- * event was received from the WKUP pin 1.
- * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup
- * event was received from the WKUP pin 2.
- * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup
- * event was received from the WKUP pin 3.
- * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup
- * event was received from the WKUP pin 4.
- * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup
- * event was received from the WKUP pin 5.
- * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
- * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
- * entered Standby mode.
- * @retval None
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
- ((((uint8_t)(__FLAG__)) == PWR_FLAG_WU) \
- ? (PWR->SCR = (__FLAG__)) \
- : (PWR->SCR = (1U << ((__FLAG__) & 31U))))
-/**
- * @brief Enable the PVD Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() \
- SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
-
-/**
- * @brief Disable the PVD Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() \
- CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() \
- SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() \
- CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() \
- SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() \
- CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() \
- SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Check whether or not the PVD EXTI interrupt flag is set.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Clear the PVD EXTI interrupt flag.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-
-#define IS_PWR_PVD_LEVEL(LEVEL) \
- (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-#define IS_PWR_PVD_MODE(MODE) \
- (((MODE) == PWR_PVD_MODE_NORMAL) || ((MODE) == PWR_PVD_MODE_IT_RISING) || \
- ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
-
-#define IS_PWR_REGULATOR(REGULATOR) \
- (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) \
- (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) \
- (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-
-/**
- * @}
- */
-
-/* Include PWR HAL Extended module */
-#include "stm32g4xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and
- * de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions
- * *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions
- * ************************************************/
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-void HAL_PWR_PVDCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_PWR_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PWR_H
+#define STM32G4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct {
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+ This parameter can be a value of @ref
+ PWR_PVD_detection_level. */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode. */
+} PWR_PVDTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
+#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
+#define PWR_PVDLEVEL_7 \
+ PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to \
+ VREFINT) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING \
+ ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger \
+ detection */
+#define PWR_PVD_MODE_IT_FALLING \
+ ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge \
+ trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING \
+ ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge \
+ trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING \
+ ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING \
+ ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection \
+ */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING \
+ ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger \
+ detection */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON \
+ ((uint32_t)0x00000000) /*!< Regulator in main mode */
+#define PWR_LOWPOWERREGULATOR_ON \
+ PWR_CR1_LPR /*!< Regulator in low-power mode \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI \
+ ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode \
+ */
+#define PWR_SLEEPENTRY_WFE \
+ ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI \
+ ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE \
+ ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
+ * @{
+ */
+#define PWR_EXTI_LINE_PVD \
+ ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD \
+ EXTI Line */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
+ * @{
+ */
+#define PWR_EVENT_LINE_PVD \
+ ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @brief Check whether or not a specific PWR flag is set.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup
+event
+ * was received from the WKUP pin 1.
+ * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup
+event
+ * was received from the WKUP pin 2.
+ * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup
+event
+ * was received from the WKUP pin 3.
+ * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup
+event
+ * was received from the WKUP pin 4.
+ * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup
+event
+ * was received from the WKUP pin 5.
+ * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
+ * entered StandBy mode.
+ * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup
+is detected on
+ * the internal wakeup line.
+ * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates
+whether or not the
+ * low-power regulator is ready.
+ * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates
+whether the
+ * regulator is ready in main mode or is in low-power mode.
+ * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether
+the regulator is ready
+ * in the selected voltage range or is still changing to the
+required voltage level.
+ * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates
+whether VDD voltage is
+ * below or above the selected PVD threshold.
+@if PWR_CR2_PVME1
+ * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1.
+Indicates whether VDDUSB voltage is
+ * is below or above PVM1 threshold (applicable when USB
+feature is supported).
+@endif
+@if PWR_CR2_PVME2
+ * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2.
+Indicates whether VDDIO2 voltage is
+ * is below or above PVM2 threshold (applicable when VDDIO2 is
+present on device).
+@endif
+ * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3.
+Indicates whether VDDA voltage is
+ * is below or above PVM3 threshold.
+ * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4.
+Indicates whether VDDA voltage is
+ * is below or above PVM4 threshold.
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
+ (((((uint8_t)(__FLAG__)) >> 5U) == 1) \
+ ? (PWR->SR1 & (1U << ((__FLAG__) & 31U))) \
+ : (PWR->SR2 & (1U << ((__FLAG__) & 31U))))
+
+/** @brief Clear a specific PWR flag.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup
+ * event was received from the WKUP pin 1.
+ * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup
+ * event was received from the WKUP pin 2.
+ * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup
+ * event was received from the WKUP pin 3.
+ * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup
+ * event was received from the WKUP pin 4.
+ * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup
+ * event was received from the WKUP pin 5.
+ * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
+ * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
+ * entered Standby mode.
+ * @retval None
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
+ ((((uint8_t)(__FLAG__)) == PWR_FLAG_WU) \
+ ? (PWR->SCR = (__FLAG__)) \
+ : (PWR->SCR = (1U << ((__FLAG__) & 31U))))
+/**
+ * @brief Enable the PVD Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() \
+ SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() \
+ CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() \
+ SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() \
+ CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() \
+ SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() \
+ CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() \
+ SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Check whether or not the PVD EXTI interrupt flag is set.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Clear the PVD EXTI interrupt flag.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+
+#define IS_PWR_PVD_LEVEL(LEVEL) \
+ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+#define IS_PWR_PVD_MODE(MODE) \
+ (((MODE) == PWR_PVD_MODE_NORMAL) || ((MODE) == PWR_PVD_MODE_IT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
+
+#define IS_PWR_REGULATOR(REGULATOR) \
+ (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) \
+ (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) \
+ (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/* Include PWR HAL Extended module */
+#include "stm32g4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and
+ * de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions
+ * *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions
+ * ************************************************/
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+void HAL_PWR_PVDCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_PWR_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
index c759064..9fccd86 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
@@ -1,887 +1,887 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pwr_ex.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_PWR_EX_H
-#define STM32G4xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWREx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVM configuration structure definition
- */
-typedef struct {
- uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and
- against which threshold. This parameter can be a value of
- @ref PWREx_PVM_Type. */
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWREx_PVM_Mode. */
-} PWR_PVMTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
- * @{
- */
-
-/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information
- * from PWR_WAKEUP_PINy_xxx constants
- * @{
- */
-#define PWR_WUP_POLARITY_SHIFT \
- 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */
-/**
- * @}
- */
-
-/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
- * @{
- */
-#define PWR_WAKEUP_PIN1 \
- PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2 \
- PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3 \
- PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
-#define PWR_WAKEUP_PIN4 \
- PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
-#define PWR_WAKEUP_PIN5 \
- PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
-#define PWR_WAKEUP_PIN1_HIGH \
- PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2_HIGH \
- PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3_HIGH \
- PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
-#define PWR_WAKEUP_PIN4_HIGH \
- PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
-#define PWR_WAKEUP_PIN5_HIGH \
- PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
-#define PWR_WAKEUP_PIN1_LOW \
- (uint32_t)((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | \
- PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
-#define PWR_WAKEUP_PIN2_LOW \
- (uint32_t)((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | \
- PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
-#define PWR_WAKEUP_PIN3_LOW \
- (uint32_t)((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | \
- PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
-#define PWR_WAKEUP_PIN4_LOW \
- (uint32_t)((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | \
- PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
-#define PWR_WAKEUP_PIN5_LOW \
- (uint32_t)((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | \
- PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
-/**
- * @}
- */
-
-/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
- * @{
- */
-#if defined(PWR_CR2_PVME1)
-#define PWR_PVM_1 \
- PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 \
- V (applicable when USB feature is supported) */
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-#define PWR_PVM_2 \
- PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 \
- V (applicable when VDDIO2 is present on device) */
-#endif /* PWR_CR2_PVME2 */
-#define PWR_PVM_3 \
- PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 \
- V */
-#define PWR_PVM_4 \
- PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V \
- */
-/**
- * @}
- */
-
-/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
- * @{
- */
-#define PWR_PVM_MODE_NORMAL 0x00000000U /*!< basic mode is used */
-#define PWR_PVM_MODE_IT_RISING \
- 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection \
- */
-#define PWR_PVM_MODE_IT_FALLING \
- 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection \
- */
-#define PWR_PVM_MODE_IT_RISING_FALLING \
- 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger \
- detection */
-#define PWR_PVM_MODE_EVENT_RISING \
- 0x00020001U /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVM_MODE_EVENT_FALLING \
- 0x00020002U /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVM_MODE_EVENT_RISING_FALLING \
- 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
- * @{
- */
-#if defined(PWR_CR5_R1MODE)
-#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST \
- ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */
-#endif /*PWR_CR5_R1MODE */
-#define PWR_REGULATOR_VOLTAGE_SCALE1 \
- PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */
-#define PWR_REGULATOR_VOLTAGE_SCALE2 \
- PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
-/**
- * @}
- */
-
-/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging
- * resistor selection
- * @{
- */
-#define PWR_BATTERY_CHARGING_RESISTOR_5 \
- 0x00000000U /*!< VBAT charging through a 5 kOhms resistor */
-#define PWR_BATTERY_CHARGING_RESISTOR_1_5 \
- PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
-/**
- * @}
- */
-
-/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
- * @{
- */
-#define PWR_BATTERY_CHARGING_DISABLE 0x00000000U
-#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
-/**
- * @}
- */
-
-/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in
- * standby/shutdown mode
- * @{
- */
-#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
-#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
-#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
-#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
-#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
-#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
-#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
-#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
-#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
-#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
-#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
-#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
-#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
-#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
-#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
-#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
-/**
- * @}
- */
-
-/** @defgroup PWREx_GPIO GPIO port
- * @{
- */
-#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
-#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
-#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
-#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
-#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
-#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */
-#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */
-/**
- * @}
- */
-
-/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
- * @{
- */
-#if defined(PWR_CR2_PVME1)
-#define PWR_EXTI_LINE_PVM1 \
- 0x00000008U /*!< External interrupt line 35 Connected to the PVM1 EXTI Line \
- */
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-#define PWR_EXTI_LINE_PVM2 \
- 0x00000010U /*!< External interrupt line 36 Connected to the PVM2 EXTI Line \
- */
-#endif /* PWR_CR2_PVME2 */
-#define PWR_EXTI_LINE_PVM3 \
- 0x00000020U /*!< External interrupt line 37 Connected to the PVM3 EXTI Line \
- */
-#define PWR_EXTI_LINE_PVM4 \
- 0x00000040U /*!< External interrupt line 38 Connected to the PVM4 EXTI Line \
- */
-/**
- * @}
- */
-
-/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
- * @{
- */
-#if defined(PWR_CR2_PVME1)
-#define PWR_EVENT_LINE_PVM1 \
- 0x00000008U /*!< Event line 35 Connected to the PVM1 EXTI Line */
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-#define PWR_EVENT_LINE_PVM2 \
- 0x00000010U /*!< Event line 36 Connected to the PVM2 EXTI Line */
-#endif /* PWR_CR2_PVME2 */
-#define PWR_EVENT_LINE_PVM3 \
- 0x00000020U /*!< Event line 37 Connected to the PVM3 EXTI Line */
-#define PWR_EVENT_LINE_PVM4 \
- 0x00000040U /*!< Event line 38 Connected to the PVM4 EXTI Line */
-/**
- * @}
- */
-
-/** @defgroup PWREx_Flag PWR Status Flags
- * Elements values convention: 0000 0000 0XXY YYYYb
- * - Y YYYY : Flag position in the XX register (5 bits)
- * - XX : Status register (2 bits)
- * - 01: SR1 register
- * - 10: SR2 register
- * The only exception is PWR_FLAG_WU, encompassing all
- * wake-up flags and set to PWR_SR1_WUF.
- * @{
- */
-#define PWR_FLAG_WUF1 0x0020U /*!< Wakeup event on wakeup pin 1 */
-#define PWR_FLAG_WUF2 0x0021U /*!< Wakeup event on wakeup pin 2 */
-#define PWR_FLAG_WUF3 0x0022U /*!< Wakeup event on wakeup pin 3 */
-#define PWR_FLAG_WUF4 0x0023U /*!< Wakeup event on wakeup pin 4 */
-#define PWR_FLAG_WUF5 0x0024U /*!< Wakeup event on wakeup pin 5 */
-#define PWR_FLAG_WU \
- PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
-#define PWR_FLAG_SB 0x0028U /*!< Standby flag */
-#define PWR_FLAG_WUFI 0x002FU /*!< Wakeup on internal wakeup line */
-
-#define PWR_FLAG_REGLPS 0x0048U /*!< Low-power regulator start flag */
-#define PWR_FLAG_REGLPF 0x0049U /*!< Low-power regulator flag */
-#define PWR_FLAG_VOSF 0x004AU /*!< Voltage scaling flag */
-#define PWR_FLAG_PVDO 0x004BU /*!< Power Voltage Detector output flag */
-#if defined(PWR_CR2_PVME1)
-#define PWR_FLAG_PVMO1 0x004CU /*!< Power Voltage Monitoring 1 output flag */
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-#define PWR_FLAG_PVMO2 0x004DU /*!< Power Voltage Monitoring 2 output flag */
-#endif /* PWR_CR2_PVME2 */
-#define PWR_FLAG_PVMO3 0x004EU /*!< Power Voltage Monitoring 3 output flag */
-#define PWR_FLAG_PVMO4 0x004FU /*!< Power Voltage Monitoring 4 output flag */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
- * @{
- */
-
-#if defined(PWR_CR2_PVME1)
-/**
- * @brief Enable the PVM1 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() \
- CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Enable the PVM1 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() \
- SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() \
- CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
-
-/**
- * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() \
- SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() \
- CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() \
- SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() \
- CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() \
- SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
- * @retval EXTI PVM1 Line Status.
- */
-#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Clear the PVM1 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() \
- WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
-
-#endif /* PWR_CR2_PVME1 */
-
-#if defined(PWR_CR2_PVME2)
-/**
- * @brief Enable the PVM2 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() \
- CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Enable the PVM2 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() \
- SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() \
- CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
-
-/**
- * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() \
- SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() \
- CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() \
- SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() \
- CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() \
- SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
- * @retval EXTI PVM2 Line Status.
- */
-#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Clear the PVM2 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() \
- WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
-
-#endif /* PWR_CR2_PVME2 */
-
-/**
- * @brief Enable the PVM3 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() \
- CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Enable the PVM3 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() \
- SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() \
- CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
-
-/**
- * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() \
- SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() \
- CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() \
- SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() \
- CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() \
- SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
- * @retval EXTI PVM3 Line Status.
- */
-#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Clear the PVM3 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() \
- WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Enable the PVM4 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() \
- CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Enable the PVM4 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() \
- SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() \
- CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
-
-/**
- * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() \
- SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() \
- CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() \
- SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() \
- CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() \
- SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
- * @retval EXTI PVM4 Line Status.
- */
-#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Clear the PVM4 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() \
- WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Configure the main internal regulator output voltage.
- * @param __REGULATOR__: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption.
- * This parameter can be one of the following values:
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage
- * output range 1 mode, typical output voltage at 1.28 V, system frequency up to
- * 170 MHz.
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output
- * range 1 mode, typical output voltage at 1.2 V, system frequency up to 150
- * MHz.
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output
- * range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
- * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but
- * doesn't check whether or not VOSF flag is cleared when moving from range 2 to
- * range 1. User may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit
- * resetting.
- * @retval None
- */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
- do { \
- __IO uint32_t tmpreg; \
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
- UNUSED(tmpreg); \
- } while (0)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
- * @{
- */
-
-#define IS_PWR_WAKEUP_PIN(PIN) \
- (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
- ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) || \
- ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN2_HIGH) || ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN4_HIGH) || ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN5_LOW))
-
-#define IS_PWR_PVM_TYPE(TYPE) \
- (((TYPE) == PWR_PVM_1) || ((TYPE) == PWR_PVM_2) || ((TYPE) == PWR_PVM_3) || \
- ((TYPE) == PWR_PVM_4))
-
-#define IS_PWR_PVM_MODE(MODE) \
- (((MODE) == PWR_PVM_MODE_NORMAL) || ((MODE) == PWR_PVM_MODE_IT_RISING) || \
- ((MODE) == PWR_PVM_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) || \
- ((MODE) == PWR_PVM_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVM_MODE_EVENT_FALLING) || \
- ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
-
-#if defined(PWR_CR5_R1MODE)
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \
- (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
- ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-#else
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \
- (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-#endif
-
-#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \
- (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) || \
- ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
-
-#define IS_PWR_BATTERY_CHARGING(CHARGING) \
- (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) || \
- ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
-
-#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) \
- (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
-#define IS_PWR_GPIO(GPIO) \
- (((GPIO) == PWR_GPIO_A) || ((GPIO) == PWR_GPIO_B) || \
- ((GPIO) == PWR_GPIO_C) || ((GPIO) == PWR_GPIO_D) || \
- ((GPIO) == PWR_GPIO_E) || ((GPIO) == PWR_GPIO_F) || ((GPIO) == PWR_GPIO_G))
-
-/**
- * @}
- */
-
-/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
- * @{
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control
- * functions
- * @{
- */
-
-/* Peripheral Control functions **********************************************/
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
-void HAL_PWREx_DisableBatteryCharging(void);
-void HAL_PWREx_EnableInternalWakeUpLine(void);
-void HAL_PWREx_DisableInternalWakeUpLine(void);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber);
-void HAL_PWREx_EnablePullUpPullDownConfig(void);
-void HAL_PWREx_DisablePullUpPullDownConfig(void);
-void HAL_PWREx_EnableSRAM2ContentRetention(void);
-void HAL_PWREx_DisableSRAM2ContentRetention(void);
-#if defined(PWR_CR2_PVME1)
-void HAL_PWREx_EnablePVM1(void);
-void HAL_PWREx_DisablePVM1(void);
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-void HAL_PWREx_EnablePVM2(void);
-void HAL_PWREx_DisablePVM2(void);
-#endif /* PWR_CR2_PVME2 */
-void HAL_PWREx_EnablePVM3(void);
-void HAL_PWREx_DisablePVM3(void);
-void HAL_PWREx_EnablePVM4(void);
-void HAL_PWREx_DisablePVM4(void);
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWREx_EnableLowPowerRunMode(void);
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSHUTDOWNMode(void);
-
-void HAL_PWREx_PVD_PVM_IRQHandler(void);
-#if defined(PWR_CR2_PVME1)
-void HAL_PWREx_PVM1Callback(void);
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-void HAL_PWREx_PVM2Callback(void);
-#endif /* PWR_CR2_PVME2 */
-void HAL_PWREx_PVM3Callback(void);
-void HAL_PWREx_PVM4Callback(void);
-
-#if defined(PWR_CR3_UCPD_STDBY)
-void HAL_PWREx_EnableUCPDStandbyMode(void);
-void HAL_PWREx_DisableUCPDStandbyMode(void);
-#endif /* PWR_CR3_UCPD_STDBY */
-#if defined(PWR_CR3_UCPD_DBDIS)
-void HAL_PWREx_EnableUCPDDeadBattery(void);
-void HAL_PWREx_DisableUCPDDeadBattery(void);
-#endif /* PWR_CR3_UCPD_DBDIS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_PWR_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PWR_EX_H
+#define STM32G4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief PWR PVM configuration structure definition
+ */
+typedef struct {
+ uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and
+ against which threshold. This parameter can be a value of
+ @ref PWREx_PVM_Type. */
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWREx_PVM_Mode. */
+} PWR_PVMTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information
+ * from PWR_WAKEUP_PINy_xxx constants
+ * @{
+ */
+#define PWR_WUP_POLARITY_SHIFT \
+ 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
+ * @{
+ */
+#define PWR_WAKEUP_PIN1 \
+ PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2 \
+ PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3 \
+ PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4 \
+ PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5 \
+ PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_HIGH \
+ PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2_HIGH \
+ PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3_HIGH \
+ PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4_HIGH \
+ PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5_HIGH \
+ PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_LOW \
+ (uint32_t)((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | \
+ PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
+#define PWR_WAKEUP_PIN2_LOW \
+ (uint32_t)((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | \
+ PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
+#define PWR_WAKEUP_PIN3_LOW \
+ (uint32_t)((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | \
+ PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
+#define PWR_WAKEUP_PIN4_LOW \
+ (uint32_t)((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | \
+ PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
+#define PWR_WAKEUP_PIN5_LOW \
+ (uint32_t)((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | \
+ PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
+ * @{
+ */
+#if defined(PWR_CR2_PVME1)
+#define PWR_PVM_1 \
+ PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 \
+ V (applicable when USB feature is supported) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_PVM_2 \
+ PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 \
+ V (applicable when VDDIO2 is present on device) */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_PVM_3 \
+ PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 \
+ V */
+#define PWR_PVM_4 \
+ PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
+ * @{
+ */
+#define PWR_PVM_MODE_NORMAL 0x00000000U /*!< basic mode is used */
+#define PWR_PVM_MODE_IT_RISING \
+ 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection \
+ */
+#define PWR_PVM_MODE_IT_FALLING \
+ 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection \
+ */
+#define PWR_PVM_MODE_IT_RISING_FALLING \
+ 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger \
+ detection */
+#define PWR_PVM_MODE_EVENT_RISING \
+ 0x00020001U /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_EVENT_FALLING \
+ 0x00020002U /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING \
+ 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
+ * @{
+ */
+#if defined(PWR_CR5_R1MODE)
+#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST \
+ ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */
+#endif /*PWR_CR5_R1MODE */
+#define PWR_REGULATOR_VOLTAGE_SCALE1 \
+ PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 \
+ PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging
+ * resistor selection
+ * @{
+ */
+#define PWR_BATTERY_CHARGING_RESISTOR_5 \
+ 0x00000000U /*!< VBAT charging through a 5 kOhms resistor */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5 \
+ PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
+ * @{
+ */
+#define PWR_BATTERY_CHARGING_DISABLE 0x00000000U
+#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in
+ * standby/shutdown mode
+ * @{
+ */
+#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
+#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
+#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
+#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
+#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
+#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
+#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
+#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
+#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
+#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
+#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
+#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
+#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
+#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
+#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
+#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_GPIO GPIO port
+ * @{
+ */
+#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
+#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
+#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
+#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
+#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
+#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */
+#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
+ * @{
+ */
+#if defined(PWR_CR2_PVME1)
+#define PWR_EXTI_LINE_PVM1 \
+ 0x00000008U /*!< External interrupt line 35 Connected to the PVM1 EXTI Line \
+ */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_EXTI_LINE_PVM2 \
+ 0x00000010U /*!< External interrupt line 36 Connected to the PVM2 EXTI Line \
+ */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_EXTI_LINE_PVM3 \
+ 0x00000020U /*!< External interrupt line 37 Connected to the PVM3 EXTI Line \
+ */
+#define PWR_EXTI_LINE_PVM4 \
+ 0x00000040U /*!< External interrupt line 38 Connected to the PVM4 EXTI Line \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
+ * @{
+ */
+#if defined(PWR_CR2_PVME1)
+#define PWR_EVENT_LINE_PVM1 \
+ 0x00000008U /*!< Event line 35 Connected to the PVM1 EXTI Line */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_EVENT_LINE_PVM2 \
+ 0x00000010U /*!< Event line 36 Connected to the PVM2 EXTI Line */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_EVENT_LINE_PVM3 \
+ 0x00000020U /*!< Event line 37 Connected to the PVM3 EXTI Line */
+#define PWR_EVENT_LINE_PVM4 \
+ 0x00000040U /*!< Event line 38 Connected to the PVM4 EXTI Line */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Flag PWR Status Flags
+ * Elements values convention: 0000 0000 0XXY YYYYb
+ * - Y YYYY : Flag position in the XX register (5 bits)
+ * - XX : Status register (2 bits)
+ * - 01: SR1 register
+ * - 10: SR2 register
+ * The only exception is PWR_FLAG_WU, encompassing all
+ * wake-up flags and set to PWR_SR1_WUF.
+ * @{
+ */
+#define PWR_FLAG_WUF1 0x0020U /*!< Wakeup event on wakeup pin 1 */
+#define PWR_FLAG_WUF2 0x0021U /*!< Wakeup event on wakeup pin 2 */
+#define PWR_FLAG_WUF3 0x0022U /*!< Wakeup event on wakeup pin 3 */
+#define PWR_FLAG_WUF4 0x0023U /*!< Wakeup event on wakeup pin 4 */
+#define PWR_FLAG_WUF5 0x0024U /*!< Wakeup event on wakeup pin 5 */
+#define PWR_FLAG_WU \
+ PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
+#define PWR_FLAG_SB 0x0028U /*!< Standby flag */
+#define PWR_FLAG_WUFI 0x002FU /*!< Wakeup on internal wakeup line */
+
+#define PWR_FLAG_REGLPS 0x0048U /*!< Low-power regulator start flag */
+#define PWR_FLAG_REGLPF 0x0049U /*!< Low-power regulator flag */
+#define PWR_FLAG_VOSF 0x004AU /*!< Voltage scaling flag */
+#define PWR_FLAG_PVDO 0x004BU /*!< Power Voltage Detector output flag */
+#if defined(PWR_CR2_PVME1)
+#define PWR_FLAG_PVMO1 0x004CU /*!< Power Voltage Monitoring 1 output flag */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_FLAG_PVMO2 0x004DU /*!< Power Voltage Monitoring 2 output flag */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_FLAG_PVMO3 0x004EU /*!< Power Voltage Monitoring 3 output flag */
+#define PWR_FLAG_PVMO4 0x004FU /*!< Power Voltage Monitoring 4 output flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+#if defined(PWR_CR2_PVME1)
+/**
+ * @brief Enable the PVM1 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Disable the PVM1 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() \
+ CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Enable the PVM1 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() \
+ SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+ * @brief Disable the PVM1 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() \
+ CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+ * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() \
+ SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() \
+ CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() \
+ SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() \
+ CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() \
+ SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
+ * @retval EXTI PVM1 Line Status.
+ */
+#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
+
+/**
+ * @brief Clear the PVM1 EXTI flag.
+ * @retval None
+ */
+#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() \
+ WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
+
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+/**
+ * @brief Enable the PVM2 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Disable the PVM2 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() \
+ CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Enable the PVM2 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() \
+ SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+ * @brief Disable the PVM2 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() \
+ CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+ * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() \
+ SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() \
+ CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() \
+ SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() \
+ CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() \
+ SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
+ * @retval EXTI PVM2 Line Status.
+ */
+#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
+
+/**
+ * @brief Clear the PVM2 EXTI flag.
+ * @retval None
+ */
+#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() \
+ WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
+
+#endif /* PWR_CR2_PVME2 */
+
+/**
+ * @brief Enable the PVM3 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Disable the PVM3 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() \
+ CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Enable the PVM3 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() \
+ SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+ * @brief Disable the PVM3 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() \
+ CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+ * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() \
+ SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() \
+ CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() \
+ SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() \
+ CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() \
+ SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
+ * @retval EXTI PVM3 Line Status.
+ */
+#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Clear the PVM3 EXTI flag.
+ * @retval None
+ */
+#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() \
+ WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
+
+/**
+ * @brief Enable the PVM4 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Disable the PVM4 Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() \
+ CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Enable the PVM4 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() \
+ SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+ * @brief Disable the PVM4 Event Line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() \
+ CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+ * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() \
+ SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() \
+ CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() \
+ SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() \
+ CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() \
+ SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
+ * @retval EXTI PVM4 Line Status.
+ */
+#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Clear the PVM4 EXTI flag.
+ * @retval None
+ */
+#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() \
+ WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
+
+/**
+ * @brief Configure the main internal regulator output voltage.
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage
+ * output range 1 mode, typical output voltage at 1.28 V, system frequency up to
+ * 170 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output
+ * range 1 mode, typical output voltage at 1.2 V, system frequency up to 150
+ * MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output
+ * range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
+ * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but
+ * doesn't check whether or not VOSF flag is cleared when moving from range 2 to
+ * range 1. User may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit
+ * resetting.
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
+ do { \
+ __IO uint32_t tmpreg; \
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
+ * @{
+ */
+
+#define IS_PWR_WAKEUP_PIN(PIN) \
+ (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
+ ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) || \
+ ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
+ ((PIN) == PWR_WAKEUP_PIN2_HIGH) || ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
+ ((PIN) == PWR_WAKEUP_PIN4_HIGH) || ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
+ ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
+ ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
+ ((PIN) == PWR_WAKEUP_PIN5_LOW))
+
+#define IS_PWR_PVM_TYPE(TYPE) \
+ (((TYPE) == PWR_PVM_1) || ((TYPE) == PWR_PVM_2) || ((TYPE) == PWR_PVM_3) || \
+ ((TYPE) == PWR_PVM_4))
+
+#define IS_PWR_PVM_MODE(MODE) \
+ (((MODE) == PWR_PVM_MODE_NORMAL) || ((MODE) == PWR_PVM_MODE_IT_RISING) || \
+ ((MODE) == PWR_PVM_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) || \
+ ((MODE) == PWR_PVM_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) || \
+ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
+
+#if defined(PWR_CR5_R1MODE)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \
+ (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \
+ (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#endif
+
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \
+ (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) || \
+ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+
+#define IS_PWR_BATTERY_CHARGING(CHARGING) \
+ (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) || \
+ ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
+
+#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) \
+ (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
+#define IS_PWR_GPIO(GPIO) \
+ (((GPIO) == PWR_GPIO_A) || ((GPIO) == PWR_GPIO_B) || \
+ ((GPIO) == PWR_GPIO_C) || ((GPIO) == PWR_GPIO_D) || \
+ ((GPIO) == PWR_GPIO_E) || ((GPIO) == PWR_GPIO_F) || ((GPIO) == PWR_GPIO_G))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control
+ * functions
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
+void HAL_PWREx_DisableBatteryCharging(void);
+void HAL_PWREx_EnableInternalWakeUpLine(void);
+void HAL_PWREx_DisableInternalWakeUpLine(void);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber);
+void HAL_PWREx_EnablePullUpPullDownConfig(void);
+void HAL_PWREx_DisablePullUpPullDownConfig(void);
+void HAL_PWREx_EnableSRAM2ContentRetention(void);
+void HAL_PWREx_DisableSRAM2ContentRetention(void);
+#if defined(PWR_CR2_PVME1)
+void HAL_PWREx_EnablePVM1(void);
+void HAL_PWREx_DisablePVM1(void);
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+void HAL_PWREx_EnablePVM2(void);
+void HAL_PWREx_DisablePVM2(void);
+#endif /* PWR_CR2_PVME2 */
+void HAL_PWREx_EnablePVM3(void);
+void HAL_PWREx_DisablePVM3(void);
+void HAL_PWREx_EnablePVM4(void);
+void HAL_PWREx_DisablePVM4(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWREx_EnableLowPowerRunMode(void);
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSHUTDOWNMode(void);
+
+void HAL_PWREx_PVD_PVM_IRQHandler(void);
+#if defined(PWR_CR2_PVME1)
+void HAL_PWREx_PVM1Callback(void);
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+void HAL_PWREx_PVM2Callback(void);
+#endif /* PWR_CR2_PVME2 */
+void HAL_PWREx_PVM3Callback(void);
+void HAL_PWREx_PVM4Callback(void);
+
+#if defined(PWR_CR3_UCPD_STDBY)
+void HAL_PWREx_EnableUCPDStandbyMode(void);
+void HAL_PWREx_DisableUCPDStandbyMode(void);
+#endif /* PWR_CR3_UCPD_STDBY */
+#if defined(PWR_CR3_UCPD_DBDIS)
+void HAL_PWREx_EnableUCPDDeadBattery(void);
+void HAL_PWREx_DisableUCPDDeadBattery(void);
+#endif /* PWR_CR3_UCPD_DBDIS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_PWR_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
index ceb7942..95e1185 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
@@ -1,4162 +1,4162 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_RCC_H
-#define STM32G4xx_HAL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct {
- uint32_t
- PLLState; /*!< The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref
- RCC_PLL_Clock_Source */
-
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a value of @ref
- RCC_PLLM_Clock_Divider */
-
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 8 and
- Max_Data = 127 */
-
- uint32_t PLLP; /*!< PLLP: Division factor for ADC clock.
- This parameter must be a value of @ref
- RCC_PLLP_Clock_Divider */
-
- uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI
- clocks. This parameter must be a value of @ref
- RCC_PLLQ_Clock_Divider */
-
- uint32_t PLLR; /*!< PLLR: Division for the main system clock.
- User have to set the PLLR parameter correctly to not
- exceed max frequency 170MHZ. This parameter must be a value
- of @ref RCC_PLLR_Clock_Divider */
-
-} RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI)
- * configuration structure definition
- */
-typedef struct {
- uint32_t OscillatorType; /*!< The oscillators to be configured.
- This parameter can be a value of @ref
- RCC_Oscillator_Type */
-
- uint32_t
- HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
-
- uint32_t
- LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
-
- uint32_t
- HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is
- RCC_HSICALIBRATION_DEFAULT). This parameter
- must be a number between Min_Data = 0x00 and
- Max_Data = 0xFF */
-
- uint32_t
- LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
-
- uint32_t
- HSI48State; /*!< The new state of the HSI48.
- This parameter can be a value of @ref RCC_HSI48_Config */
-
- RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
-
-} RCC_OscInitTypeDef;
-
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure
- * definition
- */
-typedef struct {
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref
- RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
- This parameter can be a value of @ref
- RCC_System_Clock_Source */
-
- uint32_t
- AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived
- from the system clock (SYSCLK). This parameter can be a
- value of @ref RCC_AHB_Clock_Source */
-
- uint32_t
- APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived
- from the AHB clock (HCLK). This parameter can be a
- value of @ref RCC_APB1_APB2_Clock_Source */
-
- uint32_t
- APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived
- from the AHB clock (HCLK). This parameter can be a
- value of @ref RCC_APB1_APB2_Clock_Source */
-
-} RCC_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_Timeout_Value Timeout Values
- * @{
- */
-#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
- * @{
- */
-#define RCC_OSCILLATORTYPE_NONE \
- 0x00000000U /*!< Oscillator configuration unchanged */
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
-#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Config HSE Config
- * @{
- */
-#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
-#define RCC_HSE_BYPASS \
- (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Config LSE Config
- * @{
- */
-#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
-#define RCC_LSE_BYPASS \
- (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock \
- */
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Config HSI Config
- * @{
- */
-#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-#define RCC_HSICALIBRATION_DEFAULT \
- 0x40U /* Default HSI calibration trimming value */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Config LSI Config
- * @{
- */
-#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI48_Config HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
-#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Config PLL Config
- * @{
- */
-#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
-#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
-#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
- * @{
- */
-#define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */
-#define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */
-#define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */
-#define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */
-#define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */
-#define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */
-#define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */
-#define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */
-#define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */
-#define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */
-#define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */
-#define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */
-#define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */
-#define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */
-#define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */
-#define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
- * @{
- */
-#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
-#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
-#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
-#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
-#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
-#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
-#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
-#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
-#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
-#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
-#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
-#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
-#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
-#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
-#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
-#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
-#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
-#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
-#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
-#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
-#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
-#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
-#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
-#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
-#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
-#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
-#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
-#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
-#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
-#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
- * @{
- */
-#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
-#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
-#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
-#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
- * @{
- */
-#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
-#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
-#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
-#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_NONE \
- 0x00000000U /*!< No clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSI \
- RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE \
- RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
- * @{
- */
-#define RCC_PLL_ADCCLK \
- RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
-#define RCC_PLL_48M1CLK \
- RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
-#define RCC_PLL_SYSCLK \
- RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL \
- */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI \
- RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSE \
- RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK \
- RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI \
- RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE \
- RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK \
- RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSE \
- RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI \
- RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV32 \
- RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Index MCO Index
- * @{
- */
-/* 32 28 20 16 0
- --------------------------------
- | MCO | GPIO | GPIO | GPIO |
- | Index | AF | Port | Pin |
- -------------------------------*/
-
-#define RCC_MCO_GPIOPORT_POS 16U
-#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
-#define RCC_MCO_GPIOAF_POS 20U
-#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
-#define RCC_MCO_INDEX_POS 28U
-#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
-#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */
-#define RCC_MCO_PA8 \
- (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \
- (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
-#define RCC_MCO_PG10 \
- (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \
- (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
-
-/* Legacy Defines*/
-#define RCC_MCO1 RCC_MCO_PA8
-#define RCC_MCO \
- RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
- * @{
- */
-#define RCC_MCO1SOURCE_NOCLOCK \
- 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
-#define RCC_MCO1SOURCE_SYSCLK \
- RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSI \
- (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSE \
- RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
-#define RCC_MCO1SOURCE_PLLCLK \
- (RCC_CFGR_MCOSEL_0 | \
- RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
-#define RCC_MCO1SOURCE_LSI \
- (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_LSE \
- (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1 | \
- RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSI48 \
- RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
- * @{
- */
-#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
-#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
-#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
-#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
-#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt Interrupts
- * @{
- */
-#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
-#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
-#define RCC_IT_LSECSS \
- RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
-#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag Flags
- * Elements values convention: XXXYYYYYb
- * - YYYYY : Flag position in the register
- * - XXX : Register index
- * - 001: CR register
- * - 010: BDCR register
- * - 011: CSR register
- * - 100: CRRCR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY \
- ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
-#define RCC_FLAG_HSERDY \
- ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
-#define RCC_FLAG_PLLRDY \
- ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY \
- ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
-#define RCC_FLAG_LSECSSD \
- ((BDCR_REG_INDEX << 5U) | \
- RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY \
- ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
-#define RCC_FLAG_OBLRST \
- ((CSR_REG_INDEX << 5U) | \
- RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
-#define RCC_FLAG_PINRST \
- ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
-#define RCC_FLAG_BORRST \
- ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
-#define RCC_FLAG_SFTRST \
- ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST \
- ((CSR_REG_INDEX << 5U) | \
- RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST \
- ((CSR_REG_INDEX << 5U) | \
- RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST \
- ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
-
-/* Flags in the CRRCR register */
-#define RCC_FLAG_HSI48RDY \
- ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSEDrive_Config LSE Drive Config
- * @{
- */
-#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
-#define RCC_LSEDRIVE_MEDIUMLOW \
- RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
-#define RCC_LSEDRIVE_MEDIUMHIGH \
- RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
-#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock
- * Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_DMA1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_DMA2_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_DMAMUX1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_CORDIC_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_FMAC_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_FLASH_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_CRC_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
-
-#define __HAL_RCC_DMAMUX1_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
-
-#define __HAL_RCC_CORDIC_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
-
-#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
-
-#define __HAL_RCC_FLASH_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
-
-#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock
- * Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOE_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOF_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_ADC12_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
-
-#define __HAL_RCC_GPIOB_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
-
-#define __HAL_RCC_GPIOC_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
-
-#define __HAL_RCC_GPIOD_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
-
-#define __HAL_RCC_GPIOE_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
-
-#define __HAL_RCC_GPIOG_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
-
-#define __HAL_RCC_ADC12_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_CLK_DISABLE() \
- CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* QUADSPI */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
-#endif /* QUADSPI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
- * @brief Enable or disable the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_TIM2_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM4_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_CRS_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_RTCAPB_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_WWDG_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_SPI2_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_USART2_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_USART3_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_USB_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_I2C3_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_LPUART1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
-
-#define __HAL_RCC_TIM3_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
-
-#define __HAL_RCC_TIM4_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
-
-#define __HAL_RCC_TIM7_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
-
-#define __HAL_RCC_CRS_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
-
-#define __HAL_RCC_RTCAPB_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
-
-#define __HAL_RCC_WWDG_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN)
-
-#define __HAL_RCC_SPI2_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
-
-#define __HAL_RCC_SPI3_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
-
-#define __HAL_RCC_USART2_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
-
-#define __HAL_RCC_USART3_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
-
-#define __HAL_RCC_I2C2_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
-
-#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
-
-#define __HAL_RCC_I2C3_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
-
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
-
-#define __HAL_RCC_LPUART1_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM8_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_USART1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- UNUSED(tmpreg); \
- } while (0)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_CLK_ENABLE() \
- do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
- UNUSED(tmpreg); \
- } while (0)
-#endif /* HRTIM1 */
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
-
-#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
-
-#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
-
-#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
-
-#define __HAL_RCC_USART1_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
-
-#define __HAL_RCC_TIM16_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
-
-#define __HAL_RCC_TIM17_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_CLK_DISABLE() \
- CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral
- * Clock Enabled or Disabled Status
- * @brief Check whether the AHB1 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
-
-#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
-
-#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
-
-#define __HAL_RCC_FMAC_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
-
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
-
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
-
-#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
-
-#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
-
-#define __HAL_RCC_FMAC_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
-
-#define __HAL_RCC_FLASH_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled
- * or Disabled Status
- * @brief Check whether the AHB2 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
-
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
-
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
-
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
-
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
-
-#define __HAL_RCC_ADC12_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
-
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
-
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
-
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
-
-#define __HAL_RCC_ADC12_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled
- * or Disabled Status
- * @brief Check whether the AHB3 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED() \
- (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
-#endif /* QUADSPI */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() \
- (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
-#endif /* QUADSPI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled
- * or Disabled Status
- * @brief Check whether the APB1 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
-
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
-
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
-
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
-
-#define __HAL_RCC_CRS_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
-
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
-
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
-
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
-
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
-
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
-
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
-
-#define __HAL_RCC_USB_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
-
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
-
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
-
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
-
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
-
-#define __HAL_RCC_CRS_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
-
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
-
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
-
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
-
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
-
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
-
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
-
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
-
-#if defined(USB)
-#define __HAL_RCC_USB_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
-#endif /* USB */
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
-
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled
- * or Disabled Status
- * @brief Check whether the APB2 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write
- * access) is disabled and the application software has to enable this clock
- * before using it.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
-
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
-
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
-
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
-
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
-#endif /* HRTIM1 */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
-
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
-
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
-
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() \
- (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
- * @brief Force or release AHB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_DMA1_FORCE_RESET() \
- SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
-
-#define __HAL_RCC_DMA2_FORCE_RESET() \
- SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
-
-#define __HAL_RCC_DMAMUX1_FORCE_RESET() \
- SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
-
-#define __HAL_RCC_CORDIC_FORCE_RESET() \
- SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
-
-#define __HAL_RCC_FMAC_FORCE_RESET() \
- SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
-
-#define __HAL_RCC_FLASH_FORCE_RESET() \
- SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
-
-#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
-
-#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
-
-#define __HAL_RCC_DMA1_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
-
-#define __HAL_RCC_DMA2_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
-
-#define __HAL_RCC_DMAMUX1_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
-
-#define __HAL_RCC_CORDIC_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
-
-#define __HAL_RCC_FMAC_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
-
-#define __HAL_RCC_FLASH_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
-
-#define __HAL_RCC_CRC_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
- * @brief Force or release AHB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_GPIOA_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
-
-#define __HAL_RCC_GPIOB_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
-
-#define __HAL_RCC_GPIOC_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
-
-#define __HAL_RCC_GPIOD_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
-
-#define __HAL_RCC_GPIOE_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
-
-#define __HAL_RCC_GPIOF_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
-
-#define __HAL_RCC_GPIOG_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
-
-#define __HAL_RCC_ADC12_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_FORCE_RESET() \
- SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
-
-#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
-
-#define __HAL_RCC_GPIOA_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
-
-#define __HAL_RCC_GPIOB_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
-
-#define __HAL_RCC_GPIOC_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
-
-#define __HAL_RCC_GPIOG_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
-
-#define __HAL_RCC_ADC12_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
- * @brief Force or release AHB3 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_FORCE_RESET() \
- SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
-#endif /* QUADSPI */
-
-#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_RELEASE_RESET() \
- CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
-#endif /* QUADSPI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
-
-#define __HAL_RCC_TIM2_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
-
-#define __HAL_RCC_TIM3_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
-
-#define __HAL_RCC_TIM4_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
-
-#define __HAL_RCC_TIM7_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
-
-#define __HAL_RCC_CRS_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
-
-#define __HAL_RCC_SPI2_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
-
-#define __HAL_RCC_SPI3_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
-
-#define __HAL_RCC_USART2_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
-
-#define __HAL_RCC_USART3_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
-
-#define __HAL_RCC_I2C2_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
-
-#define __HAL_RCC_USB_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
-
-#define __HAL_RCC_I2C3_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
-
-#define __HAL_RCC_LPTIM1_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
-
-#define __HAL_RCC_LPUART1_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_FORCE_RESET() \
- SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
-
-#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
-
-#define __HAL_RCC_TIM2_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
-
-#define __HAL_RCC_TIM3_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
-
-#define __HAL_RCC_TIM4_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
-
-#define __HAL_RCC_TIM7_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
-
-#define __HAL_RCC_CRS_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
-
-#define __HAL_RCC_SPI2_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
-
-#define __HAL_RCC_SPI3_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
-
-#define __HAL_RCC_USART2_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
-
-#define __HAL_RCC_USART3_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
-
-#define __HAL_RCC_I2C2_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
-
-#define __HAL_RCC_USB_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
-
-#define __HAL_RCC_I2C3_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
-
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
-
-#define __HAL_RCC_LPUART1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_SYSCFG_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
-
-#define __HAL_RCC_TIM1_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
-
-#define __HAL_RCC_SPI1_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
-
-#define __HAL_RCC_TIM8_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
-
-#define __HAL_RCC_USART1_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
-
-#define __HAL_RCC_TIM16_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
-
-#define __HAL_RCC_TIM17_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_FORCE_RESET() \
- SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
-#endif /* HRTIM1 */
-
-#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
-
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
-
-#define __HAL_RCC_TIM1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
-
-#define __HAL_RCC_SPI1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
-
-#define __HAL_RCC_TIM8_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
-
-#define __HAL_RCC_USART1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
-
-#define __HAL_RCC_TIM16_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
-
-#define __HAL_RCC_TIM17_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_RELEASE_RESET() \
- CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep
- * Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep)
- * mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
-
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
-
-#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
-
-#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
-
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
-
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
-
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
-
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
-
-#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
-
-#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
-
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
-
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
-
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep
- * Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep)
- * mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
-
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
-
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
-
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
-
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
-
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
-
-#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
-
-#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
-
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
-
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
-
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
-
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
-
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
-
-#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
-
-#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep
- * Enable Disable
- * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep)
- * mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
-#endif /* QUADSPI */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
-#endif /* QUADSPI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep
- * Enable Disable
- * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep)
- * mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
-
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
-
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
-
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
-
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
-
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
-
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
-
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
-
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
-
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
-
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
-
-#if defined(USB)
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
-#endif /* USB */
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
-
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
-
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
-
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
-
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
-
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
-
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
-
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
-
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
-
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
-
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
-
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
-
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
-
-#if defined(USB)
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
-#endif /* USB */
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
-
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
-
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep
- * Enable Disable
- * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep)
- * mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
-
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
-
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
-
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
-
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
-
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() \
- SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
-#endif /* HRTIM1 */
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
-
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
-
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
-
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
-
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
-
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() \
- CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock
- * Sleep Enabled or Disabled Status
- * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode
- * is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
-
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
-
-#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
-
-#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
-
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
-
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
-
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
-
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
-
-#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
-
-#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
-
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
-
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock
- * Sleep Enabled or Disabled Status
- * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode
- * is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
-
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
-
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
-
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
-
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
-
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
-
-#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
-
-#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
-
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
-
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
-
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
-
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
-
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
-
-#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
-
-#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
-
-#if defined(ADC345_COMMON)
-#define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
-#endif /* ADC345_COMMON */
-
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
-
-#if defined(DAC2)
-#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
-#endif /* DAC2 */
-
-#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
-
-#if defined(DAC4)
-#define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
-#endif /* DAC4 */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock
- * Sleep Enabled or Disabled Status
- * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode
- * is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
-#endif /* QUADSPI */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
-#endif /* QUADSPI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock
- * Sleep Enabled or Disabled Status
- * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode
- * is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
-
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
-
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
-
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
-
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
-
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
-
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
-
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
-
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
-
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
-
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
-
-#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
-
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
-
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
-
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
-
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
-
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
-
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
-
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
-
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
-
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
-
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
-
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
-
-#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
-
-#if defined(FDCAN1)
-#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
-#endif /* FDCAN1 */
-
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
-
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
-#endif /* I2C4 */
-
-#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock
- * Sleep Enabled or Disabled Status
- * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode
- * is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
-
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
-
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
-
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
-#endif /* HRTIM1 */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
-
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
-
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
-
-#if defined(SPI4)
-#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
-#endif /* SPI4 */
-
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
-
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
-
-#if defined(TIM20)
-#define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
-#endif /* TIM20 */
-
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
-
-#if defined(HRTIM1)
-#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() \
- (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
- * @{
- */
-
-/** @brief Macros to force or release the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup
- * registers) and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @retval None
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the RTC clock.
- * @note As the RTC is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
- * (to be done once after reset).
- * @note These macros must be used after the RTC clock source was selected.
- * @retval None
- */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-/**
- * @}
- */
-
-/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator
- * (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this
- * case, you have to select another source of the system clock then stop the
- * HSI.
- * @note After enabling the HSI, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
-
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-
-/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI)
- * calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x7F.
- * @retval None
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, \
- (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
-
-/**
- * @brief Macros to enable or disable the force of the Internal High Speed
- * oscillator (HSI) in STOP mode to be quickly available as kernel clock for
- * USARTs and I2Cs.
- * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the
- * communication speed because of the HSI startup time.
- * @note The enable of this function has not effect on the HSION bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
-
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the
- * application software should wait on HSERDY flag to be set indicating that HSE
- * clock is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security
- * system(CSS) was previously enabled you have to enable it again after calling
- * this function.
- * @param __STATE__ specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag
- * goes low after 6 HSE oscillator clock cycles.
- * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external
- * clock.
- * @retval None
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do { \
- if ((__STATE__) == RCC_HSE_ON) { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } else if ((__STATE__) == RCC_HSE_BYPASS) { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } else { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- } while (0)
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the
- * application software should wait on LSERDY flag to be set indicating that LSE
- * clock is stable and can be used to clock the RTC.
- * @param __STATE__ specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag
- * goes low after 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external
- * clock.
- * @retval None
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do { \
- if ((__STATE__) == RCC_LSE_ON) { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } else if ((__STATE__) == RCC_LSE_BYPASS) { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } else { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- } while (0)
-
-/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator
- * (HSI48).
- * @note The HSI48 is stopped by hardware when entering STOP and STANDBY
- * modes.
- * @note After enabling the HSI48, the application software should wait on
- * HSI48RDY flag to be set indicating that HSI48 clock is stable. This parameter
- * can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
-
-#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
-
-/** @brief Macros to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and
- * write access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it cannot be changed unless the
- * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or
- * by a Power On Reset (POR).
- *
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
- * selected
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- * @retval None
- */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-
-/** @brief Macro to get the RTC clock source.
- * @retval The returned value can be one of the following:
- * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
- * selected
- */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/** @brief Macros to enable or disable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY
- * modes.
- * @retval None
- */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
-
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief Macro to configure the PLL clock source.
- * @note This function must be used only when the main PLL is disabled.
- * @param __PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL
- * clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL
- * clock entry
- * @retval None
- *
- */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief Macro to configure the PLL source division factor M.
- * @note This function must be used only when the main PLL is disabled.
- * @param __PLLM__ specifies the division factor for PLL VCO input clock
- * This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO
- * input frequency ranges from 2.66 to 8 MHz. It is recommended to select a
- * frequency of 8 MHz to limit PLL jitter.
- * @retval None
- *
- */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, \
- ((__PLLM__)-1) << RCC_PLLCFGR_PLLM_Pos)
-
-/**
- * @brief Macro to configure the main PLL clock source, multiplication and
- * division factors.
- * @note This macro must be used only when the main PLL is disabled.
- * @note This macro preserves the PLL's output clocks enable state.
- *
- * @param __PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL
- * clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL
- * clock entry
- *
- * @param __PLLM__ specifies the division factor for PLL VCO input clock.
- * This parameter must be a value of @ref RCC_PLLM_Clock_Divider
- * @note You have to set the PLLM parameter correctly to ensure that the VCO
- * input frequency ranges from 2.66 to 8 MHz. It is recommended to select a
- * frequency of 8 MHz to limit PLL jitter.
- *
- * @param __PLLN__ specifies the multiplication factor for PLL VCO output
- * clock. This parameter must be a number between 8 and 127.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
- *
- * @param __PLLP__ specifies the division factor for SAI clock.
- * This parameter must be a number in the range (2 to 31).
- *
- * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG
- * clocks. This parameter must be in the range (2, 4, 6 or 8).
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to
- * work correctly.
- * @param __PLLR__ specifies the division factor for the main system clock.
- * @note You have to set the PLLR parameter correctly to not exceed 170MHZ.
- * This parameter must be in the range (2, 4, 6 or 8).
- * @retval None
- */
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, \
- __PLLQ__, __PLLR__) \
- MODIFY_REG(RCC->PLLCFGR, \
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
- ((__PLLSOURCE__) | (((__PLLM__)-1U) << RCC_PLLCFGR_PLLM_Pos) | \
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
- ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
-
-/** @brief Macro to get the oscillator used as PLL clock source.
- * @retval The oscillator used as PLL clock source. The returned value can be
- * one of the following:
- * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() \
- (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
-
-/**
- * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK,
- * RCC_PLL_ADCCLK)
- * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK
- * can be done at anytime without the need to stop the PLL in order to save
- * power. But RCC_PLL_SYSCLK cannot be stopped if used as System Clock.
- * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
- * This parameter can be one or a combination of the following values:
- * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock
- * on ADC.
- * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the
- * clock for the USB (48 MHz), FDCAN (<=48 MHz) and QSPI (<=48 MHz).
- * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high
- * speed system clock (up to 170MHz)
- * @retval None
- */
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) \
- SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) \
- CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
- * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK,
- * RCC_PLL_SAI3CLK)
- * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock
- * on ADC.
- * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the
- * clock for the USB (48 MHz), FDCAN (<=48 MHz) and QSPI (<=48 MHz).
- * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high
- * speed system clock (up to 170MHz)
- * @retval SET / RESET
- */
-#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) \
- READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
- * @brief Macro to configure the system clock source.
- * @param __SYSCLKSOURCE__ specifies the system clock source.
- * This parameter can be one of the following values:
- * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock
- * source.
- * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock
- * source.
- * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock
- * source.
- * @retval None
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE) drive
- * capability.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
- * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive
- * capability.
- * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high
- * drive capability.
- * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
- * @retval None
- */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
-
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO
- * source
- * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
- * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO
- * source
- * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
- * for devices with HSI48
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
- * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
- * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
- * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
- * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
- */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), \
- ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to
- * enable the selected interrupts).
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
- * HSI48
- * @retval None
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to
- * disable the selected interrupts).
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
- * HSI48
- * @retval None
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) \
- CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to
- * RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
- * HSI48
- * @retval None
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
-
-/** @brief Check whether the RCC interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
- * HSI48
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) \
- ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
- * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST,
- * RCC_FLAG_PINRST, RCC_FLAG_BORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
- * RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
- * @retval None
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief Check whether the selected RCC flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
- * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with
- * HSI48
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
- * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE
- * oscillator detection
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
- * @arg @ref RCC_FLAG_BORRST BOR reset
- * @arg @ref RCC_FLAG_OBLRST OBLRST reset
- * @arg @ref RCC_FLAG_PINRST Pin reset
- * @arg @ref RCC_FLAG_SFTRST Software reset
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_FLAG(__FLAG__) \
- (((((((__FLAG__) >> 5U) == 1U) \
- ? RCC->CR \
- : ((((__FLAG__) >> 5U) == 4U) \
- ? RCC->CRRCR \
- : ((((__FLAG__) >> 5U) == 2U) \
- ? RCC->BDCR \
- : ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR \
- : RCC->CIFR)))) & \
- ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
- ? 1U \
- : 0U)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RCC_Private_Constants
- * @{
- */
-/* Defines used for Flags */
-#define CR_REG_INDEX 1U
-#define BDCR_REG_INDEX 2U
-#define CSR_REG_INDEX 3U
-#define CRRCR_REG_INDEX 4U
-
-#define RCC_FLAG_MASK 0x1FU
-
-/* Define used for IS_RCC_CLOCKTYPE() */
-#define RCC_CLOCKTYPE_ALL \
- (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \
- RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros
- * @{
- */
-
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \
- (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == \
- RCC_OSCILLATORTYPE_HSI48) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-
-#define IS_RCC_HSE(__HSE__) \
- (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(__LSE__) \
- (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(__HSI__) \
- (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) \
- ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
-
-#define IS_RCC_LSI(__LSI__) \
- (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-
-#define IS_RCC_HSI48(__HSI48__) \
- (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
-
-#define IS_RCC_PLL(__PLL__) \
- (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
- ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSI) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_PLLM_VALUE(__VALUE__) \
- ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
-
-#define IS_RCC_PLLN_VALUE(__VALUE__) \
- ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
-
-#define IS_RCC_PLLP_VALUE(__VALUE__) \
- (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
-
-#define IS_RCC_PLLQ_VALUE(__VALUE__) \
- (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || ((__VALUE__) == 6U) || \
- ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLR_VALUE(__VALUE__) \
- (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || ((__VALUE__) == 6U) || \
- ((__VALUE__) == 8U))
-
-#define IS_RCC_CLOCKTYPE(__CLK__) \
- ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && \
- (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
-
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_HCLK(__HCLK__) \
- (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_PCLK(__PCLK__) \
- (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
-
-#define IS_RCC_MCO(__MCOX__) \
- (((__MCOX__) == RCC_MCO_PA8) || ((__MCOX__) == RCC_MCO_PG10))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
-
-#define IS_RCC_MCODIV(__DIV__) \
- (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
- ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
- ((__DIV__) == RCC_MCODIV_16))
-
-#define IS_RCC_LSE_DRIVE(__DRIVE__) \
- (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
- ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
-
-/**
- * @}
- */
-
-/* Include RCC HAL Extended module */
-#include "stm32g4xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions
- * ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
- uint32_t FLatency);
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions
- * ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource,
- uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_EnableLSECSS(void);
-void HAL_RCC_DisableLSECSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
- uint32_t *pFLatency);
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_RCC_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_RCC_H
+#define STM32G4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct {
+ uint32_t
+ PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref
+ RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a value of @ref
+ RCC_PLLM_Clock_Divider */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 8 and
+ Max_Data = 127 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for ADC clock.
+ This parameter must be a value of @ref
+ RCC_PLLP_Clock_Divider */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI
+ clocks. This parameter must be a value of @ref
+ RCC_PLLQ_Clock_Divider */
+
+ uint32_t PLLR; /*!< PLLR: Division for the main system clock.
+ User have to set the PLLR parameter correctly to not
+ exceed max frequency 170MHZ. This parameter must be a value
+ of @ref RCC_PLLR_Clock_Divider */
+
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI)
+ * configuration structure definition
+ */
+typedef struct {
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref
+ RCC_Oscillator_Type */
+
+ uint32_t
+ HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t
+ LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t
+ HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is
+ RCC_HSICALIBRATION_DEFAULT). This parameter
+ must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF */
+
+ uint32_t
+ LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ uint32_t
+ HSI48State; /*!< The new state of the HSI48.
+ This parameter can be a value of @ref RCC_HSI48_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
+
+} RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure
+ * definition
+ */
+typedef struct {
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref
+ RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
+ This parameter can be a value of @ref
+ RCC_System_Clock_Source */
+
+ uint32_t
+ AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived
+ from the system clock (SYSCLK). This parameter can be a
+ value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t
+ APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived
+ from the AHB clock (HCLK). This parameter can be a
+ value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t
+ APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived
+ from the AHB clock (HCLK). This parameter can be a
+ value of @ref RCC_APB1_APB2_Clock_Source */
+
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout_Value Timeout Values
+ * @{
+ */
+#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE \
+ 0x00000000U /*!< Oscillator configuration unchanged */
+#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
+#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
+#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
+#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
+#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
+#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
+#define RCC_HSE_BYPASS \
+ (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
+#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
+#define RCC_LSE_BYPASS \
+ (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
+#define RCC_HSICALIBRATION_DEFAULT \
+ 0x40U /* Default HSI calibration trimming value */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI48_Config HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
+#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
+#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
+#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
+ * @{
+ */
+#define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */
+#define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */
+#define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */
+#define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */
+#define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */
+#define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */
+#define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */
+#define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */
+#define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */
+#define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */
+#define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */
+#define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */
+#define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */
+#define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */
+#define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */
+#define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+ * @{
+ */
+#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
+#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
+#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
+#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
+#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
+#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
+#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
+#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
+#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
+#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
+#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
+#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
+#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
+#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
+#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
+#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
+#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
+#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
+#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
+#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
+#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
+#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
+#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
+#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
+#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
+#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
+#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
+#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
+#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
+#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
+ * @{
+ */
+#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
+#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
+#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
+#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
+ * @{
+ */
+#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
+#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
+#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
+#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_NONE \
+ 0x00000000U /*!< No clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSI \
+ RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE \
+ RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
+ * @{
+ */
+#define RCC_PLL_ADCCLK \
+ RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
+#define RCC_PLL_48M1CLK \
+ RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
+#define RCC_PLL_SYSCLK \
+ RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI \
+ RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSE \
+ RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK \
+ RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI \
+ RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE \
+ RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK \
+ RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSE \
+ RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI \
+ RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32 \
+ RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+/* 32 28 20 16 0
+ --------------------------------
+ | MCO | GPIO | GPIO | GPIO |
+ | Index | AF | Port | Pin |
+ -------------------------------*/
+
+#define RCC_MCO_GPIOPORT_POS 16U
+#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
+#define RCC_MCO_GPIOAF_POS 20U
+#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
+#define RCC_MCO_INDEX_POS 28U
+#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
+#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */
+#define RCC_MCO_PA8 \
+ (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \
+ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
+#define RCC_MCO_PG10 \
+ (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \
+ (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
+
+/* Legacy Defines*/
+#define RCC_MCO1 RCC_MCO_PA8
+#define RCC_MCO \
+ RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK \
+ 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
+#define RCC_MCO1SOURCE_SYSCLK \
+ RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI \
+ (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSE \
+ RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_PLLCLK \
+ (RCC_CFGR_MCOSEL_0 | \
+ RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSI \
+ (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSE \
+ (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1 | \
+ RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI48 \
+ RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
+#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
+#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
+#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
+#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
+#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
+#define RCC_IT_LSECSS \
+ RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
+#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: BDCR register
+ * - 011: CSR register
+ * - 100: CRRCR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY \
+ ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
+#define RCC_FLAG_HSERDY \
+ ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
+#define RCC_FLAG_PLLRDY \
+ ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY \
+ ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
+#define RCC_FLAG_LSECSSD \
+ ((BDCR_REG_INDEX << 5U) | \
+ RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY \
+ ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
+#define RCC_FLAG_OBLRST \
+ ((CSR_REG_INDEX << 5U) | \
+ RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
+#define RCC_FLAG_PINRST \
+ ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
+#define RCC_FLAG_BORRST \
+ ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
+#define RCC_FLAG_SFTRST \
+ ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST \
+ ((CSR_REG_INDEX << 5U) | \
+ RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST \
+ ((CSR_REG_INDEX << 5U) | \
+ RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST \
+ ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
+
+/* Flags in the CRRCR register */
+#define RCC_FLAG_HSI48RDY \
+ ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+ * @{
+ */
+#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW \
+ RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH \
+ RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock
+ * Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_DMAMUX1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_CORDIC_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_FMAC_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_FLASH_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_CRC_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
+
+#define __HAL_RCC_DMAMUX1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
+
+#define __HAL_RCC_CORDIC_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
+
+#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
+
+#define __HAL_RCC_FLASH_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
+
+#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock
+ * Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_ADC12_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
+
+#define __HAL_RCC_GPIOB_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
+
+#define __HAL_RCC_GPIOC_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
+
+#define __HAL_RCC_GPIOE_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
+
+#define __HAL_RCC_GPIOG_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
+
+#define __HAL_RCC_ADC12_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_DISABLE() \
+ CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
+#endif /* QUADSPI */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_WWDG_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_USB_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
+
+#define __HAL_RCC_TIM4_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
+
+#define __HAL_RCC_TIM7_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
+
+#define __HAL_RCC_CRS_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
+
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
+
+#define __HAL_RCC_WWDG_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
+
+#define __HAL_RCC_SPI3_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
+
+#define __HAL_RCC_USART2_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
+
+#define __HAL_RCC_USART3_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
+
+#define __HAL_RCC_I2C2_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
+
+#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
+
+#define __HAL_RCC_I2C3_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
+
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
+
+#define __HAL_RCC_LPUART1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE() \
+ do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
+ UNUSED(tmpreg); \
+ } while (0)
+#endif /* HRTIM1 */
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
+
+#define __HAL_RCC_USART1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
+
+#define __HAL_RCC_TIM16_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
+
+#define __HAL_RCC_TIM17_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_DISABLE() \
+ CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral
+ * Clock Enabled or Disabled Status
+ * @brief Check whether the AHB1 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled
+ * or Disabled Status
+ * @brief Check whether the AHB2 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled
+ * or Disabled Status
+ * @brief Check whether the AHB3 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
+#endif /* QUADSPI */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled
+ * or Disabled Status
+ * @brief Check whether the APB1 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
+
+#define __HAL_RCC_USB_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
+
+#if defined(USB)
+#define __HAL_RCC_USB_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
+#endif /* USB */
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled
+ * or Disabled Status
+ * @brief Check whether the APB2 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write
+ * access) is disabled and the application software has to enable this clock
+ * before using it.
+ * @{
+ */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
+#endif /* HRTIM1 */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() \
+ (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_DMA1_FORCE_RESET() \
+ SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
+
+#define __HAL_RCC_DMA2_FORCE_RESET() \
+ SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
+
+#define __HAL_RCC_DMAMUX1_FORCE_RESET() \
+ SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
+
+#define __HAL_RCC_CORDIC_FORCE_RESET() \
+ SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
+
+#define __HAL_RCC_FMAC_FORCE_RESET() \
+ SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
+
+#define __HAL_RCC_FLASH_FORCE_RESET() \
+ SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
+
+#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
+
+#define __HAL_RCC_DMA1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
+
+#define __HAL_RCC_DMA2_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
+
+#define __HAL_RCC_DMAMUX1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
+
+#define __HAL_RCC_CORDIC_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
+
+#define __HAL_RCC_FMAC_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
+
+#define __HAL_RCC_FLASH_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
+
+#define __HAL_RCC_CRC_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_GPIOA_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
+
+#define __HAL_RCC_GPIOB_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
+
+#define __HAL_RCC_GPIOD_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
+
+#define __HAL_RCC_GPIOE_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
+
+#define __HAL_RCC_GPIOF_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
+
+#define __HAL_RCC_GPIOG_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
+
+#define __HAL_RCC_ADC12_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_FORCE_RESET() \
+ SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_GPIOA_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
+
+#define __HAL_RCC_GPIOB_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
+
+#define __HAL_RCC_GPIOG_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
+
+#define __HAL_RCC_ADC12_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET() \
+ SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
+#endif /* QUADSPI */
+
+#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET() \
+ CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
+#endif /* QUADSPI */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
+
+#define __HAL_RCC_TIM2_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#define __HAL_RCC_TIM3_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+
+#define __HAL_RCC_TIM4_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#define __HAL_RCC_CRS_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+
+#define __HAL_RCC_SPI2_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+
+#define __HAL_RCC_SPI3_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
+
+#define __HAL_RCC_USART2_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#define __HAL_RCC_USART3_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#define __HAL_RCC_I2C2_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+
+#define __HAL_RCC_USB_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
+
+#define __HAL_RCC_I2C3_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
+
+#define __HAL_RCC_LPTIM1_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
+
+#define __HAL_RCC_LPUART1_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_FORCE_RESET() \
+ SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+
+#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+
+#define __HAL_RCC_TIM4_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#define __HAL_RCC_CRS_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+
+#define __HAL_RCC_SPI2_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+
+#define __HAL_RCC_SPI3_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
+
+#define __HAL_RCC_USART2_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#define __HAL_RCC_USART3_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#define __HAL_RCC_I2C2_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+
+#define __HAL_RCC_USB_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
+
+#define __HAL_RCC_I2C3_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
+
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
+
+#define __HAL_RCC_LPUART1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_SYSCFG_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
+
+#define __HAL_RCC_TIM1_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#define __HAL_RCC_TIM8_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+
+#define __HAL_RCC_USART1_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#define __HAL_RCC_TIM17_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_FORCE_RESET() \
+ SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
+#endif /* HRTIM1 */
+
+#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
+
+#define __HAL_RCC_TIM1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+
+#define __HAL_RCC_USART1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#define __HAL_RCC_TIM17_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_RELEASE_RESET() \
+ CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep
+ * Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep)
+ * mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
+
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
+
+#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
+
+#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
+
+#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
+
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
+
+#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
+
+#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
+
+#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep
+ * Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep)
+ * mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
+
+#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
+
+#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep
+ * Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep)
+ * mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
+#endif /* QUADSPI */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep
+ * Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep)
+ * mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
+#endif /* USB */
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
+#endif /* USB */
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep
+ * Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep)
+ * mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() \
+ SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
+#endif /* HRTIM1 */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() \
+ CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock
+ * Sleep Enabled or Disabled Status
+ * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode
+ * is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
+
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
+
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock
+ * Sleep Enabled or Disabled Status
+ * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode
+ * is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
+
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
+
+#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
+
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
+
+#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock
+ * Sleep Enabled or Disabled Status
+ * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode
+ * is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
+#endif /* QUADSPI */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock
+ * Sleep Enabled or Disabled Status
+ * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode
+ * is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
+
+#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
+
+#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock
+ * Sleep Enabled or Disabled Status
+ * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode
+ * is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
+#endif /* HRTIM1 */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() \
+ (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
+ * @{
+ */
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup
+ * registers) and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ * @retval None
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the RTC clock.
+ * @note As the RTC is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
+ * (to be done once after reset).
+ * @note These macros must be used after the RTC clock source was selected.
+ * @retval None
+ */
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/**
+ * @}
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator
+ * (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this
+ * case, you have to select another source of the system clock then stop the
+ * HSI.
+ * @note After enabling the HSI, the application software should wait on
+ * HSIRDY flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
+
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI)
+ * calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x7F.
+ * @retval None
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, \
+ (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
+
+/**
+ * @brief Macros to enable or disable the force of the Internal High Speed
+ * oscillator (HSI) in STOP mode to be quickly available as kernel clock for
+ * USARTs and I2Cs.
+ * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the
+ * communication speed because of the HSI startup time.
+ * @note The enable of this function has not effect on the HSION bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
+
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the
+ * application software should wait on HSERDY flag to be set indicating that HSE
+ * clock is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security
+ * system(CSS) was previously enabled you have to enable it again after calling
+ * this function.
+ * @param __STATE__ specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag
+ * goes low after 6 HSE oscillator clock cycles.
+ * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
+ * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external
+ * clock.
+ * @retval None
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do { \
+ if ((__STATE__) == RCC_HSE_ON) { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } else if ((__STATE__) == RCC_HSE_BYPASS) { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } else { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ } while (0)
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the
+ * application software should wait on LSERDY flag to be set indicating that LSE
+ * clock is stable and can be used to clock the RTC.
+ * @param __STATE__ specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag
+ * goes low after 6 LSE oscillator clock cycles.
+ * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external
+ * clock.
+ * @retval None
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do { \
+ if ((__STATE__) == RCC_LSE_ON) { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } else if ((__STATE__) == RCC_LSE_BYPASS) { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } else { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ } while (0)
+
+/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator
+ * (HSI48).
+ * @note The HSI48 is stopped by hardware when entering STOP and STANDBY
+ * modes.
+ * @note After enabling the HSI48, the application software should wait on
+ * HSI48RDY flag to be set indicating that HSI48 clock is stable. This parameter
+ * can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
+
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
+
+/** @brief Macros to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and
+ * write access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it cannot be changed unless the
+ * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or
+ * by a Power On Reset (POR).
+ *
+ * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
+ * selected
+ *
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ * @retval None
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The returned value can be one of the following:
+ * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
+ * selected
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief Macros to enable or disable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY
+ * modes.
+ * @retval None
+ */
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief Macro to configure the PLL clock source.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __PLLSOURCE__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL
+ * clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL
+ * clock entry
+ * @retval None
+ *
+ */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief Macro to configure the PLL source division factor M.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
+ * This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO
+ * input frequency ranges from 2.66 to 8 MHz. It is recommended to select a
+ * frequency of 8 MHz to limit PLL jitter.
+ * @retval None
+ *
+ */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, \
+ ((__PLLM__)-1) << RCC_PLLCFGR_PLLM_Pos)
+
+/**
+ * @brief Macro to configure the main PLL clock source, multiplication and
+ * division factors.
+ * @note This macro must be used only when the main PLL is disabled.
+ * @note This macro preserves the PLL's output clocks enable state.
+ *
+ * @param __PLLSOURCE__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL
+ * clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL
+ * clock entry
+ *
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock.
+ * This parameter must be a value of @ref RCC_PLLM_Clock_Divider
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO
+ * input frequency ranges from 2.66 to 8 MHz. It is recommended to select a
+ * frequency of 8 MHz to limit PLL jitter.
+ *
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output
+ * clock. This parameter must be a number between 8 and 127.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 64 and 344 MHz.
+ *
+ * @param __PLLP__ specifies the division factor for SAI clock.
+ * This parameter must be a number in the range (2 to 31).
+ *
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG
+ * clocks. This parameter must be in the range (2, 4, 6 or 8).
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to
+ * work correctly.
+ * @param __PLLR__ specifies the division factor for the main system clock.
+ * @note You have to set the PLLR parameter correctly to not exceed 170MHZ.
+ * This parameter must be in the range (2, 4, 6 or 8).
+ * @retval None
+ */
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, \
+ __PLLQ__, __PLLR__) \
+ MODIFY_REG(RCC->PLLCFGR, \
+ (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
+ RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
+ ((__PLLSOURCE__) | (((__PLLM__)-1U) << RCC_PLLCFGR_PLLM_Pos) | \
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
+ ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
+ ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
+
+/** @brief Macro to get the oscillator used as PLL clock source.
+ * @retval The oscillator used as PLL clock source. The returned value can be
+ * one of the following:
+ * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() \
+ (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
+
+/**
+ * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK,
+ * RCC_PLL_ADCCLK)
+ * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK
+ * can be done at anytime without the need to stop the PLL in order to save
+ * power. But RCC_PLL_SYSCLK cannot be stopped if used as System Clock.
+ * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
+ * This parameter can be one or a combination of the following values:
+ * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock
+ * on ADC.
+ * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the
+ * clock for the USB (48 MHz), FDCAN (<=48 MHz) and QSPI (<=48 MHz).
+ * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high
+ * speed system clock (up to 170MHz)
+ * @retval None
+ */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) \
+ SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) \
+ CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+/**
+ * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK,
+ * RCC_PLL_SAI3CLK)
+ * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock
+ * on ADC.
+ * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the
+ * clock for the USB (48 MHz), FDCAN (<=48 MHz) and QSPI (<=48 MHz).
+ * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high
+ * speed system clock (up to 170MHz)
+ * @retval SET / RESET
+ */
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) \
+ READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __SYSCLKSOURCE__ specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock
+ * source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock
+ * source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock
+ * source.
+ * @retval None
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE) drive
+ * capability.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive
+ * capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high
+ * drive capability.
+ * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
+ * @retval None
+ */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
+
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO
+ * source
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO
+ * source
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
+ * for devices with HSI48
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
+ * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
+ * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
+ * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
+ * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
+ */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), \
+ ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to
+ * enable the selected interrupts).
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
+ * HSI48
+ * @retval None
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to
+ * disable the selected interrupts).
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
+ * HSI48
+ * @retval None
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) \
+ CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to
+ * RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
+ * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
+ * HSI48
+ * @retval None
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief Check whether the RCC interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
+ * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
+ * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with
+ * HSI48
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) \
+ ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST,
+ * RCC_FLAG_PINRST, RCC_FLAG_BORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
+ * RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+ * @retval None
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief Check whether the selected RCC flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
+ * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
+ * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with
+ * HSI48
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
+ * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE
+ * oscillator detection
+ * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
+ * @arg @ref RCC_FLAG_BORRST BOR reset
+ * @arg @ref RCC_FLAG_OBLRST OBLRST reset
+ * @arg @ref RCC_FLAG_PINRST Pin reset
+ * @arg @ref RCC_FLAG_SFTRST Software reset
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_FLAG(__FLAG__) \
+ (((((((__FLAG__) >> 5U) == 1U) \
+ ? RCC->CR \
+ : ((((__FLAG__) >> 5U) == 4U) \
+ ? RCC->CRRCR \
+ : ((((__FLAG__) >> 5U) == 2U) \
+ ? RCC->BDCR \
+ : ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR \
+ : RCC->CIFR)))) & \
+ ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
+ ? 1U \
+ : 0U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+/* Defines used for Flags */
+#define CR_REG_INDEX 1U
+#define BDCR_REG_INDEX 2U
+#define CSR_REG_INDEX 3U
+#define CRRCR_REG_INDEX 4U
+
+#define RCC_FLAG_MASK 0x1FU
+
+/* Define used for IS_RCC_CLOCKTYPE() */
+#define RCC_CLOCKTYPE_ALL \
+ (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \
+ RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \
+ (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == \
+ RCC_OSCILLATORTYPE_HSI48) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+
+#define IS_RCC_HSE(__HSE__) \
+ (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(__LSE__) \
+ (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(__HSI__) \
+ (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) \
+ ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
+
+#define IS_RCC_LSI(__LSI__) \
+ (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+
+#define IS_RCC_HSI48(__HSI48__) \
+ (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
+
+#define IS_RCC_PLL(__PLL__) \
+ (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSI) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_PLLM_VALUE(__VALUE__) \
+ ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
+
+#define IS_RCC_PLLN_VALUE(__VALUE__) \
+ ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
+
+#define IS_RCC_PLLP_VALUE(__VALUE__) \
+ (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
+
+#define IS_RCC_PLLQ_VALUE(__VALUE__) \
+ (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || ((__VALUE__) == 6U) || \
+ ((__VALUE__) == 8U))
+
+#define IS_RCC_PLLR_VALUE(__VALUE__) \
+ (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || ((__VALUE__) == 6U) || \
+ ((__VALUE__) == 8U))
+
+#define IS_RCC_CLOCKTYPE(__CLK__) \
+ ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && \
+ (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HCLK(__HCLK__) \
+ (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) \
+ (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+
+#define IS_RCC_MCO(__MCOX__) \
+ (((__MCOX__) == RCC_MCO_PA8) || ((__MCOX__) == RCC_MCO_PG10))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
+
+#define IS_RCC_MCODIV(__DIV__) \
+ (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
+ ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
+ ((__DIV__) == RCC_MCODIV_16))
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) \
+ (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
+
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extended module */
+#include "stm32g4xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions
+ * ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
+ uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions
+ * ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource,
+ uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_EnableLSECSS(void);
+void HAL_RCC_DisableLSECSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
+ uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_RCC_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
index 5719831..8aaa20b 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
@@ -1,1768 +1,1808 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_RCC_EX_H
-#define STM32G4xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-
-/**
- * @brief RCC extended clocks structure definition
- */
-typedef struct {
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref
- RCCEx_Periph_Clock_Selection */
-
- uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
- This parameter can be a value of @ref
- RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
- This parameter can be a value of @ref
- RCCEx_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
- This parameter can be a value of @ref
- RCCEx_USART3_Clock_Source */
-
-#if defined(UART4)
- uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
- This parameter can be a value of @ref
- RCCEx_UART4_Clock_Source */
-#endif /* UART4 */
-
-#if defined(UART5)
- uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
- This parameter can be a value of @ref
- RCCEx_UART5_Clock_Source */
-
-#endif /* UART5 */
-
- uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
- This parameter can be a value of @ref
- RCCEx_LPUART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
- This parameter can be a value of @ref
- RCCEx_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
- This parameter can be a value of @ref
- RCCEx_I2C2_Clock_Source */
-
- uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
- This parameter can be a value of @ref
- RCCEx_I2C3_Clock_Source */
-
-#if defined(I2C4)
-
- uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
- This parameter can be a value of @ref
- RCCEx_I2C4_Clock_Source */
-#endif /* I2C4 */
-
- uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
- This parameter can be a value of @ref
- RCCEx_LPTIM1_Clock_Source */
-
- uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
- This parameter can be a value of @ref
- RCCEx_SAI1_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< Specifies I2S clock source.
- This parameter can be a value of @ref
- RCCEx_I2S_Clock_Source */
-#if defined(FDCAN1)
-
- uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source.
- This parameter can be a value of @ref
- RCCEx_FDCAN_Clock_Source */
-#endif /* FDCAN1 */
-#if defined(USB)
-
- uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same
- source for RNG). This parameter can be a value
- of @ref RCCEx_USB_Clock_Source */
-#endif /* USB */
-
- uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same
- source for USB). This parameter can be a value
- of @ref RCCEx_RNG_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source.
- This parameter can be a value of @ref
- RCCEx_ADC12_Clock_Source */
-
-#if defined(ADC345_COMMON)
- uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source.
- This parameter can be a value of @ref
- RCCEx_ADC345_Clock_Source */
-#endif /* ADC345_COMMON */
-
-#if defined(QUADSPI)
- uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source.
- This parameter can be a value of @ref
- RCCEx_QSPI_Clock_Source */
-#endif
-
- uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
- This parameter can be a value of @ref
- RCC_RTC_Clock_Source */
-} RCC_PeriphCLKInitTypeDef;
-
-/**
- * @brief RCC_CRS Init structure definition
- */
-typedef struct {
- uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
- This parameter can be a value of @ref
- RCCEx_CRS_SynchroDivider */
-
- uint32_t Source; /*!< Specifies the SYNC signal source.
- This parameter can be a value of @ref
- RCCEx_CRS_SynchroSource */
-
- uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal
- source. This parameter can be a value of @ref
- RCCEx_CRS_SynchroPolarity */
-
- uint32_t
- ReloadValue; /*!< Specifies the value to be loaded in the frequency error
- counter with each SYNC event. It can be calculated in
- using macro
- __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__,
- __FSYNC__) This parameter must be a number between 0 and
- 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
-
- uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the
- captured frequency error value. This parameter
- must be a number between 0 and 0xFF or a value of
- @ref RCCEx_CRS_ErrorLimitDefault */
-
- uint32_t
- HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value
- to the HSI48 oscillator. This parameter must be
- a number between 0 and 0x7F or a value of @ref
- RCCEx_CRS_HSI48CalibrationDefault */
-
-} RCC_CRSInitTypeDef;
-
-/**
- * @brief RCC_CRS Synchronization structure definition
- */
-typedef struct {
- uint32_t
- ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
- This parameter must be a number between 0 and 0xFFFF */
-
- uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48
- oscillator smooth trimming. This parameter
- must be a number between 0 and 0x7F */
-
- uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the
- frequency error counter value latched in the
- time of the last SYNC event. This parameter must
- be a number between 0 and 0xFFFF */
-
- uint32_t
- FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the
- counting direction of the frequency error counter
- latched in the time of the last SYNC event. It
- shows whether the actual frequency is below or
- above the target. This parameter must be a value of
- @ref RCCEx_CRS_FreqErrorDirection*/
-
-} RCC_CRSSynchroInfoTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
- * @{
- */
-
-/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
- * @{
- */
-#define RCC_LSCOSOURCE_LSI \
- 0x00000000U /*!< LSI selection for low speed clock output */
-#define RCC_LSCOSOURCE_LSE \
- RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
- * @{
- */
-#define RCC_PERIPHCLK_USART1 0x00000001U
-#define RCC_PERIPHCLK_USART2 0x00000002U
-#define RCC_PERIPHCLK_USART3 0x00000004U
-#if defined(UART4)
-#define RCC_PERIPHCLK_UART4 0x00000008U
-#endif /* UART4 */
-#if defined(UART5)
-#define RCC_PERIPHCLK_UART5 0x00000010U
-#endif /* UART5 */
-#define RCC_PERIPHCLK_LPUART1 0x00000020U
-#define RCC_PERIPHCLK_I2C1 0x00000040U
-#define RCC_PERIPHCLK_I2C2 0x00000080U
-#define RCC_PERIPHCLK_I2C3 0x00000100U
-#define RCC_PERIPHCLK_LPTIM1 0x00000200U
-#define RCC_PERIPHCLK_SAI1 0x00000400U
-#define RCC_PERIPHCLK_I2S 0x00000800U
-#if defined(FDCAN1)
-#define RCC_PERIPHCLK_FDCAN 0x00001000U
-#endif /* FDCAN1 */
-#define RCC_PERIPHCLK_USB 0x00002000U
-#define RCC_PERIPHCLK_RNG 0x00004000U
-#define RCC_PERIPHCLK_ADC12 0x00008000U
-#if defined(ADC345_COMMON)
-#define RCC_PERIPHCLK_ADC345 0x00010000U
-#endif /* ADC345_COMMON */
-#if defined(I2C4)
-#define RCC_PERIPHCLK_I2C4 0x00020000U
-#endif /* I2C4 */
-#if defined(QUADSPI)
-#define RCC_PERIPHCLK_QSPI 0x00040000U
-#endif /* QUADSPI */
-#define RCC_PERIPHCLK_RTC 0x00080000U
-/**
- * @}
- */
-
-/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
-#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
-#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
- * @{
- */
-#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
-#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
-#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
-#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
- * @{
- */
-#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
-#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
-#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
-#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
-/**
- * @}
- */
-
-#if defined(UART4)
-/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
- * @{
- */
-#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
-#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
-#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
-#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
-/**
- * @}
- */
-#endif /* UART4 */
-
-#if defined(UART5)
-/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
- * @{
- */
-#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
-#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
-#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
-#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
-/**
- * @}
- */
-#endif /* UART5 */
-
-/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
- * @{
- */
-#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
-#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
-#define RCC_LPUART1CLKSOURCE_LSE \
- (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
- * @{
- */
-#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
-#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
- * @{
- */
-#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
-#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
- * @{
- */
-#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
-#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
-/**
- * @}
- */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
- * @{
- */
-#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
-#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
-#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
-/**
- * @}
- */
-
-/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
- * @{
- */
-#define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U
-#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
-#define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1
-#define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
- * @{
- */
-#define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U
-#define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
-#define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1
-#define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
-/**
- * @}
- */
-#if defined(FDCAN1)
-/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
- * @{
- */
-#define RCC_FDCANCLKSOURCE_HSE 0x00000000U
-#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
-#define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1
-/**
- * @}
- */
-#endif /* FDCAN1 */
-
-/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
- * @{
- */
-#define RCC_RNGCLKSOURCE_HSI48 0x00000000U
-#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
-/**
- * @}
- */
-
-/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
- * @{
- */
-#define RCC_USBCLKSOURCE_HSI48 0x00000000U
-#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source
- * @{
- */
-#define RCC_ADC12CLKSOURCE_NONE 0x00000000U
-#define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0
-#define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1
-/**
- * @}
- */
-
-#if defined(ADC345_COMMON)
-/** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source
- * @{
- */
-#define RCC_ADC345CLKSOURCE_NONE 0x00000000U
-#define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0
-#define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1
-/**
- * @}
- */
-#endif /* ADC345_COMMON */
-
-#if defined(I2C4)
-/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
- * @{
- */
-#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
-#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
-/**
- * @}
- */
-#endif /* I2C4 */
-
-#if defined(QUADSPI)
-/** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source
- * @{
- */
-#define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U
-#define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0
-#define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1
-/**
- * @}
- */
-#endif /* QUADSPI */
-
-/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
- * @{
- */
-#define RCC_EXTI_LINE_LSECSS \
- EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI \
- Line */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
- * @{
- */
-#define RCC_CRS_NONE 0x00000000U
-#define RCC_CRS_TIMEOUT 0x00000001U
-#define RCC_CRS_SYNCOK 0x00000002U
-#define RCC_CRS_SYNCWARN 0x00000004U
-#define RCC_CRS_SYNCERR 0x00000008U
-#define RCC_CRS_SYNCMISS 0x00000010U
-#define RCC_CRS_TRIMOVF 0x00000020U
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
- * @{
- */
-#define RCC_CRS_SYNC_SOURCE_GPIO \
- 0x00000000U /*!< Synchro Signal source GPIO \
- */
-#define RCC_CRS_SYNC_SOURCE_LSE \
- CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
-#define RCC_CRS_SYNC_SOURCE_USB \
- CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
- * @{
- */
-#define RCC_CRS_SYNC_DIV1 \
- 0x00000000U /*!< Synchro Signal not divided (default) */
-#define RCC_CRS_SYNC_DIV2 \
- CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 \
- */
-#define RCC_CRS_SYNC_DIV4 \
- CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 \
- */
-#define RCC_CRS_SYNC_DIV8 \
- (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 \
- */
-#define RCC_CRS_SYNC_DIV16 \
- CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
-#define RCC_CRS_SYNC_DIV32 \
- (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 \
- */
-#define RCC_CRS_SYNC_DIV64 \
- (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 \
- */
-#define RCC_CRS_SYNC_DIV128 \
- CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
- * @{
- */
-#define RCC_CRS_SYNC_POLARITY_RISING \
- 0x00000000U /*!< Synchro Active on rising edge (default) */
-#define RCC_CRS_SYNC_POLARITY_FALLING \
- CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
- * @{
- */
-#define RCC_CRS_RELOADVALUE_DEFAULT \
- 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds \
- to a target frequency of 48 MHz and a synchronization \
- signal frequency of 1 kHz (SOF signal from USB). */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
- * @{
- */
-#define RCC_CRS_ERRORLIMIT_DEFAULT \
- 0x00000022U /*!< Default Frequency error limit */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS
- * HSI48CalibrationDefault
- * @{
- */
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT \
- 0x00000020U /*!< The default value is 32, which corresponds to the middle of \
- the trimming interval. The trimming step is around 67 kHz \
- between two consecutive TRIM steps. A higher TRIM value \
- corresponds to a higher output frequency */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
- * @{
- */
-#define RCC_CRS_FREQERRORDIR_UP \
- 0x00000000U /*!< Upcounting direction, the actual frequency is above the \
- target */
-#define RCC_CRS_FREQERRORDIR_DOWN \
- CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the \
- target */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
- * @{
- */
-#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
-#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
-#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
-#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
-#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
-#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
-#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
- * @{
- */
-#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
-#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
-#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
-#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
-#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
-#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
-#define RCC_CRS_FLAG_TRIMOVF \
- CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @brief Macro to configure the USART1 clock (USART1CLK).
- *
- * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1
- * clock
- * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as
- * USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
- * @retval None
- */
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
-
-/** @brief Macro to get the USART1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1
- * clock
- * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as
- * USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
- */
-#define __HAL_RCC_GET_USART1_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
-
-/** @brief Macro to configure the USART2 clock (USART2CLK).
- *
- * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2
- * clock
- * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as
- * USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
- * @retval None
- */
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
-
-/** @brief Macro to get the USART2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2
- * clock
- * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as
- * USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
- */
-#define __HAL_RCC_GET_USART2_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
-
-/** @brief Macro to configure the USART3 clock (USART3CLK).
- *
- * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3
- * clock
- * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as
- * USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
- * @retval None
- */
-#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
-
-/** @brief Macro to get the USART3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3
- * clock
- * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as
- * USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
- */
-#define __HAL_RCC_GET_USART3_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
-
-#if defined(UART4)
-/** @brief Macro to configure the UART4 clock (UART4CLK).
- *
- * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as
- * UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
- * @retval None
- */
-#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
-
-/** @brief Macro to get the UART4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as
- * UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
- */
-#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
-#endif /* UART4 */
-
-#if defined(UART5)
-
-/** @brief Macro to configure the UART5 clock (UART5CLK).
- *
- * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as
- * UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
- * @retval None
- */
-#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
-
-/** @brief Macro to get the UART5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as
- * UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
- */
-#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
-
-#endif /* UART5 */
-
-/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
- *
- * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1
- * clock
- * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as
- * LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
- * @retval None
- */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
-
-/** @brief Macro to get the LPUART1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1
- * clock
- * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as
- * LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_GET_LPUART1_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
-
-/** @brief Macro to configure the I2C1 clock (I2C1CLK).
- *
- * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1
- * clock
- * @retval None
- */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
-
-/** @brief Macro to get the I2C1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1
- * clock
- */
-#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
-
-/** @brief Macro to configure the I2C2 clock (I2C2CLK).
- *
- * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2
- * clock
- * @retval None
- */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
-
-/** @brief Macro to get the I2C2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2
- * clock
- */
-#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
-
-/** @brief Macro to configure the I2C3 clock (I2C3CLK).
- *
- * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3
- * clock
- * @retval None
- */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
-
-/** @brief Macro to get the I2C3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3
- * clock
- */
-#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
-
-#if defined(I2C4)
-
-/** @brief Macro to configure the I2C4 clock (I2C4CLK).
- *
- * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4
- * clock
- * @retval None
- */
-#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
-
-/** @brief Macro to get the I2C4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4
- * clock
- */
-#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
-
-#endif /* I2C4 */
-
-/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
- *
- * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1
- * clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
- * @retval None
- */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
-
-/** @brief Macro to get the LPTIM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1
- * clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as
- * LPUART1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
-
-/**
- * @brief Macro to configure the SAI1 clock source.
- * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is
- * derived from the HSI, system PLL, System Clock or external clock. This
- * parameter can be one of the following values:
- * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
- * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
- * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
- * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
- *
- * @retval None
- */
-#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
-
-/** @brief Macro to get the SAI1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
- * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
- * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
- * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
- *
- */
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
-
-/**
- * @brief Macro to configure the I2S clock source.
- * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
- * from the HSI, system PLL, System Clock or external clock.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
- * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
- * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
- * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
- *
- * @retval None
- */
-#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
-
-/** @brief Macro to get the I2S clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
- * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
- * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
- * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
- *
- */
-#define __HAL_RCC_GET_I2S_SOURCE() \
- ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
-
-#if defined(FDCAN1)
-/**
- * @brief Macro to configure the FDCAN clock source.
- * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is
- * derived from the HSE, system PLL or PCLK1. This parameter can be one of the
- * following values:
- * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
- * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
- * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
- *
- * @retval None
- */
-#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
-
-/** @brief Macro to get the FDCAN clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
- * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
- * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
- *
- */
-#define __HAL_RCC_GET_FDCAN_SOURCE() \
- ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
-#endif /* FDCAN1 */
-
-/** @brief Macro to configure the RNG clock.
- *
- * @note USB and RNG peripherals share the same 48MHz clock source.
- *
- * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for
- * devices with HSI48
- * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
- * @retval None
- */
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
-
-/** @brief Macro to get the RNG clock.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for
- * devices with HSI48
- * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG
- * clock
- */
-#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
-
-#if defined(USB)
-
-/** @brief Macro to configure the USB clock (USBCLK).
- *
- * @note USB, RNG peripherals share the same 48MHz clock source.
- *
- * @param __USB_CLKSOURCE__ specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock
- * for devices with HSI48
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK)
- * selected as USB clock
- * @retval None
- */
-#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
-
-/** @brief Macro to get the USB clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock
- * for devices with HSI48
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK)
- * selected as USB clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
-
-#endif /* USB */
-
-/** @brief Macro to configure the ADC12 interface clock.
- * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock
- * source. This parameter can be one of the following values:
- * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12
- * clock
- * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12
- * clock
- * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as
- * ADC12 clock
- * @retval None
- */
-#define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
-
-/** @brief Macro to get the ADC12 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12
- * clock
- * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12
- * clock
- * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as
- * ADC12 clock
- */
-#define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
-
-#if defined(ADC345_COMMON)
-/** @brief Macro to configure the ADC345 interface clock.
- * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock
- * source. This parameter can be one of the following values:
- * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345
- * clock
- * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345
- * clock
- * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as
- * ADC345 clock
- * @retval None
- */
-#define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__)
-
-/** @brief Macro to get the ADC345 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345
- * clock
- * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345
- * clock
- * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as
- * ADC345 clock
- */
-#define __HAL_RCC_GET_ADC345_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL))
-#endif /* ADC345_COMMON */
-
-#if defined(QUADSPI)
-
-/** @brief Macro to configure the QuadSPI clock.
- * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as
- * QuadSPI clock
- * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI
- * clock
- * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected
- * as QuadSPI clock
- * @retval None
- */
-#define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__)
-
-/** @brief Macro to get the QuadSPI clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as
- * QuadSPI clock
- * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI
- * clock
- * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected
- * as QuadSPI clock
- */
-#define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL))
-
-#endif /* QUADSPI */
-
-/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() \
- SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() \
- CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the RCC LSE CSS Event Line.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() \
- SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Event Line.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() \
- CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() \
- SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() \
- CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() \
- SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() \
- CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
- } while (0)
-
-/**
- * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or
- * not.
- * @retval EXTI RCC LSE CSS Line Status.
- */
-#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() \
- (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Clear the RCC LSE CSS EXTI flag.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() \
- WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() \
- SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the specified CRS interrupts.
- * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
- * interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval None
- */
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CRS interrupts.
- * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
- * interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval None
- */
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) \
- CLEAR_BIT(CRS->CR, (__INTERRUPT__))
-
-/** @brief Check whether the CRS interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the CRS interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
- * interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) \
- ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
-
-/** @brief Clear the CRS interrupt pending bits
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
- * interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow
- * interrupt
- * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
- * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
- */
-/* CRS IT Error Mask */
-#define RCC_CRS_IT_ERROR_MASK \
- (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
-
-#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) \
- do { \
- if (((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) { \
- WRITE_REG(CRS->ICR, \
- CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
- } else { \
- WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
- } \
- } while (0)
-
-/**
- * @brief Check whether the specified CRS flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
- * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
- * @arg @ref RCC_CRS_FLAG_ERR Error
- * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
- * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
- * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
- * @retval The new state of _FLAG_ (TRUE or FALSE).
- */
-#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) \
- (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the CRS specified FLAG.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
- * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
- * @arg @ref RCC_CRS_FLAG_ERR Error
- * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
- * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
- * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
- * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR,
- * RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
- * @retval None
- */
-
-/* CRS Flag Error Mask */
-#define RCC_CRS_FLAG_ERROR_MASK \
- (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
-
-#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) \
- do { \
- if (((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) { \
- WRITE_REG(CRS->ICR, \
- CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
- } else { \
- WRITE_REG(CRS->ICR, (__FLAG__)); \
- } \
- } while (0)
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
- * @{
- */
-/**
- * @brief Enable the oscillator clock for frequency error counter.
- * @note when the CEN bit is set the CRS_CFGR register becomes
- * write-protected.
- * @retval None
- */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
- * @brief Disable the oscillator clock for frequency error counter.
- * @retval None
- */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() \
- CLEAR_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
- * @brief Enable the automatic hardware adjustment of TRIM bits.
- * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes
- * write-protected.
- * @retval None
- */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() \
- SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
- * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
- * @retval None
- */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() \
- CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
- * @brief Macro to calculate reload value to be set in CRS register according
- * to target and sync frequencies
- * @note The RELOAD value should be selected according to the ratio between
- * the target frequency and the frequency of the synchronization source after
- * prescaling. It is then decreased by one in order to reach the expected
- * synchronization on the zero value. The formula is the following: RELOAD =
- * (fTARGET / fSYNC) -1
- * @param __FTARGET__ Target frequency (value in Hz)
- * @param __FSYNC__ Synchronization signal frequency (value in Hz)
- * @retval None
- */
-#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) \
- (((__FTARGET__) / (__FSYNC__)) - 1U)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(
- RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group2
- * @{
- */
-
-void HAL_RCCEx_EnableLSECSS(void);
-void HAL_RCCEx_DisableLSECSS(void);
-void HAL_RCCEx_EnableLSECSS_IT(void);
-void HAL_RCCEx_LSECSS_IRQHandler(void);
-void HAL_RCCEx_LSECSS_Callback(void);
-void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
-void HAL_RCCEx_DisableLSCO(void);
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
- * @{
- */
-
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
-void HAL_RCCEx_CRSGetSynchronizationInfo(
- RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
-void HAL_RCCEx_CRS_IRQHandler(void);
-void HAL_RCCEx_CRS_SyncOkCallback(void);
-void HAL_RCCEx_CRS_SyncWarnCallback(void);
-void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
-void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros
- * @{
- */
-
-#define IS_RCC_LSCOSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
-
-#if defined(STM32G474xx) || defined(STM32G484xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
- (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
- (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
- (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
- (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-#elif defined(STM32G473xx) || defined(STM32G483xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
- (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
- (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-
-#elif defined(STM32G471xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-
-#elif defined(STM32G431xx) || defined(STM32G441xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
- (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-
-#elif defined(STM32GBK1CB)
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
- (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-
-#endif /* STM32G474xx || STM32G484xx */
-
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
-
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
-
-#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
-
-#if defined(UART4)
-#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
-#endif /* UART4 */
-
-#if defined(UART5)
-#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
-
-#endif /* UART5 */
-
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
-
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-
-#if defined(I2C4)
-
-#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
-
-#endif /* I2C4 */
-
-#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
-
-#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \
- ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))
-
-#if defined(FDCAN1)
-#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
-
-#endif /* FDCAN1 */
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
-
-#if defined(USB)
-#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
-
-#endif /* USB */
-
-#define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))
-
-#if defined(ADC345_COMMON)
-#define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK))
-#endif /* ADC345_COMMON */
-
-#if defined(QUADSPI)
-
-#define IS_RCC_QSPICLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL))
-
-#endif /* QUADSPI */
-
-#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
-
-#define IS_RCC_CRS_SYNC_DIV(__DIV__) \
- (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
-
-#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) \
- (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
-
-#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
-
-#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
-
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
-
-#define IS_RCC_CRS_FREQERRORDIR(__DIR__) \
- (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
- ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_RCC_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_RCC_EX_H
+#define STM32G4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct {
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref
+ RCCEx_Periph_Clock_Selection */
+
+ uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
+ This parameter can be a value of @ref
+ RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
+ This parameter can be a value of @ref
+ RCCEx_USART2_Clock_Source */
+#if defined(USART3)
+ uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
+ This parameter can be a value of @ref
+ RCCEx_USART3_Clock_Source */
+#endif /* UART3 */
+
+#if defined(UART4)
+ uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
+ This parameter can be a value of @ref
+ RCCEx_UART4_Clock_Source */
+#endif /* UART4 */
+
+#if defined(UART5)
+ uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
+ This parameter can be a value of @ref
+ RCCEx_UART5_Clock_Source */
+
+#endif /* UART5 */
+
+ uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
+ This parameter can be a value of @ref
+ RCCEx_LPUART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
+ This parameter can be a value of @ref
+ RCCEx_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
+ This parameter can be a value of @ref
+ RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
+ This parameter can be a value of @ref
+ RCCEx_I2C3_Clock_Source */
+
+#if defined(I2C4)
+
+ uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
+ This parameter can be a value of @ref
+ RCCEx_I2C4_Clock_Source */
+#endif /* I2C4 */
+
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
+ This parameter can be a value of @ref
+ RCCEx_LPTIM1_Clock_Source */
+
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
+ This parameter can be a value of @ref
+ RCCEx_SAI1_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< Specifies I2S clock source.
+ This parameter can be a value of @ref
+ RCCEx_I2S_Clock_Source */
+#if defined(FDCAN1)
+
+ uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source.
+ This parameter can be a value of @ref
+ RCCEx_FDCAN_Clock_Source */
+#endif /* FDCAN1 */
+#if defined(USB)
+
+ uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same
+ source for RNG). This parameter can be a value
+ of @ref RCCEx_USB_Clock_Source */
+#endif /* USB */
+
+ uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same
+ source for USB). This parameter can be a value
+ of @ref RCCEx_RNG_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source.
+ This parameter can be a value of @ref
+ RCCEx_ADC12_Clock_Source */
+
+#if defined(ADC345_COMMON)
+ uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source.
+ This parameter can be a value of @ref
+ RCCEx_ADC345_Clock_Source */
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+ uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source.
+ This parameter can be a value of @ref
+ RCCEx_QSPI_Clock_Source */
+#endif
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
+ This parameter can be a value of @ref
+ RCC_RTC_Clock_Source */
+} RCC_PeriphCLKInitTypeDef;
+
+/**
+ * @brief RCC_CRS Init structure definition
+ */
+typedef struct {
+ uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
+ This parameter can be a value of @ref
+ RCCEx_CRS_SynchroDivider */
+
+ uint32_t Source; /*!< Specifies the SYNC signal source.
+ This parameter can be a value of @ref
+ RCCEx_CRS_SynchroSource */
+
+ uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal
+ source. This parameter can be a value of @ref
+ RCCEx_CRS_SynchroPolarity */
+
+ uint32_t
+ ReloadValue; /*!< Specifies the value to be loaded in the frequency error
+ counter with each SYNC event. It can be calculated in
+ using macro
+ __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__,
+ __FSYNC__) This parameter must be a number between 0 and
+ 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+ uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the
+ captured frequency error value. This parameter
+ must be a number between 0 and 0xFF or a value of
+ @ref RCCEx_CRS_ErrorLimitDefault */
+
+ uint32_t
+ HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value
+ to the HSI48 oscillator. This parameter must be
+ a number between 0 and 0x7F or a value of @ref
+ RCCEx_CRS_HSI48CalibrationDefault */
+
+} RCC_CRSInitTypeDef;
+
+/**
+ * @brief RCC_CRS Synchronization structure definition
+ */
+typedef struct {
+ uint32_t
+ ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48
+ oscillator smooth trimming. This parameter
+ must be a number between 0 and 0x7F */
+
+ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the
+ frequency error counter value latched in the
+ time of the last SYNC event. This parameter must
+ be a number between 0 and 0xFFFF */
+
+ uint32_t
+ FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the
+ counting direction of the frequency error counter
+ latched in the time of the last SYNC event. It
+ shows whether the actual frequency is below or
+ above the target. This parameter must be a value of
+ @ref RCCEx_CRS_FreqErrorDirection*/
+
+} RCC_CRSSynchroInfoTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
+ * @{
+ */
+#define RCC_LSCOSOURCE_LSI \
+ 0x00000000U /*!< LSI selection for low speed clock output */
+#define RCC_LSCOSOURCE_LSE \
+ RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
+ * @{
+ */
+#define RCC_PERIPHCLK_USART1 0x00000001U
+#define RCC_PERIPHCLK_USART2 0x00000002U
+#define RCC_PERIPHCLK_USART3 0x00000004U
+#if defined(UART4)
+#define RCC_PERIPHCLK_UART4 0x00000008U
+#endif /* UART4 */
+#if defined(UART5)
+#define RCC_PERIPHCLK_UART5 0x00000010U
+#endif /* UART5 */
+#define RCC_PERIPHCLK_LPUART1 0x00000020U
+#define RCC_PERIPHCLK_I2C1 0x00000040U
+#define RCC_PERIPHCLK_I2C2 0x00000080U
+#define RCC_PERIPHCLK_I2C3 0x00000100U
+#define RCC_PERIPHCLK_LPTIM1 0x00000200U
+#define RCC_PERIPHCLK_SAI1 0x00000400U
+#define RCC_PERIPHCLK_I2S 0x00000800U
+#if defined(FDCAN1)
+#define RCC_PERIPHCLK_FDCAN 0x00001000U
+#endif /* FDCAN1 */
+#define RCC_PERIPHCLK_USB 0x00002000U
+#define RCC_PERIPHCLK_RNG 0x00004000U
+#define RCC_PERIPHCLK_ADC12 0x00008000U
+#if defined(ADC345_COMMON)
+#define RCC_PERIPHCLK_ADC345 0x00010000U
+#endif /* ADC345_COMMON */
+#if defined(I2C4)
+#define RCC_PERIPHCLK_I2C4 0x00020000U
+#endif /* I2C4 */
+#if defined(QUADSPI)
+#define RCC_PERIPHCLK_QSPI 0x00040000U
+#endif /* QUADSPI */
+#define RCC_PERIPHCLK_RTC 0x00080000U
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
+#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
+#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
+ * @{
+ */
+#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
+#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
+#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
+ * @{
+ */
+#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
+#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
+#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
+/**
+ * @}
+ */
+
+#if defined(UART4)
+/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
+ * @{
+ */
+#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
+#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
+#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
+/**
+ * @}
+ */
+#endif /* UART4 */
+
+#if defined(UART5)
+/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
+ * @{
+ */
+#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
+#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
+#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
+/**
+ * @}
+ */
+#endif /* UART5 */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
+ * @{
+ */
+#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_LSE \
+ (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
+ * @{
+ */
+#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
+#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
+#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
+#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+ * @{
+ */
+#define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U
+#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U
+#define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
+#define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1
+#define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#if defined(FDCAN1)
+/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
+ * @{
+ */
+#define RCC_FDCANCLKSOURCE_HSE 0x00000000U
+#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1
+/**
+ * @}
+ */
+#endif /* FDCAN1 */
+
+/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
+ * @{
+ */
+#define RCC_RNGCLKSOURCE_HSI48 0x00000000U
+#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
+ * @{
+ */
+#define RCC_USBCLKSOURCE_HSI48 0x00000000U
+#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source
+ * @{
+ */
+#define RCC_ADC12CLKSOURCE_NONE 0x00000000U
+#define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0
+#define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1
+/**
+ * @}
+ */
+
+#if defined(ADC345_COMMON)
+/** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source
+ * @{
+ */
+#define RCC_ADC345CLKSOURCE_NONE 0x00000000U
+#define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0
+#define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1
+/**
+ * @}
+ */
+#endif /* ADC345_COMMON */
+
+#if defined(I2C4)
+/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
+ * @{
+ */
+#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
+#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
+/**
+ * @}
+ */
+#endif /* I2C4 */
+
+#if defined(QUADSPI)
+/** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source
+ * @{
+ */
+#define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U
+#define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0
+#define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1
+/**
+ * @}
+ */
+#endif /* QUADSPI */
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
+ * @{
+ */
+#define RCC_EXTI_LINE_LSECSS \
+ EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI \
+ Line */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+ * @{
+ */
+#define RCC_CRS_NONE 0x00000000U
+#define RCC_CRS_TIMEOUT 0x00000001U
+#define RCC_CRS_SYNCOK 0x00000002U
+#define RCC_CRS_SYNCWARN 0x00000004U
+#define RCC_CRS_SYNCERR 0x00000008U
+#define RCC_CRS_SYNCMISS 0x00000010U
+#define RCC_CRS_TRIMOVF 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+ * @{
+ */
+#define RCC_CRS_SYNC_SOURCE_GPIO \
+ 0x00000000U /*!< Synchro Signal source GPIO \
+ */
+#define RCC_CRS_SYNC_SOURCE_LSE \
+ CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB \
+ CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+ * @{
+ */
+#define RCC_CRS_SYNC_DIV1 \
+ 0x00000000U /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2 \
+ CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 \
+ */
+#define RCC_CRS_SYNC_DIV4 \
+ CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 \
+ */
+#define RCC_CRS_SYNC_DIV8 \
+ (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 \
+ */
+#define RCC_CRS_SYNC_DIV16 \
+ CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32 \
+ (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 \
+ */
+#define RCC_CRS_SYNC_DIV64 \
+ (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 \
+ */
+#define RCC_CRS_SYNC_DIV128 \
+ CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+ * @{
+ */
+#define RCC_CRS_SYNC_POLARITY_RISING \
+ 0x00000000U /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING \
+ CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+ * @{
+ */
+#define RCC_CRS_RELOADVALUE_DEFAULT \
+ 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds \
+ to a target frequency of 48 MHz and a synchronization \
+ signal frequency of 1 kHz (SOF signal from USB). */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+ * @{
+ */
+#define RCC_CRS_ERRORLIMIT_DEFAULT \
+ 0x00000022U /*!< Default Frequency error limit */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS
+ * HSI48CalibrationDefault
+ * @{
+ */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT \
+ 0x00000040U /*!< The default value is 64, which corresponds to the middle of \
+ the trimming interval. The trimming step is around 67 kHz \
+ between two consecutive TRIM steps. A higher TRIM value \
+ corresponds to a higher output frequency */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+ * @{
+ */
+#define RCC_CRS_FREQERRORDIR_UP \
+ 0x00000000U /*!< Upcounting direction, the actual frequency is above the \
+ target */
+#define RCC_CRS_FREQERRORDIR_DOWN \
+ CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the \
+ target */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+ * @{
+ */
+#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
+#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
+#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+ * @{
+ */
+#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
+#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
+#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
+#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
+#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF \
+ CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+
+/** @brief Macro to configure the USART1 clock (USART1CLK).
+ *
+ * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1
+ * clock
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as
+ * USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
+
+/** @brief Macro to get the USART1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1
+ * clock
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as
+ * USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ */
+#define __HAL_RCC_GET_USART1_SOURCE() \
+ (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
+
+/** @brief Macro to configure the USART2 clock (USART2CLK).
+ *
+ * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2
+ * clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as
+ * USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
+
+/** @brief Macro to get the USART2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2
+ * clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as
+ * USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ */
+#define __HAL_RCC_GET_USART2_SOURCE() \
+ (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
+
+/** @brief Macro to configure the USART3 clock (USART3CLK).
+ *
+ * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3
+ * clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as
+ * USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
+
+/** @brief Macro to get the USART3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3
+ * clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as
+ * USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ */
+#define __HAL_RCC_GET_USART3_SOURCE() \
+ (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
+
+#if defined(UART4)
+/** @brief Macro to configure the UART4 clock (UART4CLK).
+ *
+ * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as
+ * UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
+
+/** @brief Macro to get the UART4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as
+ * UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ */
+#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
+#endif /* UART4 */
+
+#if defined(UART5)
+
+/** @brief Macro to configure the UART5 clock (UART5CLK).
+ *
+ * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as
+ * UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
+
+/** @brief Macro to get the UART5 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as
+ * UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ */
+#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
+
+#endif /* UART5 */
+
+/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
+ *
+ * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1
+ * clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as
+ * LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
+ * @retval None
+ */
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
+
+/** @brief Macro to get the LPUART1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1
+ * clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as
+ * LPUART1 clock
+ * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
+ */
+#define __HAL_RCC_GET_LPUART1_SOURCE() \
+ (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
+
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).
+ *
+ * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1
+ * clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
+
+/** @brief Macro to get the I2C1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1
+ * clock
+ */
+#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
+
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ *
+ * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2
+ * clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2
+ * clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
+
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ *
+ * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3
+ * clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3
+ * clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
+
+#if defined(I2C4)
+
+/** @brief Macro to configure the I2C4 clock (I2C4CLK).
+ *
+ * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4
+ * clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
+
+/** @brief Macro to get the I2C4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
+ * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4
+ * clock
+ */
+#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
+
+#endif /* I2C4 */
+
+/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
+ *
+ * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1
+ * clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
+
+/** @brief Macro to get the LPTIM1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1
+ * clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as
+ * LPUART1 clock
+ * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
+ */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() \
+ (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
+
+/**
+ * @brief Macro to configure the SAI1 clock source.
+ * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is
+ * derived from the HSI, system PLL, System Clock or external clock. This
+ * parameter can be one of the following values:
+ * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
+ * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
+ * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
+ *
+ * @retval None
+ */
+
+#if defined(SAI1)
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
+
+/** @brief Macro to get the SAI1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
+ * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
+ * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
+ * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
+ *
+ */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Macro to configure the I2S clock source.
+ * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
+ * from the HSI, system PLL, System Clock or external clock.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
+ * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
+ * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
+ * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
+ *
+ * @retval None
+ */
+#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
+
+/** @brief Macro to get the I2S clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
+ * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
+ * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
+ * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
+ *
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() \
+ ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
+#endif /* SPI_I2S_SUPPORT */
+
+#if defined(FDCAN1)
+/**
+ * @brief Macro to configure the FDCAN clock source.
+ * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is
+ * derived from the HSE, system PLL or PCLK1. This parameter can be one of the
+ * following values:
+ * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
+ * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
+ * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
+ *
+ * @retval None
+ */
+#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
+
+/** @brief Macro to get the FDCAN clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
+ * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
+ * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
+ *
+ */
+#define __HAL_RCC_GET_FDCAN_SOURCE() \
+ ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
+#endif /* FDCAN1 */
+
+/** @brief Macro to configure the RNG clock.
+ *
+ * @note USB and RNG peripherals share the same 48MHz clock source.
+ *
+ * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for
+ * devices with HSI48
+ * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
+ * @retval None
+ */
+#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
+
+/** @brief Macro to get the RNG clock.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for
+ * devices with HSI48
+ * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG
+ * clock
+ */
+#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
+
+#if defined(USB)
+
+/** @brief Macro to configure the USB clock (USBCLK).
+ *
+ * @note USB, RNG peripherals share the same 48MHz clock source.
+ *
+ * @param __USB_CLKSOURCE__ specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock
+ * for devices with HSI48
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK)
+ * selected as USB clock
+ * @retval None
+ */
+#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
+
+/** @brief Macro to get the USB clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock
+ * for devices with HSI48
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK)
+ * selected as USB clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
+
+#endif /* USB */
+
+/** @brief Macro to configure the ADC12 interface clock.
+ * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock
+ * source. This parameter can be one of the following values:
+ * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12
+ * clock
+ * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12
+ * clock
+ * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as
+ * ADC12 clock
+ * @retval None
+ */
+#define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
+
+/** @brief Macro to get the ADC12 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12
+ * clock
+ * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12
+ * clock
+ * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as
+ * ADC12 clock
+ */
+#define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
+
+#if defined(ADC345_COMMON)
+/** @brief Macro to configure the ADC345 interface clock.
+ * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock
+ * source. This parameter can be one of the following values:
+ * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345
+ * clock
+ * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345
+ * clock
+ * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as
+ * ADC345 clock
+ * @retval None
+ */
+#define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__)
+
+/** @brief Macro to get the ADC345 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345
+ * clock
+ * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345
+ * clock
+ * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as
+ * ADC345 clock
+ */
+#define __HAL_RCC_GET_ADC345_SOURCE() \
+ (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL))
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+/** @brief Macro to configure the QuadSPI clock.
+ * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as
+ * QuadSPI clock
+ * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI
+ * clock
+ * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected
+ * as QuadSPI clock
+ * @retval None
+ */
+#define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__)
+
+/** @brief Macro to get the QuadSPI clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as
+ * QuadSPI clock
+ * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI
+ * clock
+ * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected
+ * as QuadSPI clock
+ */
+#define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL))
+
+#endif /* QUADSPI */
+
+/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() \
+ SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() \
+ CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Event Line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() \
+ SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Event Line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() \
+ CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() \
+ SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() \
+ CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() \
+ SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() \
+ CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
+ } while (0)
+
+/**
+ * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or
+ * not.
+ * @retval EXTI RCC LSE CSS Line Status.
+ */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() \
+ (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Clear the RCC LSE CSS EXTI flag.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() \
+ WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() \
+ SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the specified CRS interrupts.
+ * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
+ * interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @retval None
+ */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CRS interrupts.
+ * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
+ * interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @retval None
+ */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) \
+ CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief Check whether the CRS interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the CRS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
+ * interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) \
+ ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
+
+/** @brief Clear the CRS interrupt pending bits
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error
+ * interrupt
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
+ * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow
+ * interrupt
+ * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
+ * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
+ */
+/* CRS IT Error Mask */
+#define RCC_CRS_IT_ERROR_MASK \
+ (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) \
+ do { \
+ if (((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) { \
+ WRITE_REG(CRS->ICR, \
+ CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+ } else { \
+ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+ } \
+ } while (0)
+
+/**
+ * @brief Check whether the specified CRS flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
+ * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
+ * @arg @ref RCC_CRS_FLAG_ERR Error
+ * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
+ * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
+ * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
+ * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
+ * @retval The new state of _FLAG_ (TRUE or FALSE).
+ */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) \
+ (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the CRS specified FLAG.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
+ * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
+ * @arg @ref RCC_CRS_FLAG_ERR Error
+ * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
+ * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
+ * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
+ * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
+ * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR,
+ * RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+ * @retval None
+ */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK \
+ (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) \
+ do { \
+ if (((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) { \
+ WRITE_REG(CRS->ICR, \
+ CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+ } else { \
+ WRITE_REG(CRS->ICR, (__FLAG__)); \
+ } \
+ } while (0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+ * @{
+ */
+/**
+ * @brief Enable the oscillator clock for frequency error counter.
+ * @note when the CEN bit is set the CRS_CFGR register becomes
+ * write-protected.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+ * @brief Disable the oscillator clock for frequency error counter.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() \
+ CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+ * @brief Enable the automatic hardware adjustment of TRIM bits.
+ * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes
+ * write-protected.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() \
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+ * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() \
+ CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+ * @brief Macro to calculate reload value to be set in CRS register according
+ * to target and sync frequencies
+ * @note The RELOAD value should be selected according to the ratio between
+ * the target frequency and the frequency of the synchronization source after
+ * prescaling. It is then decreased by one in order to reach the expected
+ * synchronization on the zero value. The formula is the following: RELOAD =
+ * (fTARGET / fSYNC) -1
+ * @param __FTARGET__ Target frequency (value in Hz)
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)
+ * @retval None
+ */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) \
+ (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(
+ RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+ * @{
+ */
+
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
+void HAL_RCCEx_DisableLSCO(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+ * @{
+ */
+
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void HAL_RCCEx_CRSGetSynchronizationInfo(
+ RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void HAL_RCCEx_CRS_IRQHandler(void);
+void HAL_RCCEx_CRS_SyncOkCallback(void);
+void HAL_RCCEx_CRS_SyncWarnCallback(void);
+void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#define IS_RCC_LSCOSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
+
+#if defined(STM32G474xx) || defined(STM32G484xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+
+#elif defined(STM32G471xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+
+#elif defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+#elif defined(STM32G414xx)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+#elif defined(STM32GBK1CB)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+
+#endif /* STM32G474xx || STM32G484xx */
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+
+#if defined(UART4)
+#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
+#endif /* UART4 */
+
+#if defined(UART5)
+#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
+
+#endif /* UART5 */
+
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
+
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+
+#if defined(I2C4)
+
+#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
+
+#endif /* I2C4 */
+
+#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#if defined(SAI1)
+#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
+#endif /* SAI1 */
+
+#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \
+ ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))
+
+#if defined(FDCAN1)
+#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
+
+#endif /* FDCAN1 */
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
+
+#if defined(USB)
+#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
+
+#endif /* USB */
+
+#define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))
+
+#if defined(ADC345_COMMON)
+#define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK))
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+#define IS_RCC_QSPICLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL))
+
+#endif /* QUADSPI */
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__) \
+ (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__) \
+ (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_RCC_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h
index 5834948..0506091 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h
@@ -1,947 +1,949 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_SPI_H
-#define STM32G4xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
- * @{
- */
-
-/**
- * @brief SPI Configuration Structure definition
- */
-typedef struct {
- uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_Mode */
-
- uint32_t
- Direction; /*!< Specifies the SPI bidirectional mode state.
- This parameter can be a value of @ref SPI_Direction */
-
- uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_Data_Size */
-
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref
- SPI_Clock_Polarity */
-
- uint32_t
- CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref
- SPI_Slave_Select_management */
-
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which
- will be used to configure the transmit and
- receive SCK clock. This parameter can be a
- value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from
- the master clock. The slave clock does not need
- to be set. */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB
- bit. This parameter can be a value of @ref
- SPI_MSB_LSB_transmission */
-
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_mode */
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or
- not. This parameter can be a value of @ref
- SPI_CRC_Calculation */
-
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC
- calculation. This parameter must be an odd number
- between Min_Data = 1 and Max_Data = 65535 */
-
- uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC
- calculation. CRC Length is only used with Data8 and
- Data16, not other data size This parameter can be a
- value of @ref SPI_CRC_length */
-
- uint32_t
- NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
- This parameter can be a value of @ref SPI_NSSP_Mode
- This mode is activated by the NSSP bit in the SPIx_CR2
- register and it takes effect only if the SPI interface is
- configured as Motorola SPI master (FRF=0) with capture on the
- first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored).. */
-} SPI_InitTypeDef;
-
-/**
- * @brief HAL SPI State structure definition
- */
-typedef enum {
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX =
- 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
- HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
-} HAL_SPI_StateTypeDef;
-
-/**
- * @brief SPI handle Structure definition
- */
-typedef struct __SPI_HandleTypeDef {
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
-
- void (*RxISR)(
- struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(
- struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code */
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- void (*TxCpltCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
- void (*RxCpltCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
- void (*TxRxCpltCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
- void (*TxHalfCpltCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
- void (*RxHalfCpltCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
- void (*TxRxHalfCpltCallback)(
- struct __SPI_HandleTypeDef
- *hspi); /*!< SPI TxRx Half Completed callback */
- void (*ErrorCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
- void (*AbortCpltCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
- void (*MspInitCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
- void (*MspDeInitCallback)(
- struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
- * @brief HAL SPI Callback ID enumeration definition
- */
-typedef enum {
- HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
- HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
- HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
- HAL_SPI_TX_HALF_COMPLETE_CB_ID =
- 0x03U, /*!< SPI Tx Half Completed callback ID */
- HAL_SPI_RX_HALF_COMPLETE_CB_ID =
- 0x04U, /*!< SPI Rx Half Completed callback ID */
- HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID =
- 0x05U, /*!< SPI TxRx Half Completed callback ID */
- HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
- HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
- HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
- HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
- * @brief HAL SPI Callback pointer definition
- */
-typedef void (*pSPI_CallbackTypeDef)(
- SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_Error_Code SPI Error Code
- * @{
- */
-#define HAL_SPI_ERROR_NONE \
- (0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF \
- (0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC \
- (0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR \
- (0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_FRE \
- (0x00000008U) /*!< FRE error */
-#define HAL_SPI_ERROR_DMA \
- (0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG \
- (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_ABORT \
- (0x00000040U) /*!< Error during SPI Abort procedure */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK \
- (0x00000080U) /*!< Invalid Callback error */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SPI_Mode SPI Mode
- * @{
- */
-#define SPI_MODE_SLAVE (0x00000000U)
-#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
- * @}
- */
-
-/** @defgroup SPI_Direction SPI Direction Mode
- * @{
- */
-#define SPI_DIRECTION_2LINES (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-/**
- * @}
- */
-
-/** @defgroup SPI_Data_Size SPI Data Size
- * @{
- */
-#define SPI_DATASIZE_4BIT (0x00000300U)
-#define SPI_DATASIZE_5BIT (0x00000400U)
-#define SPI_DATASIZE_6BIT (0x00000500U)
-#define SPI_DATASIZE_7BIT (0x00000600U)
-#define SPI_DATASIZE_8BIT (0x00000700U)
-#define SPI_DATASIZE_9BIT (0x00000800U)
-#define SPI_DATASIZE_10BIT (0x00000900U)
-#define SPI_DATASIZE_11BIT (0x00000A00U)
-#define SPI_DATASIZE_12BIT (0x00000B00U)
-#define SPI_DATASIZE_13BIT (0x00000C00U)
-#define SPI_DATASIZE_14BIT (0x00000D00U)
-#define SPI_DATASIZE_15BIT (0x00000E00U)
-#define SPI_DATASIZE_16BIT (0x00000F00U)
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
- * @{
- */
-#define SPI_POLARITY_LOW (0x00000000U)
-#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
- * @{
- */
-#define SPI_PHASE_1EDGE (0x00000000U)
-#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
- * @{
- */
-#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
-/**
- * @}
- */
-
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
- * @{
- */
-#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
- * @{
- */
-#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB (0x00000000U)
-#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-/**
- * @}
- */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
- * @{
- */
-#define SPI_TIMODE_DISABLE (0x00000000U)
-#define SPI_TIMODE_ENABLE SPI_CR2_FRF
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_length SPI CRC Length
- * @{
- * This parameter can be one of the following values:
- * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
- * SPI_CRC_LENGTH_8BIT : CRC 8bit
- * SPI_CRC_LENGTH_16BIT : CRC 16bit
- */
-#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
-#define SPI_CRC_LENGTH_8BIT (0x00000001U)
-#define SPI_CRC_LENGTH_16BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
- * @{
- * This parameter can be one of the following values:
- * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
- * RXNE event is generated if the FIFO
- * level is greater or equal to 1/4(8-bits).
- * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/2(16 bits). */
-#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
- * @{
- */
-#define SPI_IT_TXE SPI_CR2_TXEIE
-#define SPI_IT_RXNE SPI_CR2_RXNEIE
-#define SPI_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
- * @{
- */
-#define SPI_FLAG_RXNE \
- SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE \
- SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY \
- SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR \
- SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF \
- SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR \
- SPI_SR_OVR /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_FRE \
- SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL \
- SPI_SR_FTLVL /* SPI fifo transmission level */
-#define SPI_FLAG_FRLVL \
- SPI_SR_FRLVL /* SPI fifo reception level */
-#define SPI_FLAG_MASK \
- (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | \
- SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
-/**
- * @}
- */
-
-/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status
- * Level
- * @{
- */
-#define SPI_FTLVL_EMPTY (0x00000000U)
-#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
-#define SPI_FTLVL_HALF_FULL (0x00001000U)
-#define SPI_FTLVL_FULL (0x00001800U)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
- * @{
- */
-#define SPI_FRLVL_EMPTY (0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
-#define SPI_FRLVL_HALF_FULL (0x00000400U)
-#define SPI_FRLVL_FULL (0x00000600U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @brief Reset SPI handle state.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while (0)
-#else
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-/** @brief Enable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Disable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI handle.
- * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Check whether the specified SPI interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) \
- ? SET \
- : RESET)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @arg SPI_FLAG_FRE: Frame format error flag
- * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
- * @arg SPI_FLAG_FRLVL: SPI fifo reception level
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) \
- ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do { \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while (0U)
-
-/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
- do { \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- } while (0U)
-
-/** @brief Clear the SPI FRE pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
- do { \
- __IO uint32_t tmpreg_fre = 0x00U; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
- } while (0U)
-
-/** @brief Enable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) \
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Disable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) \
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Reset the CRC calculation of the SPI.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
- * peripheral.
- * @retval None
- */
-#define SPI_RESET_CRC(__HANDLE__) \
- do { \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
- } while (0U)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of SPI SR register.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @arg SPI_FLAG_FRE: Frame format error flag
- * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
- * @arg SPI_FLAG_FRLVL: SPI fifo reception level
- * @retval SET or RESET.
- */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) \
- ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) \
- ? SET \
- : RESET)
-
-/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of SPI CR2 register.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval SET or RESET.
- */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) \
- ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if SPI Mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI Mode.
- * This parameter can be a value of @ref SPI_Mode
- * @retval None
- */
-#define IS_SPI_MODE(__MODE__) \
- (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief Checks if SPI Direction Mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI Direction Mode.
- * This parameter can be a value of @ref SPI_Direction
- * @retval None
- */
-#define IS_SPI_DIRECTION(__MODE__) \
- (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Direction Mode parameter is 2 lines.
- * @param __MODE__ specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
- * @param __MODE__ specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) \
- (((__MODE__) == SPI_DIRECTION_2LINES) || ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Data Size parameter is in allowed range.
- * @param __DATASIZE__ specifies the SPI Data Size.
- * This parameter can be a value of @ref SPI_Data_Size
- * @retval None
- */
-#define IS_SPI_DATASIZE(__DATASIZE__) \
- (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_4BIT))
-
-/** @brief Checks if SPI Serial clock steady state parameter is in allowed
- * range.
- * @param __CPOL__ specifies the SPI serial clock steady state.
- * This parameter can be a value of @ref SPI_Clock_Polarity
- * @retval None
- */
-#define IS_SPI_CPOL(__CPOL__) \
- (((__CPOL__) == SPI_POLARITY_LOW) || ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief Checks if SPI Clock Phase parameter is in allowed range.
- * @param __CPHA__ specifies the SPI Clock Phase.
- * This parameter can be a value of @ref SPI_Clock_Phase
- * @retval None
- */
-#define IS_SPI_CPHA(__CPHA__) \
- (((__CPHA__) == SPI_PHASE_1EDGE) || ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief Checks if SPI Slave Select parameter is in allowed range.
- * @param __NSS__ specifies the SPI Slave Select management parameter.
- * This parameter can be a value of @ref SPI_Slave_Select_management
- * @retval None
- */
-#define IS_SPI_NSS(__NSS__) \
- (((__NSS__) == SPI_NSS_SOFT) || ((__NSS__) == SPI_NSS_HARD_INPUT) || \
- ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
- * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
- * This parameter can be a value of @ref SPI_NSSP_Mode
- * @retval None
- */
-#define IS_SPI_NSSP(__NSSP__) \
- (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
- ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
-
-/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
- * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
- * This parameter can be a value of @ref SPI_BaudRate_Prescaler
- * @retval None
- */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) \
- (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
- * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer
- * starts from MSB or LSB bit). This parameter can be a value of @ref
- * SPI_MSB_LSB_transmission
- * @retval None
- */
-#define IS_SPI_FIRST_BIT(__BIT__) \
- (((__BIT__) == SPI_FIRSTBIT_MSB) || ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief Checks if SPI TI mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI TI mode.
- * This parameter can be a value of @ref SPI_TI_mode
- * @retval None
- */
-#define IS_SPI_TIMODE(__MODE__) \
- (((__MODE__) == SPI_TIMODE_DISABLE) || ((__MODE__) == SPI_TIMODE_ENABLE))
-
-/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
- * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
- * This parameter can be a value of @ref SPI_CRC_Calculation
- * @retval None
- */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) \
- (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
- ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief Checks if SPI CRC length is in allowed range.
- * @param __LENGTH__ specifies the SPI CRC length.
- * This parameter can be a value of @ref SPI_CRC_length
- * @retval None
- */
-#define IS_SPI_CRC_LENGTH(__LENGTH__) \
- (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
- ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
- ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
-
-/** @brief Checks if SPI polynomial value to be used for the CRC calculation,
- * is in allowed range.
- * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the
- * CRC calculation. This parameter must be a number between Min_Data = 0 and
- * Max_Data = 65535
- * @retval None
- */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) \
- (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && \
- (((__POLYNOMIAL__) & 0x1U) != 0U))
-
-/** @brief Checks if DMA handle is valid.
- * @param __HANDLE__ specifies a DMA Handle.
- * @retval None
- */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/**
- * @}
- */
-
-/* Include SPI HAL Extended module */
-#include "stm32g4xx_hal_spi_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi,
- HAL_SPI_CallbackIDTypeDef CallbackID,
- pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(
- SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi,
- uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi,
- uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi,
- uint8_t *pTxData,
- uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_SPI_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_SPI_H
+#define STM32G4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_Mode */
+
+ uint32_t
+ Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_Data_Size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref
+ SPI_Clock_Polarity */
+
+ uint32_t
+ CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref
+ SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which
+ will be used to configure the transmit and
+ receive SCK clock. This parameter can be a
+ value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from
+ the master clock. The slave clock does not need
+ to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB
+ bit. This parameter can be a value of @ref
+ SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or
+ not. This parameter can be a value of @ref
+ SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC
+ calculation. This parameter must be an odd number
+ between Min_Data = 1 and Max_Data = 65535 */
+
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC
+ calculation. CRC Length is only used with Data8 and
+ Data16, not other data size This parameter can be a
+ value of @ref SPI_CRC_length */
+
+ uint32_t
+ NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
+ This mode is activated by the NSSP bit in the SPIx_CR2
+ register and it takes effect only if the SPI interface is
+ configured as Motorola SPI master (FRF=0) with capture on the
+ first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum {
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX =
+ 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef {
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+
+ void (*RxISR)(
+ struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
+
+ void (*TxISR)(
+ struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ void (*TxCpltCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
+ void (*RxCpltCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
+ void (*TxRxCpltCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
+ void (*TxHalfCpltCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
+ void (*RxHalfCpltCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
+ void (*TxRxHalfCpltCallback)(
+ struct __SPI_HandleTypeDef
+ *hspi); /*!< SPI TxRx Half Completed callback */
+ void (*ErrorCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
+ void (*AbortCpltCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
+ void (*MspInitCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
+ void (*MspDeInitCallback)(
+ struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+} SPI_HandleTypeDef;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL SPI Callback ID enumeration definition
+ */
+typedef enum {
+ HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
+ HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
+ HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
+ HAL_SPI_TX_HALF_COMPLETE_CB_ID =
+ 0x03U, /*!< SPI Tx Half Completed callback ID */
+ HAL_SPI_RX_HALF_COMPLETE_CB_ID =
+ 0x04U, /*!< SPI Rx Half Completed callback ID */
+ HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID =
+ 0x05U, /*!< SPI TxRx Half Completed callback ID */
+ HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
+ HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
+ HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
+ HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPI Callback pointer definition
+ */
+typedef void (*pSPI_CallbackTypeDef)(
+ SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE \
+ (0x00000000U) /*!< No error */
+#define HAL_SPI_ERROR_MODF \
+ (0x00000001U) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC \
+ (0x00000002U) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR \
+ (0x00000004U) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE \
+ (0x00000008U) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA \
+ (0x00000010U) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG \
+ (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT \
+ (0x00000040U) /*!< Error during SPI Abort procedure */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define HAL_SPI_ERROR_INVALID_CALLBACK \
+ (0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Mode SPI Mode
+ * @{
+ */
+#define SPI_MODE_SLAVE (0x00000000U)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES (0x00000000U)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+ * @{
+ */
+#define SPI_DATASIZE_4BIT (0x00000300U)
+#define SPI_DATASIZE_5BIT (0x00000400U)
+#define SPI_DATASIZE_6BIT (0x00000500U)
+#define SPI_DATASIZE_7BIT (0x00000600U)
+#define SPI_DATASIZE_8BIT (0x00000700U)
+#define SPI_DATASIZE_9BIT (0x00000800U)
+#define SPI_DATASIZE_10BIT (0x00000900U)
+#define SPI_DATASIZE_11BIT (0x00000A00U)
+#define SPI_DATASIZE_12BIT (0x00000B00U)
+#define SPI_DATASIZE_13BIT (0x00000C00U)
+#define SPI_DATASIZE_14BIT (0x00000D00U)
+#define SPI_DATASIZE_15BIT (0x00000E00U)
+#define SPI_DATASIZE_16BIT (0x00000F00U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW (0x00000000U)
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE (0x00000000U)
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+ * @{
+ */
+#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB (0x00000000U)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode SPI TI Mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLE (0x00000000U)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+ * SPI_CRC_LENGTH_8BIT : CRC 8bit
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit
+ */
+#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
+#define SPI_CRC_LENGTH_8BIT (0x00000001U)
+#define SPI_CRC_LENGTH_16BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+ * RXNE event is generated if the FIFO
+ * level is greater or equal to 1/4(8-bits).
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/2(16 bits). */
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+ * @{
+ */
+#define SPI_FLAG_RXNE \
+ SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE \
+ SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY \
+ SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR \
+ SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF \
+ SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR \
+ SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE \
+ SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL \
+ SPI_SR_FTLVL /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL \
+ SPI_SR_FRLVL /* SPI fifo reception level */
+#define SPI_FLAG_MASK \
+ (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | \
+ SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status
+ * Level
+ * @{
+ */
+#define SPI_FTLVL_EMPTY (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
+#define SPI_FTLVL_HALF_FULL (0x00001000U)
+#define SPI_FTLVL_FULL (0x00001800U)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+ * @{
+ */
+#define SPI_FRLVL_EMPTY (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
+#define SPI_FRLVL_HALF_FULL (0x00000400U)
+#define SPI_FRLVL_FULL (0x00000600U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while (0)
+#else
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+/** @brief Enable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI handle.
+ * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) \
+ ? SET \
+ : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) \
+ ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do { \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while (0U)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do { \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ } while (0U)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do { \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
+ } while (0U)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) \
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) \
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI
+ * peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) \
+ do { \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
+ } while (0U)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of SPI SR register.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_FLAG(__SR__, __FLAG__) \
+ ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) \
+ ? SET \
+ : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of SPI CR2 register.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) \
+ ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if SPI Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Mode.
+ * This parameter can be a value of @ref SPI_Mode
+ * @retval None
+ */
+#define IS_SPI_MODE(__MODE__) \
+ (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
+
+/** @brief Checks if SPI Direction Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * This parameter can be a value of @ref SPI_Direction
+ * @retval None
+ */
+#define IS_SPI_DIRECTION(__MODE__) \
+ (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief Checks if SPI Direction Mode parameter is 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
+
+/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) \
+ (((__MODE__) == SPI_DIRECTION_2LINES) || ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief Checks if SPI Data Size parameter is in allowed range.
+ * @param __DATASIZE__ specifies the SPI Data Size.
+ * This parameter can be a value of @ref SPI_Data_Size
+ * @retval None
+ */
+#define IS_SPI_DATASIZE(__DATASIZE__) \
+ (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_4BIT))
+
+/** @brief Checks if SPI Serial clock steady state parameter is in allowed
+ * range.
+ * @param __CPOL__ specifies the SPI serial clock steady state.
+ * This parameter can be a value of @ref SPI_Clock_Polarity
+ * @retval None
+ */
+#define IS_SPI_CPOL(__CPOL__) \
+ (((__CPOL__) == SPI_POLARITY_LOW) || ((__CPOL__) == SPI_POLARITY_HIGH))
+
+/** @brief Checks if SPI Clock Phase parameter is in allowed range.
+ * @param __CPHA__ specifies the SPI Clock Phase.
+ * This parameter can be a value of @ref SPI_Clock_Phase
+ * @retval None
+ */
+#define IS_SPI_CPHA(__CPHA__) \
+ (((__CPHA__) == SPI_PHASE_1EDGE) || ((__CPHA__) == SPI_PHASE_2EDGE))
+
+/** @brief Checks if SPI Slave Select parameter is in allowed range.
+ * @param __NSS__ specifies the SPI Slave Select management parameter.
+ * This parameter can be a value of @ref SPI_Slave_Select_management
+ * @retval None
+ */
+#define IS_SPI_NSS(__NSS__) \
+ (((__NSS__) == SPI_NSS_SOFT) || ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
+
+/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
+ * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
+ * This parameter can be a value of @ref SPI_NSSP_Mode
+ * @retval None
+ */
+#define IS_SPI_NSSP(__NSSP__) \
+ (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
+ ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
+
+/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
+ * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
+ * This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ * @retval None
+ */
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
+
+/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
+ * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer
+ * starts from MSB or LSB bit). This parameter can be a value of @ref
+ * SPI_MSB_LSB_transmission
+ * @retval None
+ */
+#define IS_SPI_FIRST_BIT(__BIT__) \
+ (((__BIT__) == SPI_FIRSTBIT_MSB) || ((__BIT__) == SPI_FIRSTBIT_LSB))
+
+/** @brief Checks if SPI TI mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI TI mode.
+ * This parameter can be a value of @ref SPI_TI_mode
+ * @retval None
+ */
+#define IS_SPI_TIMODE(__MODE__) \
+ (((__MODE__) == SPI_TIMODE_DISABLE) || ((__MODE__) == SPI_TIMODE_ENABLE))
+
+/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
+ * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
+ * This parameter can be a value of @ref SPI_CRC_Calculation
+ * @retval None
+ */
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) \
+ (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
+ ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
+
+/** @brief Checks if SPI CRC length is in allowed range.
+ * @param __LENGTH__ specifies the SPI CRC length.
+ * This parameter can be a value of @ref SPI_CRC_length
+ * @retval None
+ */
+#define IS_SPI_CRC_LENGTH(__LENGTH__) \
+ (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
+ ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
+ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
+
+/** @brief Checks if SPI polynomial value to be used for the CRC calculation,
+ * is in allowed range.
+ * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the
+ * CRC calculation. This parameter must be a number between Min_Data = 0 and
+ * Max_Data = 65535
+ * @retval None
+ */
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) \
+ (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && \
+ (((__POLYNOMIAL__) & 0x1U) != 0U))
+
+/** @brief Checks if DMA handle is valid.
+ * @param __HANDLE__ specifies a DMA Handle.
+ * @retval None
+ */
+#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
+
+/**
+ * @}
+ */
+
+/* Include SPI HAL Extended module */
+#include "stm32g4xx_hal_spi_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi,
+ HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(
+ SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi,
+ const uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi,
+ const uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi,
+ const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi,
+ const uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi,
+ const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi,
+ const uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_SPI_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h
index 5753530..e299977 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h
@@ -1,72 +1,72 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_spi_ex.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_SPI_EX_H
-#define STM32G4xx_HAL_SPI_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPIEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPIEx_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-/** @addtogroup SPIEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_SPI_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_SPI_EX_H
+#define STM32G4xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_SPI_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h
index c92aad6..7f64407 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h
@@ -1,3290 +1,3294 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_TIM_H
-#define STM32G4xx_HAL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct {
- uint32_t
- Prescaler; /*!< Specifies the prescaler value used to divide the TIM
- clock. This parameter can be a number between Min_Data =
- 0x0000 and Max_Data = 0xFFFF Macro __HAL_TIM_CALC_PSC() can
- be used to calculate prescaler value */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref
- TIM_Counter_Mode */
-
- uint32_t
- Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and
- Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)Macros
- __HAL_TIM_CALC_PERIOD(),
- __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
- __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to
- calculate Period value */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref
- TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each
- time the RCR downcounter reaches zero, an
- update event is generated and counting restarts
- from the RCR value (N). This means in PWM mode
- that (N+1) corresponds to:
- - the number of PWM periods in
- edge-aligned mode
- - the number of half PWM period in
- center-aligned mode GP timers: this parameter
- must be a number between Min_Data = 0x00 and
- Max_Data = 0xFF. Advanced timers: this
- parameter must be a number between Min_Data =
- 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref
- TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct {
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref
- TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture
- Compare Register. This parameter can be a number between
- Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if
- dithering is activated) Macros __HAL_TIM_CALC_PULSE(),
- __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
- Pulse value */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref
- TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref
- TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer
- instances supporting break feature. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref
- TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2
- mode. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during
- Idle state. This parameter can be a value of @ref
- TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer
- instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during
- Idle state. This parameter can be a value of @ref
- TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer
- instances supporting break feature. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct {
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref
- TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture
- Compare Register. This parameter can be a number between
- Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if
- dithering is activated) Macros __HAL_TIM_CALC_PULSE(),
- __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
- Pulse value */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref
- TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref
- TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer
- instances supporting break feature. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during
- Idle state. This parameter can be a value of @ref
- TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer
- instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during
- Idle state. This parameter can be a value of @ref
- TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer
- instances supporting break feature. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref
- TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0
- and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct {
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref
- TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref
- TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0
- and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct {
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_Encoder_Input_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref
- TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref
- TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0
- and Max_Data = 0xF */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_Encoder_Input_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref
- TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref
- TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0
- and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
- * @brief Clock Configuration Handle Structure definition
- */
-typedef struct {
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref
- TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref
- TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref
- TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data =
- 0x0 and Max_Data = 0xF */
-} TIM_ClockConfigTypeDef;
-
-/**
- * @brief TIM Clear Input Configuration Handle Structure definition
- */
-typedef struct {
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref
- TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref
- TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear
- feature is used with ETR source, ETR
- prescaler must be off */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between
- Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- * @note Advanced timers provide TRGO2 internal line which is redirected
- * to the ADC
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref
- TIM_Master_Mode_Selection */
- uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
- This parameter can be a value of @ref
- TIM_Master_Mode_Selection_2 */
- uint32_t
- MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref
- TIM_Master_Slave_Mode
- @note When the Master/slave mode is enabled, the
- effect of an event on the trigger input (TRGI) is
- delayed to allow a perfect synchronization between the
- current timer and its slaves (through TRGO). It is not
- mandatory in case of timer synchronization mode. */
-} TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct {
- uint32_t
- SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref
- TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref
- TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref
- TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data =
- 0x0 and Max_Data = 0xF */
-
-} TIM_SlaveConfigTypeDef;
-
-/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
- */
-typedef struct {
- uint32_t
- OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a
- value of @ref
- TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint32_t
- OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a
- value of @ref
- TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref
- TIM_Lock_level */
-
- uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between
- Min_Data = 0x00 and Max_Data = 0xFF */
-
- uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of
- @ref TIM_Break_Input_enable_disable */
-
- uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a
- value of @ref TIM_Break_Polarity */
-
- uint32_t
- BreakFilter; /*!< Specifies the break input filter.This parameter can be a
- number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break
- input.This parameter can be a value of @ref
- TIM_Break_Input_AF_Mode */
-
- uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of
- @ref TIM_Break2_Input_enable_disable */
-
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be
- a value of @ref TIM_Break2_Polarity */
-
- uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a
- number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the
- break2 input.This parameter can be a value of @ref
- TIM_Break2_Input_AF_Mode */
-
- uint32_t
- AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter
- can be a value of @ref TIM_AOE_Bit_Set_Reset */
-
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum {
- HAL_TIM_STATE_RESET =
- 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-} HAL_TIM_StateTypeDef;
-
-/**
- * @brief TIM Channel States definition
- */
-typedef enum {
- HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
- HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
- HAL_TIM_CHANNEL_STATE_BUSY =
- 0x02U, /*!< An internal process is ongoing on the TIM channel */
-} HAL_TIM_ChannelStateTypeDef;
-
-/**
- * @brief DMA Burst States definition
- */
-typedef enum {
- HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
- HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
- HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
-} HAL_TIM_DMABurstStateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum {
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
- HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-} HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-typedef struct __TIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef
- *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
- __IO HAL_TIM_ChannelStateTypeDef
- ChannelState[6]; /*!< TIM channel operation state */
- __IO HAL_TIM_ChannelStateTypeDef
- ChannelNState[4]; /*!< TIM complementary channel operation state */
- __IO HAL_TIM_DMABurstStateTypeDef
- DMABurstState; /*!< DMA burst operation state */
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- void (*Base_MspInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
- void (*Base_MspDeInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
- void (*IC_MspInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
- void (*IC_MspDeInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
- void (*OC_MspInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
- void (*OC_MspDeInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
- void (*PWM_MspInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
- void (*PWM_MspDeInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
- void (*OnePulse_MspInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
- void (*OnePulse_MspDeInitCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM One Pulse Msp DeInit Callback */
- void (*Encoder_MspInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
- void (*Encoder_MspDeInitCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
- void (*HallSensor_MspInitCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Hall Sensor Msp Init Callback */
- void (*HallSensor_MspDeInitCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
- void (*PeriodElapsedCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
- void (*PeriodElapsedHalfCpltCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Period Elapsed half complete Callback */
- void (*TriggerCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
- void (*TriggerHalfCpltCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Trigger half complete Callback */
- void (*IC_CaptureCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
- void (*IC_CaptureHalfCpltCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Input Capture half complete Callback */
- void (*OC_DelayElapsedCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Output Compare Delay Elapsed Callback */
- void (*PWM_PulseFinishedCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
- void (*PWM_PulseFinishedHalfCpltCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM PWM Pulse Finished half complete Callback */
- void (*ErrorCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
- void (*CommutationCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
- void (*CommutationHalfCpltCallback)(
- struct __TIM_HandleTypeDef
- *htim); /*!< TIM Commutation half complete Callback */
- void (*BreakCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
- void (*Break2Callback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
- void (*EncoderIndexCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */
- void (*DirectionChangeCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */
- void (*IndexErrorCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */
- void (*TransitionErrorCallback)(
- struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-} TIM_HandleTypeDef;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL TIM Callback ID enumeration definition
- */
-typedef enum {
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- ,
- HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- ,
- HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- ,
- HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- ,
- HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- ,
- HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- ,
- HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- ,
- HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- ,
- HAL_TIM_ONE_PULSE_MSPINIT_CB_ID =
- 0x08U /*!< TIM One Pulse MspInit Callback ID */
- ,
- HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID =
- 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- ,
- HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- ,
- HAL_TIM_ENCODER_MSPDEINIT_CB_ID =
- 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- ,
- HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID =
- 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,
- HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID =
- 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,
- HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- ,
- HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID =
- 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- ,
- HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- ,
- HAL_TIM_TRIGGER_HALF_CB_ID =
- 0x11U /*!< TIM Trigger half complete Callback ID */
-
- ,
- HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- ,
- HAL_TIM_IC_CAPTURE_HALF_CB_ID =
- 0x13U /*!< TIM Input Capture half complete Callback ID */
- ,
- HAL_TIM_OC_DELAY_ELAPSED_CB_ID =
- 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- ,
- HAL_TIM_PWM_PULSE_FINISHED_CB_ID =
- 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- ,
- HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID =
- 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- ,
- HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- ,
- HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- ,
- HAL_TIM_COMMUTATION_HALF_CB_ID =
- 0x19U /*!< TIM Commutation half complete Callback ID */
- ,
- HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
- ,
- HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
- ,
- HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */
- ,
- HAL_TIM_DIRECTION_CHANGE_CB_ID =
- 0x1DU /*!< TIM Direction Change Callback ID */
- ,
- HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */
- ,
- HAL_TIM_TRANSITION_ERROR_CB_ID =
- 0x1FU /*!< TIM Transition Error Callback ID */
-} HAL_TIM_CallbackIDTypeDef;
-
-/**
- * @brief HAL TIM Callback pointer definition
- */
-typedef void (*pTIM_CallbackTypeDef)(
- TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
-
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */
-#define TIM_CLEARINPUTSOURCE_ETR \
- 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
-#define TIM_CLEARINPUTSOURCE_COMP1 \
- 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */
-#define TIM_CLEARINPUTSOURCE_COMP2 \
- TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */
-#define TIM_CLEARINPUTSOURCE_COMP3 \
- TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */
-#define TIM_CLEARINPUTSOURCE_COMP4 \
- (TIM1_AF2_OCRSEL_1 | \
- TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */
-#if defined(COMP5)
-#define TIM_CLEARINPUTSOURCE_COMP5 \
- TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_CLEARINPUTSOURCE_COMP6 \
- (TIM1_AF2_OCRSEL_2 | \
- TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_CLEARINPUTSOURCE_COMP7 \
- (TIM1_AF2_OCRSEL_2 | \
- TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 0x00000000U
-#define TIM_DMABASE_CR2 0x00000001U
-#define TIM_DMABASE_SMCR 0x00000002U
-#define TIM_DMABASE_DIER 0x00000003U
-#define TIM_DMABASE_SR 0x00000004U
-#define TIM_DMABASE_EGR 0x00000005U
-#define TIM_DMABASE_CCMR1 0x00000006U
-#define TIM_DMABASE_CCMR2 0x00000007U
-#define TIM_DMABASE_CCER 0x00000008U
-#define TIM_DMABASE_CNT 0x00000009U
-#define TIM_DMABASE_PSC 0x0000000AU
-#define TIM_DMABASE_ARR 0x0000000BU
-#define TIM_DMABASE_RCR 0x0000000CU
-#define TIM_DMABASE_CCR1 0x0000000DU
-#define TIM_DMABASE_CCR2 0x0000000EU
-#define TIM_DMABASE_CCR3 0x0000000FU
-#define TIM_DMABASE_CCR4 0x00000010U
-#define TIM_DMABASE_BDTR 0x00000011U
-#define TIM_DMABASE_CCR5 0x00000012U
-#define TIM_DMABASE_CCR6 0x00000013U
-#define TIM_DMABASE_CCMR3 0x00000014U
-#define TIM_DMABASE_DTR2 0x00000015U
-#define TIM_DMABASE_ECR 0x00000016U
-#define TIM_DMABASE_TISEL 0x00000017U
-#define TIM_DMABASE_AF1 0x00000018U
-#define TIM_DMABASE_AF2 0x00000019U
-#define TIM_DMABASE_OR 0x0000001AU
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE \
- TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the \
- registers */
-#define TIM_EVENTSOURCE_CC1 \
- TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 \
- TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 \
- TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 \
- TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM \
- TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER \
- TIM_EGR_TG /*!< A trigger event is generated \
- */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-#define TIM_EVENTSOURCE_BREAK2 \
- TIM_EGR_B2G /*!< A break 2 event is generated \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING \
- 0x00000000U /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING \
- TIM_CCER_CC1P /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE \
- (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED \
- 0x00000000U /*!< Polarity for ETR source \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 \
- TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 \
- TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 \
- TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
-#define TIM_COUNTERMODE_CENTERALIGNED1 \
- TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
-#define TIM_COUNTERMODE_CENTERALIGNED2 \
- TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
-#define TIM_COUNTERMODE_CENTERALIGNED3 \
- TIM_CR1_CMS /*!< Center-aligned mode 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
- * @{
- */
-#define TIM_UIFREMAP_DISABLE \
- 0x00000000U /*!< Update interrupt flag remap disabled */
-#define TIM_UIFREMAP_ENABLE \
- TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-#define TIM_CLOCKDIVISION_DIV1 \
- 0x00000000U /*!< Clock division: tDTS=tCK_INT */
-#define TIM_CLOCKDIVISION_DIV2 \
- TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
-#define TIM_CLOCKDIVISION_DIV4 \
- TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-#define TIM_OUTPUTSTATE_DISABLE \
- 0x00000000U /*!< Capture/Compare 1 output disabled */
-#define TIM_OUTPUTSTATE_ENABLE \
- TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE \
- 0x00000000U /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE \
- TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
-#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
-#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH \
- 0x00000000U /*!< Capture/Compare output polarity \
- */
-#define TIM_OCPOLARITY_LOW \
- TIM_CCER_CC1P /*!< Capture/Compare output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare
- * Polarity
- * @{
- */
-#define TIM_OCNPOLARITY_HIGH \
- 0x00000000U /*!< Capture/Compare complementary output polarity */
-#define TIM_OCNPOLARITY_LOW \
- TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-#define TIM_OCIDLESTATE_SET \
- TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
-#define TIM_OCIDLESTATE_RESET \
- 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare
- * Idle State
- * @{
- */
-#define TIM_OCNIDLESTATE_SET \
- TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
-#define TIM_OCNIDLESTATE_RESET \
- 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-#define TIM_ICPOLARITY_RISING \
- TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on \
- timer input */
-#define TIM_ICPOLARITY_FALLING \
- TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on \
- timer input */
-#define TIM_ICPOLARITY_BOTHEDGE \
- TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and \
- falling edges on timer input*/
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
- * @{
- */
-#define TIM_ENCODERINPUTPOLARITY_RISING \
- TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity \
- */
-#define TIM_ENCODERINPUTPOLARITY_FALLING \
- TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge \
- polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-#define TIM_ICSELECTION_DIRECTTI \
- TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to \
- IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI \
- TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to \
- IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC \
- TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to \
- TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-#define TIM_ICPSC_DIV1 \
- 0x00000000U /*!< Capture performed each time an edge is detected on the \
- capture input */
-#define TIM_ICPSC_DIV2 \
- TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 \
- TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 \
- TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-#define TIM_OPMODE_SINGLE \
- TIM_CR1_OPM /*!< Counter stops counting at the next update event */
-#define TIM_OPMODE_REPETITIVE \
- 0x00000000U /*!< Counter is not stopped at update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 \
- TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on \
- TI1FP1 edge depending on TI2FP2 level */
-#define TIM_ENCODERMODE_TI2 \
- TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on \
- TI2FP2 edge depending on TI1FP1 level. */
-#define TIM_ENCODERMODE_TI12 \
- (TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on \
- both TI1FP1 and TI2FP2 edges depending on the level of \
- the other input. */
-#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 \
- (TIM_SMCR_SMS_3 | \
- TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */
-#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 \
- edge sensitivity is set by CC2P */
-#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 \
- (TIM_SMCR_SMS_3 | \
- TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
-#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
- TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and \
- TI2FP2 edge sensitivity is set by CC1P and CC2P */
-#define TIM_ENCODERMODE_X1_TI1 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
- TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 \
- edges only, edge sensitivity is set by CC1P */
-#define TIM_ENCODERMODE_X1_TI2 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 \
- edges only, edge sensitivity is set by CC1P */
-/**
- * @}
- */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
-#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
-#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
-#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
-#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
-#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
-#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
-#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
-#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */
-#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */
-#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */
-#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */
-/**
- * @}
- */
-
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI \
- TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are \
- updated by setting the COMG bit or when an rising edge \
- occurs on trigger input */
-#define TIM_COMMUTATION_SOFTWARE \
- 0x00000000U /*!< When Capture/compare control bits are preloaded, they are \
- updated by setting the COMG bit */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-#define TIM_DMA_UPDATE \
- TIM_DIER_UDE /*!< DMA request is triggered by the update event */
-#define TIM_DMA_CC1 \
- TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 \
- event */
-#define TIM_DMA_CC2 \
- TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 \
- event event */
-#define TIM_DMA_CC3 \
- TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 \
- event event */
-#define TIM_DMA_CC4 \
- TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 \
- event event */
-#define TIM_DMA_COM \
- TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
-#define TIM_DMA_TRIGGER \
- TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
-#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
-#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
-#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
-#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
-#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
-#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
-#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
-#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
-#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
-#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
-#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
-#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
-#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
-#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
-#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
-#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */
-#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */
-#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */
-#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel TIM Channel
- * @{
- */
-#define TIM_CHANNEL_1 \
- 0x00000000U /*!< Capture/compare channel 1 identifier */
-#define TIM_CHANNEL_2 \
- 0x00000004U /*!< Capture/compare channel 2 identifier */
-#define TIM_CHANNEL_3 \
- 0x00000008U /*!< Capture/compare channel 3 identifier */
-#define TIM_CHANNEL_4 \
- 0x0000000CU /*!< Capture/compare channel 4 identifier */
-#define TIM_CHANNEL_5 \
- 0x00000010U /*!< Compare channel 5 identifier */
-#define TIM_CHANNEL_6 \
- 0x00000014U /*!< Compare channel 6 identifier */
-#define TIM_CHANNEL_ALL \
- 0x0000003CU /*!< Global Capture/compare channel identifier */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 \
- TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
-#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
-#define TIM_CLOCKSOURCE_ITR0 \
- TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
-#define TIM_CLOCKSOURCE_ITR1 \
- TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
-#define TIM_CLOCKSOURCE_ITR2 \
- TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
-#define TIM_CLOCKSOURCE_ITR3 \
- TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED \
- TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 \
- TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 \
- TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 \
- TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
-#if defined(TIM5)
-#define TIM_CLOCKSOURCE_ITR4 \
- TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
-#endif /* TIM5 */
-#define TIM_CLOCKSOURCE_ITR5 \
- TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
-#define TIM_CLOCKSOURCE_ITR6 \
- TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
-#define TIM_CLOCKSOURCE_ITR7 \
- TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
-#define TIM_CLOCKSOURCE_ITR8 \
- TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
-#if defined(TIM20)
-#define TIM_CLOCKSOURCE_ITR9 \
- TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */
-#endif /* TIM20 */
-#define TIM_CLOCKSOURCE_ITR10 \
- TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */
-#define TIM_CLOCKSOURCE_ITR11 \
- TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED \
- TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED \
- TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING \
- TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING \
- TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE \
- TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 \
- TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 \
- TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture \
- performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 \
- TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture \
- performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 \
- TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture \
- performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED \
- TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED \
- TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 \
- TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 \
- TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed \
- once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 \
- TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed \
- once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 \
- TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed \
- once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState
- * Selection for Run mode state
- * @{
- */
-#define TIM_OSSR_ENABLE \
- TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still \
- controlled by the timer) */
-#define TIM_OSSR_DISABLE \
- 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled \
- any longer by the timer) */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState
- * Selection for Idle mode state
- * @{
- */
-#define TIM_OSSI_ENABLE \
- TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still \
- controlled by the timer) */
-#define TIM_OSSI_DISABLE \
- 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled \
- any longer by the timer) */
-/**
- * @}
- */
-/** @defgroup TIM_Lock_level TIM Lock level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
-#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
- * @{
- */
-#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
-#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW \
- 0x00000000U /*!< Break input BRK is active low \
- */
-#define TIM_BREAKPOLARITY_HIGH \
- TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
- * @{
- */
-#define TIM_BREAK_AFMODE_INPUT \
- 0x00000000U /*!< Break input BRK in input mode \
- */
-#define TIM_BREAK_AFMODE_BIDIRECTIONAL \
- TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
- * @{
- */
-#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
-#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
- * @{
- */
-#define TIM_BREAK2POLARITY_LOW \
- 0x00000000U /*!< Break input BRK2 is active low */
-#define TIM_BREAK2POLARITY_HIGH \
- TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
- * @{
- */
-#define TIM_BREAK2_AFMODE_INPUT \
- 0x00000000U /*!< Break2 input BRK2 in input mode */
-#define TIM_BREAK2_AFMODE_BIDIRECTIONAL \
- TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_DISABLE \
- 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE \
- TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next \
- update event (if none of the break inputs BRK and BRK2 is \
- active) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
- * @{
- */
-#define TIM_GROUPCH5_NONE \
- 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC \
- TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC \
- TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC \
- TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET \
- 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
-#define TIM_TRGO_ENABLE \
- TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
-#define TIM_TRGO_UPDATE \
- TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1 \
- (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as \
- trigger output (TRGO) */
-#define TIM_TRGO_OC1REF \
- TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
-#define TIM_TRGO_OC2REF \
- (TIM_CR2_MMS_2 | \
- TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC3REF \
- (TIM_CR2_MMS_2 | \
- TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC4REF \
- (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | \
- TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_ENCODER_CLK \
- TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
- * @{
- */
-#define TIM_TRGO2_RESET \
- 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
-#define TIM_TRGO2_ENABLE \
- TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
-#define TIM_TRGO2_UPDATE \
- TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC1 \
- (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used \
- as trigger output (TRGO2) */
-#define TIM_TRGO2_OC1REF \
- TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC2REF \
- (TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC3REF \
- (TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC4REF \
- (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
- TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC5REF \
- TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC6REF \
- (TIM_CR2_MMS2_3 | \
- TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC4REF_RISINGFALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges \
- generate pulses on TRGO2 */
-#define TIM_TRGO2_OC6REF_RISINGFALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | \
- TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on \
- TRGO2 */
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges \
- generate pulses on TRGO2 */
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses \
- on TRGO2 */
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 \
- */
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
- TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
- * @{
- */
-#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
-#define TIM_MASTERSLAVEMODE_DISABLE \
- 0x00000000U /*!< Master/slave mode is selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
-#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
-#define TIM_SLAVEMODE_GATED \
- (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
-#define TIM_SLAVEMODE_TRIGGER \
- (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
-#define TIM_SLAVEMODE_EXTERNAL1 \
- (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER \
- TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
-#define TIM_SLAVEMODE_COMBINED_GATEDRESET \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING \
- 0x00000000U /*!< Frozen */
-#define TIM_OCMODE_ACTIVE \
- TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
-#define TIM_OCMODE_INACTIVE \
- TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
-#define TIM_OCMODE_PWM1 \
- (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 \
- */
-#define TIM_OCMODE_PWM2 \
- (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
-#define TIM_OCMODE_FORCED_ACTIVE \
- (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
-#define TIM_OCMODE_FORCED_INACTIVE \
- TIM_CCMR1_OC1M_2 /*!< Force inactive level */
-#define TIM_OCMODE_RETRIGERRABLE_OPM1 \
- TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
-#define TIM_OCMODE_RETRIGERRABLE_OPM2 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
-#define TIM_OCMODE_COMBINED_PWM1 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
-#define TIM_OCMODE_COMBINED_PWM2 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | \
- TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
-#define TIM_OCMODE_ASSYMETRIC_PWM1 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | \
- TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
-#define TIM_OCMODE_ASSYMETRIC_PWM2 \
- TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
-#define TIM_OCMODE_PULSE_ON_COMPARE \
- (TIM_CCMR2_OC3M_3 | \
- TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */
-#define TIM_OCMODE_DIRECTION_OUTPUT \
- (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | \
- TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
-#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
-#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
-#define TIM_TS_ITR3 \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
-#define TIM_TS_TI1F_ED \
- TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
-#define TIM_TS_TI1FP1 \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
-#define TIM_TS_TI2FP2 \
- (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
-#define TIM_TS_ETRF \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | \
- TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
-#if defined(TIM5)
-#define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */
-#endif /* TIM5 */
-#define TIM_TS_ITR5 \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
-#define TIM_TS_ITR6 \
- (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
-#define TIM_TS_ITR7 \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | \
- TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
-#define TIM_TS_ITR8 \
- (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
-#if defined(TIM20)
-#define TIM_TS_ITR9 \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | \
- TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
-#endif /* TIM20 */
-#define TIM_TS_ITR10 \
- (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | \
- TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
-#define TIM_TS_ITR11 \
- (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | \
- TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
-#define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED \
- TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED \
- TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING \
- TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger \
- sources */
-#define TIM_TRIGGERPOLARITY_FALLING \
- TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger \
- sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE \
- TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger \
- sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 \
- TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 \
- TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture \
- performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 \
- TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture \
- performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 \
- TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture \
- performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-#define TIM_TI1SELECTION_CH1 \
- 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
-#define TIM_TI1SELECTION_XORCOMBINATION \
- TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 \
- input (XOR combination) */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER \
- 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + \
- TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS \
- 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS \
- 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS \
- 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS \
- 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS \
- 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS \
- 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS \
- 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS \
- 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS \
- 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS \
- 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS \
- 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS \
- 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS \
- 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS \
- 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS \
- 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS \
- 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS \
- 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_19TRANSFERS \
- 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_20TRANSFERS \
- 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_21TRANSFERS \
- 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_22TRANSFERS \
- 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_23TRANSFERS \
- 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_24TRANSFERS \
- 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_25TRANSFERS \
- 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_26TRANSFERS \
- 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 \
- + TIMx_DCR.DBA */
-/**
- * @}
- */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE \
- ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests \
- */
-#define TIM_DMA_ID_CC1 \
- ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 \
- DMA requests */
-#define TIM_DMA_ID_CC2 \
- ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 \
- DMA requests */
-#define TIM_DMA_ID_CC3 \
- ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 \
- DMA requests */
-#define TIM_DMA_ID_CC4 \
- ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 \
- DMA requests */
-#define TIM_DMA_ID_COMMUTATION \
- ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA \
- requests */
-#define TIM_DMA_ID_TRIGGER \
- ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA \
- requests */
-/**
- * @}
- */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
-#define TIM_CCx_DISABLE \
- 0x00000000U /*!< Input or output channel is disabled \
- */
-#define TIM_CCxN_ENABLE \
- 0x00000004U /*!< Complementary output channel is enabled */
-#define TIM_CCxN_DISABLE \
- 0x00000000U /*!< Complementary output channel is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_System TIM Break System
- * @{
- */
-#define TIM_BREAK_SYSTEM_ECC \
- SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break \
- Input of TIM1/8/15/16/17/20 */
-#define TIM_BREAK_SYSTEM_PVD \
- SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with \
- TIM1/8/15/16/17/20 Break Input and also the PVDE and \
- PLS bits of the Power Control Interface */
-#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR \
- SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with \
- Break Input of TIM1/8/15/16/17/20 */
-#define TIM_BREAK_SYSTEM_LOCKUP \
- SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with \
- Break Input of TIM1/8/15/16/17/20 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state.
- * @param __HANDLE__ TIM handle.
- * @retval None
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
- } while (0)
-#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- } while (0)
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_CEN))
-
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->BDTR |= (TIM_BDTR_MOE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while (0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the
- * CCx and CCxN channels have been disabled
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while (0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled unconditionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-
-/** @brief Enable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @arg TIM_IT_IDX: Index interrupt
- * @arg TIM_IT_DIR: Direction change interrupt
- * @arg TIM_IT_IERR: Index error interrupt
- * @arg TIM_IT_TERR: Transition error interrupt
- * @retval None
- */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @arg TIM_IT_IDX: Index interrupt
- * @arg TIM_IT_DIR: Direction change interrupt
- * @arg TIM_IT_IERR: Index error interrupt
- * @arg TIM_IT_TERR: Transition error interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief Enable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) \
- ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief Disable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) \
- ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @arg TIM_FLAG_IDX: Index interrupt flag
- * @arg TIM_FLAG_DIR: Direction change interrupt flag
- * @arg TIM_FLAG_IERR: Index error interrupt flag
- * @arg TIM_FLAG_TERR: Transition error interrupt flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) \
- (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @arg TIM_FLAG_IDX: Index interrupt flag
- * @arg TIM_FLAG_DIR: Direction change interrupt flag
- * @arg TIM_FLAG_IERR: Index error interrupt flag
- * @arg TIM_FLAG_TERR: Transition error interrupt flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @arg TIM_IT_IDX: Index interrupt
- * @arg TIM_IT_DIR: Direction change interrupt
- * @arg TIM_IT_IERR: Index error interrupt
- * @arg TIM_IT_TERR: Transition error interrupt
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) \
- ? SET \
- : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @arg TIM_IT_IDX: Index interrupt
- * @arg TIM_IT_DIR: Direction change interrupt
- * @arg TIM_IT_IERR: Index error interrupt
- * @arg TIM_IT_TERR: Transition error interrupt
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
- ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
- * @brief Force a continuous copy of the update interrupt flag (UIF) into the
-timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition
-signalled by the UIFCPY flag to be read
- * in an atomic way.
- * @param __HANDLE__ TIM handle.
- * @retval None
-mode.
- */
-#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) \
- (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
-
-/**
- * @brief Disable update interrupt flag (UIF) remapping.
- * @param __HANDLE__ TIM handle.
- * @retval None
-mode.
- */
-#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) \
- (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
-
-/**
- * @brief Get update interrupt flag (UIF) copy status.
- * @param __COUNTER__ Counter value.
- * @retval The state of UIFCPY (TRUE or FALSE).
-mode.
- */
-#define __HAL_TIM_GET_UIFCPY(__COUNTER__) \
- (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__ TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as
- * downcounter)
- * @note This macro is particularly useful to get the counting mode when the
- * timer operates in Center-aligned mode or Encoder mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) \
- (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __PRESC__ specifies the Prescaler new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) \
- ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
- * @brief Set the TIM Counter Register value on runtime.
- * Note Please check if the bit 31 of CNT register is used as UIF copy or not,
- * this may affect the counter range in case of 32 bits counter TIM instance.
- * Bit 31 of CNT can be enabled/disabled using
- * __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
- * @param __HANDLE__ TIM handle.
- * @param __COUNTER__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) \
- ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Get the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Set the TIM Autoreload Register value on runtime without calling
- * another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __AUTORELOAD__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do { \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while (0)
-
-/**
- * @brief Get the TIM Autoreload Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Set the TIM Clock Division value on runtime without calling another
- * time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __CKD__ specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do { \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while (0)
-
-/**
- * @brief Get the TIM Clock Division value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do { \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while (0)
-
-/**
- * @brief Get the TIM Input Capture prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) \
- : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
- * @brief Set the TIM Capture Compare Register value on runtime without calling
- * another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) \
- ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) \
- ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) \
- : ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
-
-/**
- * @brief Get the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @arg TIM_CHANNEL_5: get capture/compare 5 register value
- * @arg TIM_CHANNEL_6: get capture/compare 6 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) \
- : ((__HANDLE__)->Instance->CCR6))
-
-/**
- * @brief Set the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) \
- ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) \
- ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) \
- : ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
-
-/**
- * @brief Reset the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) \
- ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) \
- ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) \
- : ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
-
-/**
- * @brief Enable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @note When fast mode is enabled an active edge on the trigger input acts
- * like a compare match on CCx output. Delay to sample the trigger
- * input and to activate CCx output is reduced to 3 clock cycles.
- * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) \
- ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) \
- ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) \
- : ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
-
-/**
- * @brief Disable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @note When fast mode is disabled CCx output behaves normally depending
- * on counter and CCRx values even when the trigger is ON. The minimum
- * delay to activate CCx output when an active edge occurs on the
- * trigger input is 5 clock cycles.
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) \
- ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) \
- ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) \
- : ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 |= TIM_CR1_URS)
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * _ Counter overflow underflow
- * _ Setting the UG bit
- * _ Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_URS)
-
-/**
- * @brief Set the TIM Capture x input polarity on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__ Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do { \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- } while (0)
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK \
- ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK \
- ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | \
- TIM_CCER_CC4NE))
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-#if defined(COMP5) && defined(COMP6) && defined(COMP7)
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) \
- (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
-#else /* COMP5 && COMP6 && COMP7 */
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) \
- (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
-#endif /* COMP5 && COMP6 && COMP7 */
-
-#define IS_TIM_DMA_BASE(__BASE__) \
- (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR) || \
- ((__BASE__) == TIM_DMABASE_CCMR3) || ((__BASE__) == TIM_DMABASE_CCR5) || \
- ((__BASE__) == TIM_DMABASE_CCR6) || ((__BASE__) == TIM_DMABASE_AF1) || \
- ((__BASE__) == TIM_DMABASE_AF2) || ((__BASE__) == TIM_DMABASE_TISEL) || \
- ((__BASE__) == TIM_DMABASE_DTR2) || ((__BASE__) == TIM_DMABASE_ECR) || \
- ((__BASE__) == TIM_DMABASE_OR))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) \
- ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && \
- ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_COUNTER_MODE(__MODE__) \
- (((__MODE__) == TIM_COUNTERMODE_UP) || \
- ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_UIFREMAP_MODE(__MODE__) \
- (((__MODE__) == TIM_UIFREMAP_DISABLE) || ((__MODE__) == TIM_UIFREMAP_ENALE))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) \
- (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) \
- (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__) \
- (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) \
- (((__STATE__) == TIM_OCIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) \
- (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) \
- (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) \
- (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) \
- (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) \
- (((__MODE__) == TIM_ENCODERMODE_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_TI2) || \
- ((__MODE__) == TIM_ENCODERMODE_TI12) || \
- ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \
- ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \
- ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \
- ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
- ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) \
- ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && \
- ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || \
- ((__CHANNEL__) == TIM_CHANNEL_5) || ((__CHANNEL__) == TIM_CHANNEL_6) || \
- ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))
-
-#if defined(TIM5) && defined(TIM20)
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
- (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
-#elif defined(TIM5)
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
- (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
-#elif defined(TIM20)
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
- (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
-#else
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
- (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
-#endif /* TIM5 && TIM20 */
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) \
- (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) \
- (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_OSSR_STATE(__STATE__) \
- (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) \
- (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) \
- (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
-#define IS_TIM_BREAK_STATE(__STATE__) \
- (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_BREAK_AFMODE(__AFMODE__) \
- (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
- ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
-
-#define IS_TIM_BREAK2_STATE(__STATE__) \
- (((__STATE__) == TIM_BREAK2_ENABLE) || ((__STATE__) == TIM_BREAK2_DISABLE))
-
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
-
-#define IS_TIM_BREAK2_AFMODE(__AFMODE__) \
- (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
- ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) \
- (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_GROUPCH5(__OCREF__) \
- ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || \
- ((__SOURCE__) == TIM_TRGO_OC1REF) || ((__SOURCE__) == TIM_TRGO_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF) || \
- ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
-
-#define IS_TIM_TRGO2_SOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_TRGO2_RESET) || ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO2_UPDATE) || ((__SOURCE__) == TIM_TRGO2_OC1) || \
- ((__SOURCE__) == TIM_TRGO2_OC1REF) || ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC3REF) || ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF) || ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-
-#define IS_TIM_MSM_STATE(__STATE__) \
- (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) \
- (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
- ((__MODE__) == TIM_SLAVEMODE_RESET) || \
- ((__MODE__) == TIM_SLAVEMODE_GATED) || \
- ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
- ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
- ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
-
-#define IS_TIM_PWM_MODE(__MODE__) \
- (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2) || \
- ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
- ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__) \
- (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
- ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
- ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
- ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
-
-#if defined(TIM5) && defined(TIM20)
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10) || ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_NONE))
-#elif defined(TIM5)
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_ITR11) || ((__SELECTION__) == TIM_TS_NONE))
-#elif defined(TIM20)
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_NONE))
-#else
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR11) || ((__SELECTION__) == TIM_TS_NONE))
-#endif /* TIM5 && TIM20 */
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) \
- (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__) \
- (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
- ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) \
- (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) \
- (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
-
-#define IS_TIM_BREAK_SYSTEM(__CONFIG__) \
- (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
-
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) \
- (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) \
- : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \
- : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
- : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) \
- : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] \
- : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \
- : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \
- : ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] \
- : ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] \
- : (__HANDLE__)->ChannelState[5])
-
-#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_4) \
- ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_5) \
- ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) \
- : ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
- do { \
- (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
- } while (0)
-
-#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] \
- : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \
- : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \
- : (__HANDLE__)->ChannelNState[3])
-
-#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) \
- ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_2) \
- ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
- : ((__CHANNEL__) == TIM_CHANNEL_3) \
- ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \
- : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
- do { \
- (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
- } while (0)
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32g4xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- * @{
- */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- * @{
- */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- * @{
- */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- * @{
- */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim,
- uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- * @{
- */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,
- TIM_Encoder_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- * @{
- */
-/* Interrupt Handler functions ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_IC_InitTypeDef *sConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(
- TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(
- TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(
- TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim,
- uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(
- TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(
- TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength,
- uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim,
- uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength,
- uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim,
- uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim,
- uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim,
- HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(
- TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/* Peripheral Channel state functions
- * ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ChannelState);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_TIM_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_TIM_H
+#define STM32G4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct {
+ uint32_t
+ Prescaler; /*!< Specifies the prescaler value used to divide the TIM
+ clock. This parameter can be a number between Min_Data =
+ 0x0000 and Max_Data = 0xFFFF Macro __HAL_TIM_CALC_PSC() can
+ be used to calculate prescaler value */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref
+ TIM_Counter_Mode */
+
+ uint32_t
+ Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)Macros
+ __HAL_TIM_CALC_PERIOD(),
+ __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
+ __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to
+ calculate Period value */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref
+ TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each
+ time the RCR downcounter reaches zero, an
+ update event is generated and counting restarts
+ from the RCR value (N). This means in PWM mode
+ that (N+1) corresponds to:
+ - the number of PWM periods in
+ edge-aligned mode
+ - the number of half PWM period in
+ center-aligned mode GP timers: this parameter
+ must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF. Advanced timers: this
+ parameter must be a number between Min_Data =
+ 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref
+ TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct {
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref
+ TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture
+ Compare Register. This parameter can be a number between
+ Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if
+ dithering is activated) Macros __HAL_TIM_CALC_PULSE(),
+ __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+ Pulse value */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref
+ TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref
+ TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for timer
+ instances supporting break feature. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref
+ TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2
+ mode. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during
+ Idle state. This parameter can be a value of @ref
+ TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for timer
+ instances supporting break feature. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during
+ Idle state. This parameter can be a value of @ref
+ TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for timer
+ instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct {
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref
+ TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture
+ Compare Register. This parameter can be a number between
+ Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if
+ dithering is activated) Macros __HAL_TIM_CALC_PULSE(),
+ __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+ Pulse value */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref
+ TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref
+ TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for timer
+ instances supporting break feature. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during
+ Idle state. This parameter can be a value of @ref
+ TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for timer
+ instances supporting break feature. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during
+ Idle state. This parameter can be a value of @ref
+ TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for timer
+ instances supporting break feature. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0
+ and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct {
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0
+ and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct {
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_Encoder_Input_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0
+ and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_Encoder_Input_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0
+ and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct {
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref
+ TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref
+ TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref
+ TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data =
+ 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
+ */
+typedef struct {
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref
+ TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref
+ TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter must be 0: When OCRef clear
+ feature is used with ETR source, ETR
+ prescaler must be off */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between
+ Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note Advanced timers provide TRGO2 internal line which is redirected
+ * to the ADC
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref
+ TIM_Master_Mode_Selection */
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
+ This parameter can be a value of @ref
+ TIM_Master_Mode_Selection_2 */
+ uint32_t
+ MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref
+ TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the
+ effect of an event on the trigger input (TRGI) is
+ delayed to allow a perfect synchronization between the
+ current timer and its slaves (through TRGO). It is not
+ mandatory in case of timer synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t
+ SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref
+ TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref
+ TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref
+ TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data =
+ 0x0 and Max_Data = 0xF */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct {
+ uint32_t
+ OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a
+ value of @ref
+ TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint32_t
+ OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a
+ value of @ref
+ TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref
+ TIM_Lock_level */
+
+ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF */
+
+ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of
+ @ref TIM_Break_Input_enable_disable */
+
+ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a
+ value of @ref TIM_Break_Polarity */
+
+ uint32_t
+ BreakFilter; /*!< Specifies the break input filter.This parameter can be a
+ number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break
+ input.This parameter can be a value of @ref
+ TIM_Break_Input_AF_Mode */
+
+ uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of
+ @ref TIM_Break2_Input_enable_disable */
+
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be
+ a value of @ref TIM_Break2_Polarity */
+
+ uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a
+ number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the
+ break2 input.This parameter can be a value of @ref
+ TIM_Break2_Input_AF_Mode */
+
+ uint32_t
+ AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter
+ can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum {
+ HAL_TIM_STATE_RESET =
+ 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+} HAL_TIM_StateTypeDef;
+
+/**
+ * @brief TIM Channel States definition
+ */
+typedef enum {
+ HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
+ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
+ HAL_TIM_CHANNEL_STATE_BUSY =
+ 0x02U, /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+ * @brief DMA Burst States definition
+ */
+typedef enum {
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum {
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
+ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef
+ *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_ChannelStateTypeDef
+ ChannelState[6]; /*!< TIM channel operation state */
+ __IO HAL_TIM_ChannelStateTypeDef
+ ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef
+ DMABurstState; /*!< DMA burst operation state */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ void (*Base_MspInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (*Base_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (*IC_MspInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (*IC_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (*OC_MspInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (*OC_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (*PWM_MspInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (*PWM_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (*OnePulse_MspInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (*OnePulse_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (*Encoder_MspInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (*Encoder_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (*HallSensor_MspInitCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (*HallSensor_MspDeInitCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+ void (*PeriodElapsedCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (*PeriodElapsedHalfCpltCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Period Elapsed half complete Callback */
+ void (*TriggerCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (*TriggerHalfCpltCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Trigger half complete Callback */
+ void (*IC_CaptureCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (*IC_CaptureHalfCpltCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Input Capture half complete Callback */
+ void (*OC_DelayElapsedCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (*PWM_PulseFinishedCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (*PWM_PulseFinishedHalfCpltCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM PWM Pulse Finished half complete Callback */
+ void (*ErrorCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (*CommutationCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (*CommutationHalfCpltCallback)(
+ struct __TIM_HandleTypeDef
+ *htim); /*!< TIM Commutation half complete Callback */
+ void (*BreakCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+ void (*Break2Callback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
+ void (*EncoderIndexCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */
+ void (*DirectionChangeCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */
+ void (*IndexErrorCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */
+ void (*TransitionErrorCallback)(
+ struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TIM Callback ID enumeration definition
+ */
+typedef enum {
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ ,
+ HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ ,
+ HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ ,
+ HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ ,
+ HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ ,
+ HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ ,
+ HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ ,
+ HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ ,
+ HAL_TIM_ONE_PULSE_MSPINIT_CB_ID =
+ 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ ,
+ HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID =
+ 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ ,
+ HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ ,
+ HAL_TIM_ENCODER_MSPDEINIT_CB_ID =
+ 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ ,
+ HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID =
+ 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,
+ HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID =
+ 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,
+ HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ ,
+ HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID =
+ 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ ,
+ HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ ,
+ HAL_TIM_TRIGGER_HALF_CB_ID =
+ 0x11U /*!< TIM Trigger half complete Callback ID */
+ ,
+ HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ ,
+ HAL_TIM_IC_CAPTURE_HALF_CB_ID =
+ 0x13U /*!< TIM Input Capture half complete Callback ID */
+ ,
+ HAL_TIM_OC_DELAY_ELAPSED_CB_ID =
+ 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ ,
+ HAL_TIM_PWM_PULSE_FINISHED_CB_ID =
+ 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ ,
+ HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID =
+ 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ ,
+ HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ ,
+ HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ ,
+ HAL_TIM_COMMUTATION_HALF_CB_ID =
+ 0x19U /*!< TIM Commutation half complete Callback ID */
+ ,
+ HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ ,
+ HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+ ,
+ HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */
+ ,
+ HAL_TIM_DIRECTION_CHANGE_CB_ID =
+ 0x1DU /*!< TIM Direction Change Callback ID */
+ ,
+ HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */
+ ,
+ HAL_TIM_TRANSITION_ERROR_CB_ID =
+ 0x1FU /*!< TIM Transition Error Callback ID */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pTIM_CallbackTypeDef)(
+ TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR \
+ 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
+#define TIM_CLEARINPUTSOURCE_COMP1 \
+ 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */
+#define TIM_CLEARINPUTSOURCE_COMP2 \
+ TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */
+#define TIM_CLEARINPUTSOURCE_COMP3 \
+ TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */
+#define TIM_CLEARINPUTSOURCE_COMP4 \
+ (TIM1_AF2_OCRSEL_1 | \
+ TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */
+#if defined(COMP5)
+#define TIM_CLEARINPUTSOURCE_COMP5 \
+ TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_CLEARINPUTSOURCE_COMP6 \
+ (TIM1_AF2_OCRSEL_2 | \
+ TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_CLEARINPUTSOURCE_COMP7 \
+ (TIM1_AF2_OCRSEL_2 | \
+ TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_CCR5 0x00000012U
+#define TIM_DMABASE_CCR6 0x00000013U
+#define TIM_DMABASE_CCMR3 0x00000014U
+#define TIM_DMABASE_DTR2 0x00000015U
+#define TIM_DMABASE_ECR 0x00000016U
+#define TIM_DMABASE_TISEL 0x00000017U
+#define TIM_DMABASE_AF1 0x00000018U
+#define TIM_DMABASE_AF2 0x00000019U
+#define TIM_DMABASE_OR 0x0000001AU
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE \
+ TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the \
+ registers */
+#define TIM_EVENTSOURCE_CC1 \
+ TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 \
+ TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 \
+ TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 \
+ TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM \
+ TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER \
+ TIM_EGR_TG /*!< A trigger event is generated \
+ */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2 \
+ TIM_EGR_B2G /*!< A break 2 event is generated \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING \
+ 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING \
+ TIM_CCER_CC1P /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE \
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED \
+ 0x00000000U /*!< Polarity for ETR source \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 \
+ TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 \
+ TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 \
+ TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1 \
+ TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
+#define TIM_COUNTERMODE_CENTERALIGNED2 \
+ TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
+#define TIM_COUNTERMODE_CENTERALIGNED3 \
+ TIM_CR1_CMS /*!< Center-aligned mode 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+ * @{
+ */
+#define TIM_UIFREMAP_DISABLE \
+ 0x00000000U /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE \
+ TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 \
+ 0x00000000U /*!< Clock division: tDTS=tCK_INT */
+#define TIM_CLOCKDIVISION_DIV2 \
+ TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4 \
+ TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTSTATE_DISABLE \
+ 0x00000000U /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE \
+ TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+ * @{
+ */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE \
+ 0x00000000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE \
+ TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH \
+ 0x00000000U /*!< Capture/Compare output polarity \
+ */
+#define TIM_OCPOLARITY_LOW \
+ TIM_CCER_CC1P /*!< Capture/Compare output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare
+ * Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH \
+ 0x00000000U /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW \
+ TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET \
+ TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET \
+ 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare
+ * Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET \
+ TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET \
+ 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING \
+ TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on \
+ timer input */
+#define TIM_ICPOLARITY_FALLING \
+ TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on \
+ timer input */
+#define TIM_ICPOLARITY_BOTHEDGE \
+ TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and \
+ falling edges on timer input*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING \
+ TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity \
+ */
+#define TIM_ENCODERINPUTPOLARITY_FALLING \
+ TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge \
+ polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI \
+ TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to \
+ IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI \
+ TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to \
+ IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC \
+ TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to \
+ TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 \
+ 0x00000000U /*!< Capture performed each time an edge is detected on the \
+ capture input */
+#define TIM_ICPSC_DIV2 \
+ TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 \
+ TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 \
+ TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE \
+ TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE \
+ 0x00000000U /*!< Counter is not stopped at update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 \
+ TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on \
+ TI1FP1 edge depending on TI2FP2 level */
+#define TIM_ENCODERMODE_TI2 \
+ TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on \
+ TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12 \
+ (TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on \
+ both TI1FP1 and TI2FP2 edges depending on the level of \
+ the other input. */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 \
+ (TIM_SMCR_SMS_3 | \
+ TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 \
+ edge sensitivity is set by CC2P */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 \
+ (TIM_SMCR_SMS_3 | \
+ TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
+ TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and \
+ TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define TIM_ENCODERMODE_X1_TI1 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
+ TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 \
+ edges only, edge sensitivity is set by CC1P */
+#define TIM_ENCODERMODE_X1_TI2 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 \
+ edges only, edge sensitivity is set by CC1P */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
+#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */
+#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */
+#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */
+#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI \
+ TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are \
+ updated by setting the COMG bit or when an rising edge \
+ occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE \
+ 0x00000000U /*!< When Capture/compare control bits are preloaded, they are \
+ updated by setting the COMG bit */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE \
+ TIM_DIER_UDE /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1 \
+ TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 \
+ event */
+#define TIM_DMA_CC2 \
+ TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 \
+ event event */
+#define TIM_DMA_CC3 \
+ TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 \
+ event event */
+#define TIM_DMA_CC4 \
+ TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 \
+ event event */
+#define TIM_DMA_COM \
+ TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER \
+ TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+ * @{
+ */
+#define TIM_CCDMAREQUEST_CC \
+ 0x00000000U /*!< CCx DMA request sent when capture or compare match event \
+ occurs */
+#define TIM_CCDMAREQUEST_UPDATE \
+ TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
+#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
+#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
+#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */
+#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */
+#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */
+#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 \
+ 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define TIM_CHANNEL_2 \
+ 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define TIM_CHANNEL_3 \
+ 0x00000008U /*!< Capture/compare channel 3 identifier */
+#define TIM_CHANNEL_4 \
+ 0x0000000CU /*!< Capture/compare channel 4 identifier */
+#define TIM_CHANNEL_5 \
+ 0x00000010U /*!< Compare channel 5 identifier */
+#define TIM_CHANNEL_6 \
+ 0x00000014U /*!< Compare channel 6 identifier */
+#define TIM_CHANNEL_ALL \
+ 0x0000003CU /*!< Global Capture/compare channel identifier */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ETRMODE1 \
+ TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+#define TIM_CLOCKSOURCE_ETRMODE2 \
+ TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_TI1ED \
+ TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 \
+ TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 \
+ TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
+#define TIM_CLOCKSOURCE_ITR0 \
+ TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
+#define TIM_CLOCKSOURCE_ITR1 \
+ TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
+#define TIM_CLOCKSOURCE_ITR2 \
+ TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
+#define TIM_CLOCKSOURCE_ITR3 \
+ TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
+#if defined(TIM5)
+#define TIM_CLOCKSOURCE_ITR4 \
+ TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
+#endif /* TIM5 */
+#define TIM_CLOCKSOURCE_ITR5 \
+ TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
+#define TIM_CLOCKSOURCE_ITR6 \
+ TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
+#define TIM_CLOCKSOURCE_ITR7 \
+ TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
+#define TIM_CLOCKSOURCE_ITR8 \
+ TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
+#if defined(TIM20)
+#define TIM_CLOCKSOURCE_ITR9 \
+ TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */
+#endif /* TIM20 */
+#define TIM_CLOCKSOURCE_ITR10 \
+ TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */
+#define TIM_CLOCKSOURCE_ITR11 \
+ TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED \
+ TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED \
+ TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING \
+ TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING \
+ TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE \
+ TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 \
+ TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 \
+ TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture \
+ performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 \
+ TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture \
+ performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 \
+ TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture \
+ performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED \
+ TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED \
+ TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 \
+ TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 \
+ TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed \
+ once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 \
+ TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed \
+ once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 \
+ TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed \
+ once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState
+ * Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE \
+ TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still \
+ controlled by the timer) */
+#define TIM_OSSR_DISABLE \
+ 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled \
+ any longer by the timer) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState
+ * Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE \
+ TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still \
+ controlled by the timer) */
+#define TIM_OSSI_DISABLE \
+ 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled \
+ any longer by the timer) */
+/**
+ * @}
+ */
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+ * @{
+ */
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW \
+ 0x00000000U /*!< Break input BRK is active low \
+ */
+#define TIM_BREAKPOLARITY_HIGH \
+ TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK_AFMODE_INPUT \
+ 0x00000000U /*!< Break input BRK in input mode \
+ */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL \
+ TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+ * @{
+ */
+#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
+#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+ * @{
+ */
+#define TIM_BREAK2POLARITY_LOW \
+ 0x00000000U /*!< Break input BRK2 is active low */
+#define TIM_BREAK2POLARITY_HIGH \
+ TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK2_AFMODE_INPUT \
+ 0x00000000U /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL \
+ TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_DISABLE \
+ 0x00000000U /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE \
+ TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next \
+ update event (if none of the break inputs BRK and BRK2 is \
+ active) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
+ * @{
+ */
+#define TIM_GROUPCH5_NONE \
+ 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC \
+ TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC \
+ TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC \
+ TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET \
+ 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
+#define TIM_TRGO_ENABLE \
+ TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
+#define TIM_TRGO_UPDATE \
+ TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1 \
+ (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as \
+ trigger output (TRGO) */
+#define TIM_TRGO_OC1REF \
+ TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
+#define TIM_TRGO_OC2REF \
+ (TIM_CR2_MMS_2 | \
+ TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC3REF \
+ (TIM_CR2_MMS_2 | \
+ TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC4REF \
+ (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | \
+ TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_ENCODER_CLK \
+ TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+ * @{
+ */
+#define TIM_TRGO2_RESET \
+ 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_ENABLE \
+ TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_UPDATE \
+ TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1 \
+ (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used \
+ as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF \
+ TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC2REF \
+ (TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC3REF \
+ (TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF \
+ (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
+ TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC5REF \
+ TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC6REF \
+ (TIM_CR2_MMS2_3 | \
+ TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF_RISINGFALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges \
+ generate pulses on TRGO2 */
+#define TIM_TRGO2_OC6REF_RISINGFALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | \
+ TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on \
+ TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges \
+ generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses \
+ on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 \
+ */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
+ TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE \
+ 0x00000000U /*!< Master/slave mode is selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
+#define TIM_SLAVEMODE_GATED \
+ (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
+#define TIM_SLAVEMODE_TRIGGER \
+ (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
+#define TIM_SLAVEMODE_EXTERNAL1 \
+ (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER \
+ TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
+#define TIM_SLAVEMODE_COMBINED_GATEDRESET \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING \
+ 0x00000000U /*!< Frozen */
+#define TIM_OCMODE_ACTIVE \
+ TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
+#define TIM_OCMODE_INACTIVE \
+ TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
+#define TIM_OCMODE_PWM1 \
+ (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 \
+ */
+#define TIM_OCMODE_PWM2 \
+ (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
+#define TIM_OCMODE_FORCED_ACTIVE \
+ (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
+#define TIM_OCMODE_FORCED_INACTIVE \
+ TIM_CCMR1_OC1M_2 /*!< Force inactive level */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 \
+ TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
+#define TIM_OCMODE_COMBINED_PWM1 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
+#define TIM_OCMODE_COMBINED_PWM2 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | \
+ TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
+#define TIM_OCMODE_ASYMMETRIC_PWM1 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | \
+ TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASYMMETRIC_PWM2 \
+ TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+#define TIM_OCMODE_PULSE_ON_COMPARE \
+ (TIM_CCMR2_OC3M_3 | \
+ TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */
+#define TIM_OCMODE_DIRECTION_OUTPUT \
+ (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | \
+ TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
+#define TIM_TS_ITR3 \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
+#if defined(TIM5)
+#define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */
+#endif /* TIM5 */
+#define TIM_TS_ITR5 \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
+#define TIM_TS_ITR6 \
+ (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
+#define TIM_TS_ITR7 \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | \
+ TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
+#define TIM_TS_ITR8 \
+ (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
+#if defined(TIM20)
+#define TIM_TS_ITR9 \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | \
+ TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
+#endif /* TIM20 */
+#define TIM_TS_ITR10 \
+ (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | \
+ TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
+#define TIM_TS_ITR11 \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | \
+ TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
+#define TIM_TS_TI1F_ED \
+ TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 \
+ (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF \
+ (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | \
+ TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED \
+ TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED \
+ TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING \
+ TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger \
+ sources */
+#define TIM_TRIGGERPOLARITY_FALLING \
+ TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger \
+ sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE \
+ TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger \
+ sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 \
+ TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 \
+ TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture \
+ performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 \
+ TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture \
+ performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 \
+ TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture \
+ performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 \
+ 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION \
+ TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 \
+ input (XOR combination) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER \
+ 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + \
+ TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS \
+ 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS \
+ 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS \
+ 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS \
+ 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS \
+ 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS \
+ 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS \
+ 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS \
+ 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS \
+ 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS \
+ 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS \
+ 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS \
+ 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS \
+ 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS \
+ 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS \
+ 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS \
+ 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS \
+ 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_19TRANSFERS \
+ 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_20TRANSFERS \
+ 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_21TRANSFERS \
+ 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_22TRANSFERS \
+ 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_23TRANSFERS \
+ 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_24TRANSFERS \
+ 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_25TRANSFERS \
+ 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_26TRANSFERS \
+ 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 \
+ + TIMx_DCR.DBA */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE \
+ ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests \
+ */
+#define TIM_DMA_ID_CC1 \
+ ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 \
+ DMA requests */
+#define TIM_DMA_ID_CC2 \
+ ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 \
+ DMA requests */
+#define TIM_DMA_ID_CC3 \
+ ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 \
+ DMA requests */
+#define TIM_DMA_ID_CC4 \
+ ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 \
+ DMA requests */
+#define TIM_DMA_ID_COMMUTATION \
+ ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA \
+ requests */
+#define TIM_DMA_ID_TRIGGER \
+ ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA \
+ requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE \
+ 0x00000000U /*!< Input or output channel is disabled \
+ */
+#define TIM_CCxN_ENABLE \
+ 0x00000004U /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE \
+ 0x00000000U /*!< Complementary output channel is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_System TIM Break System
+ * @{
+ */
+#define TIM_BREAK_SYSTEM_ECC \
+ SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break \
+ Input of TIM1/8/15/16/17/20 */
+#define TIM_BREAK_SYSTEM_PVD \
+ SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with \
+ TIM1/8/15/16/17/20 Break Input and also the PVDE and \
+ PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR \
+ SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with \
+ Break Input of TIM1/8/15/16/17/20 */
+#define TIM_BREAK_SYSTEM_LOCKUP \
+ SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with \
+ Break Input of TIM1/8/15/16/17/20 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+ } while (0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ } while (0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->BDTR |= (TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while (0)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the
+ * CCx and CCxN channels have been disabled
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while (0)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief Enable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief Disable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief Enable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) \
+ ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) \
+ ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief Check whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @arg TIM_FLAG_IDX: Index interrupt flag
+ * @arg TIM_FLAG_DIR: Direction change interrupt flag
+ * @arg TIM_FLAG_IERR: Index error interrupt flag
+ * @arg TIM_FLAG_TERR: Transition error interrupt flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified TIM interrupt flag.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @arg TIM_FLAG_IDX: Index interrupt flag
+ * @arg TIM_FLAG_DIR: Direction change interrupt flag
+ * @arg TIM_FLAG_IERR: Index error interrupt flag
+ * @arg TIM_FLAG_TERR: Transition error interrupt flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Check whether the specified TIM interrupt source is enabled or not.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) \
+ ? SET \
+ : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @arg TIM_IT_IDX: Index interrupt
+ * @arg TIM_IT_DIR: Direction change interrupt
+ * @arg TIM_IT_IERR: Index error interrupt
+ * @arg TIM_IT_TERR: Transition error interrupt
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
+ ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the
+timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition
+signalled by the UIFCPY flag to be read
+ * in an atomic way.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Get update interrupt flag (UIF) copy status.
+ * @param __COUNTER__ Counter value.
+ * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+ */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__) \
+ (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.
+ * @param __HANDLE__ TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as
+ * downcounter)
+ * @note This macro is particularly useful to get the counting mode when the
+ * timer operates in Center-aligned mode or Encoder mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Set the TIM Prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the Prescaler new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) \
+ ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+ * @brief Set the TIM Counter Register value on runtime.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not,
+ * this may affect the counter range in case of 32 bits counter TIM instance.
+ * Bit 31 of CNT can be enabled/disabled using
+ * __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) \
+ ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Get the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Set the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do { \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while (0)
+
+/**
+ * @brief Get the TIM Autoreload Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Set the TIM Clock Division value on runtime without calling another
+ * time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do { \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while (0)
+
+/**
+ * @brief Get the TIM Clock Division value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Set the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do { \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while (0)
+
+/**
+ * @brief Get the TIM Input Capture prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) \
+ : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+ * @brief Set the TIM Capture Compare Register value on runtime without calling
+ * another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) \
+ ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) \
+ ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) \
+ : ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+ * @brief Get the TIM Capture Compare Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) \
+ : ((__HANDLE__)->Instance->CCR6))
+
+/**
+ * @brief Set the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) \
+ ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) \
+ ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) \
+ : ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Reset the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) \
+ ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) \
+ ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) \
+ : ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) \
+ ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) \
+ ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) \
+ : ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) \
+ ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) \
+ ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) \
+ : ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 |= TIM_CR1_URS)
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_URS)
+
+/**
+ * @brief Set the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__ Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do { \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ } while (0)
+
+/** @brief Select the Capture/compare DMA request source.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __CCDMA__ specifies Capture/compare DMA request source
+ * This parameter can be one of the following values:
+ * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on
+ * Capture/Compare event
+ * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update
+ * event
+ * @retval None
+ */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
+ MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK \
+ ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK \
+ ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | \
+ TIM_CCER_CC4NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#if defined(COMP5) && defined(COMP6) && defined(COMP7)
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) \
+ (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
+#else /* COMP5 && COMP6 && COMP7 */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) \
+ (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
+#endif /* COMP5 && COMP6 && COMP7 */
+
+#define IS_TIM_DMA_BASE(__BASE__) \
+ (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6) || ((__BASE__) == TIM_DMABASE_AF1) || \
+ ((__BASE__) == TIM_DMABASE_AF2) || ((__BASE__) == TIM_DMABASE_TISEL) || \
+ ((__BASE__) == TIM_DMABASE_DTR2) || ((__BASE__) == TIM_DMABASE_ECR) || \
+ ((__BASE__) == TIM_DMABASE_OR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) \
+ ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && \
+ ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__) \
+ (((__MODE__) == TIM_COUNTERMODE_UP) || \
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__) \
+ (((__MODE__) == TIM_UIFREMAP_DISABLE) || ((__MODE__) == TIM_UIFREMAP_ENABLE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) \
+ (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) \
+ (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__) \
+ (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__) \
+ (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__) \
+ (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) \
+ (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) \
+ (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_5)) && ((__CHANNEL__) != (TIM_CHANNEL_6)))
+
+#define IS_TIM_OPM_MODE(__MODE__) \
+ (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__) \
+ (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI12) || \
+ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \
+ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \
+ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \
+ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
+ ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) \
+ ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && \
+ ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || \
+ ((__CHANNEL__) == TIM_CHANNEL_5) || ((__CHANNEL__) == TIM_CHANNEL_6) || \
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
+ ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) \
+ ? ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) \
+ ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) \
+ : (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) \
+ : ((__PERIOD__) > 0U))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#if defined(TIM5) && defined(TIM20)
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#elif defined(TIM5)
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#elif defined(TIM20)
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#else
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) \
+ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#endif /* TIM5 && TIM20 */
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__) \
+ (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__) \
+ (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) \
+ (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+#define IS_TIM_BREAK_STATE(__STATE__) \
+ (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) \
+ (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+#define IS_TIM_BREAK2_STATE(__STATE__) \
+ (((__STATE__) == TIM_BREAK2_ENABLE) || ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) \
+ (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) \
+ (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) \
+ ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || \
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF) || \
+ ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_TRGO2_RESET) || ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO2_UPDATE) || ((__SOURCE__) == TIM_TRGO2_OC1) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1REF) || ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF) || ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__) \
+ (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) \
+ (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+
+#define IS_TIM_PWM_MODE(__MODE__) \
+ (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__) \
+ (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
+ ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
+ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) \
+ (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__) \
+ (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) \
+ (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__) \
+ (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) \
+ (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) \
+ : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \
+ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
+ : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) \
+ : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] \
+ : (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_4) \
+ ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_5) \
+ ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) \
+ : ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
+ do { \
+ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
+ } while (0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \
+ : (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) \
+ ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_2) \
+ ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
+ : ((__CHANNEL__) == TIM_CHANNEL_3) \
+ ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \
+ : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
+ do { \
+ (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
+ } while (0)
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32g4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim,
+ const uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ * @{
+ */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, const uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ * @{
+ */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, const uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ * @{
+ */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ * @{
+ */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim,
+ uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ * @{
+ */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,
+ const TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ * @{
+ */
+/* Interrupt Handler functions ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ const TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ const TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim,
+ const TIM_IC_InitTypeDef *sConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(
+ TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(
+ TIM_HandleTypeDef *htim,
+ const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(
+ TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim,
+ uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(
+ TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(
+ TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ const uint32_t *BurstBuffer,
+ uint32_t BurstLength,
+ uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim,
+ uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer,
+ uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer,
+ uint32_t BurstLength,
+ uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim,
+ uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim,
+ uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim,
+ HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(
+ TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions
+ * ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(
+ const TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(
+ const TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_TIM_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h
index 0158d64..7764536 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h
@@ -1,2197 +1,2192 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_TIM_EX_H
-#define STM32G4xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
- * @{
- */
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct {
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref
- TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0
- and Max_Data = 0xF */
-
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into
- the Capture Compare Register. This parameter
- can be a number between Min_Data = 0x0000 and
- Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-
-/**
- * @brief TIM Break/Break2 input configuration
- */
-typedef struct {
- uint32_t Source; /*!< Specifies the source of the timer break input.
- This parameter can be a value of @ref
- TIMEx_Break_Input_Source */
- uint32_t Enable; /*!< Specifies whether or not the break input source is
- enabled. This parameter can be a value of @ref
- TIMEx_Break_Input_Source_Enable */
- uint32_t Polarity; /*!< Specifies the break input source polarity.
- This parameter can be a value of @ref
- TIMEx_Break_Input_Source_Polarity */
-} TIMEx_BreakInputConfigTypeDef;
-
-/**
- * @brief TIM Encoder index configuration
- */
-typedef struct {
- uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a
- value of @ref TIMEx_Encoder_Index_Polarity */
-
- uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a
- value of @ref TIMEx_Encoder_Index_Prescaler */
-
- uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number
- between Min_Data = 0x0 and Max_Data = 0xF */
-
- FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder
- first index is enabled.This parameter
- value can be ENABLE or DISABLE. */
-
- uint32_t Position; /*!< Specifies in which AB input configuration the index
- event resets the counter.This parameter can be a value
- of @ref TIMEx_Encoder_Index_Position */
-
- uint32_t Direction; /*!< Specifies in which counter direction the index event
- resets the counter.This parameter can be a value of
- @ref TIMEx_Encoder_Index_Direction */
-
-} TIMEx_EncoderIndexConfigTypeDef;
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
- * @{
- */
-#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM1_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM1_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM1_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM1_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM1_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM1_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM1_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM1_ETR_ADC1_AWD1 \
- TIM1_AF1_ETRSEL_3 /* !< ADC1 analog watchdog 1 \
- */
-#define TIM_TIM1_ETR_ADC1_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC1 analog watchdog 2 */
-#define TIM_TIM1_ETR_ADC1_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC1 analog watchdog 3 */
-#if defined(ADC4)
-#define TIM_TIM1_ETR_ADC4_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 1 */
-#define TIM_TIM1_ETR_ADC4_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC4 analog watchdog 2 */
-#define TIM_TIM1_ETR_ADC4_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 3 */
-#endif /* ADC4 */
-
-#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM2_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM2_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM2_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM2_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM2_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM2_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM2_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM2_ETR_TIM3_ETR \
- TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */
-#define TIM_TIM2_ETR_TIM4_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */
-#if defined(TIM5)
-#define TIM_TIM2_ETR_TIM5_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to TIM5 ETR */
-#endif /* TIM5 */
-#define TIM_TIM2_ETR_LSE \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to LSE */
-
-#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM3_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM3_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM3_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM3_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM3_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM3_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM3_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM3_ETR_TIM2_ETR \
- TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */
-#define TIM_TIM3_ETR_TIM4_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */
-#define TIM_TIM3_ETR_ADC2_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 1 */
-#define TIM_TIM3_ETR_ADC2_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC2 analog watchdog 2 */
-#define TIM_TIM3_ETR_ADC2_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 3 */
-
-#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM4_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM4_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM4_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM4_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM4_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM4_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM4_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM4_ETR_TIM3_ETR \
- TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */
-#if defined(TIM5)
-#define TIM_TIM4_ETR_TIM5_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM5 ETR */
-#endif /* TIM5 */
-
-#if defined(TIM5)
-#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM5_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM5_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM5_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM5_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM5_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM5_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM5_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM5_ETR_TIM2_ETR \
- TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */
-#define TIM_TIM5_ETR_TIM3_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM3 ETR */
-#endif /* TIM5 */
-
-#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM8_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM8_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM8_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM8_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM8_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM8_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM8_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM8_ETR_ADC2_AWD1 \
- TIM1_AF1_ETRSEL_3 /* !< ADC2 analog watchdog 1 \
- */
-#define TIM_TIM8_ETR_ADC2_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 2 */
-#define TIM_TIM8_ETR_ADC2_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC2 analog watchdog 3 */
-#if defined(ADC3)
-#define TIM_TIM8_ETR_ADC3_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 1 */
-#define TIM_TIM8_ETR_ADC3_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC3 analog watchdog 2 */
-#define TIM_TIM8_ETR_ADC3_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 3 */
-#endif /* ADC3 */
-
-#if defined(TIM20)
-#define TIM_TIM20_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
-#define TIM_TIM20_ETR_COMP1 \
- TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
-#define TIM_TIM20_ETR_COMP2 \
- TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
-#define TIM_TIM20_ETR_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
-#define TIM_TIM20_ETR_COMP4 \
- TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM20_ETR_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM20_ETR_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM20_ETR_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define TIM_TIM20_ETR_ADC3_AWD1 \
- TIM1_AF1_ETRSEL_3 /* !< ADC3 analog watchdog 1 */
-#define TIM_TIM20_ETR_ADC3_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 2 */
-#define TIM_TIM20_ETR_ADC3_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC3 analog watchdog 3 */
-#if defined(ADC5)
-#define TIM_TIM20_ETR_ADC5_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */
-#define TIM_TIM20_ETR_ADC5_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC5 analog watchdog 2 */
-#define TIM_TIM20_ETR_ADC5_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */
-#endif /* ADC5 */
-#endif /* TIM20 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input TIM Extended Break input
- * @{
- */
-#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
-#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_BKIN \
- 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
-#define TIM_BREAKINPUTSOURCE_COMP1 \
- 0x00000002U /* !< The COMP1 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP2 \
- 0x00000004U /* !< The COMP2 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP3 \
- 0x00000008U /* !< The COMP3 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP4 \
- 0x00000010U /* !< The COMP4 output is connected to the break input */
-#if defined(COMP5)
-#define TIM_BREAKINPUTSOURCE_COMP5 \
- 0x00000020U /* !< The COMP5 output is connected to the break input */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_BREAKINPUTSOURCE_COMP6 \
- 0x00000040U /* !< The COMP6 output is connected to the break input */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_BREAKINPUTSOURCE_COMP7 \
- 0x00000080U /* !< The COMP7 output is connected to the break input */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source
- * enabling
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_DISABLE \
- 0x00000000U /*!< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE \
- 0x00000001U /*!< Break input source is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input
- * polarity
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW \
- 0x00000001U /*!< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH \
- 0x00000000U /*!< Break input source is active_high */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
- * @{
- */
-#define TIM_TIM1_TI1_GPIO \
- 0x00000000U /*!< TIM1 input 1 is connected to GPIO \
- */
-#define TIM_TIM1_TI1_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
-#define TIM_TIM1_TI1_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
-#define TIM_TIM1_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
-#define TIM_TIM1_TI1_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
-
-#define TIM_TIM2_TI1_GPIO \
- 0x00000000U /*!< TIM2 input 1 is connected to GPIO \
- */
-#define TIM_TIM2_TI1_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
-#define TIM_TIM2_TI1_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
-#define TIM_TIM2_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
-#define TIM_TIM2_TI1_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM2_TI1_COMP5 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-
-#define TIM_TIM2_TI2_GPIO \
- 0x00000000U /*!< TIM2 input 2 is connected to GPIO \
- */
-#define TIM_TIM2_TI2_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
-#define TIM_TIM2_TI2_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
-#define TIM_TIM2_TI2_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
-#define TIM_TIM2_TI2_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
-#if defined(COMP6)
-#define TIM_TIM2_TI2_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-
-#define TIM_TIM2_TI3_GPIO \
- 0x00000000U /*!< TIM2 input 3 is connected to GPIO \
- */
-#define TIM_TIM2_TI3_COMP4 \
- TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
-
-#define TIM_TIM2_TI4_GPIO \
- 0x00000000U /*!< TIM2 input 4 is connected to GPIO \
- */
-#define TIM_TIM2_TI4_COMP1 \
- TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
-#define TIM_TIM2_TI4_COMP2 \
- TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
-
-#define TIM_TIM3_TI1_GPIO \
- 0x00000000U /*!< TIM3 input 1 is connected to GPIO \
- */
-#define TIM_TIM3_TI1_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
-#define TIM_TIM3_TI1_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
-#define TIM_TIM3_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
-#define TIM_TIM3_TI1_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM3_TI1_COMP5 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM3_TI1_COMP6 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM3_TI1_COMP7 \
- (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM3_TI2_GPIO \
- 0x00000000U /*!< TIM3 input 2 is connected to GPIO \
- */
-#define TIM_TIM3_TI2_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
-#define TIM_TIM3_TI2_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
-#define TIM_TIM3_TI2_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
-#define TIM_TIM3_TI2_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM3_TI2_COMP5 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM3_TI2_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM3_TI2_COMP7 \
- (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM3_TI3_GPIO \
- 0x00000000U /*!< TIM3 input 3 is connected to GPIO \
- */
-#define TIM_TIM3_TI3_COMP3 \
- TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
-
-#define TIM_TIM4_TI1_GPIO \
- 0x00000000U /*!< TIM4 input 1 is connected to GPIO \
- */
-#define TIM_TIM4_TI1_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
-#define TIM_TIM4_TI1_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
-#define TIM_TIM4_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
-#define TIM_TIM4_TI1_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM4_TI1_COMP5 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM4_TI1_COMP6 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM4_TI1_COMP7 \
- (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM4_TI2_GPIO \
- 0x00000000U /*!< TIM4 input 2 is connected to GPIO \
- */
-#define TIM_TIM4_TI2_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
-#define TIM_TIM4_TI2_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
-#define TIM_TIM4_TI2_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
-#define TIM_TIM4_TI2_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM4_TI2_COMP5 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM4_TI2_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM4_TI2_COMP7 \
- (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM4_TI3_GPIO \
- 0x00000000U /*!< TIM4 input 3 is connected to GPIO \
- */
-#if defined(COMP5)
-#define TIM_TIM4_TI3_COMP5 \
- TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
-#endif /* COMP5 */
-
-#define TIM_TIM4_TI4_GPIO \
- 0x00000000U /*!< TIM4 input 4 is connected to GPIO \
- */
-#if defined(COMP6)
-#define TIM_TIM4_TI4_COMP6 \
- TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
-#endif /* COMP6 */
-
-#if defined(TIM5)
-#define TIM_TIM5_TI1_GPIO \
- 0x00000000U /*!< TIM5 input 1 is connected to GPIO \
- */
-#define TIM_TIM5_TI1_LSI \
- TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
-#define TIM_TIM5_TI1_LSE \
- TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
-#define TIM_TIM5_TI1_RTC_WK \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
-#define TIM_TIM5_TI1_COMP1 \
- TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
-#define TIM_TIM5_TI1_COMP2 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
-#define TIM_TIM5_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
-#define TIM_TIM5_TI1_COMP4 \
- (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM5_TI1_COMP5 \
- TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM5_TI1_COMP6 \
- (TIM_TISEL_TI1SEL_3 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM5_TI1_COMP7 \
- (TIM_TISEL_TI1SEL_3 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM5_TI2_GPIO \
- 0x00000000U /*!< TIM5 input 2 is connected to GPIO \
- */
-#define TIM_TIM5_TI2_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
-#define TIM_TIM5_TI2_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
-#define TIM_TIM5_TI2_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
-#define TIM_TIM5_TI2_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define TIM_TIM5_TI2_COMP5 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIM_TIM5_TI2_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM5_TI2_COMP7 \
- (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-#endif /* TIM5 */
-
-#define TIM_TIM8_TI1_GPIO \
- 0x00000000U /*!< TIM8 input 1 is connected to GPIO \
- */
-#define TIM_TIM8_TI1_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
-#define TIM_TIM8_TI1_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
-#define TIM_TIM8_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
-#define TIM_TIM8_TI1_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
-
-#define TIM_TIM15_TI1_GPIO \
- 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
-#define TIM_TIM15_TI1_LSE \
- TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
-#define TIM_TIM15_TI1_COMP1 \
- TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
-#define TIM_TIM15_TI1_COMP2 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
-#if defined(COMP5)
-#define TIM_TIM15_TI1_COMP5 \
- TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP7)
-#define TIM_TIM15_TI1_COMP7 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM15_TI2_GPIO \
- 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
-#define TIM_TIM15_TI2_COMP2 \
- TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
-#define TIM_TIM15_TI2_COMP3 \
- TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
-#if defined(COMP6)
-#define TIM_TIM15_TI2_COMP6 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIM_TIM15_TI2_COMP7 \
- TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-
-#define TIM_TIM16_TI1_GPIO \
- 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
-#if defined(COMP6)
-#define TIM_TIM16_TI1_COMP6 \
- TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#define TIM_TIM16_TI1_MCO \
- TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
-#define TIM_TIM16_TI1_HSE_32 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
-#define TIM_TIM16_TI1_RTC_WK \
- TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
-#define TIM_TIM16_TI1_LSE \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
-#define TIM_TIM16_TI1_LSI \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
-
-#define TIM_TIM17_TI1_GPIO \
- 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
-#if defined(COMP5)
-#define TIM_TIM17_TI1_COMP5 \
- TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#define TIM_TIM17_TI1_MCO \
- TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
-#define TIM_TIM17_TI1_HSE_32 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
-#define TIM_TIM17_TI1_RTC_WK \
- TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
-#define TIM_TIM17_TI1_LSE \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
-#define TIM_TIM17_TI1_LSI \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
-
-#if defined(TIM20)
-#define TIM_TIM20_TI1_GPIO \
- 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
-#define TIM_TIM20_TI1_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
-#define TIM_TIM20_TI1_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
-#define TIM_TIM20_TI1_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
-#define TIM_TIM20_TI1_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
-#endif /* TIM20 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload
- * enabling
- * @{
- */
-#define TIM_SMS_PRELOAD_SOURCE_UPDATE \
- 0x00000000U /*!< Prelaod of SMS bitfield is disabled */
-#define TIM_SMS_PRELOAD_SOURCE_INDEX \
- TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
- * @{
- */
-#define TIM_ENCODERINDEX_POSITION_00 \
- 0x00000000U /*!< Encoder index position is AB=00 */
-#define TIM_ENCODERINDEX_POSITION_01 \
- TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */
-#define TIM_ENCODERINDEX_POSITION_10 \
- TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */
-#define TIM_ENCODERINDEX_POSITION_11 \
- (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */
-#define TIM_ENCODERINDEX_POSITION_0 \
- 0x00000000U /*!< In directional clock mode or clock plus direction mode, \
- index resets the counter when clock is 0 */
-#define TIM_ENCODERINDEX_POSITION_1 \
- TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, \
- index resets the counter when clock is 1 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
- * @{
- */
-#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN \
- 0x00000000U /*!< Index resets the counter whatever the direction */
-#define TIM_ENCODERINDEX_DIRECTION_UP \
- TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
-#define TIM_ENCODERINDEX_DIRECTION_DOWN \
- TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
- * @{
- */
-#define TIM_ENCODERINDEX_POLARITY_INVERTED \
- TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_ENCODERINDEX_POLARITY_NONINVERTED \
- TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index
- * prescaler
- * @{
- */
-#define TIM_ENCODERINDEX_PRESCALER_DIV1 \
- TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_ENCODERINDEX_PRESCALER_DIV2 \
- TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed \
- once every 2 events. */
-#define TIM_ENCODERINDEX_PRESCALER_DIV4 \
- TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed \
- once every 4 events. */
-#define TIM_ENCODERINDEX_PRESCALER_DIV8 \
- TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed \
- once every 8 events. */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
- * @{
- */
-
-/**
- * @brief HELPER macro calculating the prescaler value to achieve the required
- * counter clock frequency.
- * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CNTCLK__ counter clock frequency (in Hz)
- * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
- */
-#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__) / (__CNTCLK__)-1U) \
- : 0U
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the
- * required output signal frequency.
- * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __FREQ__ output signal frequency (in Hz)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
- ? ((__TIMCLK__) / ((__FREQ__) * ((__PSC__) + 1U)) - 1U) \
- : 0U
-
-/**
- * @brief HELPER macro calculating the auto-reload value, with dithering
- * feature enabled, to achieve the required output signal frequency.
- * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
- * @note This macro should be used only if dithering is already enabled
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __FREQ__ output signal frequency (in Hz)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
- */
-#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
- ? (uint32_t)(((uint64_t)(__TIMCLK__) * 16 / \
- ((__FREQ__) * ((__PSC__) + 1U)) - \
- 16U)) \
- : 0U
-
-/**
- * @brief HELPER macro calculating the compare value required to achieve the
- * required timer output compare active/inactive delay.
- * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @retval Compare value (between Min_Data=0 and Max_Data=65535)
- */
-#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \
- ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) / \
- ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
- * @brief HELPER macro calculating the compare value, with dithering feature
- * enabled, to achieve the required timer output compare active/inactive delay.
- * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
- * @note This macro should be used only if dithering is already enabled
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @retval Compare value (between Min_Data=0 and Max_Data=65519)
- */
-#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
- ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) / \
- ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the
- * required pulse duration (when the timer operates in one pulse mode).
- * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @param __PULSE__ pulse duration (in us)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, \
- __PULSE__) \
- ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) + \
- __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
- * @brief HELPER macro calculating the auto-reload value, with dithering
- * feature enabled, to achieve the required pulse duration (when the timer
- * operates in one pulse mode).
- * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
- * @note This macro should be used only if dithering is already enabled
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @param __PULSE__ pulse duration (in us)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
- */
-#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, \
- __PULSE__) \
- ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), \
- (__PULSE__)) + \
- __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), \
- (__DELAY__))))
-
-/**
- * @}
- */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
- * @{
- */
-#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
-
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \
- (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
- ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-
-#if defined(COMP5) && defined(COMP6) && defined(COMP7)
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7))
-
-#else
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4))
-
-#endif /* COMP5 && COMP6 && COMP7 */
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
- (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
- ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
-
-#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
-
-#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
- (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
-
-#if defined(TIM5) && defined(TIM20)
-#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
- ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
- (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
- (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
- (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
- (((INSTANCE) == TIM5) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
- (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
- (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
- (((INSTANCE) == TIM20) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))))
-
-#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_ITR11))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10))) || \
- (((INSTANCE) == TIM5) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10))) || \
- (((INSTANCE) == TIM20) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR10))))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM5) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM20) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_NONE))))
-
-#elif defined(TIM5)
-#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
- ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
- (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM5) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
-
-#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR11))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM5) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8))))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM5) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))))
-#elif defined(TIM20)
-#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
- ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
- (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
- (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
- (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
- (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
- (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
- (((INSTANCE) == TIM20) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
-
-#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR11))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9))) || \
- (((INSTANCE) == TIM20) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM20) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_NONE))))
-#else
-#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
- ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
- (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
- (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
-
-#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR11))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
- ((((INSTANCE) == TIM1) && \
- (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM2) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM3) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM4) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM8) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
- (((INSTANCE) == TIM15) && \
- (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))))
-
-#endif /* TIM5 && TIM20 */
-#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \
- (IS_TIM_OC_MODE(__MODE__) && \
- ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
- ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
- ? (((__CHANNEL__) == TIM_CHANNEL_3) || \
- ((__CHANNEL__) == TIM_CHANNEL_4)) \
- : (1 == 1)))
-
-#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))
-
-#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE)
-
-#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU)
-
-#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) \
- ((__PRESCALER__) <= 0x7U)
-
-#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) || \
- ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
-
-#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
-
-#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) \
- (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
-
-#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL)
-
-#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) \
- (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
- ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
- ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
- ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
- ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \
- ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
-
-#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) \
- (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
- ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \
- ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
-
-/**
- * @}
- */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor
- * functions
- * @brief Timer Hall Sensor functions
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(
- TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t *pData,
- uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary
- * Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM
- * functions
- * @brief Timer Complementary PWM functions
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One
- * Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control
- * functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim,
- uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim,
- uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim,
- uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(
- TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(
- TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(
- TIM_HandleTypeDef *htim, uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim,
- uint32_t Channels);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim,
- uint32_t Remap);
-HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim,
- uint32_t TISelection, uint32_t Channel);
-
-HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim,
- uint32_t BreakInput);
-HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim,
- uint32_t BreakInput);
-HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(
- TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth);
-HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim,
- uint32_t Source);
-HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim,
- uint32_t Deadtime);
-HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(
- TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
-HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(
- TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(
- TIM_HandleTypeDef *htim,
- TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
-HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- * @{
- */
-/* Extended Callback **********************************************************/
-void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State
- * functions
- * @brief Extended Peripheral State functions
- * @{
- */
-/* Extended Peripheral State functions ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,
- uint32_t ChannelN);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
- * @{
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_TIM_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_TIM_EX_H
+#define STM32G4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct {
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref
+ TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0
+ and Max_Data = 0xF */
+
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into
+ the Capture Compare Register. This parameter
+ can be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Break/Break2 input configuration
+ */
+typedef struct {
+ uint32_t Source; /*!< Specifies the source of the timer break input.
+ This parameter can be a value of @ref
+ TIMEx_Break_Input_Source */
+ uint32_t Enable; /*!< Specifies whether or not the break input source is
+ enabled. This parameter can be a value of @ref
+ TIMEx_Break_Input_Source_Enable */
+ uint32_t Polarity; /*!< Specifies the break input source polarity.
+ This parameter can be a value of @ref
+ TIMEx_Break_Input_Source_Polarity */
+} TIMEx_BreakInputConfigTypeDef;
+
+/**
+ * @brief TIM Encoder index configuration
+ */
+typedef struct {
+ uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a
+ value of @ref TIMEx_Encoder_Index_Polarity */
+
+ uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a
+ value of @ref TIMEx_Encoder_Index_Prescaler */
+
+ uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number
+ between Min_Data = 0x0 and Max_Data = 0xF */
+
+ FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder
+ first index is enabled.This parameter
+ value can be ENABLE or DISABLE. */
+
+ uint32_t Position; /*!< Specifies in which AB input configuration the index
+ event resets the counter.This parameter can be a value
+ of @ref TIMEx_Encoder_Index_Position */
+
+ uint32_t Direction; /*!< Specifies in which counter direction the index event
+ resets the counter.This parameter can be a value of
+ @ref TIMEx_Encoder_Index_Direction */
+
+} TIMEx_EncoderIndexConfigTypeDef;
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+ * @{
+ */
+#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM1_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM1_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM1_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM1_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM1_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM1_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM1_ETR_ADC1_AWD1 \
+ TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 \
+ */
+#define TIM_TIM1_ETR_ADC1_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
+#define TIM_TIM1_ETR_ADC1_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
+#if defined(ADC4)
+#define TIM_TIM1_ETR_ADC4_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
+#define TIM_TIM1_ETR_ADC4_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
+#define TIM_TIM1_ETR_ADC4_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
+#endif /* ADC4 */
+
+#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM2_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM2_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM2_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM2_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM2_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM2_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM2_ETR_TIM3_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
+#define TIM_TIM2_ETR_TIM4_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
+#if defined(TIM5)
+#define TIM_TIM2_ETR_TIM5_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+#define TIM_TIM2_ETR_LSE \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
+
+#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM3_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM3_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM3_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM3_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM3_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM3_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM3_ETR_TIM2_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
+#define TIM_TIM3_ETR_TIM4_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
+#define TIM_TIM3_ETR_ADC2_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
+#define TIM_TIM3_ETR_ADC2_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
+#define TIM_TIM3_ETR_ADC2_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
+
+#define TIM_TIM4_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM4_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM4_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM4_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM4_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM4_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM4_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM4_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM4_ETR_TIM3_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
+#if defined(TIM5)
+#define TIM_TIM4_ETR_TIM5_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+
+#if defined(TIM5)
+#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM5_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM5_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM5_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM5_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM5_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM5_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM5_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM5_ETR_TIM2_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
+#define TIM_TIM5_ETR_TIM3_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
+#endif /* TIM5 */
+
+#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM8_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM8_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM8_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM8_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM8_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM8_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM8_ETR_ADC2_AWD1 \
+ TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 \
+ */
+#define TIM_TIM8_ETR_ADC2_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
+#define TIM_TIM8_ETR_ADC2_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
+#if defined(ADC3)
+#define TIM_TIM8_ETR_ADC3_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
+#define TIM_TIM8_ETR_ADC3_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
+#define TIM_TIM8_ETR_ADC3_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+
+#if defined(TIM20)
+#define TIM_TIM20_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define TIM_TIM20_ETR_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define TIM_TIM20_ETR_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define TIM_TIM20_ETR_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define TIM_TIM20_ETR_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM20_ETR_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM20_ETR_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM20_ETR_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM20_ETR_ADC3_AWD1 \
+ TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 \
+ */
+#define TIM_TIM20_ETR_ADC3_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
+#define TIM_TIM20_ETR_ADC3_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
+#if defined(ADC5)
+#define TIM_TIM20_ETR_ADC5_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
+#define TIM_TIM20_ETR_ADC5_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
+#define TIM_TIM20_ETR_ADC5_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
+#endif /* ADC5 */
+#endif /* TIM20 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+ * @{
+ */
+#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
+#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_BKIN \
+ 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */
+#define TIM_BREAKINPUTSOURCE_COMP1 \
+ 0x00000002U /*!< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2 \
+ 0x00000004U /*!< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP3 \
+ 0x00000008U /*!< The COMP3 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP4 \
+ 0x00000010U /*!< The COMP4 output is connected to the break input */
+#if defined(COMP5)
+#define TIM_BREAKINPUTSOURCE_COMP5 \
+ 0x00000020U /*!< The COMP5 output is connected to the break input */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_BREAKINPUTSOURCE_COMP6 \
+ 0x00000040U /*!< The COMP6 output is connected to the break input */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_BREAKINPUTSOURCE_COMP7 \
+ 0x00000080U /*!< The COMP7 output is connected to the break input */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source
+ * enabling
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_DISABLE \
+ 0x00000000U /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE \
+ 0x00000001U /*!< Break input source is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input
+ * polarity
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW \
+ 0x00000001U /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH \
+ 0x00000000U /*!< Break input source is active_high */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+ * @{
+ */
+#define TIM_TIM1_TI1_GPIO \
+ 0x00000000U /*!< TIM1 input 1 is connected to GPIO \
+ */
+#define TIM_TIM1_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
+#define TIM_TIM1_TI1_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
+#define TIM_TIM1_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
+#define TIM_TIM1_TI1_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
+
+#define TIM_TIM2_TI1_GPIO \
+ 0x00000000U /*!< TIM2 input 1 is connected to GPIO \
+ */
+#define TIM_TIM2_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
+#define TIM_TIM2_TI1_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
+#define TIM_TIM2_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
+#define TIM_TIM2_TI1_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM2_TI1_COMP5 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+
+#define TIM_TIM2_TI2_GPIO \
+ 0x00000000U /*!< TIM2 input 2 is connected to GPIO \
+ */
+#define TIM_TIM2_TI2_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
+#define TIM_TIM2_TI2_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
+#define TIM_TIM2_TI2_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
+#define TIM_TIM2_TI2_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
+#if defined(COMP6)
+#define TIM_TIM2_TI2_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+
+#define TIM_TIM2_TI3_GPIO \
+ 0x00000000U /*!< TIM2 input 3 is connected to GPIO \
+ */
+#define TIM_TIM2_TI3_COMP4 \
+ TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
+
+#define TIM_TIM2_TI4_GPIO \
+ 0x00000000U /*!< TIM2 input 4 is connected to GPIO \
+ */
+#define TIM_TIM2_TI4_COMP1 \
+ TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
+#define TIM_TIM2_TI4_COMP2 \
+ TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
+
+#define TIM_TIM3_TI1_GPIO \
+ 0x00000000U /*!< TIM3 input 1 is connected to GPIO \
+ */
+#define TIM_TIM3_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
+#define TIM_TIM3_TI1_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
+#define TIM_TIM3_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
+#define TIM_TIM3_TI1_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM3_TI1_COMP5 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM3_TI1_COMP6 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM3_TI1_COMP7 \
+ (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM3_TI2_GPIO \
+ 0x00000000U /*!< TIM3 input 2 is connected to GPIO \
+ */
+#define TIM_TIM3_TI2_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
+#define TIM_TIM3_TI2_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
+#define TIM_TIM3_TI2_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
+#define TIM_TIM3_TI2_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM3_TI2_COMP5 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM3_TI2_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM3_TI2_COMP7 \
+ (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM3_TI3_GPIO \
+ 0x00000000U /*!< TIM3 input 3 is connected to GPIO \
+ */
+#define TIM_TIM3_TI3_COMP3 \
+ TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
+
+#define TIM_TIM4_TI1_GPIO \
+ 0x00000000U /*!< TIM4 input 1 is connected to GPIO \
+ */
+#define TIM_TIM4_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
+#define TIM_TIM4_TI1_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
+#define TIM_TIM4_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
+#define TIM_TIM4_TI1_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM4_TI1_COMP5 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM4_TI1_COMP6 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM4_TI1_COMP7 \
+ (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM4_TI2_GPIO \
+ 0x00000000U /*!< TIM4 input 2 is connected to GPIO \
+ */
+#define TIM_TIM4_TI2_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
+#define TIM_TIM4_TI2_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
+#define TIM_TIM4_TI2_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
+#define TIM_TIM4_TI2_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM4_TI2_COMP5 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM4_TI2_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM4_TI2_COMP7 \
+ (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM4_TI3_GPIO \
+ 0x00000000U /*!< TIM4 input 3 is connected to GPIO \
+ */
+#if defined(COMP5)
+#define TIM_TIM4_TI3_COMP5 \
+ TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
+#endif /* COMP5 */
+
+#define TIM_TIM4_TI4_GPIO \
+ 0x00000000U /*!< TIM4 input 4 is connected to GPIO \
+ */
+#if defined(COMP6)
+#define TIM_TIM4_TI4_COMP6 \
+ TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
+#endif /* COMP6 */
+
+#if defined(TIM5)
+#define TIM_TIM5_TI1_GPIO \
+ 0x00000000U /*!< TIM5 input 1 is connected to GPIO \
+ */
+#define TIM_TIM5_TI1_LSI \
+ TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
+#define TIM_TIM5_TI1_LSE \
+ TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
+#define TIM_TIM5_TI1_RTC_WK \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
+#define TIM_TIM5_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
+#define TIM_TIM5_TI1_COMP2 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
+#define TIM_TIM5_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
+#define TIM_TIM5_TI1_COMP4 \
+ (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM5_TI1_COMP5 \
+ TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM5_TI1_COMP6 \
+ (TIM_TISEL_TI1SEL_3 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM5_TI1_COMP7 \
+ (TIM_TISEL_TI1SEL_3 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM5_TI2_GPIO \
+ 0x00000000U /*!< TIM5 input 2 is connected to GPIO \
+ */
+#define TIM_TIM5_TI2_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
+#define TIM_TIM5_TI2_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
+#define TIM_TIM5_TI2_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
+#define TIM_TIM5_TI2_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM5_TI2_COMP5 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM5_TI2_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM5_TI2_COMP7 \
+ (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+#endif /* TIM5 */
+
+#define TIM_TIM8_TI1_GPIO \
+ 0x00000000U /*!< TIM8 input 1 is connected to GPIO \
+ */
+#define TIM_TIM8_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
+#define TIM_TIM8_TI1_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
+#define TIM_TIM8_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
+#define TIM_TIM8_TI1_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
+
+#define TIM_TIM15_TI1_GPIO \
+ 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
+#define TIM_TIM15_TI1_LSE \
+ TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
+#define TIM_TIM15_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
+#define TIM_TIM15_TI1_COMP2 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
+#if defined(COMP5)
+#define TIM_TIM15_TI1_COMP5 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP7)
+#define TIM_TIM15_TI1_COMP7 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM15_TI2_GPIO \
+ 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
+#define TIM_TIM15_TI2_COMP2 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
+#define TIM_TIM15_TI2_COMP3 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
+#if defined(COMP6)
+#define TIM_TIM15_TI2_COMP6 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM15_TI2_COMP7 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM16_TI1_GPIO \
+ 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
+#if defined(COMP6)
+#define TIM_TIM16_TI1_COMP6 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#define TIM_TIM16_TI1_MCO \
+ TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
+#define TIM_TIM16_TI1_HSE_32 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
+#define TIM_TIM16_TI1_RTC_WK \
+ TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
+#define TIM_TIM16_TI1_LSE \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
+#define TIM_TIM16_TI1_LSI \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
+
+#define TIM_TIM17_TI1_GPIO \
+ 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
+#if defined(COMP5)
+#define TIM_TIM17_TI1_COMP5 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#define TIM_TIM17_TI1_MCO \
+ TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
+#define TIM_TIM17_TI1_HSE_32 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
+#define TIM_TIM17_TI1_RTC_WK \
+ TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
+#define TIM_TIM17_TI1_LSE \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
+#define TIM_TIM17_TI1_LSI \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
+
+#if defined(TIM20)
+#define TIM_TIM20_TI1_GPIO \
+ 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
+#define TIM_TIM20_TI1_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
+#define TIM_TIM20_TI1_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
+#define TIM_TIM20_TI1_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
+#define TIM_TIM20_TI1_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
+#endif /* TIM20 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload
+ * enabling
+ * @{
+ */
+#define TIM_SMS_PRELOAD_SOURCE_UPDATE \
+ 0x00000000U /*!< Prelaod of SMS bitfield is disabled */
+#define TIM_SMS_PRELOAD_SOURCE_INDEX \
+ TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
+ * @{
+ */
+#define TIM_ENCODERINDEX_POSITION_00 \
+ 0x00000000U /*!< Encoder index position is AB=00 */
+#define TIM_ENCODERINDEX_POSITION_01 \
+ TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */
+#define TIM_ENCODERINDEX_POSITION_10 \
+ TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */
+#define TIM_ENCODERINDEX_POSITION_11 \
+ (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */
+#define TIM_ENCODERINDEX_POSITION_0 \
+ 0x00000000U /*!< In directional clock mode or clock plus direction mode, \
+ index resets the counter when clock is 0 */
+#define TIM_ENCODERINDEX_POSITION_1 \
+ TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, \
+ index resets the counter when clock is 1 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
+ * @{
+ */
+#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN \
+ 0x00000000U /*!< Index resets the counter whatever the direction */
+#define TIM_ENCODERINDEX_DIRECTION_UP \
+ TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
+#define TIM_ENCODERINDEX_DIRECTION_DOWN \
+ TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
+ * @{
+ */
+#define TIM_ENCODERINDEX_POLARITY_INVERTED \
+ TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_ENCODERINDEX_POLARITY_NONINVERTED \
+ TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index
+ * prescaler
+ * @{
+ */
+#define TIM_ENCODERINDEX_PRESCALER_DIV1 \
+ TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_ENCODERINDEX_PRESCALER_DIV2 \
+ TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed \
+ once every 2 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV4 \
+ TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed \
+ once every 4 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV8 \
+ TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed \
+ once every 8 events. */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required
+ * counter clock frequency.
+ * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__) / (__CNTCLK__)-1U) \
+ : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the
+ * required output signal frequency.
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
+ ? ((__TIMCLK__) / ((__FREQ__) * ((__PSC__) + 1U)) - 1U) \
+ : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering
+ * feature enabled, to achieve the required output signal frequency.
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
+ * @note This macro should be used only if dithering is already enabled
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
+ */
+#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
+ ? (uint32_t)(((uint64_t)(__TIMCLK__) * 16 / \
+ ((__FREQ__) * ((__PSC__) + 1U)) - \
+ 16U)) \
+ : 0U
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the
+ * required timer output compare active/inactive delay.
+ * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) / \
+ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the compare value, with dithering feature
+ * enabled, to achieve the required timer output compare active/inactive delay.
+ * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
+ * @note This macro should be used only if dithering is already enabled
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65519)
+ */
+#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) / \
+ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the
+ * required pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, \
+ __PULSE__) \
+ ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) + \
+ __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering
+ * feature enabled, to achieve the required pulse duration (when the timer
+ * operates in one pulse mode).
+ * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
+ * @note This macro should be used only if dithering is already enabled
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
+ */
+#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, \
+ __PULSE__) \
+ ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), \
+ (__PULSE__)) + \
+ __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), \
+ (__DELAY__))))
+
+/**
+ * @}
+ */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+ * @{
+ */
+#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \
+ (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#if defined(COMP5) && defined(COMP6) && defined(COMP7)
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7))
+
+#else
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4))
+
+#endif /* COMP5 && COMP6 && COMP7 */
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
+ (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
+
+#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
+ (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
+
+#if defined(TIM5) && defined(TIM20)
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+ ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
+ (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
+ (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
+ (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
+ (((INSTANCE) == TIM5) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
+ (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
+ (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) || \
+ (((INSTANCE) == TIM20) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR10))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_ITR11))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR10))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR10))) || \
+ (((INSTANCE) == TIM5) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR10))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR10))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR10))) || \
+ (((INSTANCE) == TIM20) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR10))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_ITR11) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM5) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM20) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR10) || \
+ ((__SELECTION__) == TIM_TS_NONE))))
+
+#elif defined(TIM5)
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+ ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
+ (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM5) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR11))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM5) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR11) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM5) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))))
+#elif defined(TIM20)
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+ ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
+ (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
+ (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
+ (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
+ (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
+ (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) || \
+ (((INSTANCE) == TIM20) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR11))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR9))) || \
+ (((INSTANCE) == TIM20) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_ITR11) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR9) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM20) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_NONE))))
+#else
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+ ((((INSTANCE) == TIM1) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM2) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) || \
+ (((INSTANCE) == TIM3) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM4) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM8) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) || \
+ (((INSTANCE) == TIM15) && (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR11))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF) || \
+ ((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+ ((((INSTANCE) == TIM1) && \
+ (((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM2) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_ITR11) || \
+ ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM3) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM4) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM8) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))) || \
+ (((INSTANCE) == TIM15) && \
+ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || ((__SELECTION__) == TIM_TS_NONE))))
+
+#endif /* TIM5 && TIM20 */
+
+#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \
+ (IS_TIM_OC_MODE(__MODE__) && \
+ ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
+ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
+ ? (((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4)) \
+ : (1 == 1)))
+
+#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) \
+ ((__PRESCALER__) <= 0x7U)
+
+#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) || \
+ ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
+
+#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
+
+#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) \
+ (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
+
+#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL)
+
+#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) \
+ (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \
+ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
+
+#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) \
+ (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
+ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \
+ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
+/**
+ * @}
+ */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor
+ * functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(
+ TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary
+ * Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel,
+ const uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM
+ * functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel,
+ const uint32_t *pData,
+ uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One
+ * Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control
+ * functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim,
+ uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim,
+ uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim,
+ uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(
+ TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(
+ TIM_HandleTypeDef *htim,
+ const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(
+ TIM_HandleTypeDef *htim, uint32_t BreakInput,
+ const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim,
+ uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim,
+ uint32_t Remap);
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim,
+ uint32_t TISelection, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim,
+ uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim,
+ uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(
+ TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth);
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim,
+ uint32_t Source);
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim,
+ uint32_t Deadtime);
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(
+ TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(
+ TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(
+ TIM_HandleTypeDef *htim,
+ TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ * @{
+ */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State
+ * functions
+ * @brief Extended Peripheral State functions
+ * @{
+ */
+/* Extended Peripheral State functions ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(
+ const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(
+ const TIM_HandleTypeDef *htim, uint32_t ChannelN);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
+ * @{
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_TIM_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
index e2960c8..46ecb3c 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
@@ -1,1993 +1,2016 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_uart.h
- * @author MCD Application Team
- * @brief Header file of UART HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_UART_H
-#define STM32G4xx_HAL_UART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
- * @{
- */
-
-/**
- * @brief UART Init Structure definition
- */
-typedef struct {
- uint32_t
- BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate register is computed using the following
- formula: LPUART:
- =======
- Baud Rate Register = ((256 * lpuart_ker_ckpres) /
- ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the
- UART input clock divided by a prescaler UART:
- =====
- - If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((uart_ker_ckpres) /
- ((huart->Init.BaudRate)))
- - If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
- ((huart->Init.BaudRate)))[15:4]
- Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
- ((huart->Init.BaudRate)))[3:0]) >> 1
- where uart_ker_ck_pres is the UART input clock divided by a
- prescaler */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or
- received in a frame. This parameter can be a value of
- @ref UARTEx_Word_Length. */
-
- uint32_t
- StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits. */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is
- inserted at the MSB position of the transmitted data (9th
- bit when the word length is set to 9 data bits; 8th bit
- when the word length is set to 8 data bits). */
-
- uint32_t
- Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or
- disabled. This parameter can be a value of @ref UART_Mode. */
-
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is
- enabled or disabled. This parameter can be a value of
- @ref UART_Hardware_Flow_Control. */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled
- or disabled, to achieve higher speed (up to
- f_PCLK/8). This parameter can be a value of @ref
- UART_Over_Sampling. */
-
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three
- samples' majority vote is selected. Selecting the
- single sample method increases the receiver
- tolerance to clock deviations. This parameter can
- be a value of @ref UART_OneBit_Sampling. */
-
- uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the
- UART clock source. This parameter can be a value
- of @ref UART_ClockPrescaler. */
-
-} UART_InitTypeDef;
-
-/**
- * @brief UART Advanced Features initialization structure definition
- */
-typedef struct {
- uint32_t
- AdvFeatureInit; /*!< Specifies which advanced UART features is
- initialized. Several Advanced Features may be
- initialized at the same time . This parameter can be a
- value of
- @ref UART_Advanced_Features_Initialization_Type. */
-
- uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is
- inverted. This parameter can be a value of @ref
- UART_Tx_Inv. */
-
- uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is
- inverted. This parameter can be a value of @ref
- UART_Rx_Inv. */
-
- uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct
- logic vs negative/inverted logic). This parameter can
- be a value of @ref UART_Data_Inv. */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref UART_Rx_Tx_Swap. */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun
- detection is disabled. This parameter can be a
- value of @ref UART_Overrun_Disable. */
-
- uint32_t
- DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of
- reception error. This parameter can be a value of
- @ref UART_DMA_Disable_on_Rx_Error. */
-
- uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection
- is enabled. This parameter can be a value of
- @ref UART_AutoBaudRate_Enable. */
-
- uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled,
- specifies how the rate detection is carried out.
- This parameter can be a value of @ref
- UART_AutoBaud_Rate_Mode. */
-
- uint32_t
- MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref UART_MSB_First. */
-} UART_AdvFeatureInitTypeDef;
-
-/**
- * @brief HAL UART State definition
- * @note HAL UART State value is a combination of 2 different substates:
- * gState and RxState (see @ref UART_State_Definition).
- * - gState contains UART state information related to global Handle
- * management and also information related to Tx operations. gState value coding
- * follow below described bitmap : b7-b6 Error information 00 : No Error 01 :
- * (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0
- * : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized.
- * HAL UART Init function already called) b4-b3 (not used) xx : Should be set
- * to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy
- * with some configuration or internal operations) b1 (not used) x : Should
- * be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy
- * (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 Peripheral initialization status
- * 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef uint32_t HAL_UART_StateTypeDef;
-
-/**
- * @brief UART clock sources definition
- */
-typedef enum {
- UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-} UART_ClockSourceTypeDef;
-
-/**
- * @brief HAL UART Reception type definition
- * @note HAL UART Reception type value aims to identify which type of Reception
- * is ongoing. It is expected to admit following values :
- * HAL_UART_RECEPTION_STANDARD = 0x00U,
- * HAL_UART_RECEPTION_TOIDLE = 0x01U,
- * HAL_UART_RECEPTION_TORTO = 0x02U,
- * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
- */
-typedef uint32_t HAL_UART_RxTypeTypeDef;
-
-/**
- * @brief UART handle Structure definition
- */
-typedef struct __UART_HandleTypeDef {
- USART_TypeDef *Instance; /*!< UART registers base address */
-
- UART_InitTypeDef Init; /*!< UART communication parameters */
-
- UART_AdvFeatureInitTypeDef
- AdvancedInit; /*!< UART Advanced Features initialization parameters */
-
- const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
-
- uint16_t Mask; /*!< UART Rx RDR register mask */
-
- uint32_t
- FifoMode; /*!< Specifies if the FIFO mode is being used.
- This parameter can be a value of @ref UARTEx_FIFO_mode. */
-
- uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR
- execution */
-
- uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR
- execution */
-
- __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
-
- void (*RxISR)(struct __UART_HandleTypeDef
- *huart); /*!< Function pointer on Rx IRQ handler */
-
- void (*TxISR)(struct __UART_HandleTypeDef
- *huart); /*!< Function pointer on Tx IRQ handler */
-
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_UART_StateTypeDef
- gState; /*!< UART state information related to global Handle management
- and also related to Tx operations. This parameter
- can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO HAL_UART_StateTypeDef
- RxState; /*!< UART state information related to Rx operations. This
- parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< UART Error code */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- void (*TxHalfCpltCallback)(struct __UART_HandleTypeDef
- *huart); /*!< UART Tx Half Complete Callback */
- void (*TxCpltCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
- void (*RxHalfCpltCallback)(struct __UART_HandleTypeDef
- *huart); /*!< UART Rx Half Complete Callback */
- void (*RxCpltCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
- void (*ErrorCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
- void (*AbortCpltCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
- void (*AbortTransmitCpltCallback)(
- struct __UART_HandleTypeDef
- *huart); /*!< UART Abort Transmit Complete Callback */
- void (*AbortReceiveCpltCallback)(
- struct __UART_HandleTypeDef
- *huart); /*!< UART Abort Receive Complete Callback */
- void (*WakeupCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
- void (*RxFifoFullCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
- void (*TxFifoEmptyCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
- void (*RxEventCallback)(struct __UART_HandleTypeDef *huart,
- uint16_t Pos); /*!< UART Reception Event Callback */
-
- void (*MspInitCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
- void (*MspDeInitCallback)(
- struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-} UART_HandleTypeDef;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL UART Callback ID enumeration definition
- */
-typedef enum {
- HAL_UART_TX_HALFCOMPLETE_CB_ID =
- 0x00U, /*!< UART Tx Half Complete Callback ID */
- HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
- HAL_UART_RX_HALFCOMPLETE_CB_ID =
- 0x02U, /*!< UART Rx Half Complete Callback ID */
- HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
- HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
- HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
- HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID =
- 0x06U, /*!< UART Abort Transmit Complete Callback ID */
- HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID =
- 0x07U, /*!< UART Abort Receive Complete Callback ID */
- HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
- HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */
- HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */
-
- HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
- HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
-
-} HAL_UART_CallbackIDTypeDef;
-
-/**
- * @brief HAL UART Callback pointer definition
- */
-typedef void (*pUART_CallbackTypeDef)(
- UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
-typedef void (*pUART_RxEventCallbackTypeDef)(
- struct __UART_HandleTypeDef *huart,
- uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
- * @{
- */
-
-/** @defgroup UART_State_Definition UART State Code Definition
- * @{
- */
-#define HAL_UART_STATE_RESET \
- 0x00000000U /*!< Peripheral is not initialized \
- Value is allowed for gState and RxState */
-#define HAL_UART_STATE_READY \
- 0x00000020U /*!< Peripheral Initialized and ready for use \
- Value is allowed for gState and RxState */
-#define HAL_UART_STATE_BUSY \
- 0x00000024U /*!< an internal process is ongoing \
- Value is allowed for gState only */
-#define HAL_UART_STATE_BUSY_TX \
- 0x00000021U /*!< Data Transmission process is ongoing \
- Value is allowed for gState only */
-#define HAL_UART_STATE_BUSY_RX \
- 0x00000022U /*!< Data Reception process is ongoing \
- Value is allowed for RxState only */
-#define HAL_UART_STATE_BUSY_TX_RX \
- 0x00000023U /*!< Data Transmission and Reception process is ongoing \
- Not to be used for neither gState nor RxState.Value is \
- result of combination (Or) between gState and RxState values \
- */
-#define HAL_UART_STATE_TIMEOUT \
- 0x000000A0U /*!< Timeout state \
- Value is allowed for gState only */
-#define HAL_UART_STATE_ERROR \
- 0x000000E0U /*!< Error \
- Value is allowed for gState only */
-/**
- * @}
- */
-
-/** @defgroup UART_Error_Definition UART Error Definition
- * @{
- */
-#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
-#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define HAL_UART_ERROR_INVALID_CALLBACK \
- (0x00000040U) /*!< Invalid Callback error */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
- * @{
- */
-#define UART_STOPBITS_0_5 \
- USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit \
- */
-#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
-#define UART_STOPBITS_1_5 \
- (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
-#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup UART_Parity UART Parity
- * @{
- */
-#define UART_PARITY_NONE 0x00000000U /*!< No parity */
-#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
-#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
- * @{
- */
-#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
-#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
-#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
-#define UART_HWCONTROL_RTS_CTS \
- (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
-/**
- * @}
- */
-
-/** @defgroup UART_Mode UART Transfer Mode
- * @{
- */
-#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
-#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
-#define UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup UART_State UART State
- * @{
- */
-#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
-#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
- * @{
- */
-#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
- * @{
- */
-#define UART_ONE_BIT_SAMPLE_DISABLE \
- 0x00000000U /*!< One-bit sampling disable \
- */
-#define UART_ONE_BIT_SAMPLE_ENABLE \
- USART_CR3_ONEBIT /*!< One-bit sampling enable */
-/**
- * @}
- */
-
-/** @defgroup UART_ClockPrescaler UART Clock Prescaler
- * @{
- */
-#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
-#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
-#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
-#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
-#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
-#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
-#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
-#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
-#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
-#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
-#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
-#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
-/**
- * @}
- */
-
-/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate
- * Mode
- * @{
- */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT \
- 0x00000000U /*!< Auto Baud rate detection \
- on start bit */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE \
- USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection \
- on falling edge */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME \
- USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection \
- on 0x7F frame detection */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME \
- USART_CR2_ABRMODE /*!< Auto Baud rate detection \
- on 0x55 frame detection */
-/**
- * @}
- */
-
-/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
- * @{
- */
-#define UART_RECEIVER_TIMEOUT_DISABLE \
- 0x00000000U /*!< UART Receiver Timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE \
- USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
-/**
- * @}
- */
-
-/** @defgroup UART_LIN UART Local Interconnection Network mode
- * @{
- */
-#define UART_LIN_DISABLE \
- 0x00000000U /*!< Local Interconnect Network disable \
- */
-#define UART_LIN_ENABLE \
- USART_CR2_LINEN /*!< Local Interconnect Network enable */
-/**
- * @}
- */
-
-/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
- * @{
- */
-#define UART_LINBREAKDETECTLENGTH_10B \
- 0x00000000U /*!< LIN 10-bit break detection length */
-#define UART_LINBREAKDETECTLENGTH_11B \
- USART_CR2_LBDL /*!< LIN 11-bit break detection length */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Tx UART DMA Tx
- * @{
- */
-#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
-#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Rx UART DMA Rx
- * @{
- */
-#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
-#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
- * @{
- */
-#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
-#define UART_HALF_DUPLEX_ENABLE \
- USART_CR3_HDSEL /*!< UART half-duplex enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
- * @{
- */
-#define UART_WAKEUPMETHOD_IDLELINE \
- 0x00000000U /*!< UART wake-up on idle line */
-#define UART_WAKEUPMETHOD_ADDRESSMARK \
- USART_CR1_WAKE /*!< UART wake-up on address mark */
-/**
- * @}
- */
-
-/** @defgroup UART_Request_Parameters UART Request Parameters
- * @{
- */
-#define UART_AUTOBAUD_REQUEST \
- USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST \
- USART_RQR_SBKRQ /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST \
- USART_RQR_MMRQ /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST \
- USART_RQR_RXFRQ /*!< Receive Data flush Request */
-#define UART_TXDATA_FLUSH_REQUEST \
- USART_RQR_TXFRQ /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature
- * Initialization Type
- * @{
- */
-#define UART_ADVFEATURE_NO_INIT \
- 0x00000000U /*!< No advanced feature initialization */
-#define UART_ADVFEATURE_TXINVERT_INIT \
- 0x00000001U /*!< TX pin active level inversion */
-#define UART_ADVFEATURE_RXINVERT_INIT \
- 0x00000002U /*!< RX pin active level inversion */
-#define UART_ADVFEATURE_DATAINVERT_INIT \
- 0x00000004U /*!< Binary data inversion */
-#define UART_ADVFEATURE_SWAP_INIT \
- 0x00000008U /*!< TX/RX pins swap */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT \
- 0x00000010U /*!< RX overrun disable */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT \
- 0x00000020U /*!< DMA disable on Reception Error */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT \
- 0x00000040U /*!< Auto Baud rate detection initialization */
-#define UART_ADVFEATURE_MSBFIRST_INIT \
- 0x00000080U /*!< Most significant bit sent/received first */
-/**
- * @}
- */
-
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
- * @{
- */
-#define UART_ADVFEATURE_TXINV_DISABLE \
- 0x00000000U /*!< TX pin active level inversion disable */
-#define UART_ADVFEATURE_TXINV_ENABLE \
- USART_CR2_TXINV /*!< TX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
- * @{
- */
-#define UART_ADVFEATURE_RXINV_DISABLE \
- 0x00000000U /*!< RX pin active level inversion disable */
-#define UART_ADVFEATURE_RXINV_ENABLE \
- USART_CR2_RXINV /*!< RX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
- * @{
- */
-#define UART_ADVFEATURE_DATAINV_DISABLE \
- 0x00000000U /*!< Binary data inversion disable */
-#define UART_ADVFEATURE_DATAINV_ENABLE \
- USART_CR2_DATAINV /*!< Binary data inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
- * @{
- */
-#define UART_ADVFEATURE_SWAP_DISABLE \
- 0x00000000U /*!< TX/RX pins swap disable \
- */
-#define UART_ADVFEATURE_SWAP_ENABLE \
- USART_CR2_SWAP /*!< TX/RX pins swap enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
- * @{
- */
-#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
-#define UART_ADVFEATURE_OVERRUN_DISABLE \
- USART_CR3_OVRDIS /*!< RX overrun disable */
-/**
- * @}
- */
-
-/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate
- * Enable
- * @{
- */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE \
- 0x00000000U /*!< RX Auto Baud rate detection enable */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE \
- USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable
- * On Rx Error
- * @{
- */
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR \
- 0x00000000U /*!< DMA enable on Reception Error */
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR \
- USART_CR3_DDRE /*!< DMA disable on Reception Error */
-/**
- * @}
- */
-
-/** @defgroup UART_MSB_First UART Advanced Feature MSB First
- * @{
- */
-#define UART_ADVFEATURE_MSBFIRST_DISABLE \
- 0x00000000U /*!< Most significant bit sent/received \
- first disable */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE \
- USART_CR2_MSBFIRST /*!< Most significant bit sent/received \
- first enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_STOPMODE_DISABLE \
- 0x00000000U /*!< UART stop mode disable */
-#define UART_ADVFEATURE_STOPMODE_ENABLE \
- USART_CR1_UESM /*!< UART stop mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_MUTEMODE_DISABLE \
- 0x00000000U /*!< UART mute mode disable */
-#define UART_ADVFEATURE_MUTEMODE_ENABLE \
- USART_CR1_MME /*!< UART mute mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In
- * CR2 Register
- * @{
- */
-#define UART_CR2_ADDRESS_LSB_POS \
- 24U /*!< UART address-matching LSB position in CR2 register */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
- * @{
- */
-#define UART_WAKEUP_ON_ADDRESS \
- 0x00000000U /*!< UART wake-up on address */
-#define UART_WAKEUP_ON_STARTBIT \
- USART_CR3_WUS_1 /*!< UART wake-up on start bit */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY \
- USART_CR3_WUS /*!< UART wake-up on receive data register \
- not empty or RXFIFO is not empty */
-/**
- * @}
- */
-
-/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
- * @{
- */
-#define UART_DE_POLARITY_HIGH \
- 0x00000000U /*!< Driver enable signal is active high */
-#define UART_DE_POLARITY_LOW \
- USART_CR3_DEP /*!< Driver enable signal is active low */
-/**
- * @}
- */
-
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time
- * LSB Position In CR1 Register
- * @{
- */
-#define UART_CR1_DEAT_ADDRESS_LSB_POS \
- 21U /*!< UART Driver Enable assertion time LSB \
- position in CR1 register */
-/**
- * @}
- */
-
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion
- * Time LSB Position In CR1 Register
- * @{
- */
-#define UART_CR1_DEDT_ADDRESS_LSB_POS \
- 16U /*!< UART Driver Enable de-assertion time LSB \
- position in CR1 register */
-/**
- * @}
- */
-
-/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
- * @{
- */
-#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
-/**
- * @}
- */
-
-/** @defgroup UART_TimeOut_Value UART polling-based communications time-out
- * value
- * @{
- */
-#define HAL_UART_TIMEOUT_VALUE \
- 0x1FFFFFFU /*!< UART polling-based communications time-out value */
-/**
- * @}
- */
-
-/** @defgroup UART_Flags UART Status Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define UART_FLAG_TXFT \
- USART_ISR_TXFT /*!< UART TXFIFO threshold flag */
-#define UART_FLAG_RXFT \
- USART_ISR_RXFT /*!< UART RXFIFO threshold flag */
-#define UART_FLAG_RXFF \
- USART_ISR_RXFF /*!< UART RXFIFO Full flag */
-#define UART_FLAG_TXFE \
- USART_ISR_TXFE /*!< UART TXFIFO Empty flag */
-#define UART_FLAG_REACK \
- USART_ISR_REACK /*!< UART receive enable acknowledge flag */
-#define UART_FLAG_TEACK \
- USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
-#define UART_FLAG_WUF \
- USART_ISR_WUF /*!< UART wake-up from stop mode flag */
-#define UART_FLAG_RWU \
- USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
-#define UART_FLAG_SBKF \
- USART_ISR_SBKF /*!< UART send break flag */
-#define UART_FLAG_CMF \
- USART_ISR_CMF /*!< UART character match flag */
-#define UART_FLAG_BUSY \
- USART_ISR_BUSY /*!< UART busy flag */
-#define UART_FLAG_ABRF \
- USART_ISR_ABRF /*!< UART auto Baud rate flag */
-#define UART_FLAG_ABRE \
- USART_ISR_ABRE /*!< UART auto Baud rate error */
-#define UART_FLAG_RTOF \
- USART_ISR_RTOF /*!< UART receiver timeout flag */
-#define UART_FLAG_CTS \
- USART_ISR_CTS /*!< UART clear to send flag */
-#define UART_FLAG_CTSIF \
- USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
-#define UART_FLAG_LBDF \
- USART_ISR_LBDF /*!< UART LIN break detection flag */
-#define UART_FLAG_TXE \
- USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */
-#define UART_FLAG_TXFNF \
- USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */
-#define UART_FLAG_TC \
- USART_ISR_TC /*!< UART transmission complete */
-#define UART_FLAG_RXNE \
- USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */
-#define UART_FLAG_RXFNE \
- USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */
-#define UART_FLAG_IDLE \
- USART_ISR_IDLE /*!< UART idle flag */
-#define UART_FLAG_ORE \
- USART_ISR_ORE /*!< UART overrun error */
-#define UART_FLAG_NE \
- USART_ISR_NE /*!< UART noise error */
-#define UART_FLAG_FE \
- USART_ISR_FE /*!< UART frame error */
-#define UART_FLAG_PE \
- USART_ISR_PE /*!< UART parity error */
-/**
- * @}
- */
-
-/** @defgroup UART_Interrupt_definition UART Interrupts Definition
- * Elements values convention: 000ZZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZZ : Flag position in the ISR register(5bits)
- * Elements values convention: 000000000XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * Elements values convention: 0000ZZZZ00000000b
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-#define UART_IT_PE \
- 0x0028U /*!< UART parity error interruption */
-#define UART_IT_TXE \
- 0x0727U /*!< UART transmit data register empty interruption */
-#define UART_IT_TXFNF \
- 0x0727U /*!< UART TX FIFO not full interruption */
-#define UART_IT_TC \
- 0x0626U /*!< UART transmission complete interruption */
-#define UART_IT_RXNE \
- 0x0525U /*!< UART read data register not empty interruption */
-#define UART_IT_RXFNE \
- 0x0525U /*!< UART RXFIFO not empty interruption */
-#define UART_IT_IDLE \
- 0x0424U /*!< UART idle interruption */
-#define UART_IT_LBD \
- 0x0846U /*!< UART LIN break detection interruption */
-#define UART_IT_CTS \
- 0x096AU /*!< UART CTS interruption */
-#define UART_IT_CM \
- 0x112EU /*!< UART character match interruption */
-#define UART_IT_WUF \
- 0x1476U /*!< UART wake-up from stop mode interruption */
-#define UART_IT_RXFF \
- 0x183FU /*!< UART RXFIFO full interruption */
-#define UART_IT_TXFE \
- 0x173EU /*!< UART TXFIFO empty interruption */
-#define UART_IT_RXFT \
- 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
-#define UART_IT_TXFT \
- 0x1B77U /*!< UART TXFIFO threshold reached interruption */
-#define UART_IT_RTO \
- 0x0B3AU /*!< UART receiver timeout interruption */
-
-#define UART_IT_ERR \
- 0x0060U /*!< UART error interruption */
-
-#define UART_IT_ORE \
- 0x0300U /*!< UART overrun error interruption */
-#define UART_IT_NE \
- 0x0200U /*!< UART noise error interruption */
-#define UART_IT_FE \
- 0x0100U /*!< UART frame error interruption */
-/**
- * @}
- */
-
-/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
- * @{
- */
-#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
-#define UART_CLEAR_OREF \
- USART_ICR_ORECF /*!< Overrun Error Clear Flag */
-#define UART_CLEAR_IDLEF \
- USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TXFECF \
- USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
-#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define UART_CLEAR_LBDF \
- USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
-#define UART_CLEAR_CTSF \
- USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
-#define UART_CLEAR_WUF \
- USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag \
- */
-#define UART_CLEAR_RTOF \
- USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
-/**
- * @}
- */
-
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
- * @{
- */
-#define HAL_UART_RECEPTION_STANDARD \
- (0x00000000U) /*!< Standard reception */
-#define HAL_UART_RECEPTION_TOIDLE \
- (0x00000001U) /*!< Reception till completion or IDLE event */
-#define HAL_UART_RECEPTION_TORTO \
- (0x00000002U) /*!< Reception till completion or RTO event */
-#define HAL_UART_RECEPTION_TOCHARMATCH \
- (0x00000003U) /*!< Reception till completion or CM event */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
- * @{
- */
-
-/** @brief Reset UART handle states.
- * @param __HANDLE__ UART handle.
- * @retval None
- */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while (0U)
-#else
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) \
- do { \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while (0U)
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-
-/** @brief Flush the UART Data registers.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
- do { \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while (0U)
-
-/** @brief Clear the specified UART pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
- * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag
- * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
- * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
- * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
- * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
- * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
- * @retval None
- */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the UART PE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
- __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
-
-/** @brief Clear the UART FE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) \
- __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
-
-/** @brief Clear the UART NE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) \
- __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
-
-/** @brief Clear the UART ORE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) \
- __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
-
-/** @brief Clear the UART IDLE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) \
- __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
-
-/** @brief Clear the UART TX FIFO empty clear flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) \
- __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
-
-/** @brief Check whether the specified UART flag is set or not.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag
- * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag
- * @arg @ref UART_FLAG_RXFF RXFIFO Full flag
- * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag
- * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
- * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in
- * mute mode)
- * @arg @ref UART_FLAG_SBKF Send Break flag
- * @arg @ref UART_FLAG_CMF Character match flag
- * @arg @ref UART_FLAG_BUSY Busy flag
- * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
- * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
- * @arg @ref UART_FLAG_CTS CTS Change flag
- * @arg @ref UART_FLAG_LBDF LIN Break detection flag
- * @arg @ref UART_FLAG_TXE Transmit data register empty flag
- * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
- * @arg @ref UART_FLAG_TC Transmission Complete flag
- * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
- * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
- * @arg @ref UART_FLAG_RTOF Receiver Timeout flag
- * @arg @ref UART_FLAG_IDLE Idle Line detection flag
- * @arg @ref UART_FLAG_ORE Overrun Error flag
- * @arg @ref UART_FLAG_NE Noise Error flag
- * @arg @ref UART_FLAG_FE Framing Error flag
- * @arg @ref UART_FLAG_PE Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) \
- (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Enable the specified UART interrupt.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __INTERRUPT__ specifies the UART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
- * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
- * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
- * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
- * @arg @ref UART_IT_RTO Receive Timeout interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error,
- * overrun error)
- * @retval None
- */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) \
- ? ((__HANDLE__)->Instance->CR1 |= \
- (1U << ((__INTERRUPT__) & UART_IT_MASK))) \
- : ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) \
- ? ((__HANDLE__)->Instance->CR2 |= \
- (1U << ((__INTERRUPT__) & UART_IT_MASK))) \
- : ((__HANDLE__)->Instance->CR3 |= \
- (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief Disable the specified UART interrupt.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __INTERRUPT__ specifies the UART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
- * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
- * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
- * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
- * @arg @ref UART_IT_RTO Receive Timeout interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error,
- * overrun error)
- * @retval None
- */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) \
- ? ((__HANDLE__)->Instance->CR1 &= \
- ~(1U << ((__INTERRUPT__) & UART_IT_MASK))) \
- : ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) \
- ? ((__HANDLE__)->Instance->CR2 &= \
- ~(1U << ((__INTERRUPT__) & UART_IT_MASK))) \
- : ((__HANDLE__)->Instance->CR3 &= \
- ~(1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief Check whether the specified UART interrupt has occurred or not.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __INTERRUPT__ specifies the UART interrupt to check.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
- * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
- * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
- * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
- * @arg @ref UART_IT_RTO Receive Timeout interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error,
- * overrun error)
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) \
- ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__) >> 8U))) != RESET) \
- ? SET \
- : RESET)
-
-/** @brief Check whether the specified UART interrupt source is enabled or not.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __INTERRUPT__ specifies the UART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
- * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
- * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
- * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
- * @arg @ref UART_IT_RTO Receive Timeout interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error,
- * overrun error)
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) \
- ? (__HANDLE__)->Instance->CR1 \
- : (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) \
- ? (__HANDLE__)->Instance->CR2 \
- : (__HANDLE__)->Instance->CR3)) & \
- (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) \
- ? SET \
- : RESET)
-
-/** @brief Clear the specified UART ISR flag, in setting the proper ICR
- * register flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs
- * to be set to clear the corresponding interrupt This parameter can be one of
- * the following values:
- * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
- * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
- * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
- * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
- * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
- * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
- * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
- * @retval None
- */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) \
- ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Set a specific UART request flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __REQ__ specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
- * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
- * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
- * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
- * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
- * @retval None
- */
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) \
- ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief Enable the UART one bit sample method.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
-
-/** @brief Disable the UART one bit sample method.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
-
-/** @brief Enable UART.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/** @brief Enable CTS flow control.
- * @note This macro allows to enable CTS hardware flow control for a given
- * UART instance, without need to call HAL_UART_Init() function. As involving
- * direct access to UART registers, usage of this macro should be fully endorsed
- * by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control
- * feature activation, without need for USART instance Deinit/Init, following
- * conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call
- * of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is
- * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
- * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do { \
- ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while (0U)
-
-/** @brief Disable CTS flow control.
- * @note This macro allows to disable CTS hardware flow control for a given
- * UART instance, without need to call HAL_UART_Init() function. As involving
- * direct access to UART registers, usage of this macro should be fully endorsed
- * by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control
- * feature activation, without need for USART instance Deinit/Init, following
- * conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call
- * of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is
- * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
- * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do { \
- ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while (0U)
-
-/** @brief Enable RTS flow control.
- * @note This macro allows to enable RTS hardware flow control for a given
- * UART instance, without need to call HAL_UART_Init() function. As involving
- * direct access to UART registers, usage of this macro should be fully endorsed
- * by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control
- * feature activation, without need for USART instance Deinit/Init, following
- * conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call
- * of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is
- * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
- * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do { \
- ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while (0U)
-
-/** @brief Disable RTS flow control.
- * @note This macro allows to disable RTS hardware flow control for a given
- * UART instance, without need to call HAL_UART_Init() function. As involving
- * direct access to UART registers, usage of this macro should be fully endorsed
- * by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control
- * feature activation, without need for USART instance Deinit/Init, following
- * conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call
- * of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is
- * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
- * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do { \
- ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while (0U)
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-/** @brief Get UART clok division factor from clock prescaler value.
- * @param __CLOCKPRESCALER__ UART prescaler value.
- * @retval UART clock division factor
- */
-#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
- (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U \
- : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U \
- : 1U)
-
-/** @brief BRR division operation to set BRR register with LPUART.
- * @param __PCLK__ LPUART clock.
- * @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
- * @retval Division result
- */
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
- ((uint32_t)((((((uint64_t)(__PCLK__)) / \
- (UARTPrescTable[(__CLOCKPRESCALER__)])) * \
- 256U) + \
- (uint32_t)((__BAUD__) / 2U)) / \
- (__BAUD__)))
-
-/** @brief BRR division operation to set BRR register in 8-bit oversampling
- * mode.
- * @param __PCLK__ UART clock.
- * @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
- * @retval Division result
- */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
- (((((__PCLK__) / UARTPrescTable[(__CLOCKPRESCALER__)]) * 2U) + \
- ((__BAUD__) / 2U)) / \
- (__BAUD__))
-
-/** @brief BRR division operation to set BRR register in 16-bit oversampling
- * mode.
- * @param __PCLK__ UART clock.
- * @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
- * @retval Division result
- */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
- ((((__PCLK__) / UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__) / 2U)) / \
- (__BAUD__))
-
-/** @brief Check whether or not UART instance is Low Power UART.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
- */
-#define UART_INSTANCE_LOWPOWER(__HANDLE__) \
- (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
-
-/** @brief Check UART Baud rate.
- * @param __BAUDRATE__ Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on G4 (i.e.
- * 150 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
- * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
- */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
-
-/** @brief Check UART assertion time.
- * @param __TIME__ 5-bit value assertion time.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/** @brief Check UART deassertion time.
- * @param __TIME__ 5-bit value deassertion time.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/**
- * @brief Ensure that UART frame number of stop bits is valid.
- * @param __STOPBITS__ UART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_UART_STOPBITS(__STOPBITS__) \
- (((__STOPBITS__) == UART_STOPBITS_0_5) || \
- ((__STOPBITS__) == UART_STOPBITS_1) || \
- ((__STOPBITS__) == UART_STOPBITS_1_5) || \
- ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
- * @brief Ensure that LPUART frame number of stop bits is valid.
- * @param __STOPBITS__ LPUART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_LPUART_STOPBITS(__STOPBITS__) \
- (((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
- * @brief Ensure that UART frame parity is valid.
- * @param __PARITY__ UART frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_UART_PARITY(__PARITY__) \
- (((__PARITY__) == UART_PARITY_NONE) || ((__PARITY__) == UART_PARITY_EVEN) || \
- ((__PARITY__) == UART_PARITY_ODD))
-
-/**
- * @brief Ensure that UART hardware flow control is valid.
- * @param __CONTROL__ UART hardware flow control.
- * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
- */
-#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__) \
- (((__CONTROL__) == UART_HWCONTROL_NONE) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS) || \
- ((__CONTROL__) == UART_HWCONTROL_CTS) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
-
-/**
- * @brief Ensure that UART communication mode is valid.
- * @param __MODE__ UART communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_UART_MODE(__MODE__) \
- ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && \
- ((__MODE__) != 0x00U))
-
-/**
- * @brief Ensure that UART state is valid.
- * @param __STATE__ UART state.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_UART_STATE(__STATE__) \
- (((__STATE__) == UART_STATE_DISABLE) || ((__STATE__) == UART_STATE_ENABLE))
-
-/**
- * @brief Ensure that UART oversampling is valid.
- * @param __SAMPLING__ UART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_UART_OVERSAMPLING(__SAMPLING__) \
- (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == UART_OVERSAMPLING_8))
-
-/**
- * @brief Ensure that UART frame sampling is valid.
- * @param __ONEBIT__ UART frame sampling.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) \
- (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that UART auto Baud rate detection mode is valid.
- * @param __MODE__ UART auto Baud rate detection mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) \
- (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-
-/**
- * @brief Ensure that UART receiver timeout setting is valid.
- * @param __TIMEOUT__ UART receiver timeout setting.
- * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
- */
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) \
- (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
-
-/** @brief Check the receiver timeout value.
- * @note The maximum UART receiver timeout value is 0xFFFFFF.
- * @param __TIMEOUTVALUE__ receiver timeout value.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) \
- ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
-
-/**
- * @brief Ensure that UART LIN state is valid.
- * @param __LIN__ UART LIN state.
- * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
- */
-#define IS_UART_LIN(__LIN__) \
- (((__LIN__) == UART_LIN_DISABLE) || ((__LIN__) == UART_LIN_ENABLE))
-
-/**
- * @brief Ensure that UART LIN break detection length is valid.
- * @param __LENGTH__ UART LIN break detection length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) \
- (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-
-/**
- * @brief Ensure that UART DMA TX state is valid.
- * @param __DMATX__ UART DMA TX state.
- * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
- */
-#define IS_UART_DMA_TX(__DMATX__) \
- (((__DMATX__) == UART_DMA_TX_DISABLE) || ((__DMATX__) == UART_DMA_TX_ENABLE))
-
-/**
- * @brief Ensure that UART DMA RX state is valid.
- * @param __DMARX__ UART DMA RX state.
- * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
- */
-#define IS_UART_DMA_RX(__DMARX__) \
- (((__DMARX__) == UART_DMA_RX_DISABLE) || ((__DMARX__) == UART_DMA_RX_ENABLE))
-
-/**
- * @brief Ensure that UART half-duplex state is valid.
- * @param __HDSEL__ UART half-duplex state.
- * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
- */
-#define IS_UART_HALF_DUPLEX(__HDSEL__) \
- (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
- ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up method is valid.
- * @param __WAKEUP__ UART wake-up method .
- * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
- */
-#define IS_UART_WAKEUPMETHOD(__WAKEUP__) \
- (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-/**
- * @brief Ensure that UART request parameter is valid.
- * @param __PARAM__ UART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) \
- (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
- ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
- ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-
-/**
- * @brief Ensure that UART advanced features initialization is valid.
- * @param __INIT__ UART advanced features initialization.
- * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
- */
-#define IS_UART_ADVFEATURE_INIT(__INIT__) \
- ((__INIT__) <= \
- (UART_ADVFEATURE_NO_INIT | UART_ADVFEATURE_TXINVERT_INIT | \
- UART_ADVFEATURE_RXINVERT_INIT | UART_ADVFEATURE_DATAINVERT_INIT | \
- UART_ADVFEATURE_SWAP_INIT | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
- UART_ADVFEATURE_AUTOBAUDRATE_INIT | UART_ADVFEATURE_MSBFIRST_INIT))
-
-/**
- * @brief Ensure that UART frame TX inversion setting is valid.
- * @param __TXINV__ UART frame TX inversion setting.
- * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_TXINV(__TXINV__) \
- (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
- ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame RX inversion setting is valid.
- * @param __RXINV__ UART frame RX inversion setting.
- * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_RXINV(__RXINV__) \
- (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
- ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame data inversion setting is valid.
- * @param __DATAINV__ UART frame data inversion setting.
- * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) \
- (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
- ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame RX/TX pins swap setting is valid.
- * @param __SWAP__ UART frame RX/TX pins swap setting.
- * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
- */
-#define IS_UART_ADVFEATURE_SWAP(__SWAP__) \
- (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
- ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
-
-/**
- * @brief Ensure that UART frame overrun setting is valid.
- * @param __OVERRUN__ UART frame overrun setting.
- * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
- */
-#define IS_UART_OVERRUN(__OVERRUN__) \
- (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
- ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
- * @brief Ensure that UART auto Baud rate state is valid.
- * @param __AUTOBAUDRATE__ UART auto Baud rate state.
- * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is
- * invalid)
- */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) \
- (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
- ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-
-/**
- * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
- * @param __DMA__ UART DMA enabling or disabling on error setting.
- * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
- */
-#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) \
- (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
- * @brief Ensure that UART frame MSB first setting is valid.
- * @param __MSBFIRST__ UART frame MSB first setting.
- * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
- */
-#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) \
- (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
- * @brief Ensure that UART stop mode state is valid.
- * @param __STOPMODE__ UART stop mode state.
- * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) \
- (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
- ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
-
-/**
- * @brief Ensure that UART mute mode state is valid.
- * @param __MUTE__ UART mute mode state.
- * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
- */
-#define IS_UART_MUTE_MODE(__MUTE__) \
- (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
- ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up selection is valid.
- * @param __WAKE__ UART wake-up selection.
- * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
- */
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) \
- (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
- ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
- ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
-
-/**
- * @brief Ensure that UART driver enable polarity is valid.
- * @param __POLARITY__ UART driver enable polarity.
- * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
- */
-#define IS_UART_DE_POLARITY(__POLARITY__) \
- (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
- ((__POLARITY__) == UART_DE_POLARITY_LOW))
-
-/**
- * @brief Ensure that UART Prescaler is valid.
- * @param __CLOCKPRESCALER__ UART Prescaler value.
- * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is
- * invalid)
- */
-#define IS_UART_PRESCALER(__CLOCKPRESCALER__) \
- (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
-
-/**
- * @}
- */
-
-/* Include UART HAL Extended module */
-#include "stm32g4xx_hal_uart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and
- * de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart,
- uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart,
- uint8_t Address,
- uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(
- UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
- pUART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(
- UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(
- UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart,
- const uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart,
- const uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart,
- const uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
-
-void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions
- * ************************************************/
-void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart,
- uint32_t TimeoutValue);
-HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error
- * functions
- * @{
- */
-
-/* Peripheral State and Errors functions
- * **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions
- * -----------------------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
- * @{
- */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
- uint32_t Flag, FlagStatus Status,
- uint32_t Tickstart,
- uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size);
-
-/**
- * @}
- */
-
-/* Private variables
- * -----------------------------------------------------------*/
-/** @defgroup UART_Private_variables UART Private variables
- * @{
- */
-/* Prescaler Table used in BRR computation macros.
- Declared as extern here to allow use of private UART macros, outside of HAL
- UART functions */
-extern const uint16_t UARTPrescTable[12];
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_UART_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_uart.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_UART_H
+#define STM32G4xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct {
+ uint32_t
+ BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following
+ formula: LPUART:
+ =======
+ Baud Rate Register = ((256 * lpuart_ker_ckpres) /
+ ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the
+ UART input clock divided by a prescaler UART:
+ =====
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck_pres is the UART input clock divided by a
+ prescaler */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or
+ received in a frame. This parameter can be a value of
+ @ref UARTEx_Word_Length. */
+
+ uint32_t
+ StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is
+ inserted at the MSB position of the transmitted data (9th
+ bit when the word length is set to 9 data bits; 8th bit
+ when the word length is set to 8 data bits). */
+
+ uint32_t
+ Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or
+ disabled. This parameter can be a value of @ref UART_Mode. */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is
+ enabled or disabled. This parameter can be a value of
+ @ref UART_Hardware_Flow_Control. */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled
+ or disabled, to achieve higher speed (up to
+ f_PCLK/8). This parameter can be a value of @ref
+ UART_Over_Sampling. */
+
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three
+ samples' majority vote is selected. Selecting the
+ single sample method increases the receiver
+ tolerance to clock deviations. This parameter can
+ be a value of @ref UART_OneBit_Sampling. */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the
+ UART clock source. This parameter can be a value
+ of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+ * @brief UART Advanced Features initialization structure definition
+ */
+typedef struct {
+ uint32_t
+ AdvFeatureInit; /*!< Specifies which advanced UART features is
+ initialized. Several Advanced Features may be
+ initialized at the same time . This parameter can be a
+ value of
+ @ref UART_Advanced_Features_Initialization_Type. */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is
+ inverted. This parameter can be a value of @ref
+ UART_Tx_Inv. */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is
+ inverted. This parameter can be a value of @ref
+ UART_Rx_Inv. */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct
+ logic vs negative/inverted logic). This parameter can
+ be a value of @ref UART_Data_Inv. */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun
+ detection is disabled. This parameter can be a
+ value of @ref UART_Overrun_Disable. */
+
+ uint32_t
+ DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of
+ reception error. This parameter can be a value of
+ @ref UART_DMA_Disable_on_Rx_Error. */
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection
+ is enabled. This parameter can be a value of
+ @ref UART_AutoBaudRate_Enable. */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled,
+ specifies how the rate detection is carried out.
+ This parameter can be a value of @ref
+ UART_AutoBaud_Rate_Mode. */
+
+ uint32_t
+ MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL UART State definition
+ * @note HAL UART State value is a combination of 2 different substates:
+ * gState and RxState (see @ref UART_State_Definition).
+ * - gState contains UART state information related to global Handle
+ * management and also information related to Tx operations. gState value coding
+ * follow below described bitmap : b7-b6 Error information 00 : No Error 01 :
+ * (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0
+ * : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized.
+ * HAL UART Init function already called) b4-b3 (not used) xx : Should be set
+ * to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy
+ * with some configuration or internal operations) b1 (not used) x : Should
+ * be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy
+ * (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+ * @brief UART clock sources definition
+ */
+typedef enum {
+ UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
+} UART_ClockSourceTypeDef;
+
+/**
+ * @brief HAL UART Reception type definition
+ * @note HAL UART Reception type value aims to identify which type of Reception
+ * is ongoing. This parameter can be a value of @ref UART_Reception_Type_Values
+ * : HAL_UART_RECEPTION_STANDARD = 0x00U, HAL_UART_RECEPTION_TOIDLE =
+ * 0x01U, HAL_UART_RECEPTION_TORTO = 0x02U,
+ * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
+ */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+ * @brief HAL UART Rx Event type definition
+ * @note HAL UART Rx Event type value aims to identify which type of Event has
+ * occurred leading to call of the RxEvent callback. This parameter can be a
+ * value of @ref UART_RxEvent_Type_Values : HAL_UART_RXEVENT_TC = 0x00U,
+ * HAL_UART_RXEVENT_HT = 0x01U,
+ * HAL_UART_RXEVENT_IDLE = 0x02U,
+ */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct __UART_HandleTypeDef {
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef
+ AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
+
+ uint32_t
+ FifoMode; /*!< Specifies if the FIFO mode is being used.
+ This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR
+ execution */
+
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR
+ execution */
+
+ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+
+ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
+
+ void (*RxISR)(struct __UART_HandleTypeDef
+ *huart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __UART_HandleTypeDef
+ *huart); /*!< Function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef
+ gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations. This parameter
+ can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO HAL_UART_StateTypeDef
+ RxState; /*!< UART state information related to Rx operations. This
+ parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ void (*TxHalfCpltCallback)(struct __UART_HandleTypeDef
+ *huart); /*!< UART Tx Half Complete Callback */
+ void (*TxCpltCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
+ void (*RxHalfCpltCallback)(struct __UART_HandleTypeDef
+ *huart); /*!< UART Rx Half Complete Callback */
+ void (*RxCpltCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
+ void (*ErrorCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
+ void (*AbortCpltCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
+ void (*AbortTransmitCpltCallback)(
+ struct __UART_HandleTypeDef
+ *huart); /*!< UART Abort Transmit Complete Callback */
+ void (*AbortReceiveCpltCallback)(
+ struct __UART_HandleTypeDef
+ *huart); /*!< UART Abort Receive Complete Callback */
+ void (*WakeupCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
+ void (*RxFifoFullCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
+ void (*TxFifoEmptyCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
+ void (*RxEventCallback)(struct __UART_HandleTypeDef *huart,
+ uint16_t Pos); /*!< UART Reception Event Callback */
+
+ void (*MspInitCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
+ void (*MspDeInitCallback)(
+ struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL UART Callback ID enumeration definition
+ */
+typedef enum {
+ HAL_UART_TX_HALFCOMPLETE_CB_ID =
+ 0x00U, /*!< UART Tx Half Complete Callback ID */
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
+ HAL_UART_RX_HALFCOMPLETE_CB_ID =
+ 0x02U, /*!< UART Rx Half Complete Callback ID */
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID =
+ 0x06U, /*!< UART Abort Transmit Complete Callback ID */
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID =
+ 0x07U, /*!< UART Abort Receive Complete Callback ID */
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
+ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */
+ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */
+
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL UART Callback pointer definition
+ */
+typedef void (*pUART_CallbackTypeDef)(
+ UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)(
+ struct __UART_HandleTypeDef *huart,
+ uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+ * @{
+ */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+ * @{
+ */
+#define HAL_UART_STATE_RESET \
+ 0x00000000U /*!< Peripheral is not initialized \
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_READY \
+ 0x00000020U /*!< Peripheral Initialized and ready for use \
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_BUSY \
+ 0x00000024U /*!< an internal process is ongoing \
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_TX \
+ 0x00000021U /*!< Data Transmission process is ongoing \
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_RX \
+ 0x00000022U /*!< Data Reception process is ongoing \
+ Value is allowed for RxState only */
+#define HAL_UART_STATE_BUSY_TX_RX \
+ 0x00000023U /*!< Data Transmission and Reception process is ongoing \
+ Not to be used for neither gState nor RxState.Value is \
+ result of combination (Or) between gState and RxState values \
+ */
+#define HAL_UART_STATE_TIMEOUT \
+ 0x000000A0U /*!< Timeout state \
+ Value is allowed for gState only */
+#define HAL_UART_STATE_ERROR \
+ 0x000000E0U /*!< Error \
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Error_Definition UART Error Definition
+ * @{
+ */
+#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define HAL_UART_ERROR_INVALID_CALLBACK \
+ (0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_0_5 \
+ USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit \
+ */
+#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 \
+ (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE 0x00000000U /*!< No parity */
+#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
+#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
+#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS \
+ (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
+#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+ * @{
+ */
+#define UART_ONE_BIT_SAMPLE_DISABLE \
+ 0x00000000U /*!< One-bit sampling disable \
+ */
+#define UART_ONE_BIT_SAMPLE_ENABLE \
+ USART_CR3_ONEBIT /*!< One-bit sampling enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_ClockPrescaler UART Clock Prescaler
+ * @{
+ */
+#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate
+ * Mode
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT \
+ 0x00000000U /*!< Auto Baud rate detection \
+ on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE \
+ USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection \
+ on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME \
+ USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection \
+ on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME \
+ USART_CR2_ABRMODE /*!< Auto Baud rate detection \
+ on 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE \
+ 0x00000000U /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE \
+ USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN UART Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE \
+ 0x00000000U /*!< Local Interconnect Network disable \
+ */
+#define UART_LIN_ENABLE \
+ USART_CR2_LINEN /*!< Local Interconnect Network enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B \
+ 0x00000000U /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B \
+ USART_CR2_LBDL /*!< LIN 11-bit break detection length */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Tx UART DMA Tx
+ * @{
+ */
+#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Rx UART DMA Rx
+ * @{
+ */
+#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
+ * @{
+ */
+#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE \
+ USART_CR3_HDSEL /*!< UART half-duplex enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE \
+ 0x00000000U /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK \
+ USART_CR1_WAKE /*!< UART wake-up on address mark */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+ * @{
+ */
+#define UART_AUTOBAUD_REQUEST \
+ USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST \
+ USART_RQR_SBKRQ /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST \
+ USART_RQR_MMRQ /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST \
+ USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST \
+ USART_RQR_TXFRQ /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature
+ * Initialization Type
+ * @{
+ */
+#define UART_ADVFEATURE_NO_INIT \
+ 0x00000000U /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT \
+ 0x00000001U /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT \
+ 0x00000002U /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT \
+ 0x00000004U /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT \
+ 0x00000008U /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT \
+ 0x00000010U /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT \
+ 0x00000020U /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT \
+ 0x00000040U /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT \
+ 0x00000080U /*!< Most significant bit sent/received first */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_TXINV_DISABLE \
+ 0x00000000U /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE \
+ USART_CR2_TXINV /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_RXINV_DISABLE \
+ 0x00000000U /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE \
+ USART_CR2_RXINV /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_DATAINV_DISABLE \
+ 0x00000000U /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE \
+ USART_CR2_DATAINV /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+ * @{
+ */
+#define UART_ADVFEATURE_SWAP_DISABLE \
+ 0x00000000U /*!< TX/RX pins swap disable \
+ */
+#define UART_ADVFEATURE_SWAP_ENABLE \
+ USART_CR2_SWAP /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
+ * @{
+ */
+#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE \
+ USART_CR3_OVRDIS /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate
+ * Enable
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE \
+ 0x00000000U /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE \
+ USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable
+ * On Rx Error
+ * @{
+ */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR \
+ 0x00000000U /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR \
+ USART_CR3_DDRE /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First
+ * @{
+ */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE \
+ 0x00000000U /*!< Most significant bit sent/received \
+ first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE \
+ USART_CR2_MSBFIRST /*!< Most significant bit sent/received \
+ first enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE \
+ 0x00000000U /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE \
+ USART_CR1_UESM /*!< UART stop mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE \
+ 0x00000000U /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE \
+ USART_CR1_MME /*!< UART mute mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In
+ * CR2 Register
+ * @{
+ */
+#define UART_CR2_ADDRESS_LSB_POS \
+ 24U /*!< UART address-matching LSB position in CR2 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS \
+ 0x00000000U /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT \
+ USART_CR3_WUS_1 /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY \
+ USART_CR3_WUS /*!< UART wake-up on receive data register \
+ not empty or RXFIFO is not empty */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
+ * @{
+ */
+#define UART_DE_POLARITY_HIGH \
+ 0x00000000U /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW \
+ USART_CR3_DEP /*!< Driver enable signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time
+ * LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS \
+ 21U /*!< UART Driver Enable assertion time LSB \
+ position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion
+ * Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS \
+ 16U /*!< UART Driver Enable de-assertion time LSB \
+ position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
+ * @{
+ */
+#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out
+ * value
+ * @{
+ */
+#define HAL_UART_TIMEOUT_VALUE \
+ 0x1FFFFFFU /*!< UART polling-based communications time-out value */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_TXFT \
+ USART_ISR_TXFT /*!< UART TXFIFO threshold flag */
+#define UART_FLAG_RXFT \
+ USART_ISR_RXFT /*!< UART RXFIFO threshold flag */
+#define UART_FLAG_RXFF \
+ USART_ISR_RXFF /*!< UART RXFIFO Full flag */
+#define UART_FLAG_TXFE \
+ USART_ISR_TXFE /*!< UART TXFIFO Empty flag */
+#define UART_FLAG_REACK \
+ USART_ISR_REACK /*!< UART receive enable acknowledge flag */
+#define UART_FLAG_TEACK \
+ USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
+#define UART_FLAG_WUF \
+ USART_ISR_WUF /*!< UART wake-up from stop mode flag */
+#define UART_FLAG_RWU \
+ USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF \
+ USART_ISR_SBKF /*!< UART send break flag */
+#define UART_FLAG_CMF \
+ USART_ISR_CMF /*!< UART character match flag */
+#define UART_FLAG_BUSY \
+ USART_ISR_BUSY /*!< UART busy flag */
+#define UART_FLAG_ABRF \
+ USART_ISR_ABRF /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE \
+ USART_ISR_ABRE /*!< UART auto Baud rate error */
+#define UART_FLAG_RTOF \
+ USART_ISR_RTOF /*!< UART receiver timeout flag */
+#define UART_FLAG_CTS \
+ USART_ISR_CTS /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF \
+ USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF \
+ USART_ISR_LBDF /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE \
+ USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */
+#define UART_FLAG_TXFNF \
+ USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */
+#define UART_FLAG_TC \
+ USART_ISR_TC /*!< UART transmission complete */
+#define UART_FLAG_RXNE \
+ USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */
+#define UART_FLAG_RXFNE \
+ USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */
+#define UART_FLAG_IDLE \
+ USART_ISR_IDLE /*!< UART idle flag */
+#define UART_FLAG_ORE \
+ USART_ISR_ORE /*!< UART overrun error */
+#define UART_FLAG_NE \
+ USART_ISR_NE /*!< UART noise error */
+#define UART_FLAG_FE \
+ USART_ISR_FE /*!< UART frame error */
+#define UART_FLAG_PE \
+ USART_ISR_PE /*!< UART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define UART_IT_PE \
+ 0x0028U /*!< UART parity error interruption */
+#define UART_IT_TXE \
+ 0x0727U /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF \
+ 0x0727U /*!< UART TX FIFO not full interruption */
+#define UART_IT_TC \
+ 0x0626U /*!< UART transmission complete interruption */
+#define UART_IT_RXNE \
+ 0x0525U /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE \
+ 0x0525U /*!< UART RXFIFO not empty interruption */
+#define UART_IT_IDLE \
+ 0x0424U /*!< UART idle interruption */
+#define UART_IT_LBD \
+ 0x0846U /*!< UART LIN break detection interruption */
+#define UART_IT_CTS \
+ 0x096AU /*!< UART CTS interruption */
+#define UART_IT_CM \
+ 0x112EU /*!< UART character match interruption */
+#define UART_IT_WUF \
+ 0x1476U /*!< UART wake-up from stop mode interruption */
+#define UART_IT_RXFF \
+ 0x183FU /*!< UART RXFIFO full interruption */
+#define UART_IT_TXFE \
+ 0x173EU /*!< UART TXFIFO empty interruption */
+#define UART_IT_RXFT \
+ 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
+#define UART_IT_TXFT \
+ 0x1B77U /*!< UART TXFIFO threshold reached interruption */
+#define UART_IT_RTO \
+ 0x0B3AU /*!< UART receiver timeout interruption */
+
+#define UART_IT_ERR \
+ 0x0060U /*!< UART error interruption */
+
+#define UART_IT_ORE \
+ 0x0300U /*!< UART overrun error interruption */
+#define UART_IT_NE \
+ 0x0200U /*!< UART noise error interruption */
+#define UART_IT_FE \
+ 0x0100U /*!< UART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
+#define UART_CLEAR_OREF \
+ USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF \
+ USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TXFECF \
+ USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF \
+ USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF \
+ USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_WUF \
+ USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag \
+ */
+#define UART_CLEAR_RTOF \
+ USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Reception_Type_Values UART Reception type values
+ * @{
+ */
+#define HAL_UART_RECEPTION_STANDARD \
+ (0x00000000U) /*!< Standard reception */
+#define HAL_UART_RECEPTION_TOIDLE \
+ (0x00000001U) /*!< Reception till completion or IDLE event */
+#define HAL_UART_RECEPTION_TORTO \
+ (0x00000002U) /*!< Reception till completion or RTO event */
+#define HAL_UART_RECEPTION_TOCHARMATCH \
+ (0x00000003U) /*!< Reception till completion or CM event */
+/**
+ * @}
+ */
+
+/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
+ * @{
+ */
+#define HAL_UART_RXEVENT_TC \
+ (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT \
+ (0x00000001U) /*!< RxEvent linked to Half Transfer event */
+#define HAL_UART_RXEVENT_IDLE \
+ (0x00000002U) /*!< RxEvent linked to IDLE event */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle states.
+ * @param __HANDLE__ UART handle.
+ * @retval None
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while (0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while (0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do { \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while (0U)
+
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
+ __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) \
+ __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) \
+ __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) \
+ __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) \
+ __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief Clear the UART TX FIFO empty clear flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) \
+ __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief Check whether the specified UART flag is set or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag
+ * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag
+ * @arg @ref UART_FLAG_RXFF RXFIFO Full flag
+ * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in
+ * mute mode)
+ * @arg @ref UART_FLAG_SBKF Send Break flag
+ * @arg @ref UART_FLAG_CMF Character match flag
+ * @arg @ref UART_FLAG_BUSY Busy flag
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref UART_FLAG_CTS CTS Change flag
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+ * @arg @ref UART_FLAG_TC Transmission Complete flag
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+ * @arg @ref UART_FLAG_RTOF Receiver Timeout flag
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref UART_FLAG_ORE Overrun Error flag
+ * @arg @ref UART_FLAG_NE Noise Error flag
+ * @arg @ref UART_FLAG_FE Framing Error flag
+ * @arg @ref UART_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error,
+ * overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) \
+ ? ((__HANDLE__)->Instance->CR1 |= \
+ (1U << ((__INTERRUPT__) & UART_IT_MASK))) \
+ : ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) \
+ ? ((__HANDLE__)->Instance->CR2 |= \
+ (1U << ((__INTERRUPT__) & UART_IT_MASK))) \
+ : ((__HANDLE__)->Instance->CR3 |= \
+ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error,
+ * overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) \
+ ? ((__HANDLE__)->Instance->CR1 &= \
+ ~(1U << ((__INTERRUPT__) & UART_IT_MASK))) \
+ : ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) \
+ ? ((__HANDLE__)->Instance->CR2 &= \
+ ~(1U << ((__INTERRUPT__) & UART_IT_MASK))) \
+ : ((__HANDLE__)->Instance->CR3 &= \
+ ~(1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Check whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error,
+ * overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__) >> 8U))) != RESET) \
+ ? SET \
+ : RESET)
+
+/** @brief Check whether the specified UART interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error,
+ * overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) \
+ ? (__HANDLE__)->Instance->CR1 \
+ : (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) \
+ ? (__HANDLE__)->Instance->CR2 \
+ : (__HANDLE__)->Instance->CR3)) & \
+ (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) \
+ ? SET \
+ : RESET)
+
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR
+ * register flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs
+ * to be set to clear the corresponding interrupt This parameter can be one of
+ * the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) \
+ ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific UART request flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) \
+ ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
+
+/** @brief Disable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief Enable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given
+ * UART instance, without need to call HAL_UART_Init() function. As involving
+ * direct access to UART registers, usage of this macro should be fully endorsed
+ * by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control
+ * feature activation, without need for USART instance Deinit/Init, following
+ * conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call
+ * of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is
+ * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
+ * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do { \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while (0U)
+
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given
+ * UART instance, without need to call HAL_UART_Init() function. As involving
+ * direct access to UART registers, usage of this macro should be fully endorsed
+ * by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control
+ * feature activation, without need for USART instance Deinit/Init, following
+ * conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call
+ * of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is
+ * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
+ * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do { \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while (0U)
+
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given
+ * UART instance, without need to call HAL_UART_Init() function. As involving
+ * direct access to UART registers, usage of this macro should be fully endorsed
+ * by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control
+ * feature activation, without need for USART instance Deinit/Init, following
+ * conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call
+ * of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is
+ * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
+ * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do { \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while (0U)
+
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given
+ * UART instance, without need to call HAL_UART_Init() function. As involving
+ * direct access to UART registers, usage of this macro should be fully endorsed
+ * by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control
+ * feature activation, without need for USART instance Deinit/Init, following
+ * conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call
+ * of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is
+ * disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an
+ * Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do { \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while (0U)
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+/** @brief Get UART clock division factor from clock prescaler value.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval UART clock division factor
+ */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+ (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U \
+ : ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U \
+ : 256U)
+
+/** @brief BRR division operation to set BRR register with LPUART.
+ * @param __PCLK__ LPUART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ ((uint32_t)((((((uint64_t)(__PCLK__)) / \
+ (UARTPrescTable[(__CLOCKPRESCALER__)])) * \
+ 256U) + \
+ (uint32_t)((__BAUD__) / 2U)) / \
+ (__BAUD__)))
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling
+ * mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ (((((__PCLK__) / UARTPrescTable[(__CLOCKPRESCALER__)]) * 2U) + \
+ ((__BAUD__) / 2U)) / \
+ (__BAUD__))
+
+/** @brief BRR division operation to set BRR register in 16-bit oversampling
+ * mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ ((((__PCLK__) / UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__) / 2U)) / \
+ (__BAUD__))
+
+/** @brief Check whether or not UART instance is Low Power UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+ */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) \
+ (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief Check UART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on G4 (i.e.
+ * 150 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
+
+/** @brief Check UART assertion time.
+ * @param __TIME__ 5-bit value assertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/** @brief Check UART deassertion time.
+ * @param __TIME__ 5-bit value deassertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__ UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) \
+ (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+ * @brief Ensure that LPUART frame number of stop bits is valid.
+ * @param __STOPBITS__ LPUART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_LPUART_STOPBITS(__STOPBITS__) \
+ (((__STOPBITS__) == UART_STOPBITS_1) || ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__ UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) \
+ (((__PARITY__) == UART_PARITY_NONE) || ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__ UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__) \
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__ UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) \
+ ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && \
+ ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__ UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) \
+ (((__STATE__) == UART_STATE_DISABLE) || ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__ UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) \
+ (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__ UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) \
+ (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__ UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) \
+ (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__ UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) \
+ (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum UART receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) \
+ ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__ UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) \
+ (((__LIN__) == UART_LIN_DISABLE) || ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__ UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) \
+ (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__ UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) \
+ (((__DMATX__) == UART_DMA_TX_DISABLE) || ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__ UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) \
+ (((__DMARX__) == UART_DMA_RX_DISABLE) || ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__ UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) \
+ (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__ UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) \
+ (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__ UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) \
+ (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__ UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) \
+ ((__INIT__) <= \
+ (UART_ADVFEATURE_NO_INIT | UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__ UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) \
+ (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__ UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) \
+ (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__ UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) \
+ (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) \
+ (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__ UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_UART_OVERRUN(__OVERRUN__) \
+ (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is
+ * invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) \
+ (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) \
+ (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__ UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) \
+ (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__ UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) \
+ (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__ UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) \
+ (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__ UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) \
+ (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__ UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+ * @brief Ensure that UART Prescaler is valid.
+ * @param __CLOCKPRESCALER__ UART Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is
+ * invalid)
+ */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) \
+ (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+ * @}
+ */
+
+/* Include UART HAL Extended module */
+#include "stm32g4xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and
+ * de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart,
+ uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart,
+ uint8_t Address,
+ uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(
+ UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(
+ UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(
+ UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart,
+ const uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart,
+ const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart,
+ const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions
+ * ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart,
+ uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error
+ * functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions
+ * **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions
+ * -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
+ uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart,
+ uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size);
+
+/**
+ * @}
+ */
+
+/* Private variables
+ * -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+ * @{
+ */
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL
+ UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_UART_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
index 543a9d7..d4d4fde 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
@@ -1,614 +1,854 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_uart_ex.h
- * @author MCD Application Team
- * @brief Header file of UART HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_HAL_UART_EX_H
-#define STM32G4xx_HAL_UART_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UARTEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
- * @{
- */
-
-/**
- * @brief UART wake up from stop mode parameters
- */
-typedef struct {
- uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from
- Stop mode flag (WUF). This parameter can be a value
- of @ref UART_WakeUp_from_Stop_Selection. If set to
- UART_WAKEUP_ON_ADDRESS, the two other fields below
- must be filled up. */
-
- uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
- This parameter can be a value of @ref
- UARTEx_WakeUp_Address_Length. */
-
- uint8_t Address; /*!< UART/USART node address (7-bit long max). */
-} UART_WakeUpTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
- * @{
- */
-
-/** @defgroup UARTEx_Word_Length UARTEx Word Length
- * @{
- */
-#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
-/**
- * @}
- */
-
-/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
- * @{
- */
-#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B \
- USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
-/**
- * @}
- */
-
-/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
- * @brief UART FIFO mode
- * @{
- */
-#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
-#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
- * @brief UART TXFIFO threshold level
- * @{
- */
-#define UART_TXFIFO_THRESHOLD_1_8 \
- 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_4 \
- USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_2 \
- USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
-#define UART_TXFIFO_THRESHOLD_3_4 \
- (USART_CR3_TXFTCFG_0 | \
- USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_7_8 \
- USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_8_8 \
- (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
-/**
- * @}
- */
-
-/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
- * @brief UART RXFIFO threshold level
- * @{
- */
-#define UART_RXFIFO_THRESHOLD_1_8 \
- 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_4 \
- USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_2 \
- USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
-#define UART_RXFIFO_THRESHOLD_3_4 \
- (USART_CR3_RXFTCFG_0 | \
- USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_7_8 \
- USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_8_8 \
- (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UARTEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
- uint32_t AssertionTime,
- uint32_t DeassertionTime);
-
-/**
- * @}
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group2
- * @{
- */
-
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-
-void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
-void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
- * @{
- */
-
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(
- UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(
- UART_HandleTypeDef *huart, uint32_t AddressLength);
-
-HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart,
- uint32_t Threshold);
-HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart,
- uint32_t Threshold);
-
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size,
- uint16_t *RxLen, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
- * @{
- */
-
-/** @brief Report the UART clock source.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __CLOCKSOURCE__ output variable.
- * @retval UART clocking source, written in __CLOCKSOURCE__.
- */
-#if defined(UART5)
-#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
- do { \
- if ((__HANDLE__)->Instance == USART1) { \
- switch (__HAL_RCC_GET_USART1_SOURCE()) { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == USART2) { \
- switch (__HAL_RCC_GET_USART2_SOURCE()) { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == USART3) { \
- switch (__HAL_RCC_GET_USART3_SOURCE()) { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == UART4) { \
- switch (__HAL_RCC_GET_UART4_SOURCE()) { \
- case RCC_UART4CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART4CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART4CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART4CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == UART5) { \
- switch (__HAL_RCC_GET_UART5_SOURCE()) { \
- case RCC_UART5CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART5CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART5CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART5CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == LPUART1) { \
- switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
- case RCC_LPUART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_LPUART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_LPUART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_LPUART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while (0U)
-#elif defined(UART4)
-#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
- do { \
- if ((__HANDLE__)->Instance == USART1) { \
- switch (__HAL_RCC_GET_USART1_SOURCE()) { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == USART2) { \
- switch (__HAL_RCC_GET_USART2_SOURCE()) { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == USART3) { \
- switch (__HAL_RCC_GET_USART3_SOURCE()) { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == UART4) { \
- switch (__HAL_RCC_GET_UART4_SOURCE()) { \
- case RCC_UART4CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART4CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART4CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART4CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == LPUART1) { \
- switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
- case RCC_LPUART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_LPUART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_LPUART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_LPUART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while (0U)
-#else
-#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
- do { \
- if ((__HANDLE__)->Instance == USART1) { \
- switch (__HAL_RCC_GET_USART1_SOURCE()) { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == USART2) { \
- switch (__HAL_RCC_GET_USART2_SOURCE()) { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == USART3) { \
- switch (__HAL_RCC_GET_USART3_SOURCE()) { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else if ((__HANDLE__)->Instance == LPUART1) { \
- switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
- case RCC_LPUART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_LPUART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_LPUART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_LPUART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } else { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while (0U)
-#endif /* UART5 */
-
-/** @brief Report the UART mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @note If PCE = 1, the parity bit is not included in the data extracted
- * by the reception API().
- * This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None, the mask to apply to UART RDR register is stored in
- * (__HANDLE__)->Mask field.
- */
-#define UART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { \
- (__HANDLE__)->Mask = 0x01FFU; \
- } else { \
- (__HANDLE__)->Mask = 0x00FFU; \
- } \
- } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { \
- (__HANDLE__)->Mask = 0x00FFU; \
- } else { \
- (__HANDLE__)->Mask = 0x007FU; \
- } \
- } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { \
- (__HANDLE__)->Mask = 0x007FU; \
- } else { \
- (__HANDLE__)->Mask = 0x003FU; \
- } \
- } else { \
- (__HANDLE__)->Mask = 0x0000U; \
- } \
- } while (0U)
-
-/**
- * @brief Ensure that UART frame length is valid.
- * @param __LENGTH__ UART frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_UART_WORD_LENGTH(__LENGTH__) \
- (((__LENGTH__) == UART_WORDLENGTH_7B) || \
- ((__LENGTH__) == UART_WORDLENGTH_8B) || \
- ((__LENGTH__) == UART_WORDLENGTH_9B))
-
-/**
- * @brief Ensure that UART wake-up address length is valid.
- * @param __ADDRESS__ UART wake-up address length.
- * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
- */
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) \
- (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
- ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-
-/**
- * @brief Ensure that UART TXFIFO threshold level is valid.
- * @param __THRESHOLD__ UART TXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) \
- (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
-
-/**
- * @brief Ensure that UART RXFIFO threshold level is valid.
- * @param __THRESHOLD__ UART RXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) \
- (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_HAL_UART_EX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_uart_ex.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_UART_EX_H
+#define STM32G4xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct {
+ uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from
+ Stop mode flag (WUF). This parameter can be a value
+ of @ref UART_WakeUp_from_Stop_Selection. If set to
+ UART_WAKEUP_ON_ADDRESS, the two other fields below
+ must be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref
+ UARTEx_WakeUp_Address_Length. */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+ * @{
+ */
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+ * @{
+ */
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B \
+ USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+ * @brief UART FIFO mode
+ * @{
+ */
+#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+ * @brief UART TXFIFO threshold level
+ * @{
+ */
+#define UART_TXFIFO_THRESHOLD_1_8 \
+ 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4 \
+ USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2 \
+ USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4 \
+ (USART_CR3_TXFTCFG_0 | \
+ USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8 \
+ USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8 \
+ (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+ * @brief UART RXFIFO threshold level
+ * @{
+ */
+#define UART_RXFIFO_THRESHOLD_1_8 \
+ 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4 \
+ USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2 \
+ USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4 \
+ (USART_CR3_RXFTCFG_0 | \
+ USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8 \
+ USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8 \
+ (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
+ uint32_t AssertionTime,
+ uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(
+ UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(
+ UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart,
+ uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart,
+ uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size,
+ uint16_t *RxLen, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size);
+
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(
+ const UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the UART clock source.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(UART5) && defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if ((__HANDLE__)->Instance == USART1) { \
+ switch (__HAL_RCC_GET_USART1_SOURCE()) { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART2) { \
+ switch (__HAL_RCC_GET_USART2_SOURCE()) { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART3) { \
+ switch (__HAL_RCC_GET_USART3_SOURCE()) { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == UART4) { \
+ switch (__HAL_RCC_GET_UART4_SOURCE()) { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == UART5) { \
+ switch (__HAL_RCC_GET_UART5_SOURCE()) { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == LPUART1) { \
+ switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while (0U)
+#elif defined(UART5) && !defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if ((__HANDLE__)->Instance == USART1) { \
+ switch (__HAL_RCC_GET_USART1_SOURCE()) { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART2) { \
+ switch (__HAL_RCC_GET_USART2_SOURCE()) { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == UART4) { \
+ switch (__HAL_RCC_GET_UART4_SOURCE()) { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == UART5) { \
+ switch (__HAL_RCC_GET_UART5_SOURCE()) { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == LPUART1) { \
+ switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while (0U)
+#elif defined(UART4) && defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if ((__HANDLE__)->Instance == USART1) { \
+ switch (__HAL_RCC_GET_USART1_SOURCE()) { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART2) { \
+ switch (__HAL_RCC_GET_USART2_SOURCE()) { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART3) { \
+ switch (__HAL_RCC_GET_USART3_SOURCE()) { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == UART4) { \
+ switch (__HAL_RCC_GET_UART4_SOURCE()) { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == LPUART1) { \
+ switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while (0U)
+#elif defined(UART4) && !defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if ((__HANDLE__)->Instance == USART1) { \
+ switch (__HAL_RCC_GET_USART1_SOURCE()) { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART2) { \
+ switch (__HAL_RCC_GET_USART2_SOURCE()) { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == UART4) { \
+ switch (__HAL_RCC_GET_UART4_SOURCE()) { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == LPUART1) { \
+ switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while (0U)
+#elif defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if ((__HANDLE__)->Instance == USART1) { \
+ switch (__HAL_RCC_GET_USART1_SOURCE()) { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART2) { \
+ switch (__HAL_RCC_GET_USART2_SOURCE()) { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART3) { \
+ switch (__HAL_RCC_GET_USART3_SOURCE()) { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == LPUART1) { \
+ switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while (0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if ((__HANDLE__)->Instance == USART1) { \
+ switch (__HAL_RCC_GET_USART1_SOURCE()) { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == USART2) { \
+ switch (__HAL_RCC_GET_USART2_SOURCE()) { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else if ((__HANDLE__)->Instance == LPUART1) { \
+ switch (__HAL_RCC_GET_LPUART1_SOURCE()) { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } else { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while (0U)
+#endif /* UART5 && !USART3 */
+
+/** @brief Report the UART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in
+ * (__HANDLE__)->Mask field.
+ */
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { \
+ (__HANDLE__)->Mask = 0x01FFU; \
+ } else { \
+ (__HANDLE__)->Mask = 0x00FFU; \
+ } \
+ } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { \
+ (__HANDLE__)->Mask = 0x00FFU; \
+ } else { \
+ (__HANDLE__)->Mask = 0x007FU; \
+ } \
+ } else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) { \
+ (__HANDLE__)->Mask = 0x007FU; \
+ } else { \
+ (__HANDLE__)->Mask = 0x003FU; \
+ } \
+ } else { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while (0U)
+
+/**
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__ UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_WORD_LENGTH(__LENGTH__) \
+ (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+ * @brief Ensure that UART wake-up address length is valid.
+ * @param __ADDRESS__ UART wake-up address length.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) \
+ (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+ * @brief Ensure that UART TXFIFO threshold level is valid.
+ * @param __THRESHOLD__ UART TXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) \
+ (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+ * @brief Ensure that UART RXFIFO threshold level is valid.
+ * @param __THRESHOLD__ UART RXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) \
+ (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_UART_EX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
index 978b95c..51b80b0 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
@@ -1,9904 +1,9700 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_ADC_H
-#define STM32G4xx_LL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(ADC1) || defined(ADC2) || defined(ADC3) || defined(ADC4) || \
- defined(ADC5)
-
-/** @defgroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Constants ADC Private Constants
- * @{
- */
-
-/* Internal mask for ADC group regular sequencer: */
-/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
-/* - sequencer register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group regular sequencer configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET (0x00000000UL)
-#define ADC_SQR2_REGOFFSET (0x00000100UL)
-#define ADC_SQR3_REGOFFSET (0x00000200UL)
-#define ADC_SQR4_REGOFFSET (0x00000300UL)
-
-#define ADC_REG_SQRX_REGOFFSET_MASK \
- (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | \
- ADC_SQR4_REGOFFSET)
-#define ADC_SQRX_REGOFFSET_POS \
- (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK \
- */
-#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group regular sequencer bits information to be inserted */
-/* into ADC group regular sequencer ranks literals definition. */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
-
-/* Internal mask for ADC group injected sequencer: */
-/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
-/* - data register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group injected data register */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET (0x00000000UL)
-#define ADC_JDR2_REGOFFSET (0x00000100UL)
-#define ADC_JDR3_REGOFFSET (0x00000200UL)
-#define ADC_JDR4_REGOFFSET (0x00000300UL)
-
-#define ADC_INJ_JDRX_REGOFFSET_MASK \
- (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | \
- ADC_JDR4_REGOFFSET)
-#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-#define ADC_JDRX_REGOFFSET_POS \
- (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK \
- */
-
-/* Definition of ADC group injected sequencer bits information to be inserted */
-/* into ADC group injected sequencer ranks literals definition. */
-#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
-#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
-#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
-#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
-
-/* Internal mask for ADC group regular trigger: */
-/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
-/* - regular trigger source */
-/* - regular trigger edge */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT \
- (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for \
- compatibility with some ADC on other STM32 families \
- having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_SOURCE_MASK \
- (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
- ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
- ((ADC_CFGR_EXTSEL) << (4U * 3UL)))
-
-/* Mask containing trigger edge masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_EDGE_MASK \
- (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)))
-
-/* Definition of ADC group regular trigger bits information. */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
-
-/* Internal mask for ADC group injected trigger: */
-/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
-/* - injected trigger source */
-/* - injected trigger edge */
-#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT \
- (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for \
- compatibility with some ADC on other STM32 families \
- having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_SOURCE_MASK \
- (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 3UL)))
-
-/* Mask containing trigger edge masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_EDGE_MASK \
- (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)))
-
-/* Definition of ADC group injected trigger bits information. */
-#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
-#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
-
-/* Internal mask for ADC channel: */
-/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
-/* - channel identifier defined by number */
-/* - channel identifier defined by bitfield */
-/* - channel differentiation between external channels (connected to */
-/* GPIO pins) and internal channels (connected to internal paths) */
-/* - channel sampling time defined by SMPRx register offset */
-/* and SMPx bits positions into SMPRx register */
-#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
-#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
-#define ADC_CHANNEL_ID_MASK \
- (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
- ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 \
- (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position \
- of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
-
-/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH \
- (0x80000000UL) /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_2 \
- (0x00080000UL) /* Marker of internal channel for other ADC instances, in \
- case of different ADC internal channels mapped on same \
- channel number on different ADC instances */
-#define ADC_CHANNEL_ID_INTERNAL_CH_MASK \
- (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
-
-/* Internal register offset for ADC channel sampling time configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET (0x00000000UL)
-#define ADC_SMPR2_REGOFFSET (0x02000000UL)
-#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK \
- (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
-#define ADC_SMPRX_REGOFFSET_POS \
- (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in \
- ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
-
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS \
- (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" \
- position in register */
-
-/* Definition of channels ID number information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
-#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
-#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
-#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
-#define ADC_CHANNEL_7_NUMBER \
- (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
-#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
-#define ADC_CHANNEL_11_NUMBER \
- (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
-#define ADC_CHANNEL_13_NUMBER \
- (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_14_NUMBER \
- (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
-#define ADC_CHANNEL_15_NUMBER \
- (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | \
- ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
-#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
-
-/* Definition of channels ID bitfield information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
-#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
-#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
-#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
-#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
-#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
-#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
-#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
-#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
-#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
-#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
-#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
-#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
-#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
-#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
-#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
-#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
-#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
-#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
-
-/* Definition of channels sampling time information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP0" \
- position in register */
-#define ADC_CHANNEL_1_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP1" \
- position in register */
-#define ADC_CHANNEL_2_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP2" \
- position in register */
-#define ADC_CHANNEL_3_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP3" \
- position in register */
-#define ADC_CHANNEL_4_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP4" \
- position in register */
-#define ADC_CHANNEL_5_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP5" \
- position in register */
-#define ADC_CHANNEL_6_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP6" \
- position in register */
-#define ADC_CHANNEL_7_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP7" \
- position in register */
-#define ADC_CHANNEL_8_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP8" \
- position in register */
-#define ADC_CHANNEL_9_SMP \
- (ADC_SMPR1_REGOFFSET | \
- ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR1_SMP9" \
- position in register */
-#define ADC_CHANNEL_10_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR2_SMP10" \
- position in register */
-#define ADC_CHANNEL_11_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR2_SMP11" \
- position in register */
-#define ADC_CHANNEL_12_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR2_SMP12" \
- position in register */
-#define ADC_CHANNEL_13_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent \
- to bitfield "ADC_SMPR2_SMP13" \
- position in register */
-#define ADC_CHANNEL_14_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((12UL) \
- << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to \
- bitfield "ADC_SMPR2_SMP14" position \
- in register */
-#define ADC_CHANNEL_15_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((15UL) \
- << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to \
- bitfield "ADC_SMPR2_SMP15" position \
- in register */
-#define ADC_CHANNEL_16_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((18UL) \
- << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to \
- bitfield "ADC_SMPR2_SMP16" position \
- in register */
-#define ADC_CHANNEL_17_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((21UL) \
- << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to \
- bitfield "ADC_SMPR2_SMP17" position \
- in register */
-#define ADC_CHANNEL_18_SMP \
- (ADC_SMPR2_REGOFFSET | \
- ((24UL) \
- << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to \
- bitfield "ADC_SMPR2_SMP18" position \
- in register */
-
-/* Internal mask for ADC mode single or differential ended: */
-/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
-/* the relevant bits for: */
-/* (concatenation of multiple bits used in different registers) */
-/* - ADC calibration: calibration start, calibration factor get or set */
-/* - ADC channels: set each ADC channel ending mode */
-#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
-#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK \
- (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
-#define ADC_SINGLEDIFF_CHANNEL_MASK \
- (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
-#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK \
- (ADC_CALFACT_CALFACT_S_4 | \
- ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single \
- mode is selected, shift value out of channels \
- bits range. */
-#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK \
- (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask \
- of bit */
-#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS \
- (16UL) /* Selection of 1 bit to discriminate differential mode: position of \
- bit */
-#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 \
- (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - \
- 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a \
- shift of 4 ranks */
-
-/* Internal mask for ADC analog watchdog: */
-/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
-/* (concatenation of multiple bits used in different analog watchdogs, */
-/* (feature of several watchdogs not available on all STM32 families)). */
-/* - analog watchdog 1: monitored channel defined by number, */
-/* selection of ADC group (ADC groups regular and-or injected). */
-/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
-/* selection on groups. */
-
-/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
-#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
-#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
-
-/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
-/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
-#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
-#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
-
-#define ADC_AWD_CRX_REGOFFSET_MASK \
- (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
-
-#define ADC_AWD_CR1_CHANNEL_MASK \
- (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
-#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
-#define ADC_AWD_CR_ALL_CHANNEL_MASK \
- (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
-
-#define ADC_AWD_CRX_REGOFFSET_POS \
- (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in \
- ADC_AWD_CRX_REGOFFSET_MASK */
-
-/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
-#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
-#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
-#define ADC_AWD_TRX_REGOFFSET_MASK \
- (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
-#define ADC_AWD_TRX_REGOFFSET_POS \
- (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in \
- ADC_AWD_TRX_REGOFFSET_MASK */
-#define ADC_AWD_TRX_BIT_HIGH_MASK \
- (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of \
- bit */
-#define ADC_AWD_TRX_BIT_HIGH_POS \
- (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit \
- */
-#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 \
- (ADC_AWD_TRX_BIT_HIGH_POS - \
- 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of \
- 4 ranks */
-
-/* Internal mask for ADC offset: */
-/* Internal register offset for ADC offset number configuration */
-#define ADC_OFR1_REGOFFSET (0x00000000UL)
-#define ADC_OFR2_REGOFFSET (0x00000001UL)
-#define ADC_OFR3_REGOFFSET (0x00000002UL)
-#define ADC_OFR4_REGOFFSET (0x00000003UL)
-#define ADC_OFRx_REGOFFSET_MASK \
- (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | \
- ADC_OFR4_REGOFFSET)
-
-/* ADC registers bits positions */
-#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
-#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
-#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
-#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
-#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
-
-/* ADC registers bits groups */
-#define ADC_CR_BITS_PROPERTY_RS \
- (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \
- ADC_CR_ADSTART | ADC_CR_ADDIS | \
- ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can \
- read as well as set this bit. Writing '0' has no effect on \
- the bit value. */
-
-/* ADC internal channels related definitions */
-/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR \
- ((uint16_t \
- *)(0x1FFF75AAUL)) /* Internal voltage reference, address of parameter \
- VREFINT_CAL: VrefInt ADC raw data acquired at \
- temperature 30 DegC (tolerance: +-5 DegC), Vref+ \
- = 3.0 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF \
- (3000UL) /* Analog voltage reference (Vref+) value with which temperature \
- sensor has been calibrated in production (tolerance: +-10 mV) \
- (unit: mV). */
-/* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR \
- ((uint16_t \
- *)(0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter \
- TS_CAL1: On STM32G4, temperature sensor ADC raw \
- data acquired at temperature 30 DegC (tolerance: \
- +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR \
- ((uint16_t \
- *)(0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter \
- TS_CAL2: On STM32G4, temperature sensor ADC raw \
- data acquired at temperature 110 DegC (tolerance: \
- +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL1_TEMP \
- (30L) /* Internal temperature sensor, temperature at which temperature \
- sensor has been calibrated in production for data into \
- TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP \
- (130L) /* Internal temperature sensor, temperature at which temperature \
- sensor has been calibrated in production for data into \
- TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG \
- (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature \
- sensor has been calibrated in production (+-10 mV) (unit: mV). \
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
- */
-#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((__IO uint32_t *)((uint32_t)((uint32_t)(&(__REG__)) + \
- ((__REG_OFFFSET__) << 2UL))))
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of ADC common parameters
- * and multimode
- * (all ADC instances belonging to the same ADC common instance).
- * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
- * is conditioned to ADC instances state (all ADC instances
- * sharing the same ADC common instance):
- * All ADC instances sharing the same ADC common instance must be
- * disabled.
- */
-typedef struct {
- uint32_t
- CommonClock; /*!< Set parameter common to several ADC: Clock source and
- prescaler. This parameter can be a value of @ref
- ADC_LL_EC_COMMON_CLOCK_SOURCE
- @note On this STM32 series, if ADC group injected is
- used, some clock ratio constraints between ADC clock and
- AHB clock must be respected. Refer to reference manual.
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_SetCommonClock(). */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- uint32_t
- Multimode; /*!< Set ADC multimode configuration to operate in independent
- mode or multimode (for devices with several ADC instances).
- This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_SetMultimode(). */
-
- uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no
- transfer or transfer by DMA. This parameter can
- be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_ADC_SetMultiDMATransfer(). */
-
- uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2
- sampling phases. This parameter can be a
- value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
-
- This feature can be modified afterwards
- using unitary function @ref
- LL_ADC_SetMultiTwoSamplingDelay(). */
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-} LL_ADC_CommonInitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct {
- uint32_t Resolution; /*!< Set ADC resolution.
- This parameter can be a value of @ref
- ADC_LL_EC_RESOLUTION
-
- This feature can be modified afterwards using
- unitary function @ref LL_ADC_SetResolution(). */
-
- uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
- This parameter can be a value of @ref
- ADC_LL_EC_DATA_ALIGN
-
- This feature can be modified afterwards using
- unitary function @ref LL_ADC_SetDataAlignment(). */
-
- uint32_t
- LowPowerMode; /*!< Set ADC low power mode.
- This parameter can be a value of @ref ADC_LL_EC_LP_MODE
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_SetLowPowerMode(). */
-
-} LL_ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct {
- uint32_t
- TriggerSource; /*!< Set ADC group regular conversion trigger source:
- internal (SW start) or from external peripheral (timer
- event, external interrupt line). This parameter can be a
- value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 series, setting trigger source to
- external trigger also set trigger polarity to rising
- edge (default setting for compatibility with some ADC on
- other STM32 families having this setting set by HW
- default value). In case of need to modify trigger edge,
- use function @ref LL_ADC_REG_SetTriggerEdge().
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_REG_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- This parameter can be a value of @ref
- ADC_LL_EC_REG_SEQ_SCAN_LENGTH
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_ADC_REG_SetSequencerLength(). */
-
- uint32_t
- SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode:
- sequence subdivided and scan conversions interrupted
- every selected number of ranks. This parameter can be
- a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group
- regular sequencer is enabled (scan length of 2 ranks
- or more).
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_ADC_REG_SetSequencerDiscont(). */
-
- uint32_t
- ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group
- regular, whether ADC conversions are performed in
- single mode (one conversion per trigger) or in
- continuous mode (after the first trigger, following
- conversions launched successively automatically). This
- parameter can be a value of @ref
- ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible
- to enable both ADC group regular continuous mode and
- discontinuous mode.
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_REG_SetContinuousMode(). */
-
- uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no
- transfer or transfer by DMA, and DMA requests mode.
- This parameter can be a value of @ref
- ADC_LL_EC_REG_DMA_TRANSFER
-
- This feature can be modified afterwards using
- unitary function @ref LL_ADC_REG_SetDMATransfer(). */
-
- uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
- data preserved or overwritten.
- This parameter can be a value of @ref
- ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_REG_SetOverrun(). */
-
-} LL_ADC_REG_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct {
- uint32_t
- TriggerSource; /*!< Set ADC group injected conversion trigger source:
- internal (SW start) or from external peripheral (timer
- event, external interrupt line). This parameter can be a
- value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 series, setting trigger source to
- external trigger also set trigger polarity to rising
- edge (default setting for compatibility with some ADC on
- other STM32 families having this setting set by HW
- default value). In case of need to modify trigger edge,
- use function @ref LL_ADC_INJ_SetTriggerEdge().
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_INJ_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
- This parameter can be a value of @ref
- ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_ADC_INJ_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous
- mode: sequence subdivided and scan conversions
- interrupted every selected number of ranks. This
- parameter can be a value of @ref
- ADC_LL_EC_INJ_SEQ_DISCONT_MODE
- @note This parameter has an effect only if
- group injected sequencer is enabled (scan length
- of 2 ranks or more).
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_ADC_INJ_SetSequencerDiscont(). */
-
- uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent
- or from ADC group regular. This parameter can be a value
- of @ref ADC_LL_EC_INJ_TRIG_AUTO Note: This parameter
- must be set to set to independent trigger if injected
- trigger source is set to an external trigger.
-
- This feature can be modified afterwards using unitary
- function @ref LL_ADC_INJ_SetTrigAuto(). */
-
-} LL_ADC_INJ_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_LL_EC_FLAG ADC flags
- * @brief Flags defines which can be used with LL_ADC_ReadReg function
- * @{
- */
-#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
-#define LL_ADC_FLAG_EOC \
- ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
-#define LL_ADC_FLAG_EOS \
- ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
-#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
-#define LL_ADC_FLAG_EOSMP \
- ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
-#define LL_ADC_FLAG_JEOC \
- ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
-#define LL_ADC_FLAG_JEOS \
- ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
-#define LL_ADC_FLAG_JQOVF \
- ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
-#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
-#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
-#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_FLAG_ADRDY_MST \
- ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
-#define LL_ADC_FLAG_ADRDY_SLV \
- ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
-#define LL_ADC_FLAG_EOC_MST \
- ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of \
- unitary conversion */
-#define LL_ADC_FLAG_EOC_SLV \
- ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of \
- unitary conversion */
-#define LL_ADC_FLAG_EOS_MST \
- ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of \
- sequence conversions */
-#define LL_ADC_FLAG_EOS_SLV \
- ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of \
- sequence conversions */
-#define LL_ADC_FLAG_OVR_MST \
- ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
-#define LL_ADC_FLAG_OVR_SLV \
- ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
-#define LL_ADC_FLAG_EOSMP_MST \
- ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of \
- sampling phase */
-#define LL_ADC_FLAG_EOSMP_SLV \
- ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of \
- sampling phase */
-#define LL_ADC_FLAG_JEOC_MST \
- ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of \
- unitary conversion */
-#define LL_ADC_FLAG_JEOC_SLV \
- ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of \
- unitary conversion */
-#define LL_ADC_FLAG_JEOS_MST \
- ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of \
- sequence conversions */
-#define LL_ADC_FLAG_JEOS_SLV \
- ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of \
- sequence conversions */
-#define LL_ADC_FLAG_JQOVF_MST \
- ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts \
- queue overflow */
-#define LL_ADC_FLAG_JQOVF_SLV \
- ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts \
- queue overflow */
-#define LL_ADC_FLAG_AWD1_MST \
- ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the \
- ADC master */
-#define LL_ADC_FLAG_AWD1_SLV \
- ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the \
- ADC slave */
-#define LL_ADC_FLAG_AWD2_MST \
- ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the \
- ADC master */
-#define LL_ADC_FLAG_AWD2_SLV \
- ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the \
- ADC slave */
-#define LL_ADC_FLAG_AWD3_MST \
- ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the \
- ADC master */
-#define LL_ADC_FLAG_AWD3_SLV \
- ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the \
- ADC slave */
-#endif /* ADC_MULTIMODE_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption
- * enable or disable)
- * @brief IT defines which can be used with LL_ADC_ReadReg and
- * LL_ADC_WriteReg functions
- * @{
- */
-#define LL_ADC_IT_ADRDY \
- ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
-#define LL_ADC_IT_EOC \
- ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary \
- conversion */
-#define LL_ADC_IT_EOS \
- ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence \
- conversions */
-#define LL_ADC_IT_OVR \
- ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_EOSMP \
- ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling \
- phase */
-#define LL_ADC_IT_JEOC \
- ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary \
- conversion */
-#define LL_ADC_IT_JEOS \
- ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence \
- conversions */
-#define LL_ADC_IT_JQOVF \
- ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue \
- overflow */
-#define LL_ADC_IT_AWD1 \
- ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
-#define LL_ADC_IT_AWD2 \
- ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
-#define LL_ADC_IT_AWD3 \
- ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
- * @{
- */
-/* List of ADC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA \
- (0x00000000UL) /* ADC group regular conversion data register (corresponding \
- to register DR) to be used with ADC configured in \
- independent mode. Without DMA transfer, register accessed \
- by LL function @ref LL_ADC_REG_ReadConversionData32() and \
- other functions @ref LL_ADC_REG_ReadConversionDatax() */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI \
- (0x00000001UL) /* ADC group regular conversion data register (corresponding \
- to register CDR) to be used with ADC configured in \
- multimode (available on STM32 devices with several ADC \
- instances). Without DMA transfer, register accessed by LL \
- function @ref LL_ADC_REG_ReadMultiConversionData32() */
-#endif /* ADC_MULTIMODE_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
- * @{
- */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 \
- (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without \
- prescaler */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 \
- (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock with \
- prescaler division by 2 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 \
- (ADC_CCR_CKMODE_1 | \
- ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with \
- prescaler division by 4 */
-#define LL_ADC_CLOCK_ASYNC_DIV1 \
- (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
-#define LL_ADC_CLOCK_ASYNC_DIV2 \
- (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 \
- */
-#define LL_ADC_CLOCK_ASYNC_DIV4 \
- (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 4 \
- */
-#define LL_ADC_CLOCK_ASYNC_DIV6 \
- (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
- prescaler division by 6 */
-#define LL_ADC_CLOCK_ASYNC_DIV8 \
- (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with prescaler division by 8 \
- */
-#define LL_ADC_CLOCK_ASYNC_DIV10 \
- (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
- prescaler division by 10 */
-#define LL_ADC_CLOCK_ASYNC_DIV12 \
- (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with \
- prescaler division by 12 */
-#define LL_ADC_CLOCK_ASYNC_DIV16 \
- (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | \
- ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 \
- */
-#define LL_ADC_CLOCK_ASYNC_DIV32 \
- (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 \
- */
-#define LL_ADC_CLOCK_ASYNC_DIV64 \
- (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
- prescaler division by 64 */
-#define LL_ADC_CLOCK_ASYNC_DIV128 \
- (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with \
- prescaler division by 128 */
-#define LL_ADC_CLOCK_ASYNC_DIV256 \
- (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | \
- ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to
- * internal channels
- * @{
- */
-/* Note: Other measurement paths to internal channels may be available */
-/* (connections to other peripherals). */
-/* If they are not listed below, they do not require any specific */
-/* path enable. In this case, Access to measurement path is done */
-/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE \
- (0x00000000UL) /*!< ADC measurement paths all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT \
- (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR \
- (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel \
- temperature sensor */
-#define LL_ADC_PATH_INTERNAL_VBAT \
- (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
- * @{
- */
-#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_10B (ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
-#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1) /*!< ADC resolution 8 bits */
-#define LL_ADC_RESOLUTION_6B \
- (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
- * @{
- */
-#define LL_ADC_DATA_ALIGN_RIGHT \
- (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment \
- on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT \
- (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment \
- on data register MSB bit 15)*/
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
- * @{
- */
-#define LL_ADC_LP_MODE_NONE \
- (0x00000000UL) /*!< No ADC low power mode activated */
-#define LL_ADC_LP_AUTOWAIT \
- (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power \
- mode, ADC conversions are performed only when necessary \
- (when previous ADC conversion data is read). See \
- description with function @ref \
- LL_ADC_SetLowPowerMode(). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
- * @{
- */
-#define LL_ADC_OFFSET_1 \
- ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-#define LL_ADC_OFFSET_2 \
- ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-#define LL_ADC_OFFSET_3 \
- ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-#define LL_ADC_OFFSET_4 \
- ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to \
- which the offset programmed will be applied \
- (independently of channel mapped on ADC group regular \
- or group injected) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
- * @{
- */
-#define LL_ADC_OFFSET_DISABLE \
- (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, \
- 2, 3 or 4) */
-#define LL_ADC_OFFSET_ENABLE \
- (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset \
- number 1, 2, 3 or 4) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
- * @{
- */
-#define LL_ADC_OFFSET_SIGN_NEGATIVE \
- (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number \
- 1, 2, 3 or 4) */
-#define LL_ADC_OFFSET_SIGN_POSITIVE \
- (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset \
- number 1, 2, 3 or 4) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
- * @{
- */
-#define LL_ADC_OFFSET_SATURATION_DISABLE \
- (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected \
- offset number 1, 2, 3 or 4) */
-#define LL_ADC_OFFSET_SATURATION_ENABLE \
- (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected \
- offset number 1, 2, 3 or 4) */
-/**
- * @}
- */
-/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
- * @{
- */
-#define LL_ADC_GROUP_REGULAR \
- (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED \
- (0x00000002UL) /*!< ADC group injected (not available on all STM32 \
- devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED \
- (0x00000003UL) /*!< ADC both groups regular and injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
- * @{
- */
-#define LL_ADC_CHANNEL_0 \
- (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | \
- ADC_CHANNEL_0_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN0 */
-#define LL_ADC_CHANNEL_1 \
- (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | \
- ADC_CHANNEL_1_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN1 */
-#define LL_ADC_CHANNEL_2 \
- (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | \
- ADC_CHANNEL_2_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN2 */
-#define LL_ADC_CHANNEL_3 \
- (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | \
- ADC_CHANNEL_3_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN3 */
-#define LL_ADC_CHANNEL_4 \
- (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | \
- ADC_CHANNEL_4_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN4 */
-#define LL_ADC_CHANNEL_5 \
- (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | \
- ADC_CHANNEL_5_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN5 */
-#define LL_ADC_CHANNEL_6 \
- (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | \
- ADC_CHANNEL_6_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN6 */
-#define LL_ADC_CHANNEL_7 \
- (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | \
- ADC_CHANNEL_7_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN7 */
-#define LL_ADC_CHANNEL_8 \
- (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | \
- ADC_CHANNEL_8_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN8 */
-#define LL_ADC_CHANNEL_9 \
- (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | \
- ADC_CHANNEL_9_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN9 */
-#define LL_ADC_CHANNEL_10 \
- (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | \
- ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN10 */
-#define LL_ADC_CHANNEL_11 \
- (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | \
- ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN11 */
-#define LL_ADC_CHANNEL_12 \
- (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | \
- ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN12 */
-#define LL_ADC_CHANNEL_13 \
- (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | \
- ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN13 */
-#define LL_ADC_CHANNEL_14 \
- (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | \
- ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN14 */
-#define LL_ADC_CHANNEL_15 \
- (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | \
- ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN15 */
-#define LL_ADC_CHANNEL_16 \
- (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
- ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN16 */
-#define LL_ADC_CHANNEL_17 \
- (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
- ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN17 */
-#define LL_ADC_CHANNEL_18 \
- (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
- ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to \
- GPIO pin) ADCx_IN18 */
-#define LL_ADC_CHANNEL_VREFINT \
- (LL_ADC_CHANNEL_18 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: \
- Internal voltage reference. On this STM32 \
- series, ADC channel available on all \
- instances but ADC2. */
-#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 \
- (LL_ADC_CHANNEL_16 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to \
- Temperature sensor. On this STM32 series, \
- ADC channel available only on ADC1 instance. \
- */
-#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 \
- (LL_ADC_CHANNEL_4 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to \
- Temperature sensor. On this STM32 series, \
- ADC channel available only on ADC5 instance. \
- Refer to device datasheet for ADC5 \
- availaibility */
-#define LL_ADC_CHANNEL_VBAT \
- (LL_ADC_CHANNEL_17 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: \
- Vbat voltage through a divider ladder of \
- factor 1/3 to have Vbat always below Vdda. \
- On this STM32 series, ADC channel available \
- on all ADC instances but ADC2 & ADC4. Refer \
- to device datasheet for ADC4 availaibility \
- */
-#define LL_ADC_CHANNEL_VOPAMP1 \
- (LL_ADC_CHANNEL_13 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 \
- output. On this STM32 series, ADC channel \
- available only on ADC1 instance. */
-#define LL_ADC_CHANNEL_VOPAMP2 \
- (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \
- ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 \
- output. On this STM32 series, ADC channel \
- available only on ADC2 instance. */
-#define LL_ADC_CHANNEL_VOPAMP3_ADC2 \
- (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
- ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 \
- output. On this STM32 series, ADC channel \
- available only on ADC2 instance. */
-#define LL_ADC_CHANNEL_VOPAMP3_ADC3 \
- (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \
- ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 \
- output. On this STM32 series, ADC channel \
- available only on ADC3 instance. Refer to \
- device datasheet for ADC3 availability */
-#define LL_ADC_CHANNEL_VOPAMP4 \
- (LL_ADC_CHANNEL_5 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 \
- output. On this STM32 series, ADC channel \
- available only on ADC5 instance. Refer to \
- device datasheet for ADC5 & OPAMP4 \
- availability */
-#define LL_ADC_CHANNEL_VOPAMP5 \
- (LL_ADC_CHANNEL_3 | \
- ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 \
- output. On this STM32 series, ADC channel \
- available only on ADC5 instance. Refer to \
- device datasheet for ADC5 & OPAMP5 \
- availability */
-#define LL_ADC_CHANNEL_VOPAMP6 \
- (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
- ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 \
- output. On this STM32 series, ADC channel \
- available only on ADC4 instance. Refer to \
- device datasheet for ADC4 & OPAMP6 \
- availability */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
- * @{
- */
-#define LL_ADC_REG_TRIG_SOFTWARE \
- (0x00000000UL) /*!< \
-ADC group regular conversion trigger internal: SW start. */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM1 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 \
- (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM1 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 \
- (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM1 channel 2 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 \
- (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM1 channel 3 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM2 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH1 \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
- ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM2 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 \
- (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM2 channel 2 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 \
- (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM2 channel 3 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO \
- (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM3 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 \
- (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM3 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
- ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM3 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM4 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH1 \
- (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM4 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 \
- (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM4 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM6 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
- ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM7 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO \
- (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM8 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 \
- (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 \
- (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM8 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO \
- (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM15 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO \
- (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM20 TRGO. \
-Trigger edge set to rising edge (default setting). Note: On this STM32 series, \
-TIM20 is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. \
-Trigger edge set to rising edge (default setting). Note: On this STM32 series, \
-TIM20 is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH1 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM20 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, TIM20 is not \
-available on all devices. Refer to device datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH2 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM20 channel 2 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances, and TIM20 is not available on all devices. \
-Refer to device datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH3 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: TIM20 channel 3 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances, and TIM20 is not available on all devices. \
-Refer to device datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 1 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 2 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC3/4/5 instances, and \
-HRTIM is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 3 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 4 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC3/4/5 instances, and \
-HRTIM is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
- ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 5 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 6 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 7 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 8 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
- ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 9 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
- ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: HRTIMER ADC \
-trigger 10 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 \
- (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: external \
-interrupt line 11. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC1/2 instances */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 \
- (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: external \
-interrupt line 2. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer \
-to device datasheet for ADCx availaibility */
-#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT \
- (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
- ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group regular conversion trigger from external peripheral: LPTIMER OUT \
-event. Trigger edge set to rising edge (default setting). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
- * @{
- */
-#define LL_ADC_REG_TRIG_EXT_RISING \
- (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to \
- rising edge */
-#define LL_ADC_REG_TRIG_EXT_FALLING \
- (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion trigger polarity set to \
- falling edge */
-#define LL_ADC_REG_TRIG_EXT_RISINGFALLING \
- (ADC_CFGR_EXTEN_1 | \
- ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to \
- both rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
- * @{
- */
-#define LL_ADC_REG_SAMPLING_MODE_NORMAL \
- (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using \
- @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
-#define LL_ADC_REG_SAMPLING_MODE_BULB \
- (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately \
- after end of conversion, and stops upon trigger event. \
- Note: First conversion is using minimal sampling time \
- (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
-#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED \
- (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by \
- trigger events: Trigger rising edge = start sampling \
- Trigger falling edge = stop sampling and start \
- conversion */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
- * @{
- */
-#define LL_ADC_REG_CONV_SINGLE \
- (0x00000000UL) /*!< ADC conversions are performed in single mode: one \
- conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS \
- (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after \
- the first trigger, following conversions launched \
- successively automatically */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of
- * ADC conversion data
- * @{
- */
-#define LL_ADC_REG_DMA_TRANSFER_NONE \
- (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_LIMITED \
- (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited \
- mode (one shot mode): DMA transfer requests are stopped \
- when number of DMA data transfers (number of ADC \
- conversions) is reached. This ADC mode is intended to be \
- used with DMA mode non-circular. */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED \
- (ADC_CFGR_DMACFG | \
- ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in \
- unlimited mode: DMA transfer requests are unlimited, \
- whatever number of DMA data transferred (number of ADC \
- conversions). This ADC mode is intended to be used with \
- DMA mode circular. */
-/**
- * @}
- */
-
-#if defined(ADC_SMPR1_SMPPLUS)
-/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling
- * time common configuration
- * @{
- */
-#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT \
- (0x00000000UL) /*!< ADC sampling time let to default settings. */
-#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 \
- (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles \
- replacing 2.5 ADC clock cycles (this applies to all \
- channels mapped with selection sampling time 2.5 ADC \
- clock cycles, whatever channels mapped on ADC groups \
- regular or injected). */
-/**
- * @}
- */
-#endif
-
-/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun
- * behavior on conversion data
- * @{
- */
-#define LL_ADC_REG_OVR_DATA_PRESERVED \
- (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data \
- preserved */
-#define LL_ADC_REG_OVR_DATA_OVERWRITTEN \
- (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data \
- overwritten */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan
- * length
- * @{
- */
-#define LL_ADC_REG_SEQ_SCAN_DISABLE \
- (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to \
- sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS \
- (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS \
- (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with 3 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS \
- (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 \
- ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS \
- (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable with 5 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS \
- (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 \
- ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS \
- (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with 7 \
- ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS \
- (ADC_SQR1_L_2 | ADC_SQR1_L_1 | \
- ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS \
- (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable with 9 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with \
- 10 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with \
- 11 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_1 | \
- ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable with \
- 13 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_2 | \
- ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_2 | \
- ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with 15 ranks in the \
- sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS \
- (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | \
- ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the \
- sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer
- * discontinuous mode
- * @{
- */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE \
- (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable \
- */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK \
- (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every rank */
-#define LL_ADC_REG_SEQ_DISCONT_2RANKS \
- (ADC_CFGR_DISCNUM_0 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode \
- enabled with sequence interruption every 2 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_3RANKS \
- (ADC_CFGR_DISCNUM_1 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every 3 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_4RANKS \
- (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every 4 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_5RANKS \
- (ADC_CFGR_DISCNUM_2 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every 5 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_6RANKS \
- (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every 6 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_7RANKS \
- (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every 7 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_8RANKS \
- (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | \
- ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable \
- with sequence interruption every 8 ranks */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
- * @{
- */
-#define LL_ADC_REG_RANK_1 \
- (ADC_SQR1_REGOFFSET | \
- ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 \
- */
-#define LL_ADC_REG_RANK_2 \
- (ADC_SQR1_REGOFFSET | \
- ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 \
- */
-#define LL_ADC_REG_RANK_3 \
- (ADC_SQR1_REGOFFSET | \
- ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 \
- */
-#define LL_ADC_REG_RANK_4 \
- (ADC_SQR1_REGOFFSET | \
- ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 \
- */
-#define LL_ADC_REG_RANK_5 \
- (ADC_SQR2_REGOFFSET | \
- ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 \
- */
-#define LL_ADC_REG_RANK_6 \
- (ADC_SQR2_REGOFFSET | \
- ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 \
- */
-#define LL_ADC_REG_RANK_7 \
- (ADC_SQR2_REGOFFSET | \
- ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 \
- */
-#define LL_ADC_REG_RANK_8 \
- (ADC_SQR2_REGOFFSET | \
- ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 \
- */
-#define LL_ADC_REG_RANK_9 \
- (ADC_SQR2_REGOFFSET | \
- ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 \
- */
-#define LL_ADC_REG_RANK_10 \
- (ADC_SQR3_REGOFFSET | \
- ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 10 */
-#define LL_ADC_REG_RANK_11 \
- (ADC_SQR3_REGOFFSET | \
- ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 11 */
-#define LL_ADC_REG_RANK_12 \
- (ADC_SQR3_REGOFFSET | \
- ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 12 */
-#define LL_ADC_REG_RANK_13 \
- (ADC_SQR3_REGOFFSET | \
- ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 13 */
-#define LL_ADC_REG_RANK_14 \
- (ADC_SQR3_REGOFFSET | \
- ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 14 */
-#define LL_ADC_REG_RANK_15 \
- (ADC_SQR4_REGOFFSET | \
- ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 15 */
-#define LL_ADC_REG_RANK_16 \
- (ADC_SQR4_REGOFFSET | \
- ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank \
- 16 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
- * @{
- */
-#define LL_ADC_INJ_TRIG_SOFTWARE \
- (0x00000000UL) /*!< \
-ADC group injected conversion trigger internal: SW start.. Trigger edge set to \
-rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO \
- (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM1 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 \
- (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM1 channel 3 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 \
- (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM1 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO \
- (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM2 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 \
- (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM2 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM3 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM3 channel 1 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM3 channel 3 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 \
- (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM3 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO \
- (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM4 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 \
- (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM4 channel 3 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 \
- (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM4 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM6 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
- ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM7 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM8 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 \
- (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM8 channel 2 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC3/4/5 instances. Refer to device datasheet for ADCx \
-availaibility */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 \
- (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM8 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
- ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM15 TRGO. \
-Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
- ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM8 channel 4 \
-event (capture compare: input capture or output capture). Trigger edge set to \
-rising edge (default setting). Note: On this STM32 series, this trigger is \
-available only on ADC1/2 instances */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO \
- (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM20 TRGO. \
-Trigger edge set to rising edge (default setting). Note: On this STM32 series, \
-TIM20 is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. \
-Trigger edge set to rising edge (default setting). Note: On this STM32 series, \
-TIM20 is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM20 channel \
-2 event (capture compare: input capture or output capture). Trigger edge set \
-to rising edge (default setting). Trigger available only on ADC3/4/5 \
-instances. On this STM32 series, TIM20 is not available on all devices. Refer \
-to device datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: TIM20 channel \
-4 event (capture compare: input capture or output capture). Trigger edge set \
-to rising edge (default setting). Trigger available only on ADC1/2 instances. \
-On this STM32 series, TIM20 is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
- ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 1 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC3/4/5 instances, and \
-HRTIM is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 2 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 3 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC3/4/5 instances, and \
-HRTIM is not available on all devices. Refer to device datasheet for more \
-details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 4 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 5 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 6 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
- ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 7 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 8 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 9 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
-trigger 10 event. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, HRTIM is not available on all devices. Refer to device \
-datasheet for more details */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 \
- (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: external \
-interrupt line 3. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer \
-to device datasheet for ADCx availaibility */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 \
- (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
- ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: external \
-interrupt line 15. Trigger edge set to rising edge (default setting). Note: On \
-this STM32 series, this trigger is available only on ADC1/2 instances. */
-#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT \
- (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
- ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
-ADC group injected conversion trigger from external peripheral: LPTIMER OUT \
-event. Trigger edge set to rising edge (default setting). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
- * @{
- */
-#define LL_ADC_INJ_TRIG_EXT_RISING \
- (ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set \
- to rising edge */
-#define LL_ADC_INJ_TRIG_EXT_FALLING \
- (ADC_JSQR_JEXTEN_1) /*!< ADC group injected conversion trigger polarity set \
- to falling edge */
-#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING \
- (ADC_JSQR_JEXTEN_1 | \
- ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set \
- to both rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger
- * mode
- * @{
- */
-#define LL_ADC_INJ_TRIG_INDEPENDENT \
- (0x00000000UL) /*!< ADC group injected conversion trigger independent. \
- Setting mandatory if ADC group injected injected trigger \
- source is set to an external trigger. */
-#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR \
- (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group \
- regular. Setting compliant only with group injected \
- trigger source set to SW start, without any further \
- action on ADC group injected conversion start or stop: \
- in this case, ADC group injected is controlled only from \
- ADC group regular. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue
- * mode
- * @{
- */
-#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE \
- (0x00000000UL) /* Group injected sequence context queue is enabled and can \
- contain up to 2 contexts. When all contexts have been \
- processed, the queue maintains the last context active \
- perpetually. */
-#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY \
- (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can \
- contain up to 2 contexts. When all contexts have been \
- processed, the queue is empty and injected group triggers \
- are disabled. */
-#define LL_ADC_INJ_QUEUE_DISABLE \
- (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only \
- 1 sequence can be configured and is active perpetually. \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan
- * length
- * @{
- */
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE \
- (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to \
- sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS \
- (ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the \
- sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS \
- (ADC_JSQR_JL_1) /*!< ADC group injected sequencer enable with 3 ranks in the \
- sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS \
- (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable \
- with 4 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer
- * discontinuous mode
- * @{
- */
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE \
- (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable \
- */
-#define LL_ADC_INJ_SEQ_DISCONT_1RANK \
- (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode \
- enable with sequence interruption every rank */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
- * @{
- */
-#define LL_ADC_INJ_RANK_1 \
- (ADC_JDR1_REGOFFSET | \
- ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 \
- */
-#define LL_ADC_INJ_RANK_2 \
- (ADC_JDR2_REGOFFSET | \
- ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 \
- */
-#define LL_ADC_INJ_RANK_3 \
- (ADC_JDR3_REGOFFSET | \
- ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 \
- */
-#define LL_ADC_INJ_RANK_4 \
- (ADC_JDR4_REGOFFSET | \
- ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
- * @{
- */
-#define LL_ADC_SAMPLINGTIME_2CYCLES_5 \
- (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_6CYCLES_5 \
- (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_12CYCLES_5 \
- (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_24CYCLES_5 \
- (ADC_SMPR2_SMP10_1 | \
- ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_47CYCLES_5 \
- (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_92CYCLES_5 \
- (ADC_SMPR2_SMP10_2 | \
- ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_247CYCLES_5 \
- (ADC_SMPR2_SMP10_2 | \
- ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_640CYCLES_5 \
- (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | \
- ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or
- * differential ending
- * @{
- */
-#define LL_ADC_SINGLE_ENDED \
- (ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal \
- also used to set calibration mode) */
-#define LL_ADC_DIFFERENTIAL_ENDED \
- (ADC_CR_ADCALDIF | \
- ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal \
- also used to set calibration mode) */
-#define LL_ADC_BOTH_SINGLE_DIFF_ENDED \
- (LL_ADC_SINGLE_ENDED | \
- LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended \
- and differential (literal used only to set \
- calibration factors) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
- * @{
- */
-#define LL_ADC_AWD1 \
- (ADC_AWD_CR1_CHANNEL_MASK | \
- ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-#define LL_ADC_AWD2 \
- (ADC_AWD_CR23_CHANNEL_MASK | \
- ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
-#define LL_ADC_AWD3 \
- (ADC_AWD_CR23_CHANNEL_MASK | \
- ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
- * @{
- */
-#define LL_ADC_AWD_DISABLE \
- (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG \
- (ADC_AWD_CR23_CHANNEL_MASK | \
- ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, \
- converted by group regular only */
-#define LL_ADC_AWD_ALL_CHANNELS_INJ \
- (ADC_AWD_CR23_CHANNEL_MASK | \
- ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring of all channels, \
- converted by group injected only */
-#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ \
- (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_0_REG \
- ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN0, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_INJ \
- ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN0, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_0_REG_INJ \
- ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN0, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_1_REG \
- ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN1, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_INJ \
- ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN1, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_1_REG_INJ \
- ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN1, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_2_REG \
- ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN2, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_INJ \
- ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN2, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_2_REG_INJ \
- ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN2, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_3_REG \
- ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN3, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_INJ \
- ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN3, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_3_REG_INJ \
- ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN3, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_4_REG \
- ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN4, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_INJ \
- ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN4, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_4_REG_INJ \
- ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN4, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_5_REG \
- ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN5, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_INJ \
- ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN5, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_5_REG_INJ \
- ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN5, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_6_REG \
- ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN6, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_INJ \
- ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN6, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_6_REG_INJ \
- ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN6, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_7_REG \
- ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN7, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_INJ \
- ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN7, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_7_REG_INJ \
- ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN7, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_8_REG \
- ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN8, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_INJ \
- ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN8, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_8_REG_INJ \
- ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN8, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_9_REG \
- ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN9, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_INJ \
- ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN9, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_9_REG_INJ \
- ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN9, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_10_REG \
- ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN10, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_INJ \
- ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN10, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_10_REG_INJ \
- ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN10, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_11_REG \
- ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN11, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_INJ \
- ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN11, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_11_REG_INJ \
- ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN11, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_12_REG \
- ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN12, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_INJ \
- ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN12, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_12_REG_INJ \
- ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN12, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_13_REG \
- ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN13, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_INJ \
- ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN13, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_13_REG_INJ \
- ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN13, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_14_REG \
- ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN14, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_INJ \
- ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN14, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_14_REG_INJ \
- ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN14, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_15_REG \
- ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN15, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_INJ \
- ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN15, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_15_REG_INJ \
- ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN15, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_16_REG \
- ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN16, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_16_INJ \
- ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN16, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_16_REG_INJ \
- ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN16, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_17_REG \
- ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN17, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_INJ \
- ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN17, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_17_REG_INJ \
- ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN17, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_18_REG \
- ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN18, \
- converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_18_INJ \
- ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN18, \
- converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_18_REG_INJ \
- ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external \
- channel (channel connected to GPIO pin) ADCx_IN18, \
- converted by either group regular or injected */
-#define LL_ADC_AWD_CH_VREFINT_REG \
- ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to VrefInt: Internal voltage \
- reference, converted by group regular only */
-#define LL_ADC_AWD_CH_VREFINT_INJ \
- ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to VrefInt: Internal voltage \
- reference, converted by group injected only */
-#define LL_ADC_AWD_CH_VREFINT_REG_INJ \
- ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to VrefInt: Internal voltage \
- reference, converted by either group regular or \
- injected */
-#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG \
- ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal \
- channel connected to Temperature sensor, converted by \
- group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ \
- ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal \
- channel connected to Temperature sensor, converted by \
- group injected only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ \
- ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal \
- channel connected to Temperature sensor, converted by \
- either group regular or injected */
-#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG \
- ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal \
- channel connected to Temperature sensor, converted by \
- group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ \
- ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal \
- channel connected to Temperature sensor, converted by \
- group injected only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ \
- ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal \
- channel connected to Temperature sensor, converted by \
- either group regular or injected */
-#define LL_ADC_AWD_CH_VBAT_REG \
- ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to Vbat/3: Vbat voltage through a \
- divider ladder of factor 1/3 to have Vbat always below \
- Vdda, converted by group regular only */
-#define LL_ADC_AWD_CH_VBAT_INJ \
- ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to Vbat/3: Vbat voltage through a \
- divider ladder of factor 1/3 to have Vbat always below \
- Vdda, converted by group injected only */
-#define LL_ADC_AWD_CH_VBAT_REG_INJ \
- ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to Vbat/3: Vbat voltage through a \
- divider ladder of factor 1/3 to have Vbat always below \
- Vdda */
-#define LL_ADC_AWD_CH_VOPAMP1_REG \
- ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP1 output, channel specific \
- to ADC1, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP1_INJ \
- ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP1 output, channel specific \
- to ADC1, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP1 output, channel specific \
- to ADC1, converted by either group regular or injected \
- */
-#define LL_ADC_AWD_CH_VOPAMP2_REG \
- ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP2 output, channel specific \
- to ADC2, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP2_INJ \
- ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP2 output, channel specific \
- to ADC2, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP2 output, channel specific \
- to ADC2, converted by either group regular or injected \
- */
-#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG \
- ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP3 output, channel specific \
- to ADC2, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ \
- ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP3 output, channel specific \
- to ADC2, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP3 output, channel specific \
- to ADC2, converted by either group regular or injected \
- */
-#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG \
- ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP3 output, channel specific \
- to ADC3, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ \
- ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP3 output, channel specific \
- to ADC3, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP3 output, channel specific \
- to ADC3, converted by either group regular or injected \
- */
-#define LL_ADC_AWD_CH_VOPAMP4_REG \
- ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP4 output, channel specific \
- to ADC5, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP4_INJ \
- ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP4 output, channel specific \
- to ADC5, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP4 output, channel specific \
- to ADC5, converted by either group regular or injected \
- */
-#define LL_ADC_AWD_CH_VOPAMP5_REG \
- ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP5 output, channel specific \
- to ADC5, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP5_INJ \
- ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP5 output, channel specific \
- to ADC5, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP5 output, channel specific \
- to ADC5, converted by either group regular or injected \
- */
-#define LL_ADC_AWD_CH_VOPAMP6_REG \
- ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP6 output, channel specific \
- to ADC4, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP6_INJ \
- ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP6 output, channel specific \
- to ADC4, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ \
- ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal \
- channel connected to OPAMP6 output, channel specific \
- to ADC4, converted by either group regular or injected \
- */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
- * @{
- */
-#define LL_ADC_AWD_THRESHOLD_HIGH \
- (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW \
- (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
-#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW \
- (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high \
- and low concatenated into the same data */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
- * @{
- */
-#define LL_ADC_AWD_FILTERING_NONE \
- (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window \
- sample is needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_2SAMPLES \
- (ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_3SAMPLES \
- (ADC_TR1_AWDFILT_1) /*!< ADC analog wathdog 3 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_4SAMPLES \
- (ADC_TR1_AWDFILT_1 | \
- ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_5SAMPLES \
- (ADC_TR1_AWDFILT_2) /*!< ADC analog wathdog 5 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_6SAMPLES \
- (ADC_TR1_AWDFILT_2 | \
- ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_7SAMPLES \
- (ADC_TR1_AWDFILT_2 | \
- ADC_TR1_AWDFILT_1) /*!< ADC analog wathdog 7 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-#define LL_ADC_AWD_FILTERING_8SAMPLES \
- (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | \
- ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window \
- samples are needed to raise flag or interrupt */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
- * @{
- */
-#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
-#define LL_ADC_OVS_GRP_REGULAR_CONTINUED \
- (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. \
- If group injected interrupts group regular: when ADC \
- group injected is triggered, the oversampling on ADC \
- group regular is temporary stopped and continued \
- afterwards. */
-#define LL_ADC_OVS_GRP_REGULAR_RESUMED \
- (ADC_CFGR2_ROVSM | \
- ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. \
- If group injected interrupts group regular: when ADC \
- group injected is triggered, the oversampling on ADC \
- group regular is resumed from start (oversampler buffer \
- reset). */
-#define LL_ADC_OVS_GRP_INJECTED \
- (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of ADC group \
- injected. */
-#define LL_ADC_OVS_GRP_INJ_REG_RESUMED \
- (ADC_CFGR2_JOVSE | \
- ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups \
- regular and injected. If group injected interrupting \
- group regular: when ADC group injected is triggered, \
- the oversampling on ADC group regular is resumed from \
- start (oversampler buffer reset). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
- * @{
- */
-#define LL_ADC_OVS_REG_CONT \
- (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode \
- (all conversions of oversampling ratio are done from 1 \
- trigger) */
-#define LL_ADC_OVS_REG_DISCONT \
- (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous \
- mode (each conversion of oversampling ratio needs a \
- trigger) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
- * @{
- */
-#define LL_ADC_OVS_RATIO_2 \
- (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are \
- performed, sum of these conversions data is computed to \
- result as the ADC oversampling conversion data (before \
- potential shift) */
-#define LL_ADC_OVS_RATIO_4 \
- (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define LL_ADC_OVS_RATIO_8 \
- (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 (8 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define LL_ADC_OVS_RATIO_16 \
- (ADC_CFGR2_OVSR_1 | \
- ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define LL_ADC_OVS_RATIO_32 \
- (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 (32 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define LL_ADC_OVS_RATIO_64 \
- (ADC_CFGR2_OVSR_2 | \
- ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are \
- performed, sum of these conversions data is computed \
- to result as the ADC oversampling conversion data \
- (before potential shift) */
-#define LL_ADC_OVS_RATIO_128 \
- (ADC_CFGR2_OVSR_2 | \
- ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 (128 ADC conversions \
- are performed, sum of these conversions data is \
- computed to result as the ADC oversampling conversion \
- data (before potential shift) */
-#define LL_ADC_OVS_RATIO_256 \
- (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | \
- ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions \
- are performed, sum of these conversions data is \
- computed to result as the ADC oversampling conversion \
- data (before potential shift) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
- * @{
- */
-#define LL_ADC_OVS_SHIFT_NONE \
- (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions \
- data is not divided to result as the ADC oversampling \
- conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_1 \
- (ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC \
- conversions data is divided by 2 to result as the ADC \
- oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_2 \
- (ADC_CFGR2_OVSS_1) /*!< ADC oversampling shift of 2 (sum of the ADC \
- conversions data is divided by 4 to result as the ADC \
- oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_3 \
- (ADC_CFGR2_OVSS_1 | \
- ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC \
- conversions data is divided by 8 to result as the ADC \
- oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_4 \
- (ADC_CFGR2_OVSS_2) /*!< ADC oversampling shift of 4 (sum of the ADC \
- conversions data is divided by 16 to result as the ADC \
- oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_5 \
- (ADC_CFGR2_OVSS_2 | \
- ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC \
- conversions data is divided by 32 to result as the ADC \
- oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_6 \
- (ADC_CFGR2_OVSS_2 | \
- ADC_CFGR2_OVSS_1) /*!< ADC oversampling shift of 6 (sum of the ADC \
- conversions data is divided by 64 to result as the ADC \
- oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_7 \
- (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | \
- ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC \
- conversions data is divided by 128 to result as the \
- ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_8 \
- (ADC_CFGR2_OVSS_3) /*!< ADC oversampling shift of 8 (sum of the ADC \
- conversions data is divided by 256 to result as the \
- ADC oversampling conversion data) */
-/**
- * @}
- */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- * @{
- */
-#define LL_ADC_MULTI_INDEPENDENT \
- (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
-#define LL_ADC_MULTI_DUAL_REG_SIMULT \
- (ADC_CCR_DUAL_2 | \
- ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_INTERL \
- (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | \
- ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular \
- interleaved */
-#define LL_ADC_MULTI_DUAL_INJ_SIMULT \
- (ADC_CCR_DUAL_2 | \
- ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_INJ_ALTERN \
- (ADC_CCR_DUAL_3 | \
- ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate \
- trigger. Works only with external triggers (not internal \
- SW start) */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM \
- (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular \
- simultaneous + group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT \
- (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group regular \
- simultaneous + group injected alternate trigger */
-#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM \
- (ADC_CCR_DUAL_1 | \
- ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular \
- interleaved + group injected simultaneous */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
- * @{
- */
-#define LL_ADC_MULTI_REG_DMA_EACH_ADC \
- (0x00000000UL) /*!< ADC multimode group regular conversions are transferred \
- by DMA: each ADC uses its own DMA channel, with its \
- individual DMA transfer settings */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B \
- (ADC_CCR_MDMA_1) /*!< ADC multimode group regular conversions are \
- transferred by DMA, one DMA channel for both ADC (DMA of \
- ADC master), in limited mode (one shot mode): DMA \
- transfer requests are stopped when number of DMA data \
- transfers (number of ADC conversions) is reached. This \
- ADC mode is intended to be used with DMA mode \
- non-circular. Setting for ADC resolution of 12 and 10 \
- bits */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B \
- (ADC_CCR_MDMA_1 | \
- ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are \
- transferred by DMA, one DMA channel for both ADC (DMA of \
- ADC master), in limited mode (one shot mode): DMA \
- transfer requests are stopped when number of DMA data \
- transfers (number of ADC conversions) is reached. This \
- ADC mode is intended to be used with DMA mode \
- non-circular. Setting for ADC resolution of 8 and 6 bits \
- */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B \
- (ADC_CCR_DMACFG | \
- ADC_CCR_MDMA_1) /*!< ADC multimode group regular conversions are \
- transferred by DMA, one DMA channel for both ADC (DMA of \
- ADC master), in unlimited mode: DMA transfer requests \
- are unlimited, whatever number of DMA data transferred \
- (number of ADC conversions). This ADC mode is intended \
- to be used with DMA mode circular. Setting for ADC \
- resolution of 12 and 10 bits */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B \
- (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | \
- ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are \
- transferred by DMA, one DMA channel for both ADC (DMA of \
- ADC master), in unlimited mode: DMA transfer requests \
- are unlimited, whatever number of DMA data transferred \
- (number of ADC conversions). This ADC mode is intended \
- to be used with DMA mode circular. Setting for ADC \
- resolution of 8 and 6 bits */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two
- * sampling phases
- * @{
- */
-#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE \
- (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC \
- clock cycle */
-#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES \
- (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES \
- (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two sampling phases: 3 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES \
- (ADC_CCR_DELAY_1 | \
- ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES \
- (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two sampling phases: 5 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES \
- (ADC_CCR_DELAY_2 | \
- ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES \
- (ADC_CCR_DELAY_2 | \
- ADC_CCR_DELAY_1) /*!< ADC multimode delay between two sampling phases: 7 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES \
- (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | \
- ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES \
- (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two sampling phases: 9 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES \
- (ADC_CCR_DELAY_3 | \
- ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES \
- (ADC_CCR_DELAY_3 | \
- ADC_CCR_DELAY_1) /*!< ADC multimode delay between two sampling phases: 11 \
- ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES \
- (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | \
- ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 \
- ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
- * @{
- */
-#define LL_ADC_MULTI_MASTER \
- (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC \
- instances: ADC master */
-#define LL_ADC_MULTI_SLAVE \
- (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC \
- instances: ADC slave */
-#define LL_ADC_MULTI_MASTER_SLAVE \
- (ADC_CDR_RDATA_SLV | \
- ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC \
- instances: both ADC master and ADC slave */
-/**
- * @}
- */
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints
- * delays
- * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
-/* not timeout values. */
-/* Timeout values for ADC operations are dependent to device clock */
-/* configuration (system clock versus ADC clock), */
-/* and therefore must be defined in user application. */
-/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 series: */
-/* - ADC calibration time: maximum delay is 112/fADC. */
-/* (refer to device datasheet, parameter "tCAL") */
-/* - ADC enable time: maximum delay is 1 conversion cycle. */
-/* (refer to device datasheet, parameter "tSTAB") */
-/* - ADC disable time: maximum delay should be a few ADC clock cycles */
-/* - ADC stop conversion time: maximum delay should be a few ADC clock */
-/* cycles */
-/* - ADC conversion time: duration depending on ADC clock and ADC */
-/* configuration. */
-/* (refer to device reference manual, section "Timing") */
-
-/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
-/* Delay set to maximum value (refer to device datasheet, */
-/* parameter "tADCVREG_STUP"). */
-/* Unit: us */
-#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US \
- (20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up \
- time) */
-
-/* Delay for internal voltage reference stabilization time. */
-/* Delay set to maximum value (refer to device datasheet, */
-/* parameter "tstart_vrefint"). */
-/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US \
- (12UL) /*!< Delay for internal voltage reference stabilization time */
-
-/* Delay for temperature sensor stabilization time. */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSTART"). */
-/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US \
- (120UL) /*!< Delay for temperature sensor stabilization time */
-
-/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 series, a minimum number of ADC clock cycles */
-/* are required between ADC end of calibration and ADC enable. */
-/* Wait time can be computed in user application by waiting for the */
-/* equivalent number of CPU cycles, by taking into account */
-/* ratio of CPU clock versus ADC clock prescalers. */
-/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES \
- (4UL) /*!< Delay required between ADC end of calibration and ADC enable */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
- * @{
- */
-
-/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get ADC channel number in decimal format
- * from literals LL_ADC_CHANNEL_x.
- * @note Example:
- * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
- * will return decimal number "4".
- * @note The input can be a value from functions where a channel
- * number is returned, either defined with number
- * or with bitfield (only one bit must be set).
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Value between Min_Data=0 and Max_Data=18
- */
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> \
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
- : ((uint32_t)POSITION_VAL((__CHANNEL__))))
-
-/**
- * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
- * from number in decimal format.
- * @note Example:
- * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
- * will return a data equivalent to "LL_ADC_CHANNEL_4".
- * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
- * register, comparison with internal channel parameter to be done using helper
- * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9UL) \
- ? (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
- (ADC_SMPR1_REGOFFSET | \
- (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))) \
- : (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
- (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__)-10UL))) \
- << ADC_CHANNEL_SMPx_BITOFFSET_POS))))
-
-/**
- * @brief Helper macro to determine whether the selected channel
- * corresponds to literal definitions of driver.
- * @note The different literal definitions of ADC channels are:
- * - ADC internal channel:
- * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
- * - ADC external channel (channel connected to a GPIO pin):
- * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
- * @note The channel parameter must be a value defined from literal
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
- * must not be a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Value "0" if the channel corresponds to a parameter definition of a
- * ADC external channel (channel connected to a GPIO pin). Value "1" if the
- * channel corresponds to a parameter definition of a ADC internal channel.
- */
-#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
-
-/**
- * @brief Helper macro to convert a channel defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * to its equivalent parameter definition of a ADC external channel
- * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
- * @note The channel parameter can be, additionally to a value
- * defined from parameter definition of a ADC internal channel
- * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is returned
- * from ADC registers.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- */
-#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-
-/**
- * @brief Helper macro to determine whether the internal channel
- * selected is available on the ADC instance selected.
- * @note The channel parameter must be a value defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * must not be a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __ADC_INSTANCE__ ADC instance
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details.
- * @retval Value "0" if the internal channel selected is not available on the
- * ADC instance selected. Value "1" if the internal channel selected is
- * available on the ADC instance selected.
- */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
- defined(STM32G483xx)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ((((__ADC_INSTANCE__) == ADC1) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
- (((__ADC_INSTANCE__) == ADC2) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))) || \
- (((__ADC_INSTANCE__) == ADC3) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
- (((__ADC_INSTANCE__) == ADC4) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
- (((__ADC_INSTANCE__) == ADC5) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))))
-#elif defined(STM32G471xx)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ((((__ADC_INSTANCE__) == ADC1) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
- (((__ADC_INSTANCE__) == ADC2) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))) || \
- (((__ADC_INSTANCE__) == ADC3) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ((((__ADC_INSTANCE__) == ADC1) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
- (((__ADC_INSTANCE__) == ADC2) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ((((__ADC_INSTANCE__) == ADC1) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
- (((__ADC_INSTANCE__) == ADC2) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))) || \
- (((__ADC_INSTANCE__) == ADC3) && \
- (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))))
-#endif
-
-/**
- * @brief Helper macro to define ADC analog watchdog parameter:
- * define a single channel to monitor with analog watchdog
- * from sequencer channel and groups definition.
- * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
- * Example:
- * LL_ADC_SetAnalogWDMonitChannels(
- * ADC1, LL_ADC_AWD1,
- * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4,
- * LL_ADC_GROUP_REGULAR))
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
- * register, comparison with internal channel parameter to be done using helper
- * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- * @param __GROUP__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_GROUP_REGULAR
- * @arg @ref LL_ADC_GROUP_INJECTED
- * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
- * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
- *
- * (0) On STM32G4, parameter available only on analog watchdog number:
- * AWD1.\n (1) On STM32G4, parameter available only on ADC instance: ADC1.\n (2)
- * On STM32G4, parameter available only on ADC instance: ADC2.\n (3) On STM32G4,
- * parameter available only on ADC instance: ADC3.\n (4) On STM32G4, parameter
- * available only on ADC instance: ADC4.\n (5) On STM32G4, parameter available
- * only on ADC instance: ADC5.\n (6) On STM32G4, parameter available only on ADC
- * instances: ADC1, ADC3, ADC5.\n (7) On STM32G4, parameter available only on
- * ADC instances: ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details.
- */
-#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
- (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
- ADC_CFGR_AWD1SGL) \
- : ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1SGL) \
- : (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL))
-
-/**
- * @brief Helper macro to set the value of ADC analog watchdog threshold high
- * or low in function of ADC resolution, when ADC resolution is
- * different of 12 bits.
- * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
- * or @ref LL_ADC_SetAnalogWDThresholds().
- * Example, with a ADC resolution of 8 bits, to set the value of
- * analog watchdog threshold high (on 8 bits):
- * LL_ADC_SetAnalogWDThresholds
- * (< ADCx param >,
- * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B,
- * <threshold_value_8_bits>)
- * );
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, \
- __AWD_THRESHOLD__) \
- ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> \
- (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
-
-/**
- * @brief Helper macro to get the value of ADC analog watchdog threshold high
- * or low in function of ADC resolution, when ADC resolution is
- * different of 12 bits.
- * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
- * Example, with a ADC resolution of 8 bits, to get the value of
- * analog watchdog threshold high (on 8 bits):
- * < threshold_value_6_bits > =
- * __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B,
- * LL_ADC_GetAnalogWDThresholds(<ADCx param>,
- * LL_ADC_AWD_THRESHOLD_HIGH)
- * );
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and
- * Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, \
- __AWD_THRESHOLD_12_BITS__) \
- ((__AWD_THRESHOLD_12_BITS__) >> \
- ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
-
-/**
- * @brief Helper macro to get the ADC analog watchdog threshold high
- * or low from raw value containing both thresholds concatenated.
- * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
- * Example, to get analog watchdog threshold high from the register raw
- * value:
- * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH,
- * <raw_value_with_both_thresholds>);
- * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
- * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
- * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and
- * Max_Data=0xFFFFFFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, \
- __AWD_THRESHOLDS__) \
- (((__AWD_THRESHOLDS__) >> \
- (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> \
- ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & \
- LL_ADC_AWD_THRESHOLD_LOW)
-
-/**
- * @brief Helper macro to set the ADC calibration value with both single ended
- * and differential modes calibration factors concatenated.
- * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
- * Example, to set calibration factors single ended to 0x55
- * and differential ended to 0x2A:
- * LL_ADC_SetCalibrationFactor(
- * ADC1,
- * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
- * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and
- * Max_Data=0x7F
- * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and
- * Max_Data=0x7F
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, \
- __CALIB_FACTOR_DIFFERENTIAL__) \
- (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | \
- (__CALIB_FACTOR_SINGLE_ENDED__))
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Helper macro to get the ADC multimode conversion data of ADC master
- * or ADC slave from raw value with both ADC conversion data
- * concatenated.
- * @note This macro is intended to be used when multimode transfer by DMA
- * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
- * In this case the transferred data need to processed with this macro
- * to separate the conversion data of ADC master and ADC slave.
- * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_MULTI_MASTER
- * @arg @ref LL_ADC_MULTI_SLAVE
- * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and
- * Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, \
- __ADC_MULTI_CONV_DATA__) \
- (((__ADC_MULTI_CONV_DATA__) >> \
- ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & \
- ADC_CDR_RDATA_MST)
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Helper macro to select, from a ADC instance, to which ADC instance
- * it has a dependence in multimode (ADC master of the corresponding
- * ADC common instance).
- * @note In case of device with multimode available and a mix of
- * ADC instances compliant and not compliant with multimode feature,
- * ADC instances not compliant with multimode feature are
- * considered as master instances (do not depend to
- * any other ADC instance).
- * @param __ADCx__ ADC instance
- * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
- */
-#if defined(ADC5)
-#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
- ((((__ADCx__) == ADC2)) ? (ADC1) \
- : ((((__ADCx__) == ADC4)) ? (ADC3) : (__ADCx__)))
-#else
-#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
- ((((__ADCx__) == ADC2)) ? (ADC1) : (__ADCx__))
-#endif /* ADC5 */
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @brief Helper macro to select the ADC common instance
- * to which is belonging the selected ADC instance.
- * @note ADC common register instance can be used for:
- * - Set parameters common to several ADC instances
- * - Multimode (for devices with several ADC instances)
- * Refer to functions having argument "ADCxy_COMMON" as parameter.
- * @param __ADCx__ ADC instance
- * @retval ADC common register instance
- */
-#if defined(ADC345_COMMON)
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) ? ((ADC12_COMMON)) \
- : ((ADC345_COMMON)))
-#else
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
-#endif /* ADC345_COMMON */
-/**
- * @brief Helper macro to check if all ADC instances sharing the same
- * ADC common instance are disabled.
- * @note This check is required by functions with setting conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled.
- * Refer to functions having argument "ADCxy_COMMON" as parameter.
- * @note On devices with only 1 ADC common instance, parameter of this macro
- * is useless and can be ignored (parameter kept for compatibility
- * with devices featuring several ADC common instances).
- * @param __ADCXY_COMMON__ ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Value "0" if all ADC instances sharing the same ADC common instance
- * are disabled.
- * Value "1" if at least one ADC instance sharing the same ADC common
- * instance is enabled.
- */
-#if defined(ADC345_COMMON)
-#if defined(ADC4) && defined(ADC5)
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- (((__ADCXY_COMMON__) == ADC12_COMMON) \
- ? ((LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))) \
- : ((LL_ADC_IsEnabled(ADC3) | LL_ADC_IsEnabled(ADC4) | \
- LL_ADC_IsEnabled(ADC5))))
-#else
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- (((__ADCXY_COMMON__) == ADC12_COMMON) \
- ? ((LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))) \
- : (LL_ADC_IsEnabled(ADC3)))
-#endif /* ADC4 && ADC5 */
-#else
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
-#endif
-
-/**
- * @brief Helper macro to define the ADC conversion data full-scale digital
- * value corresponding to the selected ADC resolution.
- * @note ADC conversion data full-scale corresponds to voltage range
- * determined by analog voltage references Vref+ and Vref-
- * (refer to reference manual).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval ADC conversion data full-scale digital value (unit: digital value of
- * ADC conversion data)
- */
-#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
-
-/**
- * @brief Helper macro to convert the ADC conversion data from
- * a resolution to another resolution.
- * @param __DATA__ ADC conversion data to be converted
- * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
- * This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
- * This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval ADC conversion data to the requested resolution
- */
-#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, \
- __ADC_RESOLUTION_TARGET__) \
- (((__DATA__) << ((__ADC_RESOLUTION_CURRENT__) >> \
- (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) >> \
- ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
-
-/**
- * @brief Helper macro to calculate the voltage (unit: mVolt)
- * corresponding to a ADC conversion data (unit: digital value).
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
- * (unit: digital value).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, \
- __ADC_RESOLUTION__) \
- ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / \
- __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))
-
-/**
- * @brief Helper macro to calculate analog reference voltage (Vref+)
- * (unit: mVolt) from ADC conversion data of internal voltage
- * reference VrefInt.
- * @note Computation is using VrefInt calibration value
- * stored in system memory for each device during production.
- * @note This voltage depends on user board environment: voltage level
- * connected to pin Vref+.
- * On devices with small package, the pin Vref+ is not present
- * and internally bonded to pin Vdda.
- * @note On this STM32 series, calibration data of internal voltage reference
- * VrefInt corresponds to a resolution of 12 bits,
- * this is the recommended ADC resolution to convert voltage of
- * internal voltage reference VrefInt.
- * Otherwise, this macro performs the processing to scale
- * ADC conversion data to 12 bits.
- * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
- * of internal voltage reference VrefInt (unit: digital value).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval Analog reference voltage (unit: mV)
- */
-#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, \
- __ADC_RESOLUTION__) \
- (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) / \
- __LL_ADC_CONVERT_DATA_RESOLUTION( \
- (__VREFINT_ADC_DATA__), (__ADC_RESOLUTION__), LL_ADC_RESOLUTION_12B))
-
-/**
- * @brief Helper macro to calculate the temperature (unit: degree Celsius)
- * from ADC conversion data of internal temperature sensor.
- * @note Computation is using temperature sensor calibration values
- * stored in system memory for each device during production.
- * @note Calculation formula:
- * Temperature = ((TS_ADC_DATA - TS_CAL1)
- * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
- * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
- * with TS_ADC_DATA = temperature sensor raw data measured by ADC
- * Avg_Slope = (TS_CAL2 - TS_CAL1)
- * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
- * TS_CAL1 = equivalent TS_ADC_DATA at temperature
- * TEMP_DEGC_CAL1 (calibrated in factory)
- * TS_CAL2 = equivalent TS_ADC_DATA at temperature
- * TEMP_DEGC_CAL2 (calibrated in factory)
- * Caution: Calculation relevancy under reserve that calibration
- * parameters are correct (address and data).
- * To calculate temperature using temperature sensor
- * datasheet typical values (generic values less, therefore
- * less accurate than calibrated values),
- * use helper macro @ref
- * __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
- * @note As calculation input, the analog reference voltage (Vref+) must be
- * defined as it impacts the ADC LSB equivalent voltage.
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 series, calibration data of temperature sensor
- * corresponds to a resolution of 12 bits,
- * this is the recommended ADC resolution to convert voltage of
- * temperature sensor.
- * Otherwise, this macro performs the processing to scale
- * ADC conversion data to 12 bits.
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
- * temperature sensor (unit: digital value).
- * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
- * sensor voltage has been measured.
- * This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval Temperature (unit: degree Celsius)
- */
-#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, \
- __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__) \
- ((((((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_12B) * \
- (__VREFANALOG_VOLTAGE__)) / \
- TEMPSENSOR_CAL_VREFANALOG) - \
- (int32_t) * TEMPSENSOR_CAL1_ADDR)) * \
- (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)) / \
- (int32_t)((int32_t) * TEMPSENSOR_CAL2_ADDR - \
- (int32_t) * TEMPSENSOR_CAL1_ADDR)) + \
- TEMPSENSOR_CAL1_TEMP)
-
-/**
- * @brief Helper macro to calculate the temperature (unit: degree Celsius)
- * from ADC conversion data of internal temperature sensor.
- * @note Computation is using temperature sensor typical values
- * (refer to device datasheet).
- * @note Calculation formula:
- * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
- * / Avg_Slope + CALx_TEMP
- * with TS_ADC_DATA = temperature sensor raw data measured by ADC
- * (unit: digital value)
- * Avg_Slope = temperature sensor slope
- * (unit: uV/Degree Celsius)
- * TS_TYP_CALx_VOLT = temperature sensor digital value at
- * temperature CALx_TEMP (unit: mV)
- * Caution: Calculation relevancy under reserve the temperature sensor
- * of the current device has characteristics in line with
- * datasheet typical values.
- * If temperature sensor calibration values are available on
- * on this device (presence of macro
- * __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate
- * using helper macro @ref __LL_ADC_CALC_TEMPERATURE().
- * @note As calculation input, the analog reference voltage (Vref+) must be
- * defined as it impacts the ADC LSB equivalent voltage.
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note ADC measurement data must correspond to a resolution of 12 bits
- * (full scale digital value 4095). If not the case, the data must be
- * preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature
- * sensor slope typical value (unit: uV/DegCelsius). On STM32G4, refer to device
- * datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature
- * sensor voltage typical value (at temperature and Vref+ defined in parameters
- * below) (unit: mV). On STM32G4, refer to device datasheet parameter "V30"
- * (corresponding to TS_CAL1).
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at
- * which temperature sensor voltage (see parameter above) is corresponding
- * (unit: mV)
- * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+)
- * voltage (unit: mV)
- * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
- * temperature sensor (unit: digital value).
- * @param __ADC_RESOLUTION__ ADC resolution at which internal
- * temperature sensor voltage has been measured. This parameter can be one of
- * the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval Temperature (unit: degree Celsius)
- */
-#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS( \
- __TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, \
- __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, \
- __ADC_RESOLUTION__) \
- (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) / \
- __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) * \
- 1000UL) - \
- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) * 1000UL))) / \
- (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)) + \
- (int32_t)(__TEMPSENSOR_CALX_TEMP__))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
- * @{
- */
-/* Note: LL ADC functions to set DMA transfer are located into sections of */
-/* configuration of ADC instance, groups and multimode (if available): */
-/* @ref LL_ADC_REG_SetDMATransfer(), ... */
-
-/**
- * @brief Function to help to configure DMA transfer from ADC: retrieve the
- * ADC register address from ADC instance and a list of ADC registers
- * intended to be used (most commonly) with DMA transfer.
- * @note These ADC registers are data registers:
- * when ADC conversion data is available in ADC data registers,
- * ADC generates a DMA transfer request.
- * @note This macro is intended to be used with LL DMA driver, refer to
- * function "LL_DMA_ConfigAddresses()".
- * Example:
- * LL_DMA_ConfigAddresses(DMA1,
- * LL_DMA_CHANNEL_1,
- * LL_ADC_DMA_GetRegAddr(ADC1,
- * LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >,
- * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
- * @note For devices with several ADC: in multimode, some devices
- * use a different data register outside of ADC instance scope
- * (common data register). This macro manages this register difference,
- * only ADC instance has to be set as parameter.
- * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
- * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
- * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
- * @param ADCx ADC instance
- * @param Register This parameter can be one of the following values:
- * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
- * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
- *
- * (1) Available on devices with several ADC instances.
- * @retval ADC register address
- */
-#if defined(ADC_MULTIMODE_SUPPORT)
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx,
- uint32_t Register) {
- uint32_t data_reg_addr;
-
- if (Register == LL_ADC_DMA_REG_REGULAR_DATA) {
- /* Retrieve address of register DR */
- data_reg_addr = (uint32_t) & (ADCx->DR);
- } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
- {
- /* Retrieve address of register CDR */
- data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
- }
-
- return data_reg_addr;
-}
-#else
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx,
- uint32_t Register) {
- /* Prevent unused argument(s) compilation warning */
- (void)(Register);
-
- /* Retrieve address of register DR */
- return (uint32_t) & (ADCx->DR);
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC
- * hierarchical scope: common to several ADC instances
- * @{
- */
-
-/**
- * @brief Set parameter common to several ADC: Clock source and prescaler.
- * @note On this STM32 series, if ADC group injected is used, some
- * clock ratio constraints between ADC clock and AHB clock
- * must be respected.
- * Refer to reference manual.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled.
- * This check can be done with function @ref LL_ADC_IsEnabled() for each
- * ADC instance or by using helper macro helper macro
- * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
- * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
- * CCR PRESC LL_ADC_SetCommonClock
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param CommonClock This parameter can be one of the following values:
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON,
- uint32_t CommonClock) {
- MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
-}
-
-/**
- * @brief Get parameter common to several ADC: Clock source and prescaler.
- * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
- * CCR PRESC LL_ADC_GetCommonClock
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
- * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
- */
-__STATIC_INLINE uint32_t
-LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) {
- return (
- uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
-}
-
-/**
- * @brief Set parameter common to several ADC: measurement path to
- * internal channels (VrefInt, temperature sensor, ...).
- * Configure all paths (overwrite current configuration).
- * @note One or several values can be selected.
- * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * The values not selected are removed from configuration.
- * @note Stabilization time of measurement path to internal channel:
- * After enabling internal paths, before starting ADC conversion,
- * a delay is required for internal voltage reference and
- * temperature sensor stabilization time.
- * Refer to device datasheet.
- * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
- * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
- * @note ADC internal channel sampling time constraint:
- * For ADC conversion of internal channels,
- * a sampling time minimum value is required.
- * Refer to device datasheet.
- * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
- * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
- * CCR VBATSEL LL_ADC_SetCommonPathInternalCh
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param PathInternal This parameter can be a combination of the following
- * values:
- * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(
- ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) {
- MODIFY_REG(ADCxy_COMMON->CCR,
- ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL,
- PathInternal);
-}
-
-/**
- * @brief Set parameter common to several ADC: measurement path to
- * internal channels (VrefInt, temperature sensor, ...).
- * Add paths to the current configuration.
- * @note One or several values can be selected.
- * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @note Stabilization time of measurement path to internal channel:
- * After enabling internal paths, before starting ADC conversion,
- * a delay is required for internal voltage reference and
- * temperature sensor stabilization time.
- * Refer to device datasheet.
- * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
- * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
- * @note ADC internal channel sampling time constraint:
- * For ADC conversion of internal channels,
- * a sampling time minimum value is required.
- * Refer to device datasheet.
- * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
- * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
- * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param PathInternal This parameter can be a combination of the following
- * values:
- * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(
- ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) {
- SET_BIT(ADCxy_COMMON->CCR, PathInternal);
-}
-
-/**
- * @brief Set parameter common to several ADC: measurement path to
- * internal channels (VrefInt, temperature sensor, ...).
- * Remove paths to the current configuration.
- * @note One or several values can be selected.
- * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
- * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
- * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param PathInternal This parameter can be a combination of the following
- * values:
- * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(
- ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) {
- CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
-}
-
-/**
- * @brief Get parameter common to several ADC: measurement path to internal
- * channels (VrefInt, temperature sensor, ...).
- * @note One or several values can be selected.
- * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
- * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
- * CCR VBATSEL LL_ADC_GetCommonPathInternalCh
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be a combination of the following values:
- * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
- */
-__STATIC_INLINE uint32_t
-LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) {
- return (uint32_t)(READ_BIT(
- ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC
- * hierarchical scope: ADC instance
- * @{
- */
-
-/**
- * @brief Set ADC calibration factor in the mode single-ended
- * or differential (for devices with differential mode available).
- * @note This function is intended to set calibration parameters
- * without having to perform a new calibration using
- * @ref LL_ADC_StartCalibration().
- * @note For devices with differential mode available:
- * Calibration of offset is specific to each of
- * single-ended and differential modes
- * (calibration factor must be specified for each of these
- * differential modes, if used afterwards and if the application
- * requires their calibration).
- * @note In case of setting calibration factors of both modes single ended
- * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
- * both calibration factors must be concatenated.
- * To perform this processing, use helper macro
- * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled, without calibration on going, without conversion
- * on going on group regular.
- * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
- * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
- * @param ADCx ADC instance
- * @param SingleDiff This parameter can be one of the following values:
- * @arg @ref LL_ADC_SINGLE_ENDED
- * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
- * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
- * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx,
- uint32_t SingleDiff,
- uint32_t CalibrationFactor) {
- MODIFY_REG(
- ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
- CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
- ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) &
- ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
-}
-
-/**
- * @brief Get ADC calibration factor in the mode single-ended
- * or differential (for devices with differential mode available).
- * @note Calibration factors are set by hardware after performing
- * a calibration run using function @ref LL_ADC_StartCalibration().
- * @note For devices with differential mode available:
- * Calibration of offset is specific to each of
- * single-ended and differential modes
- * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
- * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
- * @param ADCx ADC instance
- * @param SingleDiff This parameter can be one of the following values:
- * @arg @ref LL_ADC_SINGLE_ENDED
- * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
- * @retval Value between Min_Data=0x00 and Max_Data=0x7F
- */
-__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx,
- uint32_t SingleDiff) {
- /* Retrieve bits with position in register depending on parameter */
- /* "SingleDiff". */
- /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
- /* containing other bits reserved for other purpose. */
- return (uint32_t)(READ_BIT(ADCx->CALFACT,
- (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >>
- ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
- ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
-}
-
-/**
- * @brief Set ADC resolution.
- * Refer to reference manual for alignments formats
- * dependencies to ADC resolutions.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR RES LL_ADC_SetResolution
- * @param ADCx ADC instance
- * @param Resolution This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx,
- uint32_t Resolution) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
-}
-
-/**
- * @brief Get ADC resolution.
- * Refer to reference manual for alignments formats
- * dependencies to ADC resolutions.
- * @rmtoll CFGR RES LL_ADC_GetResolution
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @arg @ref LL_ADC_RESOLUTION_10B
- * @arg @ref LL_ADC_RESOLUTION_8B
- * @arg @ref LL_ADC_RESOLUTION_6B
- */
-__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
-}
-
-/**
- * @brief Set ADC conversion data alignment.
- * @note Refer to reference manual for alignments formats
- * dependencies to ADC resolutions.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
- * @param ADCx ADC instance
- * @param DataAlignment This parameter can be one of the following values:
- * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
- * @arg @ref LL_ADC_DATA_ALIGN_LEFT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx,
- uint32_t DataAlignment) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
-}
-
-/**
- * @brief Get ADC conversion data alignment.
- * @note Refer to reference manual for alignments formats
- * dependencies to ADC resolutions.
- * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
- * @arg @ref LL_ADC_DATA_ALIGN_LEFT
- */
-__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
-}
-
-/**
- * @brief Set ADC low power mode.
- * @note Description of ADC low power modes:
- * - ADC low power mode "auto wait": Dynamic low power mode,
- * ADC conversions occurrences are limited to the minimum necessary
- * in order to reduce power consumption.
- * New ADC conversion starts only when the previous
- * unitary conversion data (for ADC group regular)
- * or previous sequence conversions data (for ADC group injected)
- * has been retrieved by user software.
- * In the meantime, ADC remains idle: does not performs any
- * other conversion.
- * This mode allows to automatically adapt the ADC conversions
- * triggers to the speed of the software that reads the data.
- * Moreover, this avoids risk of overrun for low frequency
- * applications.
- * How to use this low power mode:
- * - It is not recommended to use with interruption or DMA
- * since these modes have to clear immediately the EOC flag
- * (by CPU to free the IRQ pending event or by DMA).
- * Auto wait will work but fort a very short time, discarding
- * its intended benefit (except specific case of high load of CPU
- * or DMA transfers which can justify usage of auto wait).
- * - Do use with polling: 1. Start conversion,
- * 2. Later on, when conversion data is needed: poll for end of
- * conversion to ensure that conversion is completed and
- * retrieve ADC conversion data. This will trig another
- * ADC conversion start.
- * - ADC low power mode "auto power-off" (feature available on
- * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
- * the ADC automatically powers-off after a conversion and
- * automatically wakes up when a new conversion is triggered
- * (with startup time between trigger and start of sampling).
- * This feature can be combined with low power mode "auto wait".
- * @note With ADC low power mode "auto wait", the ADC conversion data read
- * is corresponding to previous ADC conversion start, independently
- * of delay during which ADC was idle.
- * Therefore, the ADC conversion data may be outdated: does not
- * correspond to the current voltage level on the selected
- * ADC channel.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
- * @param ADCx ADC instance
- * @param LowPowerMode This parameter can be one of the following values:
- * @arg @ref LL_ADC_LP_MODE_NONE
- * @arg @ref LL_ADC_LP_AUTOWAIT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx,
- uint32_t LowPowerMode) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
-}
-
-/**
- * @brief Get ADC low power mode:
- * @note Description of ADC low power modes:
- * - ADC low power mode "auto wait": Dynamic low power mode,
- * ADC conversions occurrences are limited to the minimum necessary
- * in order to reduce power consumption.
- * New ADC conversion starts only when the previous
- * unitary conversion data (for ADC group regular)
- * or previous sequence conversions data (for ADC group injected)
- * has been retrieved by user software.
- * In the meantime, ADC remains idle: does not performs any
- * other conversion.
- * This mode allows to automatically adapt the ADC conversions
- * triggers to the speed of the software that reads the data.
- * Moreover, this avoids risk of overrun for low frequency
- * applications.
- * How to use this low power mode:
- * - It is not recommended to use with interruption or DMA
- * since these modes have to clear immediately the EOC flag
- * (by CPU to free the IRQ pending event or by DMA).
- * Auto wait will work but fort a very short time, discarding
- * its intended benefit (except specific case of high load of CPU
- * or DMA transfers which can justify usage of auto wait).
- * - Do use with polling: 1. Start conversion,
- * 2. Later on, when conversion data is needed: poll for end of
- * conversion to ensure that conversion is completed and
- * retrieve ADC conversion data. This will trig another
- * ADC conversion start.
- * - ADC low power mode "auto power-off" (feature available on
- * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
- * the ADC automatically powers-off after a conversion and
- * automatically wakes up when a new conversion is triggered
- * (with startup time between trigger and start of sampling).
- * This feature can be combined with low power mode "auto wait".
- * @note With ADC low power mode "auto wait", the ADC conversion data read
- * is corresponding to previous ADC conversion start, independently
- * of delay during which ADC was idle.
- * Therefore, the ADC conversion data may be outdated: does not
- * correspond to the current voltage level on the selected
- * ADC channel.
- * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_LP_MODE_NONE
- * @arg @ref LL_ADC_LP_AUTOWAIT
- */
-__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
-}
-
-/**
- * @brief Set ADC selected offset number 1, 2, 3 or 4.
- * @note This function set the 2 items of offset configuration:
- * - ADC channel to which the offset programmed will be applied
- * (independently of channel mapped on ADC group regular
- * or group injected)
- * - Offset level (offset to be subtracted from the raw
- * converted data).
- * @note Caution: Offset format is dependent to ADC resolution:
- * offset has to be left-aligned on bit 11, the LSB (right bits)
- * are set to 0.
- * @note This function enables the offset, by default. It can be forced
- * to disable state using function LL_ADC_SetOffsetState().
- * @note If a channel is mapped on several offsets numbers, only the offset
- * with the lowest value is considered for the subtraction.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @note On STM32G4, some fast channels are available: fast analog inputs
- * coming from GPIO pads (ADC_IN1..5).
- * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
- * OFR1 OFFSET1 LL_ADC_SetOffset\n
- * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
- * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
- * OFR2 OFFSET2 LL_ADC_SetOffset\n
- * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
- * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
- * OFR3 OFFSET3 LL_ADC_SetOffset\n
- * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
- * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
- * OFR4 OFFSET4 LL_ADC_SetOffset\n
- * OFR4 OFFSET4_EN LL_ADC_SetOffset
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety,
- uint32_t Channel, uint32_t OffsetLevel) {
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- MODIFY_REG(*preg,
- ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
- ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) |
- OffsetLevel);
-}
-
-/**
- * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
- * Channel to which the offset programmed will be applied
- * (independently of channel mapped on ADC group regular
- * or group injected)
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * @note On STM32G4, some fast channels are available: fast analog inputs
- * coming from GPIO pads (ADC_IN1..5).
- * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
- * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
- * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
- * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
- * register, comparison with internal channel parameter to be done using helper
- * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx,
- uint32_t Offsety) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
-}
-
-/**
- * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
- * Offset level (offset to be subtracted from the raw
- * converted data).
- * @note Caution: Offset format is dependent to ADC resolution:
- * offset has to be left-aligned on bit 11, the LSB (right bits)
- * are set to 0.
- * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
- * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
- * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
- * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx,
- uint32_t Offsety) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSET1);
-}
-
-/**
- * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
- * force offset state disable or enable
- * without modifying offset channel or offset value.
- * @note This function should be needed only in case of offset to be
- * enabled-disabled dynamically, and should not be needed in other
- * cases: function LL_ADC_SetOffset() automatically enables the offset.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
- * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
- * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
- * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @param OffsetState This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_DISABLE
- * @arg @ref LL_ADC_OFFSET_ENABLE
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety,
- uint32_t OffsetState) {
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, OffsetState);
-}
-
-/**
- * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
- * offset state disabled or enabled.
- * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
- * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
- * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
- * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_DISABLE
- * @arg @ref LL_ADC_OFFSET_ENABLE
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx,
- uint32_t Offsety) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
-}
-
-/**
- * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
- * choose offset sign.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
- * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
- * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
- * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @param OffsetSign This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
- * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety,
- uint32_t OffsetSign) {
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign);
-}
-
-/**
- * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
- * offset sign if positive or negative.
- * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
- * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
- * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
- * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
- * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx,
- uint32_t Offsety) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
-}
-
-/**
- * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
- * choose offset saturation mode.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
- * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
- * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
- * OFR4 SATEN LL_ADC_SetOffsetSaturation
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @param OffsetSaturation This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
- * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx,
- uint32_t Offsety,
- uint32_t OffsetSaturation) {
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- MODIFY_REG(*preg, ADC_OFR1_SATEN, OffsetSaturation);
-}
-
-/**
- * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
- * offset saturation if enabled or disabled.
- * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
- * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
- * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
- * OFR4 SATEN LL_ADC_GetOffsetSaturation
- * @param ADCx ADC instance
- * @param Offsety This parameter can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_1
- * @arg @ref LL_ADC_OFFSET_2
- * @arg @ref LL_ADC_OFFSET_3
- * @arg @ref LL_ADC_OFFSET_4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
- * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx,
- uint32_t Offsety) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- return (uint32_t)READ_BIT(*preg, ADC_OFR1_SATEN);
-}
-
-/**
- * @brief Set ADC gain compensation.
- * @note This function set the gain compensation coefficient
- * that is applied to raw converted data using the formula:
- * DATA = DATA(raw) * (gain compensation coef) / 4096
- * @note This function enables the gain compensation if given
- * coefficient is above 0, otherwise it disables it.
- * @note Gain compensation when enabled is applied to all channels.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
- * CFGR2 GCOMP LL_ADC_SetGainCompensation
- * @param ADCx ADC instance
- * @param GainCompensation This parameter can be:
- * 0 Gain compensation will be disabled and value set to 0
- * 1 -> 16393 Gain compensation will be enabled with specified value
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx,
- uint32_t GainCompensation) {
- MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
- MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP,
- ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
-}
-
-/**
- * @brief Get the ADC gain compensation value
- * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
- * CFGR2 GCOMP LL_ADC_GetGainCompensation
- * @param ADCx ADC instance
- * @retval Returned value can be:
- * 0 Gain compensation is disabled
- * 1 -> 16393 Gain compensation is enabled with returned value
- */
-__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP)
- ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF)
- : 0UL);
-}
-
-#if defined(ADC_SMPR1_SMPPLUS)
-/**
- * @brief Set ADC sampling time common configuration impacting
- * settings of sampling time channel wise.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
- * @param ADCx ADC instance
- * @param SamplingTimeCommonConfig This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
- * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(
- ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) {
- MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
-}
-
-/**
- * @brief Get ADC sampling time common configuration impacting
- * settings of sampling time channel wise.
- * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
- * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
- */
-__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
-}
-#endif /* ADC_SMPR1_SMPPLUS */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC
- * hierarchical scope: group regular
- * @{
- */
-
-/**
- * @brief Set ADC group regular conversion trigger source:
- * internal (SW start) or from external peripheral (timer event,
- * external interrupt line).
- * @note On this STM32 series, setting trigger source to external trigger
- * also set trigger polarity to rising edge
- * (default setting for compatibility with some ADC on other
- * STM32 families having this setting set by HW default value).
- * In case of need to modify trigger edge, use
- * function @ref LL_ADC_REG_SetTriggerEdge().
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
- * CFGR EXTEN LL_ADC_REG_SetTriggerSource
- * @param ADCx ADC instance
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
- * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
- *
- * (1) On STM32G4 series, parameter not available on all ADC instances:
- * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
- * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
- * on all devices. Refer to device datasheet for more details.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx,
- uint32_t TriggerSource) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
-}
-
-/**
- * @brief Get ADC group regular conversion trigger source:
- * internal (SW start) or from external peripheral (timer event,
- * external interrupt line).
- * @note To determine whether group regular trigger source is
- * internal (SW start) or external, without detail
- * of which peripheral is selected as external trigger,
- * (equivalent to
- * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
- * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
- * CFGR EXTEN LL_ADC_REG_GetTriggerSource
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
- * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
- * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
- *
- * (1) On STM32G4 series, parameter not available on all ADC instances:
- * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
- * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
- * on all devices. Refer to device datasheet for more details.
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) {
- __IO uint32_t TriggerSource =
- READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
-
- /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
- /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
- uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >>
- (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
-
- /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
- /* to match with triggers literals definition. */
- return ((TriggerSource & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) &
- ADC_CFGR_EXTSEL) |
- ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN));
-}
-
-/**
- * @brief Get ADC group regular conversion trigger source internal (SW start)
- * or external.
- * @note In case of group regular trigger source set to external trigger,
- * to determine which peripheral is selected as external trigger,
- * use function @ref LL_ADC_REG_GetTriggerSource().
- * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
- * @param ADCx ADC instance
- * @retval Value "0" if trigger source external trigger
- * Value "1" if trigger source SW start.
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) ==
- (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set ADC group regular conversion trigger polarity.
- * @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
- * @param ADCx ADC instance
- * @param ExternalTriggerEdge This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
- * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
- * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx,
- uint32_t ExternalTriggerEdge) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
-}
-
-/**
- * @brief Get ADC group regular conversion trigger polarity.
- * @note Applicable only for trigger source set to external trigger.
- * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
- * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
- * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
-}
-
-/**
- * @brief Set ADC sampling mode.
- * @note This function set the ADC conversion sampling mode
- * @note This mode applies to regular group only.
- * @note Set sampling mode is applied to all conversion of regular group.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
- * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
- * @param ADCx ADC instance
- * @param SamplingMode This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
- * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
- * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx,
- uint32_t SamplingMode) {
- MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
-}
-
-/**
- * @brief Get the ADC sampling mode
- * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
- * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
- * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
- * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
-}
-
-/**
- * @brief Set ADC group regular sequencer length and scan direction.
- * @note Description of ADC group regular sequencer features:
- * - For devices with sequencer fully configurable
- * (function "LL_ADC_REG_SetSequencerRanks()" available):
- * sequencer length and each rank affectation to a channel
- * are configurable.
- * This function performs configuration of:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerRanks()".
- * - For devices with sequencer not fully configurable
- * (function "LL_ADC_REG_SetSequencerChannels()" available):
- * sequencer length and each rank affectation to a channel
- * are defined by channel number.
- * This function performs configuration of:
- * - Sequence length: Number of ranks in the scan sequence is
- * defined by number of channels set in the sequence,
- * rank of each channel is fixed by channel HW number.
- * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from lowest channel number to
- * highest channel number).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerChannels()".
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
- * @param ADCx ADC instance
- * @param SequencerNbRanks This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx,
- uint32_t SequencerNbRanks) {
- MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
-}
-
-/**
- * @brief Get ADC group regular sequencer length and scan direction.
- * @note Description of ADC group regular sequencer features:
- * - For devices with sequencer fully configurable
- * (function "LL_ADC_REG_SetSequencerRanks()" available):
- * sequencer length and each rank affectation to a channel
- * are configurable.
- * This function retrieves:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerRanks()".
- * - For devices with sequencer not fully configurable
- * (function "LL_ADC_REG_SetSequencerChannels()" available):
- * sequencer length and each rank affectation to a channel
- * are defined by channel number.
- * This function retrieves:
- * - Sequence length: Number of ranks in the scan sequence is
- * defined by number of channels set in the sequence,
- * rank of each channel is fixed by channel HW number.
- * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from lowest channel number to
- * highest channel number).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerChannels()".
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
-}
-
-/**
- * @brief Set ADC group regular sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @note It is not possible to enable both ADC group regular
- * continuous mode and sequencer discontinuous mode.
- * @note It is not possible to enable both ADC auto-injected mode
- * and ADC group regular sequencer discontinuous mode.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
- * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
- * @param ADCx ADC instance
- * @param SeqDiscont This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx,
- uint32_t SeqDiscont) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
-}
-
-/**
- * @brief Get ADC group regular sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
- * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
-}
-
-/**
- * @brief Set ADC group regular sequence: channel on the selected
- * scan sequence rank.
- * @note This function performs configuration of:
- * - Channels ordering into each rank of scan sequence:
- * whatever channel can be placed into whatever rank.
- * @note On this STM32 series, ADC group regular sequencer is
- * fully configurable: sequencer length and each rank
- * affectation to a channel are configurable.
- * Refer to description of function @ref
- * LL_ADC_REG_SetSequencerLength().
- * @note Depending on devices and packages, some channels may not be
- * available. Refer to device datasheet for channels availability.
- * @note On this STM32 series, to measure internal channels (VrefInt,
- * TempSensor, ...), measurement paths to internal channels must be
- * enabled separately.
- * This can be done using function @ref
- * LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
- * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
- * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_RANK_1
- * @arg @ref LL_ADC_REG_RANK_2
- * @arg @ref LL_ADC_REG_RANK_3
- * @arg @ref LL_ADC_REG_RANK_4
- * @arg @ref LL_ADC_REG_RANK_5
- * @arg @ref LL_ADC_REG_RANK_6
- * @arg @ref LL_ADC_REG_RANK_7
- * @arg @ref LL_ADC_REG_RANK_8
- * @arg @ref LL_ADC_REG_RANK_9
- * @arg @ref LL_ADC_REG_RANK_10
- * @arg @ref LL_ADC_REG_RANK_11
- * @arg @ref LL_ADC_REG_RANK_12
- * @arg @ref LL_ADC_REG_RANK_13
- * @arg @ref LL_ADC_REG_RANK_14
- * @arg @ref LL_ADC_REG_RANK_15
- * @arg @ref LL_ADC_REG_RANK_16
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx,
- uint32_t Rank,
- uint32_t Channel) {
- /* Set bits with content of parameter "Channel" with bits position */
- /* in register and register position depending on parameter "Rank". */
- /* Parameters "Rank" and "Channel" are used with masks because containing */
- /* other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->SQR1,
- ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
-
- MODIFY_REG(
- *preg,
- ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
- ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
-}
-
-/**
- * @brief Get ADC group regular sequence: channel on the selected
- * scan sequence rank.
- * @note On this STM32 series, ADC group regular sequencer is
- * fully configurable: sequencer length and each rank
- * affectation to a channel are configurable.
- * Refer to description of function @ref
- * LL_ADC_REG_SetSequencerLength().
- * @note Depending on devices and packages, some channels may not be
- * available. Refer to device datasheet for channels availability.
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
- * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
- * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_RANK_1
- * @arg @ref LL_ADC_REG_RANK_2
- * @arg @ref LL_ADC_REG_RANK_3
- * @arg @ref LL_ADC_REG_RANK_4
- * @arg @ref LL_ADC_REG_RANK_5
- * @arg @ref LL_ADC_REG_RANK_6
- * @arg @ref LL_ADC_REG_RANK_7
- * @arg @ref LL_ADC_REG_RANK_8
- * @arg @ref LL_ADC_REG_RANK_9
- * @arg @ref LL_ADC_REG_RANK_10
- * @arg @ref LL_ADC_REG_RANK_11
- * @arg @ref LL_ADC_REG_RANK_12
- * @arg @ref LL_ADC_REG_RANK_13
- * @arg @ref LL_ADC_REG_RANK_14
- * @arg @ref LL_ADC_REG_RANK_15
- * @arg @ref LL_ADC_REG_RANK_16
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
- * register, comparison with internal channel parameter to be done using helper
- * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->SQR1,
- ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
-
- return (
- uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
- << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >>
- (Rank & ADC_REG_RANK_ID_SQRX_MASK))
- << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
-}
-
-/**
- * @brief Set ADC continuous conversion mode on ADC group regular.
- * @note Description of ADC continuous conversion mode:
- * - single mode: one conversion per trigger
- * - continuous mode: after the first trigger, following
- * conversions launched successively automatically.
- * @note It is not possible to enable both ADC group regular
- * continuous mode and sequencer discontinuous mode.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
- * @param ADCx ADC instance
- * @param Continuous This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_CONV_SINGLE
- * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx,
- uint32_t Continuous) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
-}
-
-/**
- * @brief Get ADC continuous conversion mode on ADC group regular.
- * @note Description of ADC continuous conversion mode:
- * - single mode: one conversion per trigger
- * - continuous mode: after the first trigger, following
- * conversions launched successively automatically.
- * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_CONV_SINGLE
- * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
-}
-
-/**
- * @brief Set ADC group regular conversion data transfer: no transfer or
- * transfer by DMA, and DMA requests mode.
- * @note If transfer by DMA selected, specifies the DMA requests
- * mode:
- * - Limited mode (One shot mode): DMA transfer requests are stopped
- * when number of DMA data transfers (number of
- * ADC conversions) is reached.
- * This ADC mode is intended to be used with DMA mode non-circular.
- * - Unlimited mode: DMA transfer requests are unlimited,
- * whatever number of DMA data transfers (number of
- * ADC conversions).
- * This ADC mode is intended to be used with DMA mode circular.
- * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- * mode non-circular:
- * when DMA transfers size will be reached, DMA will stop transfers of
- * ADC conversions data ADC will raise an overrun error
- * (overrun flag and interruption if enabled).
- * @note For devices with several ADC instances: ADC multimode DMA
- * settings are available using function @ref
- * LL_ADC_SetMultiDMATransfer().
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_ADC_DMA_GetRegAddr().
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
- * CFGR DMACFG LL_ADC_REG_SetDMATransfer
- * @param ADCx ADC instance
- * @param DMATransfer This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx,
- uint32_t DMATransfer) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
-}
-
-/**
- * @brief Get ADC group regular conversion data transfer: no transfer or
- * transfer by DMA, and DMA requests mode.
- * @note If transfer by DMA selected, specifies the DMA requests
- * mode:
- * - Limited mode (One shot mode): DMA transfer requests are stopped
- * when number of DMA data transfers (number of
- * ADC conversions) is reached.
- * This ADC mode is intended to be used with DMA mode non-circular.
- * - Unlimited mode: DMA transfer requests are unlimited,
- * whatever number of DMA data transfers (number of
- * ADC conversions).
- * This ADC mode is intended to be used with DMA mode circular.
- * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- * mode non-circular:
- * when DMA transfers size will be reached, DMA will stop transfers of
- * ADC conversions data ADC will raise an overrun error
- * (overrun flag and interruption if enabled).
- * @note For devices with several ADC instances: ADC multimode DMA
- * settings are available using function @ref
- * LL_ADC_GetMultiDMATransfer().
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_ADC_DMA_GetRegAddr().
- * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
- * CFGR DMACFG LL_ADC_REG_GetDMATransfer
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
-}
-
-/**
- * @brief Set ADC group regular behavior in case of overrun:
- * data preserved or overwritten.
- * @note Compatibility with devices without feature overrun:
- * other devices without this feature have a behavior
- * equivalent to data overwritten.
- * The default setting of overrun is data preserved.
- * Therefore, for compatibility with all devices, parameter
- * overrun should be set to data overwritten.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
- * @param ADCx ADC instance
- * @param Overrun This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
- * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx,
- uint32_t Overrun) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
-}
-
-/**
- * @brief Get ADC group regular behavior in case of overrun:
- * data preserved or overwritten.
- * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
- * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC
- * hierarchical scope: group injected
- * @{
- */
-
-/**
- * @brief Set ADC group injected conversion trigger source:
- * internal (SW start) or from external peripheral (timer event,
- * external interrupt line).
- * @note On this STM32 series, setting trigger source to external trigger
- * also set trigger polarity to rising edge
- * (default setting for compatibility with some ADC on other
- * STM32 families having this setting set by HW default value).
- * In case of need to modify trigger edge, use
- * function @ref LL_ADC_INJ_SetTriggerEdge().
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must not be disabled. Can be enabled with or without conversion
- * on going on either groups regular or injected.
- * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
- * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
- * @param ADCx ADC instance
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
- *
- * (1) On STM32G4 series, parameter not available on all ADC instances:
- * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
- * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
- * on all devices. Refer to device datasheet for more details.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx,
- uint32_t TriggerSource) {
- MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
-}
-
-/**
- * @brief Get ADC group injected conversion trigger source:
- * internal (SW start) or from external peripheral (timer event,
- * external interrupt line).
- * @note To determine whether group injected trigger source is
- * internal (SW start) or external, without detail
- * of which peripheral is selected as external trigger,
- * (equivalent to
- * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
- * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
- * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
- *
- * (1) On STM32G4 series, parameter not available on all ADC instances:
- * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
- * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
- * on all devices. Refer to device datasheet for more details.
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) {
- __IO uint32_t TriggerSource =
- READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
-
- /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
- /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
- uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >>
- (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
-
- /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
- /* to match with triggers literals definition. */
- return ((TriggerSource & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) &
- ADC_JSQR_JEXTSEL) |
- ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN));
-}
-
-/**
- * @brief Get ADC group injected conversion trigger source internal (SW start)
- or external
- * @note In case of group injected trigger source set to external trigger,
- * to determine which peripheral is selected as external trigger,
- * use function @ref LL_ADC_INJ_GetTriggerSource.
- * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
- * @param ADCx ADC instance
- * @retval Value "0" if trigger source external trigger
- * Value "1" if trigger source SW start.
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) ==
- (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set ADC group injected conversion trigger polarity.
- * Applicable only for trigger source set to external trigger.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must not be disabled. Can be enabled with or without conversion
- * on going on either groups regular or injected.
- * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
- * @param ADCx ADC instance
- * @param ExternalTriggerEdge This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
- * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx,
- uint32_t ExternalTriggerEdge) {
- MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
-}
-
-/**
- * @brief Get ADC group injected conversion trigger polarity.
- * Applicable only for trigger source set to external trigger.
- * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
- * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
-}
-
-/**
- * @brief Set ADC group injected sequencer length and scan direction.
- * @note This function performs configuration of:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must not be disabled. Can be enabled with or without conversion
- * on going on either groups regular or injected.
- * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
- * @param ADCx ADC instance
- * @param SequencerNbRanks This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx,
- uint32_t SequencerNbRanks) {
- MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
-}
-
-/**
- * @brief Get ADC group injected sequencer length and scan direction.
- * @note This function retrieves:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
-}
-
-/**
- * @brief Set ADC group injected sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @note It is not possible to enable both ADC group injected
- * auto-injected mode and sequencer discontinuous mode.
- * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
- * @param ADCx ADC instance
- * @param SeqDiscont This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx,
- uint32_t SeqDiscont) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
-}
-
-/**
- * @brief Get ADC group injected sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
-}
-
-/**
- * @brief Set ADC group injected sequence: channel on the selected
- * sequence rank.
- * @note Depending on devices and packages, some channels may not be
- * available. Refer to device datasheet for channels availability.
- * @note On this STM32 series, to measure internal channels (VrefInt,
- * TempSensor, ...), measurement paths to internal channels must be
- * enabled separately.
- * This can be done using function @ref
- * LL_ADC_SetCommonPathInternalCh().
- * @note On STM32G4, some fast channels are available: fast analog inputs
- * coming from GPIO pads (ADC_IN1..5).
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must not be disabled. Can be enabled with or without conversion
- * on going on either groups regular or injected.
- * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx,
- uint32_t Rank,
- uint32_t Channel) {
- /* Set bits with content of parameter "Channel" with bits position */
- /* in register depending on parameter "Rank". */
- /* Parameters "Rank" and "Channel" are used with masks because containing */
- /* other bits reserved for other purpose. */
- MODIFY_REG(ADCx->JSQR,
- (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
- ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
-}
-
-/**
- * @brief Get ADC group injected sequence: channel on the selected
- * sequence rank.
- * @note Depending on devices and packages, some channels may not be
- * available. Refer to device datasheet for channels availability.
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
- * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
- * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
- * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC
- * register, comparison with internal channel parameter to be done using helper
- * macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- return (uint32_t)((READ_BIT(ADCx->JSQR,
- (ADC_CHANNEL_ID_NUMBER_MASK >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) >>
- (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
- << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
-}
-
-/**
- * @brief Set ADC group injected conversion trigger:
- * independent or from ADC group regular.
- * @note This mode can be used to extend number of data registers
- * updated after one ADC conversion trigger and with data
- * permanently kept (not erased by successive conversions of scan of
- * ADC sequencer ranks), up to 5 data registers:
- * 1 data register on ADC group regular, 4 data registers
- * on ADC group injected.
- * @note If ADC group injected injected trigger source is set to an
- * external trigger, this feature must be must be set to
- * independent trigger.
- * ADC group injected automatic trigger is compliant only with
- * group injected trigger source set to SW start, without any
- * further action on ADC group injected conversion start or stop:
- * in this case, ADC group injected is controlled only
- * from ADC group regular.
- * @note It is not possible to enable both ADC group injected
- * auto-injected mode and sequencer discontinuous mode.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
- * @param ADCx ADC instance
- * @param TrigAuto This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
- * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx,
- uint32_t TrigAuto) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
-}
-
-/**
- * @brief Get ADC group injected conversion trigger:
- * independent or from ADC group regular.
- * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
- * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
-}
-
-/**
- * @brief Set ADC group injected contexts queue mode.
- * @note A context is a setting of group injected sequencer:
- * - group injected trigger
- * - sequencer length
- * - sequencer ranks
- * If contexts queue is disabled:
- * - only 1 sequence can be configured
- * and is active perpetually.
- * If contexts queue is enabled:
- * - up to 2 contexts can be queued
- * and are checked in and out as a FIFO stack (first-in, first-out).
- * - If a new context is set when queues is full, error is triggered
- * by interruption "Injected Queue Overflow".
- * - Two behaviors are possible when all contexts have been processed:
- * the contexts queue can maintain the last context active perpetually
- * or can be empty and injected group triggers are disabled.
- * - Triggers can be only external (not internal SW start)
- * - Caution: The sequence must be fully configured in one time
- * (one write of register JSQR makes a check-in of a new context
- * into the queue).
- * Therefore functions to set separately injected trigger and
- * sequencer channels cannot be used, register JSQR must be set
- * using function @ref LL_ADC_INJ_ConfigQueueContext().
- * @note This parameter can be modified only when no conversion is on going
- * on either groups regular or injected.
- * @note A modification of the context mode (bit JQDIS) causes the contexts
- * queue to be flushed and the register JSQR is cleared.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
- * CFGR JQDIS LL_ADC_INJ_SetQueueMode
- * @param ADCx ADC instance
- * @param QueueMode This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
- * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
- * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx,
- uint32_t QueueMode) {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
-}
-
-/**
- * @brief Get ADC group injected context queue mode.
- * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
- * CFGR JQDIS LL_ADC_INJ_GetQueueMode
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
- * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
- * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
-}
-
-/**
- * @brief Set one context on ADC group injected that will be checked in
- * contexts queue.
- * @note A context is a setting of group injected sequencer:
- * - group injected trigger
- * - sequencer length
- * - sequencer ranks
- * This function is intended to be used when contexts queue is enabled,
- * because the sequence must be fully configured in one time
- * (functions to set separately injected trigger and sequencer channels
- * cannot be used):
- * Refer to function @ref LL_ADC_INJ_SetQueueMode().
- * @note In the contexts queue, only the active context can be read.
- * The parameters of this function can be read using functions:
- * @arg @ref LL_ADC_INJ_GetTriggerSource()
- * @arg @ref LL_ADC_INJ_GetTriggerEdge()
- * @arg @ref LL_ADC_INJ_GetSequencerRanks()
- * @note On this STM32 series, to measure internal channels (VrefInt,
- * TempSensor, ...), measurement paths to internal channels must be
- * enabled separately.
- * This can be done using function @ref
- * LL_ADC_SetCommonPathInternalCh().
- * @note On STM32G4, some fast channels are available: fast analog inputs
- * coming from GPIO pads (ADC_IN1..5).
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must not be disabled. Can be enabled with or without conversion
- * on going on either groups regular or injected.
- * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
- * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
- * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
- * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
- * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
- * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
- * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
- * @param ADCx ADC instance
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
- * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
- *
- * (1) On STM32G4 series, parameter not available on all ADC instances:
- * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
- * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
- * on all devices. Refer to device datasheet for more details.
- * @param ExternalTriggerEdge This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
- * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
- *
- * Note: This parameter is discarded in case of SW start:
- * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
- * @param SequencerNbRanks This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- * @param Rank1_Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @param Rank2_Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @param Rank3_Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @param Rank4_Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(
- ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge,
- uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel,
- uint32_t Rank3_Channel, uint32_t Rank4_Channel) {
- /* Set bits with content of parameter "Rankx_Channel" with bits position */
- /* in register depending on literal "LL_ADC_INJ_RANK_x". */
- /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
- /* because containing other bits reserved for other purpose. */
- /* If parameter "TriggerSource" is set to SW start, then parameter */
- /* "ExternalTriggerEdge" is discarded. */
- uint32_t is_trigger_not_sw =
- (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
- MODIFY_REG(ADCx->JSQR,
- ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 |
- ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JL,
- (TriggerSource & ADC_JSQR_JEXTSEL) |
- (ExternalTriggerEdge * (is_trigger_not_sw)) |
- (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
- (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
- (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
- (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
- ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
- SequencerNbRanks);
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical
- * scope: channels
- * @{
- */
-
-/**
- * @brief Set sampling time of the selected ADC channel
- * Unit: ADC clock cycles.
- * @note On this device, sampling time is on channel scope: independently
- * of channel mapped on ADC group regular or injected.
- * @note In case of internal channel (VrefInt, TempSensor, ...) to be
- * converted:
- * sampling time constraints must be respected (sampling time can be
- * adjusted in function of ADC clock frequency and sampling time
- * setting).
- * Refer to device datasheet for timings values (parameters TS_vrefint,
- * TS_temp, ...).
- * @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 series, ADC processing time is:
- * - 12.5 ADC clock cycles at ADC resolution 12 bits
- * - 10.5 ADC clock cycles at ADC resolution 10 bits
- * - 8.5 ADC clock cycles at ADC resolution 8 bits
- * - 6.5 ADC clock cycles at ADC resolution 6 bits
- * @note In case of ADC conversion of internal channel (VrefInt,
- * temperature sensor, ...), a sampling time minimum value
- * is required.
- * Refer to device datasheet.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
- * @param ADCx ADC instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @param SamplingTime This parameter can be one of the following values:
- * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
- * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
- *
- * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
- * can be replaced by 3.5 ADC clock cycles.
- * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx,
- uint32_t Channel,
- uint32_t SamplingTime) {
- /* Set bits with content of parameter "SamplingTime" with bits position */
- /* in register and register position depending on parameter "Channel". */
- /* Parameter "Channel" is used with masks because containing */
- /* other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >>
- ADC_SMPRX_REGOFFSET_POS));
-
- MODIFY_REG(*preg,
- ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
- ADC_CHANNEL_SMPx_BITOFFSET_POS),
- SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
- ADC_CHANNEL_SMPx_BITOFFSET_POS));
-}
-
-/**
- * @brief Get sampling time of the selected ADC channel
- * Unit: ADC clock cycles.
- * @note On this device, sampling time is on channel scope: independently
- * of channel mapped on ADC group regular or injected.
- * @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 series, ADC processing time is:
- * - 12.5 ADC clock cycles at ADC resolution 12 bits
- * - 10.5 ADC clock cycles at ADC resolution 10 bits
- * - 8.5 ADC clock cycles at ADC resolution 8 bits
- * - 6.5 ADC clock cycles at ADC resolution 6 bits
- * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
- * @param ADCx ADC instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1 (8)
- * @arg @ref LL_ADC_CHANNEL_2 (8)
- * @arg @ref LL_ADC_CHANNEL_3 (8)
- * @arg @ref LL_ADC_CHANNEL_4 (8)
- * @arg @ref LL_ADC_CHANNEL_5 (8)
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
- * @arg @ref LL_ADC_CHANNEL_VBAT (6)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
- *
- * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
- * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
- * (6) On STM32G4, parameter available only on ADC instances: ADC1,
- * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
- * ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details. (8) On STM32G4, fast channel
- * allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
- * convert in 12-bit resolution. Other channels are slow channels allows: 6.5
- * (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in
- * 12-bit resolution.\n
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
- * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
- *
- * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
- * can be replaced by 3.5 ADC clock cycles.
- * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
- */
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx,
- uint32_t Channel) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >>
- ADC_SMPRX_REGOFFSET_POS));
-
- return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0
- << ((Channel &
- ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
- ADC_CHANNEL_SMPx_BITOFFSET_POS)) >>
- ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
- ADC_CHANNEL_SMPx_BITOFFSET_POS));
-}
-
-/**
- * @brief Set mode single-ended or differential input of the selected
- * ADC channel.
- * @note Channel ending is on channel scope: independently of channel mapped
- * on ADC group regular or injected.
- * In differential mode: Differential measurement is carried out
- * between the selected channel 'i' (positive input) and
- * channel 'i+1' (negative input). Only channel 'i' has to be
- * configured, channel 'i+1' is configured automatically.
- * @note Refer to Reference Manual to ensure the selected channel is
- * available in differential mode.
- * For example, internal channels (VrefInt, TempSensor, ...) are
- * not available in differential mode.
- * @note When configuring a channel 'i' in differential mode,
- * the channel 'i+1' is not usable separately.
- * @note On STM32G4, some channels are internally fixed to single-ended inputs
- * configuration:
- * - ADC1: Channels 12, 15, 16, 17 and 18
- * - ADC2: Channels 15, 17 and 18
- * - ADC3: Channels 12, 16, 17 and 18 (1)
- * - ADC4: Channels 16, 17 and 18 (1)
- * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
- * (1) ADC3/4/5 are not available on all devices, refer to device
- * datasheet for more details.
- * @note For ADC channels configured in differential mode, both inputs
- * should be biased at (Vref+)/2 +/-200mV.
- * (Vref+ is the analog voltage reference)
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled.
- * @note One or several values can be selected.
- * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
- * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
- * @param ADCx ADC instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @param SingleDiff This parameter can be a combination of the following
- * values:
- * @arg @ref LL_ADC_SINGLE_ENDED
- * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx,
- uint32_t Channel,
- uint32_t SingleDiff) {
- /* Bits for single or differential mode selection for each channel are set */
- /* to 1 only when the differential mode is selected, and to 0 when the */
- /* single mode is selected. */
-
- if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED) {
- SET_BIT(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
- } else {
- CLEAR_BIT(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
- }
-}
-
-/**
- * @brief Get mode single-ended or differential input of the selected
- * ADC channel.
- * @note When configuring a channel 'i' in differential mode,
- * the channel 'i+1' is not usable separately.
- * Therefore, to ensure a channel is configured in single-ended mode,
- * the configuration of channel itself and the channel 'i-1' must be
- * read back (to ensure that the selected channel channel has not been
- * configured in differential mode by the previous channel).
- * @note Refer to Reference Manual to ensure the selected channel is
- * available in differential mode.
- * For example, internal channels (VrefInt, TempSensor, ...) are
- * not available in differential mode.
- * @note When configuring a channel 'i' in differential mode,
- * the channel 'i+1' is not usable separately.
- * @note On STM32G4, some channels are internally fixed to single-ended inputs
- * configuration:
- * - ADC1: Channels 12, 15, 16, 17 and 18
- * - ADC2: Channels 15, 17 and 18
- * - ADC3: Channels 12, 16, 17 and 18 (1)
- * - ADC4: Channels 16, 17 and 18 (1)
- * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
- * (1) ADC3/4/5 are not available on all devices, refer to device
- * datasheet for more details.
- * @note One or several values can be selected. In this case, the value
- * returned is null if all channels are in single ended-mode.
- * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
- * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
- * @param ADCx ADC instance
- * @param Channel This parameter can be a combination of the following values:
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @retval 0: channel in single-ended mode, else: channel in differential mode
- */
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx,
- uint32_t Channel) {
- return (uint32_t)(READ_BIT(ADCx->DIFSEL,
- (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC
- * transversal scope: analog watchdog
- * @{
- */
-
-/**
- * @brief Set ADC analog watchdog monitored channels:
- * a single channel, multiple channels or all channels,
- * on ADC groups regular and-or injected.
- * @note Once monitored channels are selected, analog watchdog
- * is enabled.
- * @note In case of need to define a single channel to monitor
- * with analog watchdog from sequencer channel definition,
- * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 series, there are 2 kinds of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * - AWD flexible (instances AWD2, AWD3):
- * - channels monitored: flexible on channels monitored, selection is
- * channel wise, from from 1 to all channels.
- * Specificity of this analog watchdog: Multiple channels can
- * be selected. For example:
- * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
- * - groups monitored: not selection possible (monitoring on both
- * groups regular and injected).
- * Channels selected are monitored on groups regular and injected:
- * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
- * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
- * - resolution: resolution is limited to 8 bits: if ADC resolution is
- * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
- * the 2 LSB are ignored.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
- * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
- * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
- * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
- * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
- * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
- * @param AWDChannelGroup This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
- * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
- *
- * (0) On STM32G4, parameter available only on analog watchdog number:
- * AWD1.\n (1) On STM32G4, parameter available only on ADC instance: ADC1.\n (2)
- * On STM32G4, parameter available only on ADC instance: ADC2.\n (3) On STM32G4,
- * parameter available only on ADC instance: ADC3.\n (4) On STM32G4, parameter
- * available only on ADC instance: ADC4.\n (5) On STM32G4, parameter available
- * only on ADC instance: ADC5.\n (6) On STM32G4, parameter available only on ADC
- * instances: ADC1, ADC3, ADC5.\n (7) On STM32G4, parameter available only on
- * ADC instances: ADC1, ADC3, ADC4, ADC5.\n
- * - On this STM32 series, all ADCx are not available on all devices.
- * Refer to device datasheet for more details.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx,
- uint32_t AWDy,
- uint32_t AWDChannelGroup) {
- /* Set bits with content of parameter "AWDChannelGroup" with bits position */
- /* in register and register position depending on parameter "AWDy". */
- /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
- /* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->CFGR,
- ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) +
- ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) *
- ADC_AWD_CR12_REGOFFSETGAP_VAL));
-
- MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
- AWDChannelGroup & AWDy);
-}
-
-/**
- * @brief Get ADC analog watchdog monitored channel.
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Applicable only when the analog watchdog is set to monitor
- * one channel.
- * @note On this STM32 series, there are 2 kinds of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * - AWD flexible (instances AWD2, AWD3):
- * - channels monitored: flexible on channels monitored, selection is
- * channel wise, from from 1 to all channels.
- * Specificity of this analog watchdog: Multiple channels can
- * be selected. For example:
- * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
- * - groups monitored: not selection possible (monitoring on both
- * groups regular and injected).
- * Channels selected are monitored on groups regular and injected:
- * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
- * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
- * - resolution: resolution is limited to 8 bits: if ADC resolution is
- * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
- * the 2 LSB are ignored.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
- * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
- * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
- * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
- * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
- * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2 (1)
- * @arg @ref LL_ADC_AWD3 (1)
- *
- * (1) On this AWD number, monitored channel can be retrieved
- * if only 1 channel is programmed (or none or all channels).
- * This function cannot retrieve monitored channel if
- * multiple channels are programmed simultaneously
- * by bitfield.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
- *
- * (0) On STM32G4, parameter available only on analog watchdog number:
- * AWD1.
- */
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx,
- uint32_t AWDy) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->CFGR,
- ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) +
- ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) *
- ADC_AWD_CR12_REGOFFSETGAP_VAL));
-
- uint32_t AnalogWDMonitChannels =
- (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
-
- /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
- /* (parameter value LL_ADC_AWD_DISABLE). */
- /* Else, the selected AWD is enabled and is monitoring a group of channels */
- /* or a single channel. */
- if (AnalogWDMonitChannels != 0UL) {
- if (AWDy == LL_ADC_AWD1) {
- if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) {
- /* AWD monitoring a group of channels */
- AnalogWDMonitChannels =
- ((AnalogWDMonitChannels | (ADC_AWD_CR23_CHANNEL_MASK)) &
- (~(ADC_CFGR_AWD1CH)));
- } else {
- /* AWD monitoring a single channel */
- AnalogWDMonitChannels =
- (AnalogWDMonitChannels |
- (ADC_AWD2CR_AWD2CH_0
- << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)));
- }
- } else {
- if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) ==
- ADC_AWD_CR23_CHANNEL_MASK) {
- /* AWD monitoring a group of channels */
- AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK |
- ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)));
- } else {
- /* AWD monitoring a single channel */
- /* AWD monitoring a group of channels */
- AnalogWDMonitChannels =
- (AnalogWDMonitChannels |
- (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) |
- (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels)
- << ADC_CFGR_AWD1CH_Pos));
- }
- }
- }
-
- return AnalogWDMonitChannels;
-}
-
-/**
- * @brief Set ADC analog watchdog thresholds value of both thresholds
- * high and low.
- * @note If value of only one threshold high or low must be set,
- * use function @ref LL_ADC_SetAnalogWDThresholds().
- * @note In case of ADC resolution different of 12 bits,
- * analog watchdog thresholds data require a specific shift.
- * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 series, there are 2 kinds of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * - AWD flexible (instances AWD2, AWD3):
- * - channels monitored: flexible on channels monitored, selection is
- * channel wise, from from 1 to all channels.
- * Specificity of this analog watchdog: Multiple channels can
- * be selected. For example:
- * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
- * - groups monitored: not selection possible (monitoring on both
- * groups regular and injected).
- * Channels selected are monitored on groups regular and injected:
- * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
- * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
- * - resolution: resolution is limited to 8 bits: if ADC resolution is
- * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
- * the 2 LSB are ignored.
- * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
- * impacted: the comparison of analog watchdog thresholds is done on
- * oversampling final computation (after ratio and shift application):
- * ADC data register bitfield [15:4] (12 most significant bits).
- * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
- * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
- * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
- * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
- * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
- * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
- * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(
- ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
- uint32_t AWDThresholdLowValue) {
- /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
- /* position in register and register position depending on parameter */
- /* "AWDy". */
- /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
- /* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->TR1,
- ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
-
- MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1,
- (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) |
- AWDThresholdLowValue);
-}
-
-/**
- * @brief Set ADC analog watchdog threshold value of threshold
- * high or low.
- * @note If values of both thresholds high or low must be set,
- * use function @ref LL_ADC_ConfigAnalogWDThresholds().
- * @note In case of ADC resolution different of 12 bits,
- * analog watchdog thresholds data require a specific shift.
- * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 series, there are 2 kinds of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * - AWD flexible (instances AWD2, AWD3):
- * - channels monitored: flexible on channels monitored, selection is
- * channel wise, from from 1 to all channels.
- * Specificity of this analog watchdog: Multiple channels can
- * be selected. For example:
- * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
- * - groups monitored: not selection possible (monitoring on both
- * groups regular and injected).
- * Channels selected are monitored on groups regular and injected:
- * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
- * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
- * - resolution: resolution is limited to 8 bits: if ADC resolution is
- * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
- * the 2 LSB are ignored.
- * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
- * impacted: the comparison of analog watchdog thresholds is done on
- * oversampling final computation (after ratio and shift application):
- * ADC data register bitfield [15:4] (12 most significant bits).
- * @note On this STM32 series, setting of this feature is not conditioned to
- * ADC state:
- * ADC can be disabled, enabled with or without conversion on going
- * on either ADC groups regular or injected.
- * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
- * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
- * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
- * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
- * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
- * TR3 LT3 LL_ADC_SetAnalogWDThresholds
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
- * @param AWDThresholdsHighLow This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
- * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
- * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx,
- uint32_t AWDy,
- uint32_t AWDThresholdsHighLow,
- uint32_t AWDThresholdValue) {
- /* Set bits with content of parameter "AWDThresholdValue" with bits */
- /* position in register and register position depending on parameters */
- /* "AWDThresholdsHighLow" and "AWDy". */
- /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
- /* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->TR1,
- ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
-
- MODIFY_REG(*preg, AWDThresholdsHighLow,
- AWDThresholdValue
- << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >>
- ADC_AWD_TRX_BIT_HIGH_SHIFT4));
-}
-
-/**
- * @brief Get ADC analog watchdog threshold value of threshold high,
- * threshold low or raw data with ADC thresholds high and low
- * concatenated.
- * @note If raw data with ADC thresholds high and low is retrieved,
- * the data of each threshold high or low can be isolated
- * using helper macro:
- * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
- * @note In case of ADC resolution different of 12 bits,
- * analog watchdog thresholds data require a specific shift.
- * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
- * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
- * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
- * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
- * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
- * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
- * TR3 LT3 LL_ADC_GetAnalogWDThresholds
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
- * @param AWDThresholdsHighLow This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
- * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
- * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(
- ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->TR1,
- ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
-
- return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >>
- (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >>
- ADC_AWD_TRX_BIT_HIGH_SHIFT4) &
- ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
-}
-
-/**
- * @brief Set ADC analog watchdog filtering configuration
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @note On this STM32 series, this feature is only available on first
- * analog watchdog (AWD1)
- * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @param FilteringConfig This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD_FILTERING_NONE
- * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(
- ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig) {
- /* Prevent unused argument(s) compilation warning */
- (void)(AWDy);
- MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
-}
-
-/**
- * @brief Get ADC analog watchdog filtering configuration
- * @note On this STM32 series, this feature is only available on first
- * analog watchdog (AWD1)
- * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
- * @param ADCx ADC instance
- * @param AWDy This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD1
- * @retval Returned value can be:
- * @arg @ref LL_ADC_AWD_FILTERING_NONE
- * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
- * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
- */
-__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx,
- uint32_t AWDy) {
- /* Prevent unused argument(s) compilation warning */
- (void)(AWDy);
- return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC
- * transversal scope: oversampling
- * @{
- */
-
-/**
- * @brief Set ADC oversampling scope: ADC groups regular and-or injected
- * (availability of ADC group injected depends on STM32 families).
- * @note If both groups regular and injected are selected,
- * specify behavior of ADC group injected interrupting
- * group regular: when ADC group injected is triggered,
- * the oversampling on ADC group regular is either
- * temporary stopped and continued, or resumed from start
- * (oversampler buffer reset).
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
- * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
- * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
- * @param ADCx ADC instance
- * @param OvsScope This parameter can be one of the following values:
- * @arg @ref LL_ADC_OVS_DISABLE
- * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
- * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
- * @arg @ref LL_ADC_OVS_GRP_INJECTED
- * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx,
- uint32_t OvsScope) {
- MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM,
- OvsScope);
-}
-
-/**
- * @brief Get ADC oversampling scope: ADC groups regular and-or injected
- * (availability of ADC group injected depends on STM32 families).
- * @note If both groups regular and injected are selected,
- * specify behavior of ADC group injected interrupting
- * group regular: when ADC group injected is triggered,
- * the oversampling on ADC group regular is either
- * temporary stopped and continued, or resumed from start
- * (oversampler buffer reset).
- * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
- * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
- * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_OVS_DISABLE
- * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
- * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
- * @arg @ref LL_ADC_OVS_GRP_INJECTED
- * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(
- ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
-}
-
-/**
- * @brief Set ADC oversampling discontinuous mode (triggered mode)
- * on the selected ADC group.
- * @note Number of oversampled conversions are done either in:
- * - continuous mode (all conversions of oversampling ratio
- * are done from 1 trigger)
- * - discontinuous mode (each conversion of oversampling ratio
- * needs a trigger)
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on group regular.
- * @note On this STM32 series, oversampling discontinuous mode
- * (triggered mode) can be used only when oversampling is
- * set on group regular only and in resumed mode.
- * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
- * @param ADCx ADC instance
- * @param OverSamplingDiscont This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_OVS_REG_CONT
- * @arg @ref LL_ADC_OVS_REG_DISCONT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(
- ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) {
- MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
-}
-
-/**
- * @brief Get ADC oversampling discontinuous mode (triggered mode)
- * on the selected ADC group.
- * @note Number of oversampled conversions are done either in:
- * - continuous mode (all conversions of oversampling ratio
- * are done from 1 trigger)
- * - discontinuous mode (each conversion of oversampling ratio
- * needs a trigger)
- * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_OVS_REG_CONT
- * @arg @ref LL_ADC_OVS_REG_DISCONT
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
-}
-
-/**
- * @brief Set ADC oversampling
- * (impacting both ADC groups regular and injected)
- * @note This function set the 2 items of oversampling configuration:
- * - ratio
- * - shift
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be disabled or enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
- * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
- * @param ADCx ADC instance
- * @param Ratio This parameter can be one of the following values:
- * @arg @ref LL_ADC_OVS_RATIO_2
- * @arg @ref LL_ADC_OVS_RATIO_4
- * @arg @ref LL_ADC_OVS_RATIO_8
- * @arg @ref LL_ADC_OVS_RATIO_16
- * @arg @ref LL_ADC_OVS_RATIO_32
- * @arg @ref LL_ADC_OVS_RATIO_64
- * @arg @ref LL_ADC_OVS_RATIO_128
- * @arg @ref LL_ADC_OVS_RATIO_256
- * @param Shift This parameter can be one of the following values:
- * @arg @ref LL_ADC_OVS_SHIFT_NONE
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx,
- uint32_t Ratio,
- uint32_t Shift) {
- MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
-}
-
-/**
- * @brief Get ADC oversampling ratio
- * (impacting both ADC groups regular and injected)
- * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
- * @param ADCx ADC instance
- * @retval Ratio This parameter can be one of the following values:
- * @arg @ref LL_ADC_OVS_RATIO_2
- * @arg @ref LL_ADC_OVS_RATIO_4
- * @arg @ref LL_ADC_OVS_RATIO_8
- * @arg @ref LL_ADC_OVS_RATIO_16
- * @arg @ref LL_ADC_OVS_RATIO_32
- * @arg @ref LL_ADC_OVS_RATIO_64
- * @arg @ref LL_ADC_OVS_RATIO_128
- * @arg @ref LL_ADC_OVS_RATIO_256
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
-}
-
-/**
- * @brief Get ADC oversampling shift
- * (impacting both ADC groups regular and injected)
- * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
- * @param ADCx ADC instance
- * @retval Shift This parameter can be one of the following values:
- * @arg @ref LL_ADC_OVS_SHIFT_NONE
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
- * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
- */
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC
- * hierarchical scope: multimode
- * @{
- */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Set ADC multimode configuration to operate in independent mode
- * or multimode (for devices with several ADC instances).
- * @note If multimode configuration: the selected ADC instance is
- * either master or slave depending on hardware.
- * Refer to reference manual.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled.
- * This check can be done with function @ref LL_ADC_IsEnabled() for each
- * ADC instance or by using helper macro
- * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
- * @rmtoll CCR DUAL LL_ADC_SetMultimode
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param Multimode This parameter can be one of the following values:
- * @arg @ref LL_ADC_MULTI_INDEPENDENT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON,
- uint32_t Multimode) {
- MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
-}
-
-/**
- * @brief Get ADC multimode configuration to operate in independent mode
- * or multimode (for devices with several ADC instances).
- * @note If multimode configuration: the selected ADC instance is
- * either master or slave depending on hardware.
- * Refer to reference manual.
- * @rmtoll CCR DUAL LL_ADC_GetMultimode
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_MULTI_INDEPENDENT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
- */
-__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) {
- return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
-}
-
-/**
- * @brief Set ADC multimode conversion data transfer: no transfer
- * or transfer by DMA.
- * @note If ADC multimode transfer by DMA is not selected:
- * each ADC uses its own DMA channel, with its individual
- * DMA transfer settings.
- * If ADC multimode transfer by DMA is selected:
- * One DMA channel is used for both ADC (DMA of ADC master)
- * Specifies the DMA requests mode:
- * - Limited mode (One shot mode): DMA transfer requests are stopped
- * when number of DMA data transfers (number of
- * ADC conversions) is reached.
- * This ADC mode is intended to be used with DMA mode non-circular.
- * - Unlimited mode: DMA transfer requests are unlimited,
- * whatever number of DMA data transfers (number of
- * ADC conversions).
- * This ADC mode is intended to be used with DMA mode circular.
- * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- * mode non-circular:
- * when DMA transfers size will be reached, DMA will stop transfers of
- * ADC conversions data ADC will raise an overrun error
- * (overrun flag and interruption if enabled).
- * @note How to retrieve multimode conversion data:
- * Whatever multimode transfer by DMA setting: using function
- * @ref LL_ADC_REG_ReadMultiConversionData32().
- * If ADC multimode transfer by DMA is selected: conversion data
- * is a raw data with ADC master and slave concatenated.
- * A macro is available to get the conversion data of
- * ADC master or ADC slave: see helper macro
- * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled
- * or enabled without conversion on going on group regular.
- * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
- * CCR DMACFG LL_ADC_SetMultiDMATransfer
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param MultiDMATransfer This parameter can be one of the following values:
- * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
- * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
- * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
- * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
- * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(
- ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) {
- MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
- MultiDMATransfer);
-}
-
-/**
- * @brief Get ADC multimode conversion data transfer: no transfer
- * or transfer by DMA.
- * @note If ADC multimode transfer by DMA is not selected:
- * each ADC uses its own DMA channel, with its individual
- * DMA transfer settings.
- * If ADC multimode transfer by DMA is selected:
- * One DMA channel is used for both ADC (DMA of ADC master)
- * Specifies the DMA requests mode:
- * - Limited mode (One shot mode): DMA transfer requests are stopped
- * when number of DMA data transfers (number of
- * ADC conversions) is reached.
- * This ADC mode is intended to be used with DMA mode non-circular.
- * - Unlimited mode: DMA transfer requests are unlimited,
- * whatever number of DMA data transfers (number of
- * ADC conversions).
- * This ADC mode is intended to be used with DMA mode circular.
- * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- * mode non-circular:
- * when DMA transfers size will be reached, DMA will stop transfers of
- * ADC conversions data ADC will raise an overrun error
- * (overrun flag and interruption if enabled).
- * @note How to retrieve multimode conversion data:
- * Whatever multimode transfer by DMA setting: using function
- * @ref LL_ADC_REG_ReadMultiConversionData32().
- * If ADC multimode transfer by DMA is selected: conversion data
- * is a raw data with ADC master and slave concatenated.
- * A macro is available to get the conversion data of
- * ADC master or ADC slave: see helper macro
- * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
- * CCR DMACFG LL_ADC_GetMultiDMATransfer
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
- * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
- * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
- * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
- * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
- */
-__STATIC_INLINE uint32_t
-LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) {
- return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
-}
-
-/**
- * @brief Set ADC multimode delay between 2 sampling phases.
- * @note The sampling delay range depends on ADC resolution:
- * - ADC resolution 12 bits can have maximum delay of 12 cycles.
- * - ADC resolution 10 bits can have maximum delay of 10 cycles.
- * - ADC resolution 8 bits can have maximum delay of 8 cycles.
- * - ADC resolution 6 bits can have maximum delay of 6 cycles.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled.
- * This check can be done with function @ref LL_ADC_IsEnabled() for each
- * ADC instance or by using helper macro helper macro
- * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
- * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param MultiTwoSamplingDelay This parameter can be one of the following
- * values:
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
- *
- * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
- * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
- * (3) Parameter available only if ADC resolution is 12 bits.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(
- ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) {
- MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
-}
-
-/**
- * @brief Get ADC multimode delay between 2 sampling phases.
- * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
- * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
- *
- * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
- * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
- * (3) Parameter available only if ADC resolution is 12 bits.
- */
-__STATIC_INLINE uint32_t
-LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) {
- return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical
- * scope: ADC instance
- * @{
- */
-
-/**
- * @brief Put ADC instance in deep power down state.
- * @note In case of ADC calibration necessary: When ADC is in deep-power-down
- * state, the internal analog calibration is lost. After exiting from
- * deep power down, calibration must be relaunched or calibration factor
- * (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled.
- * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD);
-}
-
-/**
- * @brief Disable ADC deep power down mode.
- * @note In case of ADC calibration necessary: When ADC is in deep-power-down
- * state, the internal analog calibration is lost. After exiting from
- * deep power down, calibration must be relaunched or calibration factor
- * (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled.
- * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
-}
-
-/**
- * @brief Get the selected ADC instance deep power down state.
- * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
- * @param ADCx ADC instance
- * @retval 0: deep power down is disabled, 1: deep power down is enabled.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable ADC instance internal voltage regulator.
- * @note On this STM32 series, after ADC internal voltage regulator enable,
- * a delay for ADC internal voltage regulator stabilization
- * is required before performing a ADC calibration or ADC enable.
- * Refer to device datasheet, parameter tADCVREG_STUP.
- * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled.
- * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN);
-}
-
-/**
- * @brief Disable ADC internal voltage regulator.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled.
- * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
-}
-
-/**
- * @brief Get the selected ADC instance internal voltage regulator state.
- * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
- * @param ADCx ADC instance
- * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable the selected ADC instance.
- * @note On this STM32 series, after ADC enable, a delay for
- * ADC internal analog stabilization is required before performing a
- * ADC conversion start.
- * Refer to device datasheet, parameter tSTAB.
- * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
- * is enabled and when conversion clock is active.
- * (not only core clock: this ADC has a dual clock domain)
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled and ADC internal voltage regulator enabled.
- * @rmtoll CR ADEN LL_ADC_Enable
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN);
-}
-
-/**
- * @brief Disable the selected ADC instance.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be not disabled. Must be enabled without conversion on going
- * on either groups regular or injected.
- * @rmtoll CR ADDIS LL_ADC_Disable
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS);
-}
-
-/**
- * @brief Get the selected ADC instance enable state.
- * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
- * is enabled and when conversion clock is active.
- * (not only core clock: this ADC has a dual clock domain)
- * @rmtoll CR ADEN LL_ADC_IsEnabled
- * @param ADCx ADC instance
- * @retval 0: ADC is disabled, 1: ADC is enabled.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get the selected ADC instance disable state.
- * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
- * @param ADCx ADC instance
- * @retval 0: no ADC disable command on going.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Start ADC calibration in the mode single-ended
- * or differential (for devices with differential mode available).
- * @note On this STM32 series, a minimum number of ADC clock cycles
- * are required between ADC end of calibration and ADC enable.
- * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
- * @note For devices with differential mode available:
- * Calibration of offset is specific to each of
- * single-ended and differential modes
- * (calibration run must be performed for each of these
- * differential modes, if used afterwards and if the application
- * requires their calibration).
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be ADC disabled.
- * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
- * CR ADCALDIF LL_ADC_StartCalibration
- * @param ADCx ADC instance
- * @param SingleDiff This parameter can be one of the following values:
- * @arg @ref LL_ADC_SINGLE_ENDED
- * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx,
- uint32_t SingleDiff) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
- ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
-}
-
-/**
- * @brief Get ADC calibration state.
- * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
- * @param ADCx ADC instance
- * @retval 0: calibration complete, 1: calibration in progress.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC
- * hierarchical scope: group regular
- * @{
- */
-
-/**
- * @brief Start ADC group regular conversion.
- * @note On this STM32 series, this function is relevant for both
- * internal trigger (SW start) and external trigger:
- * - If ADC trigger has been set to software start, ADC conversion
- * starts immediately.
- * - If ADC trigger has been set to external trigger, ADC conversion
- * will start at next trigger event (on the selected trigger edge)
- * following the ADC start conversion command.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled without conversion on going on group regular,
- * without conversion stop command on going on group regular,
- * without ADC disable command on going.
- * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART);
-}
-
-/**
- * @brief Stop ADC group regular conversion.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled with conversion on going on group regular,
- * without ADC disable command on going.
- * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP);
-}
-
-/**
- * @brief Get ADC group regular conversion state.
- * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
- * @param ADCx ADC instance
- * @retval 0: no conversion is on going on ADC group regular.
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get ADC group regular command of conversion stop state
- * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
- * @param ADCx ADC instance
- * @retval 0: no command of conversion stop is on going on ADC group regular.
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Start ADC sampling phase for sampling time trigger mode
- * @note This function is relevant only when
- * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
- * using @ref LL_ADC_REG_SetSamplingMode
- * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled without conversion on going on group regular,
- * without conversion stop command on going on group regular,
- * without ADC disable command on going.
- * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
-}
-
-/**
- * @brief Stop ADC sampling phase for sampling time trigger mode and start
- * conversion
- * @note This function is relevant only when
- * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
- * using @ref LL_ADC_REG_SetSamplingMode
- * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
- * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
- * the sampling phase
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled without conversion on going on group regular,
- * without conversion stop command on going on group regular,
- * without ADC disable command on going.
- * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * all ADC configurations: all ADC resolutions and
- * all oversampling increased data width (for devices
- * with feature oversampling).
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) {
- return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * ADC resolution 12 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_REG_ReadConversionData32.
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) {
- return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * ADC resolution 10 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_REG_ReadConversionData32.
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
- */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) {
- return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * ADC resolution 8 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_REG_ReadConversionData32.
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) {
- return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * ADC resolution 6 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_REG_ReadConversionData32.
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x3F
- */
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) {
- return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Get ADC multimode conversion data of ADC master, ADC slave
- * or raw data with ADC master and slave concatenated.
- * @note If raw data with ADC master and slave concatenated is retrieved,
- * a macro is available to get the conversion data of
- * ADC master or ADC slave: see helper macro
- * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * (however this macro is mainly intended for multimode
- * transfer by DMA, because this function can do the same
- * by getting multimode conversion data of ADC master or ADC slave
- * separately).
- * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
- * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param ConversionData This parameter can be one of the following values:
- * @arg @ref LL_ADC_MULTI_MASTER
- * @arg @ref LL_ADC_MULTI_SLAVE
- * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(
- ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) {
- return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >>
- (POSITION_VAL(ConversionData) & 0x1FUL));
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC
- * hierarchical scope: group injected
- * @{
- */
-
-/**
- * @brief Start ADC group injected conversion.
- * @note On this STM32 series, this function is relevant for both
- * internal trigger (SW start) and external trigger:
- * - If ADC trigger has been set to software start, ADC conversion
- * starts immediately.
- * - If ADC trigger has been set to external trigger, ADC conversion
- * will start at next trigger event (on the selected trigger edge)
- * following the ADC start conversion command.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled without conversion on going on group injected,
- * without conversion stop command on going on group injected,
- * without ADC disable command on going.
- * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART);
-}
-
-/**
- * @brief Stop ADC group injected conversion.
- * @note On this STM32 series, setting of this feature is conditioned to
- * ADC state:
- * ADC must be enabled with conversion on going on group injected,
- * without ADC disable command on going.
- * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) {
- /* Note: Write register with some additional bits forced to state reset */
- /* instead of modifying only the selected bit for this function, */
- /* to not interfere with bits with HW property "rs". */
- MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP);
-}
-
-/**
- * @brief Get ADC group injected conversion state.
- * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
- * @param ADCx ADC instance
- * @retval 0: no conversion is on going on ADC group injected.
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get ADC group injected command of conversion stop state
- * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
- * @param ADCx ADC instance
- * @retval 0: no command of conversion stop is on going on ADC group injected.
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get ADC group injected conversion data, range fit for
- * all ADC configurations: all ADC resolutions and
- * all oversampling increased data width (for devices
- * with feature oversampling).
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->JDR1,
- ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
-
- return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
-}
-
-/**
- * @brief Get ADC group injected conversion data, range fit for
- * ADC resolution 12 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->JDR1,
- ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
-
- return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
-}
-
-/**
- * @brief Get ADC group injected conversion data, range fit for
- * ADC resolution 10 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
- */
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->JDR1,
- ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
-
- return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
-}
-
-/**
- * @brief Get ADC group injected conversion data, range fit for
- * ADC resolution 8 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->JDR1,
- ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
-
- return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
-}
-
-/**
- * @brief Get ADC group injected conversion data, range fit for
- * ADC resolution 6 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x00 and Max_Data=0x3F
- */
-__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx,
- uint32_t Rank) {
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
- ADCx->JDR1,
- ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
-
- return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
- * @{
- */
-
-/**
- * @brief Get flag ADC ready.
- * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
- * is enabled and when conversion clock is active.
- * (not only core clock: this ADC has a dual clock domain)
- * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC group regular end of unitary conversion.
- * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get flag ADC group regular end of sequence conversions.
- * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC group regular overrun.
- * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC group regular end of sampling phase.
- * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC group injected end of unitary conversion.
- * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC group injected end of sequence conversions.
- * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC group injected contexts queue overflow.
- * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC analog watchdog 1 flag
- * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC analog watchdog 2.
- * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag ADC analog watchdog 3.
- * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Clear flag ADC ready.
- * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
- * is enabled and when conversion clock is active.
- * (not only core clock: this ADC has a dual clock domain)
- * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
-}
-
-/**
- * @brief Clear flag ADC group regular end of unitary conversion.
- * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
-}
-
-/**
- * @brief Clear flag ADC group regular end of sequence conversions.
- * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
-}
-
-/**
- * @brief Clear flag ADC group regular overrun.
- * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
-}
-
-/**
- * @brief Clear flag ADC group regular end of sampling phase.
- * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
-}
-
-/**
- * @brief Clear flag ADC group injected end of unitary conversion.
- * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
-}
-
-/**
- * @brief Clear flag ADC group injected end of sequence conversions.
- * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
-}
-
-/**
- * @brief Clear flag ADC group injected contexts queue overflow.
- * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
-}
-
-/**
- * @brief Clear flag ADC analog watchdog 1.
- * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
-}
-
-/**
- * @brief Clear flag ADC analog watchdog 2.
- * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
-}
-
-/**
- * @brief Clear flag ADC analog watchdog 3.
- * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) {
- WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Get flag multimode ADC ready of the ADC master.
- * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) ==
- (LL_ADC_FLAG_ADRDY_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC ready of the ADC slave.
- * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) ==
- (LL_ADC_FLAG_ADRDY_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of unitary conversion of the
- * ADC master.
- * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) ==
- (LL_ADC_FLAG_EOC_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of unitary conversion of the
- * ADC slave.
- * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) ==
- (LL_ADC_FLAG_EOC_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of sequence conversions of
- * the ADC master.
- * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) ==
- (LL_ADC_FLAG_EOS_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of sequence conversions of
- * the ADC slave.
- * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) ==
- (LL_ADC_FLAG_EOS_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular overrun of the ADC master.
- * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) ==
- (LL_ADC_FLAG_OVR_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular overrun of the ADC slave.
- * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) ==
- (LL_ADC_FLAG_OVR_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of sampling of the ADC
- * master.
- * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) ==
- (LL_ADC_FLAG_EOSMP_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of sampling of the ADC
- * slave.
- * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) ==
- (LL_ADC_FLAG_EOSMP_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group injected end of unitary conversion of
- * the ADC master.
- * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) ==
- (LL_ADC_FLAG_JEOC_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group injected end of unitary conversion of
- * the ADC slave.
- * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) ==
- (LL_ADC_FLAG_JEOC_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group injected end of sequence conversions of
- * the ADC master.
- * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) ==
- (LL_ADC_FLAG_JEOS_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group injected end of sequence conversions of
- * the ADC slave.
- * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) ==
- (LL_ADC_FLAG_JEOS_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group injected context queue overflow of the
- * ADC master.
- * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) ==
- (LL_ADC_FLAG_JQOVF_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC group injected context queue overflow of the
- * ADC slave.
- * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) ==
- (LL_ADC_FLAG_JQOVF_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
- * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) ==
- (LL_ADC_FLAG_AWD1_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode analog watchdog 1 of the ADC slave.
- * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) ==
- (LL_ADC_FLAG_AWD1_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
- * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) ==
- (LL_ADC_FLAG_AWD2_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
- * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) ==
- (LL_ADC_FLAG_AWD2_SLV))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
- * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) ==
- (LL_ADC_FLAG_AWD3_MST))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
- * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) {
- return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) ==
- (LL_ADC_FLAG_AWD3_SLV))
- ? 1UL
- : 0UL);
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_IT_Management ADC IT management
- * @{
- */
-
-/**
- * @brief Enable ADC ready.
- * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
-}
-
-/**
- * @brief Enable interruption ADC group regular end of unitary conversion.
- * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
-}
-
-/**
- * @brief Enable interruption ADC group regular end of sequence conversions.
- * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
-}
-
-/**
- * @brief Enable ADC group regular interruption overrun.
- * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
-}
-
-/**
- * @brief Enable interruption ADC group regular end of sampling.
- * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
-}
-
-/**
- * @brief Enable interruption ADC group injected end of unitary conversion.
- * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
-}
-
-/**
- * @brief Enable interruption ADC group injected end of sequence conversions.
- * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
-}
-
-/**
- * @brief Enable interruption ADC group injected context queue overflow.
- * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
-}
-
-/**
- * @brief Enable interruption ADC analog watchdog 1.
- * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
-}
-
-/**
- * @brief Enable interruption ADC analog watchdog 2.
- * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
-}
-
-/**
- * @brief Enable interruption ADC analog watchdog 3.
- * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) {
- SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
-}
-
-/**
- * @brief Disable interruption ADC ready.
- * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
-}
-
-/**
- * @brief Disable interruption ADC group regular end of unitary conversion.
- * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
-}
-
-/**
- * @brief Disable interruption ADC group regular end of sequence conversions.
- * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
-}
-
-/**
- * @brief Disable interruption ADC group regular overrun.
- * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
-}
-
-/**
- * @brief Disable interruption ADC group regular end of sampling.
- * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
-}
-
-/**
- * @brief Disable interruption ADC group regular end of unitary conversion.
- * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
-}
-
-/**
- * @brief Disable interruption ADC group injected end of sequence conversions.
- * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
-}
-
-/**
- * @brief Disable interruption ADC group injected context queue overflow.
- * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
-}
-
-/**
- * @brief Disable interruption ADC analog watchdog 1.
- * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
-}
-
-/**
- * @brief Disable interruption ADC analog watchdog 2.
- * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
-}
-
-/**
- * @brief Disable interruption ADC analog watchdog 3.
- * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) {
- CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
-}
-
-/**
- * @brief Get state of interruption ADC ready
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group regular end of unitary conversion
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group regular end of sequence
- * conversions (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group regular overrun
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group regular end of sampling
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group injected end of unitary
- * conversion (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group injected end of sequence
- * conversions (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC group injected context queue overflow
- * interrupt state (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption ADC analog watchdog 1
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption Get ADC analog watchdog 2
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get state of interruption Get ADC analog watchdog 3
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) {
- return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization of some features of ADC common parameters and multimode */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON,
- LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-
-/* De-initialization of ADC instance, ADC group regular and ADC group injected
- */
-/* (availability of ADC group injected depends on STM32 families) */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
-
-/* Initialization of some features of ADC instance */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group regular */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx,
- LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group injected */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx,
- LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_ADC_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_ADC_H
+#define STM32G4xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(ADC1) || defined(ADC2) || defined(ADC3) || defined(ADC4) || \
+ defined(ADC5)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET (0x00000000UL)
+#define ADC_SQR2_REGOFFSET (0x00000100UL)
+#define ADC_SQR3_REGOFFSET (0x00000200UL)
+#define ADC_SQR4_REGOFFSET (0x00000300UL)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK \
+ (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | \
+ ADC_SQR4_REGOFFSET)
+#define ADC_SQRX_REGOFFSET_POS \
+ (8UL) /* Position of bits ADC_SQRx_REGOFFSET in \
+ ADC_REG_SQRX_REGOFFSET_MASK*/
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET (0x00000000UL)
+#define ADC_JDR2_REGOFFSET (0x00000100UL)
+#define ADC_JDR3_REGOFFSET (0x00000200UL)
+#define ADC_JDR4_REGOFFSET (0x00000300UL)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK \
+ (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | \
+ ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+#define ADC_JDRX_REGOFFSET_POS \
+ (8UL) /* Position of bits ADC_JDRx_REGOFFSET in \
+ ADC_INJ_JDRX_REGOFFSET_MASK*/
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
+
+/* Internal mask for ADC group regular trigger: */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
+/* - regular trigger source */
+/* - regular trigger edge */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT \
+ (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for \
+ compatibility with some ADC on other STM32 series \
+ having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_SOURCE_MASK \
+ (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 3UL)))
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_EDGE_MASK \
+ (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)))
+
+/* Definition of ADC group regular trigger bits information. */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
+
+/* Internal mask for ADC group injected trigger: */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
+/* - injected trigger source */
+/* - injected trigger edge */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT \
+ (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for \
+ compatibility with some ADC on other STM32 series \
+ having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_SOURCE_MASK \
+ (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)))
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_EDGE_MASK \
+ (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)))
+
+/* Definition of ADC group injected trigger bits information. */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel identifier defined by bitfield */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
+#define ADC_CHANNEL_ID_MASK \
+ (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
+ ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 \
+ (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK \
+>> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH \
+ (0x80000000UL) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 \
+ (0x00080000UL) /* Marker of internal channel for other ADC instances, in \
+ case of different ADC internal channels mapped on same \
+ channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK \
+ (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET (0x00000000UL)
+#define ADC_SMPR2_REGOFFSET (0x02000000UL)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK \
+ (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+#define ADC_SMPRX_REGOFFSET_POS \
+ (25UL) /* Position of bits ADC_SMPRx_REGOFFSET \
+ in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS \
+ (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" \
+ position in register */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER \
+ (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER \
+ (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER \
+ (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER \
+ (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER \
+ (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | \
+ ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
+
+/* Definition of channels ID bitfield information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+/* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
+/* in register. */
+#define ADC_CHANNEL_0_SMP \
+ (ADC_SMPR1_REGOFFSET | ((0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_1_SMP \
+ (ADC_SMPR1_REGOFFSET | ((3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_2_SMP \
+ (ADC_SMPR1_REGOFFSET | ((6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_3_SMP \
+ (ADC_SMPR1_REGOFFSET | ((9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_4_SMP \
+ (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_5_SMP \
+ (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_6_SMP \
+ (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_7_SMP \
+ (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_8_SMP \
+ (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_9_SMP \
+ (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_10_SMP \
+ (ADC_SMPR2_REGOFFSET | ((0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_11_SMP \
+ (ADC_SMPR2_REGOFFSET | ((3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_12_SMP \
+ (ADC_SMPR2_REGOFFSET | ((6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_13_SMP \
+ (ADC_SMPR2_REGOFFSET | ((9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_14_SMP \
+ (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_15_SMP \
+ (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_16_SMP \
+ (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_17_SMP \
+ (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_18_SMP \
+ (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+
+/* Internal mask for ADC mode single or differential ended: */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration: calibration start, calibration factor get or set */
+/* - ADC channels: set each ADC channel ending mode */
+#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK \
+ (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK \
+ (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK \
+ (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen \
+ to perform of shift when single mode is selected, shift value out of \
+ channels bits range. */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK \
+ (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: \
+ mask of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS \
+ (16UL) /* Selection of 1 bit to discriminate differential mode: \
+position of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 \
+ (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit \
+ ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 series)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
+/* selection on groups. */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
+#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK \
+ (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK \
+ (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK \
+ (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS \
+ (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET \
+ in ADC_AWD_CRX_REGOFFSET_MASK */
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK \
+ (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS \
+ (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET \
+ in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK \
+ (0x00010000UL) /* Selection of 1 bit to discriminate \
+ threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS \
+ (16UL) /* Selection of 1 bit to discriminate \
+ threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 \
+ (ADC_AWD_TRX_BIT_HIGH_POS - \
+ 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to \
+ position to perform a shift of 4 ranks */
+
+/* Internal mask for ADC offset: */
+/* Internal register offset for ADC offset instance configuration */
+#define ADC_OFR1_REGOFFSET (0x00000000UL)
+#define ADC_OFR2_REGOFFSET (0x00000001UL)
+#define ADC_OFR3_REGOFFSET (0x00000002UL)
+#define ADC_OFR4_REGOFFSET (0x00000003UL)
+#define ADC_OFRx_REGOFFSET_MASK \
+ (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | \
+ ADC_OFR4_REGOFFSET)
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
+#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS \
+ (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS | ADC_CR_JADSTART | \
+ ADC_CR_JADSTP | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with \
+ HW property "rs": Software can read as well as set this bit. \
+ Writing '0' has no effect on the bit value. */
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR \
+ ((uint16_t *)(0x1FFF75AAUL)) /* Internal voltage reference, address of \
+ parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC \
+ (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF \
+ (3000UL) /* Analog voltage reference (Vref+) value \
+with which VrefInt has been calibrated in production \
+(tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR \
+ ((uint16_t *)(0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4, \
+ temperature sensor ADC raw data acquired at temperature 30 DegC \
+ (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR \
+ ((uint16_t *)(0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4, \
+ temperature sensor ADC raw data acquired at temperature 110 DegC \
+ (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP \
+ (30L) /* Temperature at which temperature sensor \
+has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR \
+(tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP \
+ (110L) /* Temperature at which temperature sensor \
+has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR \
+(tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG \
+ (3000UL) /* Analog voltage reference (Vref+) value \
+with which temperature sensor has been calibrated in production \
+(tolerance +-10 mV) (unit: mV). */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t)((uint32_t)(&(__REG__)) + \
+ ((__REG_OFFFSET__) << 2UL))))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct {
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source
+ and prescaler. This parameter can be a value of @ref
+ ADC_LL_EC_COMMON_CLOCK_SOURCE
+ @note On this STM32 series, if ADC group injected
+ is used, some clock ratio constraints between ADC
+ clock and AHB clock must be respected. Refer to
+ reference manual. This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in
+ independent mode or multimode (for devices with several
+ ADC instances). This parameter can be a value of @ref
+ ADC_LL_EC_MULTI_MODE This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_SetMultimode(). */
+
+ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no
+ transfer or transfer by DMA. This parameter can
+ be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_ADC_SetMultiDMATransfer(). */
+
+ uint32_t
+ MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling
+ phases. This parameter can be a value of @ref
+ ADC_LL_EC_MULTI_TWOSMP_DELAY This feature can be
+ modified afterwards using unitary function
+ @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 series).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 series. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct {
+ uint32_t Resolution; /*!< Set ADC resolution.
+ This parameter can be a value of @ref
+ ADC_LL_EC_RESOLUTION This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_SetResolution(). */
+
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref
+ ADC_LL_EC_DATA_ALIGN This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t LowPowerMode; /*!< Set ADC low power mode.
+ This parameter can be a value of @ref
+ ADC_LL_EC_LP_MODE This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 series. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct {
+ uint32_t
+ TriggerSource; /*!< Set ADC group regular conversion trigger source:
+ internal (SW start) or from external peripheral (timer
+ event, external interrupt line). This parameter can be a
+ value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 series, setting trigger source to
+ external trigger also set trigger polarity to rising
+ edge(default setting for compatibility with some ADC on
+ other STM32 series having this setting set by HW default
+ value). In case of need to modify trigger edge, use
+ function
+ @ref LL_ADC_REG_SetTriggerEdge().
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref
+ ADC_LL_EC_REG_SEQ_SCAN_LENGTH This feature can be
+ modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t
+ SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode:
+ sequence subdivided and scan conversions interrupted
+ every selected number of ranks. This parameter can be
+ a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group
+ regular sequencer is enabled (scan length of 2 ranks
+ or more). This feature can be modified afterwards
+ using unitary function
+ @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t
+ ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group
+ regular, whether ADC conversions are performed in
+ single mode (one conversion per trigger) or in
+ continuous mode (after the first trigger, following
+ conversions launched successively automatically). This
+ parameter can be a value of @ref
+ ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible
+ to enable both ADC group regular continuous mode and
+ discontinuous mode. This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no
+ transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref
+ ADC_LL_EC_REG_DMA_TRANSFER This feature can be
+ modified afterwards using unitary function
+ @ref LL_ADC_REG_SetDMATransfer(). */
+
+ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
+ data preserved or overwritten.
+ This parameter can be a value of @ref
+ ADC_LL_EC_REG_OVR_DATA_BEHAVIOR This feature can be
+ modified afterwards using unitary function
+ @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 series. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct {
+ uint32_t
+ TriggerSource; /*!< Set ADC group injected conversion trigger source:
+ internal (SW start) or from external peripheral (timer
+ event, external interrupt line). This parameter can be a
+ value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 series, setting trigger source to
+ external trigger also set trigger polarity to rising
+ edge (default setting for compatibility with some ADC on
+ other STM32 series having this setting set by HW default
+ value). In case of need to modify trigger edge, use
+ function
+ @ref LL_ADC_INJ_SetTriggerEdge().
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref
+ ADC_LL_EC_INJ_SEQ_SCAN_LENGTH This feature can be
+ modified afterwards using unitary function
+ @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous
+ mode: sequence subdivided and scan conversions
+ interrupted every selected number of ranks. This
+ parameter can be a value of @ref
+ ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if
+ group injected sequencer is enabled (scan length
+ of 2 ranks or more). This feature can be
+ modified afterwards using unitary function
+ @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t
+ TrigAuto; /*!< Set ADC group injected conversion trigger: independent or
+ from ADC group regular. This parameter can be a value of @ref
+ ADC_LL_EC_INJ_TRIG_AUTO Note: This parameter must be set to
+ set to independent trigger if injected trigger source is set
+ to an external trigger. This feature can be modified
+ afterwards using unitary function
+ @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC \
+ ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary \
+conversion */
+#define LL_ADC_FLAG_EOS \
+ ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence \
+conversions */
+#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP \
+ ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC \
+ ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary \
+ conversion */
+#define LL_ADC_FLAG_JEOS \
+ ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence \
+ conversions */
+#define LL_ADC_FLAG_JQOVF \
+ ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue \
+ overflow */
+#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST \
+ ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV \
+ ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST \
+ ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of \
+ unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV \
+ ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of \
+ unitary conversion */
+#define LL_ADC_FLAG_EOS_MST \
+ ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of \
+ sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV \
+ ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of \
+ sequence conversions */
+#define LL_ADC_FLAG_OVR_MST \
+ ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular \
+ overrun */
+#define LL_ADC_FLAG_OVR_SLV \
+ ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular \
+ overrun */
+#define LL_ADC_FLAG_EOSMP_MST \
+ ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of \
+ sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV \
+ ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of \
+ sampling phase */
+#define LL_ADC_FLAG_JEOC_MST \
+ ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of \
+ unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV \
+ ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of \
+ unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST \
+ ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of \
+ sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV \
+ ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of \
+ sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST \
+ ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected \
+ contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV \
+ ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected \
+ contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST \
+ ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 \
+ of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV \
+ ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 \
+ of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST \
+ ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 \
+ of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV \
+ ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 \
+ of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST \
+ ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 \
+ of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV \
+ ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 \
+ of the ADC slave */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption
+ * enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and
+ * LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_ADRDY \
+ ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC \
+ ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary \
+ conversion */
+#define LL_ADC_IT_EOS \
+ ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence \
+ conversions */
+#define LL_ADC_IT_OVR \
+ ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP \
+ ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling \
+ phase */
+#define LL_ADC_IT_JEOC \
+ ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary \
+ conversion */
+#define LL_ADC_IT_JEOS \
+ ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence \
+ conversions */
+#define LL_ADC_IT_JQOVF \
+ ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue \
+ overflow */
+#define LL_ADC_IT_AWD1 \
+ ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2 \
+ ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3 \
+ ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA \
+ (0x00000000UL) /* ADC group regular conversion data register \
+(corresponding to register DR) to be used with ADC configured in independent \
+mode. Without DMA transfer, register accessed by LL function \
+@ref LL_ADC_REG_ReadConversionData32() and other \
+functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI \
+ (0x00000001UL) /* ADC group regular conversion data register \
+(corresponding to register CDR) to be used with ADC configured in multimode \
+(available on STM32 devices with several ADC instances). \
+Without DMA transfer, register accessed by LL function \
+@ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 \
+ (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from \
+AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 \
+ (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from \
+AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 \
+ (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived \
+ from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1 \
+ (0x00000000UL) /*!< ADC asynchronous clock without \
+prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2 \
+ (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
+prescaler division by 2 */
+#define LL_ADC_CLOCK_ASYNC_DIV4 \
+ (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with \
+prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV6 \
+ (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
+ prescaler division by 6 */
+#define LL_ADC_CLOCK_ASYNC_DIV8 \
+ (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with \
+prescaler division by 8 */
+#define LL_ADC_CLOCK_ASYNC_DIV10 \
+ (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
+ prescaler division by 10 */
+#define LL_ADC_CLOCK_ASYNC_DIV12 \
+ (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with \
+ prescaler division by 12 */
+#define LL_ADC_CLOCK_ASYNC_DIV16 \
+ (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous \
+ clock with prescaler division by 16 */
+#define LL_ADC_CLOCK_ASYNC_DIV32 \
+ (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with \
+prescaler division by 32 */
+#define LL_ADC_CLOCK_ASYNC_DIV64 \
+ (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with \
+ prescaler division by 64 */
+#define LL_ADC_CLOCK_ASYNC_DIV128 \
+ (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with \
+ prescaler division by 128 */
+#define LL_ADC_CLOCK_ASYNC_DIV256 \
+ (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous \
+ clock with prescaler division by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to
+ * internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE \
+ (0x00000000UL) /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT \
+ (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR \
+ (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel \
+ temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT \
+ (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B (ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1) /*!< ADC resolution 8 bits */
+#define LL_ADC_RESOLUTION_6B \
+ (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT \
+ (0x00000000UL) /*!< ADC conversion data alignment: right aligned \
+(alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT \
+ (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned \
+(alignment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
+ * @{
+ */
+#define LL_ADC_LP_MODE_NONE \
+ (0x00000000UL) /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT \
+ (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power \
+ mode, ADC conversions are performed only when necessary \
+ (when previous ADC conversion data is read). \
+ See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
+ * @{
+ */
+#define LL_ADC_OFFSET_1 \
+ ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level \
+ to which the offset programmed will be applied (independently of channel \
+ mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_2 \
+ ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level \
+ to which the offset programmed will be applied (independently of channel \
+ mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_3 \
+ ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level \
+ to which the offset programmed will be applied (independently of channel \
+ mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_4 \
+ ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level \
+ to which the offset programmed will be applied (independently of channel \
+ mapped on ADC group regular or injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+ * @{
+ */
+#define LL_ADC_OFFSET_DISABLE \
+ (0x00000000UL) /*!< ADC offset disabled \
+(setting offset instance wise) */
+#define LL_ADC_OFFSET_ENABLE \
+ (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled \
+ (setting offset instance wise) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+ * @{
+ */
+#define LL_ADC_OFFSET_SIGN_NEGATIVE \
+ (0x00000000UL) /*!< ADC offset is negative */
+#define LL_ADC_OFFSET_SIGN_POSITIVE \
+ (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
+ * @{
+ */
+#define LL_ADC_OFFSET_SATURATION_DISABLE \
+ (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC \
+selected offset instance 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SATURATION_ENABLE \
+ (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC \
+selected offset instance 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR \
+ (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED \
+ (0x00000002UL) /*!< ADC group injected (not available on all STM32 \
+devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED \
+ (0x00000003UL) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 \
+ (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | \
+ ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 \
+ (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | \
+ ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 \
+ (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | \
+ ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 \
+ (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | \
+ ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 \
+ (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | \
+ ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 \
+ (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | \
+ ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 \
+ (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | \
+ ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 \
+ (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | \
+ ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 \
+ (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | \
+ ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 \
+ (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | \
+ ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 \
+ (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | \
+ ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 \
+ (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | \
+ ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 \
+ (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | \
+ ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 \
+ (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | \
+ ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 \
+ (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | \
+ ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 \
+ (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | \
+ ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 \
+ (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
+ ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 \
+ (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
+ ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 \
+ (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
+ ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT \
+ (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+ connected to VrefInt: Internal voltage reference. \
+ On this STM32 series, ADC channel available on all instances but ADC2. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 \
+ (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+ connected to internal temperature sensor. \
+ On this STM32 series, ADC channel available only on ADC1 instance. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 \
+ (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+ connected to internal temperature sensor. \
+ On this STM32 series, ADC channel available only on ADC5 instance. \
+ Refer to device datasheet for ADC5 availability */
+#define LL_ADC_CHANNEL_VBAT \
+ (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+ connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 \
+ to have channel voltage always below Vdda. On this STM32 series, ADC channel \
+ available on all ADC instances but ADC2 & ADC4. Refer to device datasheet \
+ for ADC4 availability */
+#define LL_ADC_CHANNEL_VOPAMP1 \
+ (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+ connected to OPAMP1 output. \
+ On this STM32 series, ADC channel available only on ADC1 instance. */
+#define LL_ADC_CHANNEL_VOPAMP2 \
+ (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \
+ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 \
+ output. On this STM32 series, ADC channel available only on ADC2 instance. \
+ */
+#define LL_ADC_CHANNEL_VOPAMP3_ADC2 \
+ (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
+ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 \
+ output. On this STM32 series, ADC channel available only on ADC2 instance. \
+ */
+#define LL_ADC_CHANNEL_VOPAMP3_ADC3 \
+ (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \
+ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 \
+ output. On this STM32 series, ADC channel available only on ADC3 instance. \
+ Refer to device datasheet for ADC3 availability */
+#define LL_ADC_CHANNEL_VOPAMP4 \
+ (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+connected to OPAMP4 output. On this STM32 series, ADC channel available only \
+on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */
+#define LL_ADC_CHANNEL_VOPAMP5 \
+ (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel \
+connected to OPAMP5 output. On this STM32 series, ADC channel available only \
+on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */
+#define LL_ADC_CHANNEL_VOPAMP6 \
+ (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
+ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel \
+connected to OPAMP6 output. \
+On this STM32 series, ADC channel available only on ADC4 instance. \
+Refer to device datasheet for ADC4 & OPAMP6 availability */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE \
+ (0x00000000UL) /*!< ADC group regular \
+conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM1 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM1 TRGO2. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 \
+ (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM1 channel 1 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 \
+ (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM1 channel 2 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 \
+ (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM1 channel 3 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM2 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH1 \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ conversion trigger from external peripheral: TIM2 channel 1 event (capture \
+ compare: input capture or output capture). \
+ Trigger edge set to rising edge (default setting). \
+ Note: On this STM32 series, this trigger is available only on \
+ ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 \
+ (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ ADC group regular conversion trigger from external \
+ peripheral: TIM2 channel 2 event (capture compare: input \
+ capture or output capture). Trigger edge set to rising \
+ edge (default setting). Note: On this STM32 series, this \
+ trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 \
+ (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM2 channel 3 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO \
+ (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM3 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 \
+ (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM3 channel 1 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM3 channel 4 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM4 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH1 \
+ (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM4 channel 1 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 \
+ (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ ADC group regular conversion trigger from external \
+ peripheral: TIM4 channel 4 event (capture compare: input \
+ capture or output capture). Trigger edge set to rising \
+ edge (default setting). Note: On this STM32 series, this \
+ trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM6 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+ ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< \
+conversion trigger from external peripheral: TIM7 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO \
+ (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM8 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 \
+ (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM8 TRGO2. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 \
+ (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM8 channel 1 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO \
+ (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM15 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO \
+ (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+ conversion trigger from external peripheral: TIM20 TRGO. \
+ Trigger edge set to rising edge (default setting). \
+ Note: On this STM32 series, TIM20 is not available on all devices. \
+ Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM20 TRGO2. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, TIM20 is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM20 channel 1 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, TIM20 is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH2 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM20 channel 2 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC1/2 instances, and TIM20 is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH3 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: TIM20 channel 3 event (capture \
+compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC1/2 instances, and TIM20 is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances, and HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances, and HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
+ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. \
+Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 \
+ (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: external interrupt line 11. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 \
+ (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: external interrupt line 2. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on \
+ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT \
+ (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular \
+conversion trigger from external peripheral: LPTIMER OUT event. \
+Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING \
+ (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion \
+trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING \
+ (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion \
+trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING \
+ (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion \
+trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
+ * @{
+ */
+#define LL_ADC_REG_SAMPLING_MODE_NORMAL \
+ (0x00000000UL) /*!< ADC conversions sampling phase duration \
+is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
+#define LL_ADC_REG_SAMPLING_MODE_BULB \
+ (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts \
+immediately after end of conversion, and stops upon trigger event. \
+Note: First conversion is using minimal sampling time \
+(see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
+#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED \
+ (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is \
+controlled by trigger events: trigger rising edge for start sampling, \
+trigger falling edge for stop sampling and start conversion */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+ * @{
+ */
+#define LL_ADC_REG_CONV_SINGLE \
+ (0x00000000UL) /*!< ADC conversions performed in single mode: \
+one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS \
+ (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode: \
+after the first trigger, following conversions launched successively \
+automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of
+ * ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE \
+ (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED \
+ (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA \
+in limited mode (one shot mode): DMA transfer requests are stopped when \
+number of DMA data transfers (number of ADC conversions) is reached. \
+This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED \
+ (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are \
+transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, \
+whatever number of DMA data transferred (number of ADC conversions). \
+This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling
+ * time common configuration
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT \
+ (0x00000000UL) /*!< ADC sampling time let to default settings. */
+#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 \
+ (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock \
+cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped \
+with selection sampling time 2.5 ADC clock cycles, whatever channels mapped \
+on ADC groups regular or injected). */
+/**
+ * @}
+ */
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun
+ * behavior on conversion data
+ * @{
+ */
+#define LL_ADC_REG_OVR_DATA_PRESERVED \
+ (0x00000000UL) /*!< ADC group regular behavior in case of overrun: \
+ data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN \
+ (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: \
+ data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan
+ * length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE \
+ (0x00000000UL) /*!< ADC group regular sequencer disable \
+(equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS \
+ (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable \
+with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS \
+ (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable \
+with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS \
+ (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable \
+ with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS \
+ (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable \
+with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS \
+ (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable \
+ with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS \
+ (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable \
+ with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS \
+ (ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular \
+ sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS \
+ (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable \
+with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable \
+ with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable \
+ with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular \
+ sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable \
+ with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular \
+ sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular \
+ sequencerenable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS \
+ (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | \
+ ADC_SQR1_L_0) /*!< ADC group regular sequencer enable \
+ with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer
+ * discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE \
+ (0x00000000UL) /*!< ADC group regular sequencer \
+discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK \
+ (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS \
+ (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+ discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS \
+ (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+ discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS \
+ (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | \
+ ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS \
+ (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS \
+ (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | \
+ ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS \
+ (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | \
+ ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS \
+ (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | \
+ ADC_CFGR_DISCEN) /*!< ADC group regular sequencer \
+discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 \
+ (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 \
+ (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 \
+ (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 \
+ (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 \
+ (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 \
+ (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 \
+ (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 \
+ (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 \
+ (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 \
+ (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 \
+ (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 \
+ (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 \
+ (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 \
+ (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 \
+ (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 \
+ (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group \
+ regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE \
+ (0x00000000UL) /*!< ADC group injected \
+conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO \
+ (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM1 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 \
+ (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM1 \
+channel 3 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 \
+ (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM1 \
+channel 4 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO \
+ (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM2 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 \
+ (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM2 \
+channel 1 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC1/2 \
+instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM3 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM3 \
+channel 1 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC1/2 \
+instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM3 \
+channel 3 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC1/2 \
+instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 \
+ (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM3 \
+channel 4 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC1/2 \
+instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO \
+ (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM4 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 \
+ (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM4 \
+channel 3 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 \
+ (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM4 \
+channel 4 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM6 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+ ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM7 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM8 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 \
+ (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM8 \
+channel 2 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 \
+ (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM8 \
+channel 4 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM15 TRGO. \
+Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM8 \
+channel 4 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC1/2 \
+instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO \
+ (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM20 TRGO. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, TIM20 is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. \
+Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, TIM20 is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM20 \
+channel 2 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is \
+not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: TIM20 \
+channel 4 event (capture compare: input capture or output capture). \
+Trigger edge set to rising edge (default setting). \
+Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is \
+not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER \
+ADC trigger 1 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances, and HRTIM is not available on all devices. Refer to device \
+datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 2 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER \
+ADC trigger 3 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances, and HRTIM is not available on all devices. Refer to device \
+datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 4 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 5 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 6 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 7 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 8 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 9 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices. Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: HRTIMER ADC \
+trigger 10 event. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, HRTIM is not available on all devices.Refer to \
+device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 \
+ (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: external \
+interrupt line 3. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC3/4/5 \
+instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 \
+ (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: external \
+interrupt line 15. Trigger edge set to rising edge (default setting). \
+Note: On this STM32 series, this trigger is available only on ADC1/2 \
+instances. */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT \
+ (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< \
+ADC group injected conversion trigger from external peripheral: LPTIMER OUT \
+event. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING \
+ (ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion \
+trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING \
+ (ADC_JSQR_JEXTEN_1) /*!< ADC group injected conversion \
+trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING \
+ (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion \
+ trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger
+ * mode
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_INDEPENDENT \
+ (0x00000000UL) /*!< ADC group injected conversion trigger independent. \
+Setting mandatory if ADC group injected injected trigger source is set to \
+an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR \
+ (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group \
+regular. Setting compliant only with group injected trigger source set to \
+SW start, without any further action on ADC group injected conversion start \
+or stop: in this case, ADC group injected is controlled only from ADC group \
+regular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue
+ * mode
+ * @{
+ */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE \
+ (0x00000000UL) /* Group injected sequence context queue is enabled \
+and can contain up to 2 contexts. When all contexts have been processed, \
+the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY \
+ (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled \
+and can contain up to 2 contexts. When all contexts have been processed, \
+the queue is empty and injected group triggers are disabled. */
+#define LL_ADC_INJ_QUEUE_DISABLE \
+ (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: \
+only 1 sequence can be configured and is active perpetually. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan
+ * length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE \
+ (0x00000000UL) /*!< ADC group injected sequencer disable \
+(equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS \
+ (ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable \
+with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS \
+ (ADC_JSQR_JL_1) /*!< ADC group injected sequencer enable \
+with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS \
+ (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable \
+ with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer
+ * discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE \
+ (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode \
+disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK \
+ (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode \
+ enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 \
+ (ADC_JDR1_REGOFFSET | \
+ ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 \
+ (ADC_JDR2_REGOFFSET | \
+ ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 \
+ (ADC_JDR3_REGOFFSET | \
+ ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 \
+ (ADC_JDR4_REGOFFSET | \
+ ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5 \
+ (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_6CYCLES_5 \
+ (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5 \
+ (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_24CYCLES_5 \
+ (ADC_SMPR2_SMP10_1 | \
+ ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_47CYCLES_5 \
+ (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_92CYCLES_5 \
+ (ADC_SMPR2_SMP10_2 | \
+ ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_247CYCLES_5 \
+ (ADC_SMPR2_SMP10_2 | \
+ ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_640CYCLES_5 \
+ (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | \
+ ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or
+ * differential ending
+ * @{
+ */
+#define LL_ADC_SINGLE_ENDED \
+ (ADC_CALFACT_CALFACT_S) /*!< ADC channel ending \
+set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED \
+ (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending \
+set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED \
+ (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending \
+ set to both single ended and differential (literal used only to set \
+ calibration factors) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 \
+ (ADC_AWD_CR1_CHANNEL_MASK | \
+ ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2 \
+ (ADC_AWD_CR23_CHANNEL_MASK | \
+ ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3 \
+ (ADC_AWD_CR23_CHANNEL_MASK | \
+ ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE \
+ (0x00000000UL) /*!< ADC analog watchdog monitoring \
+disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG \
+ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog \
+ monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ \
+ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog \
+ monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ \
+ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring \
+of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG \
+ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ \
+ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ \
+ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG \
+ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ \
+ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ \
+ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG \
+ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ \
+ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ \
+ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG \
+ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ \
+ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ \
+ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG \
+ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ \
+ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ \
+ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG \
+ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ \
+ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ \
+ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG \
+ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ \
+ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ \
+ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG \
+ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ \
+ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ \
+ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG \
+ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ \
+ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ \
+ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG \
+ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ \
+ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ \
+ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG \
+ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ \
+ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ \
+ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG \
+ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ \
+ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ \
+ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG \
+ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ \
+ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ \
+ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG \
+ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ \
+ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ \
+ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG \
+ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ \
+ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN14, converted by group only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ \
+ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG \
+ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+monitoring of ADC channel ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ \
+ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ \
+ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN15, converted by either group \
+regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG \
+ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ \
+ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ \
+ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG \
+ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ \
+ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ \
+ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG \
+ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ \
+ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ \
+ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC channel ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG \
+ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to VrefInt: Internal \
+voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ \
+ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to VrefInt: Internal \
+voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ \
+ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to VrefInt: Internal \
+voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG \
+ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC1 internal channel connected to internal temperature sensor, \
+converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ \
+ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog \
+of ADC1 internal channel connected to internal temperature sensor, \
+converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ \
+ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC1 internal channel connected to internal temperature sensor, \
+converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG \
+ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC5 internal channel connected to internal temperature sensor, \
+converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ \
+ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog \
+of ADC5 internal channel connected to internal temperature sensor, \
+converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ \
+ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC5 internal channel connected to internal temperature sensor, \
+converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG \
+ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to Vbat/3: Vbat \
+voltage through a divider ladder of factor 1/3 to have channel voltage always \
+below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ \
+ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to Vbat/3: Vbat \
+voltage through a divider ladder of factor 1/3 to have channel voltage always \
+below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ \
+ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to Vbat/3: Vbat \
+voltage through a divider ladder of factor 1/3 to have channel voltage always \
+below Vdda */
+#define LL_ADC_AWD_CH_VOPAMP1_REG \
+ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP1 output, \
+channel specific to ADC1, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP1_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP1 output, \
+channel specific to ADC1, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP1 output, \
+channel specific to ADC1, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP2_REG \
+ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP2_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP2 output, \
+channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP2 output, \
+channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG \
+ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP3 output, \
+channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP3 output, \
+channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP3 output, \
+channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG \
+ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP3 output, \
+channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP3 output, \
+channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP3 output, \
+channel specific to ADC3, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP4_REG \
+ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP4 output, \
+channel specific to ADC5, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP4_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP4 output, \
+channel specific to ADC5, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP4 output, \
+channel specific to ADC5, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP5_REG \
+ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP5 output, \
+channel specific to ADC5, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP5_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP5 output, \
+channel specific to ADC5, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP5 output, \
+channel specific to ADC5, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP6_REG \
+ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP6 output, \
+channel specific to ADC4, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP6_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP6 output, \
+channel specific to ADC4, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ \
+ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring \
+of ADC internal channel connected to OPAMP6 output, \
+channel specific to ADC4, converted by either group regular or injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH \
+ (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW \
+ (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW \
+ (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high \
+ and low concatenated into the same data */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
+ * @{
+ */
+#define LL_ADC_AWD_FILTERING_NONE \
+ (0x00000000UL) /*!< ADC analog watchdog no filtering, \
+one out-of-window sample is needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_2SAMPLES \
+ (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2 \
+out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_3SAMPLES \
+ (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3 \
+consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_4SAMPLES \
+ (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4 \
+ consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_5SAMPLES \
+ (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5 \
+consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_6SAMPLES \
+ (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6 \
+ consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_7SAMPLES \
+ (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7 \
+ consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_8SAMPLES \
+ (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | \
+ ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8 \
+consecutives out-of-window samples are needed to raise flag or interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
+ * @{
+ */
+#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED \
+ (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of \
+ADC group regular. If group injected interrupts group regular: \
+when ADC group injected is triggered, the oversampling on ADC group regular \
+is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED \
+ (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of \
+ ADC group regular. If group injected interrupts group regular: \
+ when ADC group injected is triggered, the oversampling on ADC group regular \
+ is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED \
+ (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of \
+ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED \
+ (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of \
+ both ADC groups regular and injected. If group injected interrupting group \
+ regular: when ADC group injected is triggered, the oversampling on ADC group \
+ regular is resumed from start (oversampler buffer reset). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define LL_ADC_OVS_REG_CONT \
+ (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode \
+(all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT \
+ (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous \
+ mode (each conversion of oversampling ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+#define LL_ADC_OVS_RATIO_2 \
+ (0x00000000UL) /*!< ADC oversampling ratio of 2 \
+(sum of conversions data computed to result as oversampling conversion data \
+(before potential shift) */
+#define LL_ADC_OVS_RATIO_4 \
+ (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 \
+(sum of conversions data computed to result as oversampling conversion data \
+(before potential shift) */
+#define LL_ADC_OVS_RATIO_8 \
+ (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 \
+(sum of conversions data computed to result as oversampling conversion data \
+(before potential shift) */
+#define LL_ADC_OVS_RATIO_16 \
+ (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 \
+ (sum of conversions data computed to result as oversampling conversion data \
+ (before potential shift) */
+#define LL_ADC_OVS_RATIO_32 \
+ (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 \
+(sum of conversions data computed to result as oversampling conversion data \
+(before potential shift) */
+#define LL_ADC_OVS_RATIO_64 \
+ (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 \
+ (sum of conversions data computed to result as oversampling conversion data \
+ (before potential shift) */
+#define LL_ADC_OVS_RATIO_128 \
+ (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 \
+ (sum of conversions data computed to result as oversampling conversion data \
+ (before potential shift) */
+#define LL_ADC_OVS_RATIO_256 \
+ (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | \
+ ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 \
+(sum of conversions data computed to result as oversampling conversion data \
+(before potential shift) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
+ * @{
+ */
+#define LL_ADC_OVS_SHIFT_NONE \
+ (0x00000000UL) /*!< ADC oversampling no shift \
+(sum of the ADC conversions data is not divided to result as oversampling \
+conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1 \
+ (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 \
+(sum of the ADC conversions data (after OVS ratio) is divided by 2 \
+to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2 \
+ (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 \
+(sum of the ADC conversions data (after OVS ratio) is divided by 4 \
+to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3 \
+ (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 \
+ (sum of the ADC conversions data (after OVS ratio) is divided by 8 \
+ to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4 \
+ (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 \
+(sum of the ADC conversions data (after OVS ratio) is divided by 16 \
+to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5 \
+ (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 \
+ (sum of the ADC conversions data (after OVS ratio) is divided by 32 \
+ to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6 \
+ (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 \
+ (sum of the ADC conversions data (after OVS ratio) is divided by 64 \
+ to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7 \
+ (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | \
+ ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 \
+(sum of the ADC conversions data (after OVS ratio) is divided by 128 \
+to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8 \
+ (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 \
+(sum of the ADC conversions data (after OVS ratio) is divided by 256 \
+to result as oversampling conversion data) */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT \
+ (0x00000000UL) /*!< ADC dual mode disabled (ADC \
+independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT \
+ (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular \
+ simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL \
+ (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode \
+ enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT \
+ (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected \
+ simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN \
+ (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected \
+ alternate trigger. Works only with external triggers (not SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM \
+ (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group \
+regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT \
+ (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group \
+regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM \
+ (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group \
+ regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
+ * @{
+ */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC \
+ (0x00000000UL) /*!< ADC multimode group regular \
+conversions are transferred by DMA: each ADC uses its own DMA channel, \
+with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B \
+ (ADC_CCR_MDMA_1) /*!< ADC multimode group regular \
+conversions are transferred by DMA, one DMA channel for both ADC(DMA of \
+ADC master), in limited mode (one shot mode): DMA transfer requests \
+are stopped when number of DMA data transfers (number of ADC conversions) \
+is reached. This ADC mode is intended to be used with DMA mode \
+non-circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B \
+ (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular \
+ conversions are transferred by DMA, one DMA channel for both ADC(DMA of \
+ ADC master), in limited mode (one shot mode): DMA transfer requests \
+ are stopped when number of DMA data transfers (number of ADC conversions) \
+ is reached. This ADC mode is intended to be used with DMA mode \
+ non-circular. Setting for ADC resolution of 8 and 6 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B \
+ (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular \
+ conversions are transferred by DMA, one DMA channel for both ADC(DMA of \
+ ADC master), in unlimited mode: DMA transfer requests are unlimited, \
+ whatever number of DMA data transferred (number of ADC conversions). \
+ This ADC mode is intended to be used with DMA mode circular. \
+ Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B \
+ (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | \
+ ADC_CCR_MDMA_0) /*!< ADC multimode group regular \
+conversions are transferred by DMA, one DMA channel for both ADC (DMA of \
+ADC master), in unlimited mode: DMA transfer requests are unlimited, \
+whatever number of DMA data transferred (number of ADC conversions). \
+This ADC mode is intended to be used with DMA mode circular. \
+Setting for ADC resolution of 8 and 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two
+ * sampling phases
+ * @{
+ */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE \
+ (0x00000000UL) /*!< ADC multimode delay between two \
+sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES \
+ (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two \
+sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES \
+ (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two \
+sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES \
+ (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two \
+ sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES \
+ (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two \
+sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES \
+ (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two \
+ sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES \
+ (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two \
+ sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES \
+ (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode \
+ delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES \
+ (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two \
+sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES \
+ (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two \
+ sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES \
+ (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two \
+ sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES \
+ (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode \
+ delay between two sampling phases: 12 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER \
+ (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC \
+ instances: ADC master */
+#define LL_ADC_MULTI_SLAVE \
+ (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC \
+ instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE \
+ (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among \
+ several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper
+ * macro
+ * @{
+ */
+#define LL_ADC_TEMPERATURE_CALC_ERROR \
+ ((int16_t)0x7FFF) /* Temperature calculation error using helper macro \
+ @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on \
+ calibration parameters. This value is coded on 16 bits \
+ (to fit on signed word or double word) and corresponds \
+ to an inconsistent temperature value. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints
+ * delays
+ * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 series: */
+/* - ADC calibration time: maximum delay is 112/fADC. */
+/* (refer to device datasheet, parameter "tCAL") */
+/* - ADC enable time: maximum delay is 1 conversion cycle. */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC disable time: maximum delay should be a few ADC clock cycles */
+/* - ADC stop conversion time: maximum delay should be a few ADC clock */
+/* cycles */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tADCVREG_STUP"). */
+/* Unit: us */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US \
+ (20UL) /*!< Delay for ADC stabilization time (ADC voltage \
+ regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time. */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tstart_vrefint"). */
+/* Unit: us */
+#define LL_ADC_DELAY_VREFINT_STAB_US \
+ (12UL) /*!< Delay for internal voltage reference stabilization \
+ time */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US \
+ (120UL) /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US \
+ (15UL) /*!< Delay for temperature sensor buffer stabilization \
+ time (starting from ADC enable, refer to \
+ @ref LL_ADC_Enable()) */
+
+/* Delay required between ADC end of calibration and ADC enable. */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
+/* are required between ADC end of calibration and ADC enable. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES \
+ (4UL) /*!< Delay required between ADC end of calibration \
+ and ADC enable */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> \
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ : ((uint32_t)POSITION_VAL((__CHANNEL__))))
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back
+ * from ADC register, comparison with internal channel parameter to be done
+ * using helper macro @ref
+ * __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9UL) \
+ ? (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR1_REGOFFSET | \
+ (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))) \
+ : (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__)-10UL))) \
+ << ADC_CHANNEL_SMPx_BITOFFSET_POS))))
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ ADC3, ADC5.\n
+ * (7) On STM32G4, parameter available only on ADC instances: ADC1,
+ ADC3, ADC4, ADC5.\n
+ * On this STM32 series, all ADCx are not available on all devices.
+ Refer to device datasheet
+ * for more details.
+ * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5
+ (conversion) = 15 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.
+ * Other channels are slow channels allows: 6.5 (sampling) + 12.5
+ (conversion) = 19 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution.\n
+ * @retval Value "0" if the channel corresponds to a parameter definition of a
+ ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a
+ ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details.
+ * @retval Value "0" if the internal channel selected is not available on the
+ * ADC instance selected. Value "1" if the internal channel selected is
+ * available on the ADC instance selected.
+ */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || \
+ defined(STM32G483xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC1) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
+ (((__ADC_INSTANCE__) == ADC2) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ (((__ADC_INSTANCE__) == ADC3) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
+ (((__ADC_INSTANCE__) == ADC4) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
+ (((__ADC_INSTANCE__) == ADC5) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G471xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC1) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
+ (((__ADC_INSTANCE__) == ADC2) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ (((__ADC_INSTANCE__) == ADC3) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || \
+ defined(STM32G431xx) || defined(STM32G441xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC1) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
+ (((__ADC_INSTANCE__) == ADC2) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC1) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))) || \
+ (((__ADC_INSTANCE__) == ADC2) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ (((__ADC_INSTANCE__) == ADC3) && \
+ (((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT))))
+#endif /* STM32G4xx */
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4,
+ * LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back
+ * from ADC register, comparison with internal channel parameter to be done
+ * using helper macro @ref
+ * __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
+ *
+ * (0) On STM32G4, parameter available only on analog watchdog number:
+ * AWD1.\n (1) On STM32G4, parameter available only on ADC instance: ADC1.\n (2)
+ * On STM32G4, parameter available only on ADC instance: ADC2.\n (3) On STM32G4,
+ * parameter available only on ADC instance: ADC3.\n (4) On STM32G4, parameter
+ * available only on ADC instance: ADC4.\n (5) On STM32G4, parameter available
+ * only on ADC instance: ADC5.\n (6) On STM32G4, parameter available only on ADC
+ * instances: ADC1, ADC3, ADC5.\n (7) On STM32G4, parameter available only on
+ * ADC instances: ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are
+ * not available on all devices. Refer to device datasheet for more details.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | \
+ ADC_CFGR_AWD1SGL) \
+ : ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1SGL) \
+ : (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | \
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL))
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+ * or @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B,
+ * <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, \
+ __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> \
+ (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > =
+ * __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>,
+ * LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and
+ * Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, \
+ __AWD_THRESHOLD_12_BITS__) \
+ ((__AWD_THRESHOLD_12_BITS__) >> \
+ ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
+
+/**
+ * @brief Helper macro to get the ADC analog watchdog threshold high
+ * or low from raw value containing both thresholds concatenated.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, to get analog watchdog threshold high from the register raw
+ * value:
+ * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH,
+ * <raw_value_with_both_thresholds>);
+ * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and
+ * Max_Data=0xFFFFFFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, \
+ __AWD_THRESHOLDS__) \
+ (((__AWD_THRESHOLDS__) >> \
+ (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> \
+ ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & \
+ LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+ * @brief Helper macro to set the ADC calibration value with both single ended
+ * and differential modes calibration factors concatenated.
+ * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
+ * Example, to set calibration factors single ended to 0x55
+ * and differential ended to 0x2A:
+ * LL_ADC_SetCalibrationFactor(
+ * ADC1,
+ * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+ * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and
+ * Max_Data=0x7F
+ * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and
+ * Max_Data=0x7F
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, \
+ __CALIB_FACTOR_DIFFERENTIAL__) \
+ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | \
+ (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data
+ * concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and
+ * Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, \
+ __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> \
+ ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & \
+ ADC_CDR_RDATA_MST)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to select, from a ADC instance, to which ADC instance
+ * it has a dependence in multimode (ADC master of the corresponding
+ * ADC common instance).
+ * @note In case of device with multimode available and a mix of
+ * ADC instances compliant and not compliant with multimode feature,
+ * ADC instances not compliant with multimode feature are
+ * considered as master instances (do not depend to
+ * any other ADC instance).
+ * @param __ADCx__ ADC instance
+ * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+ */
+#if defined(ADC5)
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+ ((((__ADCx__) == ADC2)) ? (ADC1) \
+ : ((((__ADCx__) == ADC4)) ? (ADC3) : (__ADCx__)))
+#else
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+ ((((__ADCx__) == ADC2)) ? (ADC1) : (__ADCx__))
+#endif /* ADC5 */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#if defined(ADC345_COMMON)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) ? ((ADC12_COMMON)) \
+ : ((ADC345_COMMON)))
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
+#endif /* ADC345_COMMON */
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common
+ * instance is enabled.
+ */
+#if defined(ADC345_COMMON)
+#if defined(ADC4) && defined(ADC5)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \
+ ? ((LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))) \
+ : ((LL_ADC_IsEnabled(ADC3) | LL_ADC_IsEnabled(ADC4) | \
+ LL_ADC_IsEnabled(ADC5))))
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \
+ ? ((LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))) \
+ : (LL_ADC_IsEnabled(ADC3)))
+#endif /* ADC4 && ADC5 */
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
+#endif /* ADC345_COMMON */
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data full-scale digital value (unit: digital value of
+ * ADC conversion data)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, \
+ __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) << ((__ADC_RESOLUTION_CURRENT__) >> \
+ (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) >> \
+ ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / \
+ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value) in
+ * differential ended mode.
+ * @note ADC data from ADC data register is unsigned and centered around
+ * middle code in. Converted voltage can be positive or negative
+ * depending on differential input voltages.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, \
+ __ADC_DATA__, __ADC_RESOLUTION__) \
+ ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__) / \
+ (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) - \
+ (int32_t)(__VREFANALOG_VOLTAGE__))
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) / \
+ __LL_ADC_CONVERT_DATA_RESOLUTION( \
+ (__VREFINT_ADC_DATA__), (__ADC_RESOLUTION__), LL_ADC_RESOLUTION_12B))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref
+ * __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 series, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned
+ * (inconsistent temperature value)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, \
+ __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__) \
+ ((((int32_t) * TEMPSENSOR_CAL2_ADDR - (int32_t) * TEMPSENSOR_CAL1_ADDR) != \
+ 0) \
+ ? ((((((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION( \
+ (__TEMPSENSOR_ADC_DATA__), (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) * \
+ (__VREFANALOG_VOLTAGE__)) / \
+ TEMPSENSOR_CAL_VREFANALOG) - \
+ (int32_t) * TEMPSENSOR_CAL1_ADDR)) * \
+ (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)) / \
+ (int32_t)((int32_t) * TEMPSENSOR_CAL2_ADDR - \
+ (int32_t) * TEMPSENSOR_CAL1_ADDR)) + \
+ TEMPSENSOR_CAL1_TEMP) \
+ : ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro
+ * __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate
+ * using helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12 bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature
+ * sensor slope typical value (unit: uV/DegCelsius). On STM32G4, refer to device
+ * datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature
+ * sensor voltage typical value (at temperature and Vref+ defined in parameters
+ * below) (unit: mV). On STM32G4, refer to datasheet parameter "V30"
+ * (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at
+ * which temperature sensor voltage (see parameter above) is corresponding
+ * (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value
+ * (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal
+ * temperature sensor voltage has been measured. This parameter can be one of
+ * the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS( \
+ __TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, \
+ __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, \
+ __ADC_RESOLUTION__) \
+ (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) / \
+ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) * \
+ 1000UL) - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) * 1000UL))) / \
+ (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)) + \
+ (int32_t)(__TEMPSENSOR_CALX_TEMP__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1,
+ * LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx,
+ uint32_t Register) {
+ uint32_t data_reg_addr;
+
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA) {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t) & (ADCx->DR);
+ } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register CDR */
+ data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ }
+
+ return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx,
+ uint32_t Register) {
+ /* Prevent unused argument(s) compilation warning */
+ (void)(Register);
+
+ /* Retrieve address of register DR */
+ return (uint32_t) & (ADCx->DR);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC
+ * hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: Clock source and prescaler.
+ * @note On this STM32 series, if ADC group injected is used, some
+ * clock ratio constraints between ADC clock and AHB clock
+ * must be respected.
+ * Refer to reference manual.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
+ * CCR PRESC LL_ADC_SetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param CommonClock This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON,
+ uint32_t CommonClock) {
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+ * @brief Get parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
+ * CCR PRESC LL_ADC_GetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return (
+ uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Configure all paths (overwrite current configuration).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * The values not selected are removed from configuration.
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+ * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
+ * CCR VBATSEL LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following
+ * values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(
+ ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL,
+ PathInternal);
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Add paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+ * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following
+ * values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(
+ ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) {
+ SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Remove paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
+ * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following
+ * values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(
+ ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) {
+ CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
+ * CCR VBATSEL LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return (uint32_t)(READ_BIT(
+ ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC
+ * hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note This function is intended to set calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration factor must be specified for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note In case of setting calibration factors of both modes single ended
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+ * both calibration factors must be concatenated.
+ * To perform this processing, use helper macro
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx,
+ uint32_t SingleDiff,
+ uint32_t CalibrationFactor) {
+ MODIFY_REG(
+ ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+ CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+ ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) &
+ ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
+}
+
+/**
+ * @brief Get ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx,
+ uint32_t SingleDiff) {
+ /* Retrieve bits with position in register depending on parameter */
+ /* "SingleDiff". */
+ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ return (uint32_t)(READ_BIT(ADCx->CALFACT,
+ (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >>
+ ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+ ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+}
+
+/**
+ * @brief Set ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR RES LL_ADC_SetResolution
+ * @param ADCx ADC instance
+ * @param Resolution This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx,
+ uint32_t Resolution) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+ * @brief Get ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR RES LL_ADC_GetResolution
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx,
+ uint32_t DataAlignment) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+}
+
+/**
+ * @brief Set ADC low power mode.
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx,
+ uint32_t LowPowerMode) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+ * @brief Get ADC low power mode:
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+ * @brief Set ADC selected offset instance 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @note If a channel is mapped on several offsets numbers, only the offset
+ * with the lowest value is considered for the subtraction.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @note On STM32G4, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
+ * OFR1 OFFSET1 LL_ADC_SetOffset\n
+ * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
+ * OFR2 OFFSET2 LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
+ * OFR3 OFFSET3 LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
+ * OFR4 OFFSET4 LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffset
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety,
+ uint32_t Channel, uint32_t OffsetLevel) {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) |
+ OffsetLevel);
+}
+
+/**
+ * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
+ * Channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @note On STM32G4, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
+ * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
+ * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
+ * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back
+ * from ADC register, comparison with internal channel parameter to be done
+ * using helper macro @ref
+ * __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx,
+ uint32_t Offsety) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+ * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
+ * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
+ * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
+ * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx,
+ uint32_t Offsety) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+ * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
+ * force offset state disable or enable
+ * without modifying offset channel or offset value.
+ * @note This function should be needed only in case of offset to be
+ * enabled-disabled dynamically, and should not be needed in other
+ * cases: function LL_ADC_SetOffset() automatically enables the offset.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetState This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety,
+ uint32_t OffsetState) {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, OffsetState);
+}
+
+/**
+ * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
+ * offset state disabled or enabled.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx,
+ uint32_t Offsety) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+}
+
+/**
+ * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
+ * choose offset sign.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
+ * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
+ * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
+ * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSign This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+ * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety,
+ uint32_t OffsetSign) {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign);
+}
+
+/**
+ * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
+ * offset sign if positive or negative.
+ * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
+ * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
+ * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
+ * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+ * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx,
+ uint32_t Offsety) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t)READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
+}
+
+/**
+ * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
+ * choose offset saturation mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
+ * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
+ * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
+ * OFR4 SATEN LL_ADC_SetOffsetSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSaturation This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx,
+ uint32_t Offsety,
+ uint32_t OffsetSaturation) {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg, ADC_OFR1_SATEN, OffsetSaturation);
+}
+
+/**
+ * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
+ * offset saturation if enabled or disabled.
+ * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
+ * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
+ * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
+ * OFR4 SATEN LL_ADC_GetOffsetSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx,
+ uint32_t Offsety) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t)READ_BIT(*preg, ADC_OFR1_SATEN);
+}
+
+/**
+ * @brief Set ADC gain compensation.
+ * @note This function set the gain compensation coefficient
+ * that is applied to raw converted data using the formula:
+ * DATA = DATA(raw) * (gain compensation coef) / 4096
+ * @note This function enables the gain compensation if given
+ * coefficient is above 0, otherwise it disables it.
+ * @note Gain compensation when enabled is applied to all channels.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
+ * CFGR2 GCOMP LL_ADC_SetGainCompensation
+ * @param ADCx ADC instance
+ * @param GainCompensation This parameter can be:
+ * 0 Gain compensation will be disabled and value set to 0
+ * 1 -> 16393 Gain compensation will be enabled with specified value
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx,
+ uint32_t GainCompensation) {
+ MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP,
+ ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
+}
+
+/**
+ * @brief Get the ADC gain compensation value
+ * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
+ * CFGR2 GCOMP LL_ADC_GetGainCompensation
+ * @param ADCx ADC instance
+ * @retval Returned value can be:
+ * 0 Gain compensation is disabled
+ * 1 -> 16393 Gain compensation is enabled with returned value
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP)
+ ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF)
+ : 0UL);
+}
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/**
+ * @brief Set ADC sampling time common configuration impacting
+ * settings of sampling time channel wise.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
+ * @param ADCx ADC instance
+ * @param SamplingTimeCommonConfig This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(
+ ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) {
+ MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
+}
+
+/**
+ * @brief Get ADC sampling time common configuration impacting
+ * settings of sampling time channel wise.
+ * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
+}
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC
+ * hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note On this STM32 series, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 series having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_REG_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+ *
+ * (1) On STM32G4 series, parameter not available on all ADC instances:
+ * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
+ * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
+ * on all devices. Refer to device datasheet for more details.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx,
+ uint32_t TriggerSource) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+ *
+ * (1) On STM32G4 series, parameter not available on all ADC instances:
+ * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
+ * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
+ * on all devices. Refer to device datasheet for more details.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) {
+ __IO uint32_t trigger_source =
+ READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
+ uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >>
+ (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((trigger_source & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) &
+ ADC_CFGR_EXTSEL) |
+ ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ * or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) ==
+ (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx,
+ uint32_t ExternalTriggerEdge) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+/**
+ * @brief Set ADC sampling mode.
+ * @note This function set the ADC conversion sampling mode
+ * @note This mode applies to regular group only.
+ * @note Set sampling mode is applied to all conversion of regular group.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
+ * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
+ * @param ADCx ADC instance
+ * @param SamplingMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx,
+ uint32_t SamplingMode) {
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+}
+
+/**
+ * @brief Get the ADC sampling mode
+ * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
+ * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+}
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx,
+ uint32_t SequencerNbRanks) {
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx,
+ uint32_t SeqDiscont) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 series, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref
+ * LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be
+ * available. Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref
+ * LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx,
+ uint32_t Rank,
+ uint32_t Channel) {
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->SQR1,
+ ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+ MODIFY_REG(
+ *preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 series, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref
+ * LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be
+ * available. Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back
+ * from ADC register, comparison with internal channel parameter to be done
+ * using helper macro @ref
+ * __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx,
+ uint32_t Rank) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->SQR1,
+ ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+ return (
+ uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
+ << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >>
+ (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx,
+ uint32_t Continuous) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref
+ * LL_ADC_SetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx,
+ uint32_t DMATransfer) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref
+ * LL_ADC_GetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+}
+
+/**
+ * @brief Set ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @note Compatibility with devices without feature overrun:
+ * other devices without this feature have a behavior
+ * equivalent to data overwritten.
+ * The default setting of overrun is data preserved.
+ * Therefore, for compatibility with all devices, parameter
+ * overrun should be set to data overwritten.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
+ * @param ADCx ADC instance
+ * @param Overrun This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx,
+ uint32_t Overrun) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+ * @brief Get ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC
+ * hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note On this STM32 series, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 series having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_INJ_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+ *
+ * (1) On STM32G4 series, parameter not available on all ADC instances:
+ * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
+ * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
+ * on all devices. Refer to device datasheet for more details.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx,
+ uint32_t TriggerSource) {
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+ *
+ * (1) On STM32G4 series, parameter not available on all ADC instances:
+ * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
+ * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
+ * on all devices. Refer to device datasheet for more details.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) {
+ __IO uint32_t trigger_source =
+ READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
+ uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >>
+ (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
+ /* to match with triggers literals definition. */
+ return ((trigger_source & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) &
+ ADC_JSQR_JEXTSEL) |
+ ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) ==
+ (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx,
+ uint32_t ExternalTriggerEdge) {
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx,
+ uint32_t SequencerNbRanks) {
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx,
+ uint32_t SeqDiscont) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be
+ * available. Refer to device datasheet for channels availability.
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref
+ * LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32G4, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx,
+ uint32_t Rank,
+ uint32_t Channel) {
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be
+ * available. Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n (1, 2, 3, 4, 5, 7) For ADC channel read back
+ * from ADC register, comparison with internal channel parameter to be done
+ * using helper macro @ref
+ * __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx,
+ uint32_t Rank) {
+ return (uint32_t)((READ_BIT(ADCx->JSQR,
+ (ADC_CHANNEL_ID_NUMBER_MASK >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) >>
+ (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx,
+ uint32_t TrigAuto) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected contexts queue mode.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * If contexts queue is disabled:
+ * - only 1 sequence can be configured
+ * and is active perpetually.
+ * If contexts queue is enabled:
+ * - up to 2 contexts can be queued
+ * and are checked in and out as a FIFO stack (first-in, first-out).
+ * - If a new context is set when queues is full, error is triggered
+ * by interruption "Injected Queue Overflow".
+ * - Two behaviors are possible when all contexts have been processed:
+ * the contexts queue can maintain the last context active perpetually
+ * or can be empty and injected group triggers are disabled.
+ * - Triggers can be only external (not internal SW start)
+ * - Caution: The sequence must be fully configured in one time
+ * (one write of register JSQR makes a check-in of a new context
+ * into the queue).
+ * Therefore functions to set separately injected trigger and
+ * sequencer channels cannot be used, register JSQR must be set
+ * using function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note This parameter can be modified only when no conversion is on going
+ * on either groups regular or injected.
+ * @note A modification of the context mode (bit JQDIS) causes the contexts
+ * queue to be flushed and the register JSQR is cleared.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
+ * CFGR JQDIS LL_ADC_INJ_SetQueueMode
+ * @param ADCx ADC instance
+ * @param QueueMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx,
+ uint32_t QueueMode) {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+}
+
+/**
+ * @brief Get ADC group injected context queue mode.
+ * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
+ * CFGR JQDIS LL_ADC_INJ_GetQueueMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+}
+
+/**
+ * @brief Set one context on ADC group injected that will be checked in
+ * contexts queue.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * This function is intended to be used when contexts queue is enabled,
+ * because the sequence must be fully configured in one time
+ * (functions to set separately injected trigger and sequencer channels
+ * cannot be used):
+ * Refer to function @ref LL_ADC_INJ_SetQueueMode().
+ * @note In the contexts queue, only the active context can be read.
+ * The parameters of this function can be read using functions:
+ * @arg @ref LL_ADC_INJ_GetTriggerSource()
+ * @arg @ref LL_ADC_INJ_GetTriggerEdge()
+ * @arg @ref LL_ADC_INJ_GetSequencerRanks()
+ * @note On this STM32 series, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref
+ * LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32G4, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+ *
+ * (1) On STM32G4 series, parameter not available on all ADC instances:
+ * ADC1, ADC2.\n (2) On STM32G4 series, parameter not available on all ADC
+ * instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available
+ * on all devices. Refer to device datasheet for more details.
+ * @param ExternalTriggerEdge This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ *
+ * Note: This parameter is discarded in case of SW start:
+ * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @param Rank1_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @param Rank2_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @param Rank3_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @param Rank4_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(
+ ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge,
+ uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel,
+ uint32_t Rank3_Channel, uint32_t Rank4_Channel) {
+ /* Set bits with content of parameter "Rankx_Channel" with bits position */
+ /* in register depending on literal "LL_ADC_INJ_RANK_x". */
+ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
+ /* because containing other bits reserved for other purpose. */
+ /* If parameter "TriggerSource" is set to SW start, then parameter */
+ /* "ExternalTriggerEdge" is discarded. */
+ uint32_t is_trigger_not_sw =
+ (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+ MODIFY_REG(ADCx->JSQR,
+ ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JL,
+ (TriggerSource & ADC_JSQR_JEXTSEL) |
+ (ExternalTriggerEdge * (is_trigger_not_sw)) |
+ (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >>
+ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ SequencerNbRanks);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical
+ * scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 series, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
+ * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+ *
+ * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+ * can be replaced by 3.5 ADC clock cycles.
+ * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx,
+ uint32_t Channel,
+ uint32_t SamplingTime) {
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >>
+ ADC_SMPRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
+ ADC_CHANNEL_SMPx_BITOFFSET_POS),
+ SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
+ ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 series, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (8)
+ * @arg @ref LL_ADC_CHANNEL_2 (8)
+ * @arg @ref LL_ADC_CHANNEL_3 (8)
+ * @arg @ref LL_ADC_CHANNEL_4 (8)
+ * @arg @ref LL_ADC_CHANNEL_5 (8)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (6)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
+ *
+ * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+ * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+ * (6) On STM32G4, parameter available only on ADC instances: ADC1,
+ * ADC3, ADC5.\n (7) On STM32G4, parameter available only on ADC instances:
+ * ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are not available on
+ * all devices. Refer to device datasheet for more details. (8) On STM32G4, fast
+ * channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles
+ * (fADC) to convert in 12-bit resolution. Other channels are slow channels
+ * allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to
+ * convert in 12-bit resolution.\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
+ * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+ *
+ * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+ * can be replaced by 3.5 ADC clock cycles.
+ * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx,
+ uint32_t Channel) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >>
+ ADC_SMPRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0
+ << ((Channel &
+ ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
+ ADC_CHANNEL_SMPx_BITOFFSET_POS)) >>
+ ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >>
+ ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+
+/**
+ * @brief Set mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note Channel ending is on channel scope: independently of channel mapped
+ * on ADC group regular or injected.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32G4, some channels are internally fixed to single-ended inputs
+ * configuration:
+ * - ADC1: Channels 12, 15, 16, 17 and 18
+ * - ADC2: Channels 15, 17 and 18
+ * - ADC3: Channels 12, 16, 17 and 18 (1)
+ * - ADC4: Channels 16, 17 and 18 (1)
+ * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
+ * (1) ADC3/4/5 are not available on all devices, refer to device
+ * datasheet for more details.
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @param SingleDiff This parameter can be a combination of the following
+ * values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx,
+ uint32_t Channel,
+ uint32_t SingleDiff) {
+ /* Bits of channels in single or differential mode are set only for */
+ /* differential mode (for single mode, mask of bits allowed to be set is */
+ /* shifted out of range of bits of channels in single or differential mode. */
+ MODIFY_REG(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) &
+ (ADC_DIFSEL_DIFSEL >>
+ (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+ * @brief Get mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * Therefore, to ensure a channel is configured in single-ended mode,
+ * the configuration of channel itself and the channel 'i-1' must be
+ * read back (to ensure that the selected channel channel has not been
+ * configured in differential mode by the previous channel).
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32G4, some channels are internally fixed to single-ended inputs
+ * configuration:
+ * - ADC1: Channels 12, 15, 16, 17 and 18
+ * - ADC2: Channels 15, 17 and 18
+ * - ADC3: Channels 12, 16, 17 and 18 (1)
+ * - ADC4: Channels 16, 17 and 18 (1)
+ * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
+ * (1) ADC3/4/5 are not available on all devices, refer to device
+ * datasheet for more details.
+ * @note One or several values can be selected. In this case, the value
+ * returned is null if all channels are in single ended-mode.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @retval 0: channel in single-ended mode, else: channel in differential mode
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx,
+ uint32_t Channel) {
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC
+ * transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel, multiple channels or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
+ *
+ * (0) On STM32G4, parameter available only on analog watchdog number:
+ * AWD1.\n (1) On STM32G4, parameter available only on ADC instance: ADC1.\n (2)
+ * On STM32G4, parameter available only on ADC instance: ADC2.\n (3) On STM32G4,
+ * parameter available only on ADC instance: ADC3.\n (4) On STM32G4, parameter
+ * available only on ADC instance: ADC4.\n (5) On STM32G4, parameter available
+ * only on ADC instance: ADC5.\n (6) On STM32G4, parameter available only on ADC
+ * instances: ADC1, ADC3, ADC5.\n (7) On STM32G4, parameter available only on
+ * ADC instances: ADC1, ADC3, ADC4, ADC5.\n On this STM32 series, all ADCx are
+ * not available on all devices. Refer to device datasheet for more details.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx,
+ uint32_t AWDy,
+ uint32_t AWDChannelGroup) {
+ /* Set bits with content of parameter "AWDChannelGroup" with bits position */
+ /* in register and register position depending on parameter "AWDy". */
+ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->CFGR,
+ ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) +
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) *
+ ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ AWDChannelGroup & AWDy);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On this AWD number, monitored channel can be retrieved
+ * if only 1 channel is programmed (or none or all channels).
+ * This function cannot retrieve monitored channel if
+ * multiple channels are programmed simultaneously
+ * by bitfield.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ *
+ * (0) On STM32G4, parameter available only on analog watchdog number:
+ * AWD1.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->CFGR,
+ ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) +
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) *
+ ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ uint32_t analog_wd_monit_channels =
+ (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+ /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
+ /* (parameter value LL_ADC_AWD_DISABLE). */
+ /* Else, the selected AWD is enabled and is monitoring a group of channels */
+ /* or a single channel. */
+ if (analog_wd_monit_channels != 0UL) {
+ if (AWDy == LL_ADC_AWD1) {
+ if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL) {
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels =
+ ((analog_wd_monit_channels | (ADC_AWD_CR23_CHANNEL_MASK)) &
+ (~(ADC_CFGR_AWD1CH)));
+ } else {
+ /* AWD monitoring a single channel */
+ analog_wd_monit_channels =
+ (analog_wd_monit_channels |
+ (ADC_AWD2CR_AWD2CH_0
+ << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos)));
+ }
+ } else {
+ if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) ==
+ ADC_AWD_CR23_CHANNEL_MASK) {
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK |
+ ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)));
+ } else {
+ /* AWD monitoring a single channel */
+ /* AWD monitoring a group of channels */
+ analog_wd_monit_channels =
+ (analog_wd_monit_channels |
+ (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) |
+ (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels)
+ << ADC_CFGR_AWD1CH_Pos));
+ }
+ }
+ }
+
+ return analog_wd_monit_channels;
+}
+
+/**
+ * @brief Set ADC analog watchdog thresholds value of both thresholds
+ * high and low.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ * impacted: the comparison of analog watchdog thresholds is done on
+ * oversampling final computation (after ratio and shift application):
+ * ADC data register bitfield [15:4] (12 most significant bits).
+ * Examples:
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+ * ADC analog watchdog thresholds must be divided by 16.
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+ * ADC analog watchdog thresholds must be divided by 4.
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+ * ADC analog watchdog thresholds match directly to ADC data register.
+ * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(
+ ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
+ uint32_t AWDThresholdLowValue) {
+ /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
+ /* position in register and register position depending on parameter */
+ /* "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1,
+ (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) |
+ AWDThresholdLowValue);
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note If values of both thresholds high or low must be set,
+ * use function @ref LL_ADC_ConfigAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ * impacted: the comparison of analog watchdog thresholds is done on
+ * oversampling final computation (after ratio and shift application):
+ * ADC data register bitfield [15:4] (12 most significant bits).
+ * Examples:
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+ * ADC analog watchdog thresholds must be divided by 16.
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+ * ADC analog watchdog thresholds must be divided by 4.
+ * - Oversampling ratio and shift selected to have ADC conversion data
+ * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+ * ADC analog watchdog thresholds match directly to ADC data register.
+ * @note On this STM32 series, setting of this feature is not conditioned to
+ * ADC state:
+ * ADC can be disabled, enabled with or without conversion on going
+ * on either ADC groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx,
+ uint32_t AWDy,
+ uint32_t AWDThresholdsHighLow,
+ uint32_t AWDThresholdValue) {
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg, AWDThresholdsHighLow,
+ AWDThresholdValue
+ << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >>
+ ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high,
+ * threshold low or raw data with ADC thresholds high and low
+ * concatenated.
+ * @note If raw data with ADC thresholds high and low is retrieved,
+ * the data of each threshold high or low can be isolated
+ * using helper macro:
+ * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(
+ const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >>
+ (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >>
+ ADC_AWD_TRX_BIT_HIGH_SHIFT4) &
+ ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
+}
+
+/**
+ * @brief Set ADC analog watchdog filtering configuration
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @note On this STM32 series, this feature is only available on first
+ * analog watchdog (AWD1)
+ * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @param FilteringConfig This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_FILTERING_NONE
+ * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(
+ ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig) {
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+ MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
+}
+
+/**
+ * @brief Get ADC analog watchdog filtering configuration
+ * @note On this STM32 series, this feature is only available on first
+ * analog watchdog (AWD1)
+ * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @retval Returned value can be:
+ * @arg @ref LL_ADC_AWD_FILTERING_NONE
+ * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) {
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+ return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC
+ * transversal scope: oversampling
+ * @{
+ */
+
+/**
+ * @brief Set ADC oversampling scope: ADC groups regular and-or injected
+ * (availability of ADC group injected depends on STM32 series).
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
+ * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
+ * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
+ * @param ADCx ADC instance
+ * @param OvsScope This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_DISABLE
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx,
+ uint32_t OvsScope) {
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM,
+ OvsScope);
+}
+
+/**
+ * @brief Get ADC oversampling scope: ADC groups regular and-or injected
+ * (availability of ADC group injected depends on STM32 series).
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
+ * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
+ * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OVS_DISABLE
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(
+ ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+}
+
+/**
+ * @brief Set ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note On this STM32 series, oversampling discontinuous mode
+ * (triggered mode) can be used only when oversampling is
+ * set on group regular only and in resumed mode.
+ * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
+ * @param ADCx ADC instance
+ * @param OverSamplingDiscont This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_OVS_REG_CONT
+ * @arg @ref LL_ADC_OVS_REG_DISCONT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(
+ ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) {
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+ * @brief Get ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OVS_REG_CONT
+ * @arg @ref LL_ADC_OVS_REG_DISCONT
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+ * @brief Set ADC oversampling
+ * (impacting both ADC groups regular and injected)
+ * @note This function set the 2 items of oversampling configuration:
+ * - ratio
+ * - shift
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
+ * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
+ * @param ADCx ADC instance
+ * @param Ratio This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_RATIO_2
+ * @arg @ref LL_ADC_OVS_RATIO_4
+ * @arg @ref LL_ADC_OVS_RATIO_8
+ * @arg @ref LL_ADC_OVS_RATIO_16
+ * @arg @ref LL_ADC_OVS_RATIO_32
+ * @arg @ref LL_ADC_OVS_RATIO_64
+ * @arg @ref LL_ADC_OVS_RATIO_128
+ * @arg @ref LL_ADC_OVS_RATIO_256
+ * @param Shift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx,
+ uint32_t Ratio,
+ uint32_t Shift) {
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+}
+
+/**
+ * @brief Get ADC oversampling ratio
+ * (impacting both ADC groups regular and injected)
+ * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
+ * @param ADCx ADC instance
+ * @retval Ratio This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_RATIO_2
+ * @arg @ref LL_ADC_OVS_RATIO_4
+ * @arg @ref LL_ADC_OVS_RATIO_8
+ * @arg @ref LL_ADC_OVS_RATIO_16
+ * @arg @ref LL_ADC_OVS_RATIO_32
+ * @arg @ref LL_ADC_OVS_RATIO_64
+ * @arg @ref LL_ADC_OVS_RATIO_128
+ * @arg @ref LL_ADC_OVS_RATIO_256
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+}
+
+/**
+ * @brief Get ADC oversampling shift
+ * (impacting both ADC groups regular and injected)
+ * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
+ * @param ADCx ADC instance
+ * @retval Shift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC
+ * hierarchical scope: multimode
+ * @{
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Set ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DUAL LL_ADC_SetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param Multimode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON,
+ uint32_t Multimode) {
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+ * @brief Get ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CCR DUAL LL_ADC_GetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+ * @brief Set ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled
+ * or enabled without conversion on going on group regular.
+ * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
+ * CCR DMACFG LL_ADC_SetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiDMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(
+ ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) {
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
+ MultiDMATransfer);
+}
+
+/**
+ * @brief Get ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
+ * CCR DMACFG LL_ADC_GetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+}
+
+/**
+ * @brief Set ADC multimode delay between 2 sampling phases.
+ * @note The sampling delay range depends on ADC resolution:
+ * - ADC resolution 12 bits can have maximum delay of 12 cycles.
+ * - ADC resolution 10 bits can have maximum delay of 10 cycles.
+ * - ADC resolution 8 bits can have maximum delay of 8 cycles.
+ * - ADC resolution 6 bits can have maximum delay of 6 cycles.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiTwoSamplingDelay This parameter can be one of the following
+ * values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ *
+ * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+ * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+ * (3) Parameter available only if ADC resolution is 12 bits.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(
+ ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) {
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+ * @brief Get ADC multimode delay between 2 sampling phases.
+ * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ *
+ * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+ * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+ * (3) Parameter available only if ADC resolution is 12 bits.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical
+ * scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Put ADC instance in deep power down state.
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down
+ * state, the internal analog calibration is lost. After exiting from
+ * deep power down, calibration must be relaunched or calibration factor
+ * (preliminarily saved) must be set back into calibration register.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD);
+}
+
+/**
+ * @brief Disable ADC deep power down mode.
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down
+ * state, the internal analog calibration is lost. After exiting from
+ * deep power down, calibration must be relaunched or calibration factor
+ * (preliminarily saved) must be set back into calibration register.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance deep power down state.
+ * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
+ * @param ADCx ADC instance
+ * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable ADC instance internal voltage regulator.
+ * @note On this STM32 series, after ADC internal voltage regulator enable,
+ * a delay for ADC internal voltage regulator stabilization
+ * is required before performing a ADC calibration or ADC enable.
+ * Refer to device datasheet, parameter tADCVREG_STUP.
+ * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN);
+}
+
+/**
+ * @brief Disable ADC internal voltage regulator.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance internal voltage regulator state.
+ * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
+ * @param ADCx ADC instance
+ * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 series, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled and ADC internal voltage regulator enabled.
+ * @rmtoll CR ADEN LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be not disabled. Must be enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CR ADDIS LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll CR ADEN LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the selected ADC instance disable state.
+ * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no ADC disable command on going.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 series, a minimum number of ADC clock cycles
+ * are required between ADC end of calibration and ADC enable.
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration run must be performed for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
+ * CR ADCALDIF LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx,
+ uint32_t SingleDiff) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC
+ * hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 series, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART);
+}
+
+/**
+ * @brief Stop ADC group regular conversion.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP);
+}
+
+/**
+ * @brief Get ADC group regular conversion state.
+ * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group regular command of conversion stop state
+ * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Start ADC sampling phase for sampling time trigger mode
+ * @note This function is relevant only when
+ * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+ * using @ref LL_ADC_REG_SetSamplingMode
+ * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+ * @brief Stop ADC sampling phase for sampling time trigger mode and start
+ * conversion
+ * @note This function is relevant only when
+ * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+ * using @ref LL_ADC_REG_SetSamplingMode
+ * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+ * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+ * the sampling phase
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) {
+ return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t
+LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) {
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t
+LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) {
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t
+LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) {
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t
+LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) {
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
+ * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(
+ const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) {
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >>
+ (POSITION_VAL(ConversionData) & 0x1FUL));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC
+ * hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 series, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group injected,
+ * without conversion stop command on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART);
+}
+
+/**
+ * @brief Stop ADC group injected conversion.
+ * @note On this STM32 series, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) {
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP);
+}
+
+/**
+ * @brief Get ADC group injected conversion state.
+ * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get ADC group injected command of conversion stop state
+ * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->JDR1,
+ ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t
+LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->JDR1,
+ ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t
+LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->JDR1,
+ ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx,
+ uint32_t Rank) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->JDR1,
+ ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx,
+ uint32_t Rank) {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(
+ ADCx->JDR1,
+ ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC ready.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Clear flag ADC ready.
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) {
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get flag multimode ADC ready of the ADC master.
+ * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) ==
+ (LL_ADC_FLAG_ADRDY_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC ready of the ADC slave.
+ * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) ==
+ (LL_ADC_FLAG_ADRDY_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the
+ * ADC master.
+ * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) ==
+ (LL_ADC_FLAG_EOC_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the
+ * ADC slave.
+ * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) ==
+ (LL_ADC_FLAG_EOC_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of
+ * the ADC master.
+ * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) ==
+ (LL_ADC_FLAG_EOS_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of
+ * the ADC slave.
+ * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) ==
+ (LL_ADC_FLAG_EOS_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC master.
+ * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) ==
+ (LL_ADC_FLAG_OVR_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave.
+ * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) ==
+ (LL_ADC_FLAG_OVR_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC
+ * master.
+ * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) ==
+ (LL_ADC_FLAG_EOSMP_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC
+ * slave.
+ * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) ==
+ (LL_ADC_FLAG_EOSMP_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of
+ * the ADC master.
+ * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) ==
+ (LL_ADC_FLAG_JEOC_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of
+ * the ADC slave.
+ * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) ==
+ (LL_ADC_FLAG_JEOC_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of
+ * the ADC master.
+ * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) ==
+ (LL_ADC_FLAG_JEOS_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of
+ * the ADC slave.
+ * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) ==
+ (LL_ADC_FLAG_JEOS_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the
+ * ADC master.
+ * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) ==
+ (LL_ADC_FLAG_JQOVF_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the
+ * ADC slave.
+ * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) ==
+ (LL_ADC_FLAG_JQOVF_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
+ * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) ==
+ (LL_ADC_FLAG_AWD1_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave.
+ * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) ==
+ (LL_ADC_FLAG_AWD1_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
+ * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) ==
+ (LL_ADC_FLAG_AWD2_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
+ * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) ==
+ (LL_ADC_FLAG_AWD2_SLV))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
+ * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) ==
+ (LL_ADC_FLAG_AWD3_MST))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
+ * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) ==
+ (LL_ADC_FLAG_AWD3_SLV))
+ ? 1UL
+ : 0UL);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Enable ADC group regular interruption overrun.
+ * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) {
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Disable interruption ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Disable interruption ADC group regular overrun.
+ * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) {
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Get state of interruption ADC ready
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence
+ * conversions (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sampling
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of unitary
+ * conversion (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence
+ * conversions (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected context queue overflow
+ * interrupt state (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 2
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 3
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) {
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(
+ ADC_Common_TypeDef *ADCxy_COMMON,
+ const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected
+ */
+/* (availability of ADC group injected depends on STM32 series) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx,
+ const LL_ADC_InitTypeDef *pADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx,
+ const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx,
+ const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_ADC_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h
index 0d71cac..009725b 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h
@@ -1,1636 +1,1636 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_bus.h
- * @author MCD Application Team
- * @brief Header file of BUS LL module.
-
- @verbatim
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective
- peripheral enabling should be taken into account in order to manage the
- peripheral read/write from/to registers.
- (+) This delay depends on the peripheral mapping.
- (++) AHB & APB peripherals, 1 dummy read is necessary
-
- [..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has
- been inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_BUS_H
-#define STM32G4xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
- * @{
- */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
- * @{
- */
-#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
-#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
-#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
-#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
-#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
-#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
-#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
-#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
- * @{
- */
-#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
-#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
-#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
-#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
-#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
-#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
-#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
-#define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN
-#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
-#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
-#if defined(ADC345_COMMON)
-#define LL_AHB2_GRP1_PERIPH_ADC345 RCC_AHB2ENR_ADC345EN
-#endif /* ADC345_COMMON */
-#define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
-#if defined(DAC2)
-#define LL_AHB2_GRP1_PERIPH_DAC2 RCC_AHB2ENR_DAC2EN
-#endif /* DAC2 */
-#define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
-#if defined(DAC4)
-#define LL_AHB2_GRP1_PERIPH_DAC4 RCC_AHB2ENR_DAC4EN
-#endif /* DAC4 */
-#if defined(AES)
-#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
-#endif /* AES */
-#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
- * @{
- */
-#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#if defined(FMC_Bank1_R)
-#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
-#endif /* FMC_Bank1_R */
-#if defined(QUADSPI)
-#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
-#endif /* QUADSPI */
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
- * @{
- */
-#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
-#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
-#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
-#if defined(TIM5)
-#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
-#endif /* TIM5 */
-#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
-#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
-#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
-#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
-#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
-#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
-#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
-#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
-#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
-#if defined(UART4)
-#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
-#endif /* UART4 */
-#if defined(UART5)
-#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
-#endif /* UART5 */
-#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
-#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
-#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
-#if defined(FDCAN1)
-#define LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
-#endif /* FDCAN1 */
-#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
-#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
-#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
- * @{
- */
-#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
-#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
-#if defined(I2C4)
-#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
-#endif /* I2C4 */
-#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
- * @{
- */
-#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
-#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
-#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
-#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
-#if defined(SPI4)
-#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
-#endif /* SPI4 */
-#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
-#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
-#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
-#if defined(TIM20)
-#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
-#endif /* TIM20 */
-#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
-#if defined(HRTIM1)
-#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
-#endif /* HRTIM1 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
- * @{
- */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
- * @{
- */
-
-/**
- * @brief Enable AHB1 peripherals clock.
- * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR DMAMMUXEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval None
- */
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB1ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB1 peripheral clock is enabled or not
- * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR DMAMUXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval State of Periphs (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) {
- return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
- * @brief Disable AHB1 peripherals clock.
- * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR DMAMUXEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval None
- */
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB1ENR, Periphs);
-}
-
-/**
- * @brief Force AHB1 peripherals reset.
- * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval None
- */
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) {
- SET_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
- * @brief Release AHB1 peripherals reset.
- * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval None
- */
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
- * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
- * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
- * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
- * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
- * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
- * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
- * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
- * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval None
- */
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB1SMENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
- * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
- * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @retval None
- */
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB1SMENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_AHB2 AHB2
- * @{
- */
-
-/**
- * @brief Enable AHB2 peripherals clock.
- * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR ADC345EN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR DAC2EN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR DAC3EN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR DAC4EN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB2 peripheral clock is enabled or not
- * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR ADC345EN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR DAC2EN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR DAC3EN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR DAC4EN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) {
- return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
- * @brief Disable AHB2 peripherals clock.
- * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR ADC345EN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR DAC2EN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR DAC3EN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR DAC4EN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB2ENR, Periphs);
-}
-
-/**
- * @brief Force AHB2 peripherals reset.
- * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR ADC345RST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR DAC2RST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR DAC3RST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR DAC4RST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) {
- SET_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
- * @brief Release AHB2 peripherals reset.
- * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR ADC345RST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR DAC2RST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR DAC3RST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR DAC4RST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
- * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
- * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR CCMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
- * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
- * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB2SMENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
- * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR CCMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
- * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
- * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
- * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB2SMENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_AHB3 AHB3
- * @{
- */
-
-/**
- * @brief Enable AHB3 peripherals clock.
- * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
- * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB3ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB3 peripheral clock is enabled or not
- * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
- * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) {
- return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
- * @brief Disable AHB3 peripherals clock.
- * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
- * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB3ENR, Periphs);
-}
-
-/**
- * @brief Force AHB3 peripherals reset.
- * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
- * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) {
- SET_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
- * @brief Release AHB3 peripherals reset.
- * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
- * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
- * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
- * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
- * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB3SMENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
- * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
- * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) {
- CLEAR_BIT(RCC->AHB3SMENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
- * @{
- */
-
-/**
- * @brief Enable APB1 peripherals clock.
- * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1ENR1, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Enable APB1 peripherals clock.
- * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
- * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
- * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1ENR2, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB1 peripheral clock is enabled or not
- * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) {
- return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if APB1 peripheral clock is enabled or not
- * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
- * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
- * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) {
- return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
- * @brief Disable APB1 peripherals clock.
- * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB1ENR1, Periphs);
-}
-
-/**
- * @brief Disable APB1 peripherals clock.
- * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
- * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
- * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB1ENR2, Periphs);
-}
-
-/**
- * @brief Force APB1 peripherals reset.
- * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) {
- SET_BIT(RCC->APB1RSTR1, Periphs);
-}
-
-/**
- * @brief Force APB1 peripherals reset.
- * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
- * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
- * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) {
- SET_BIT(RCC->APB1RSTR2, Periphs);
-}
-
-/**
- * @brief Release APB1 peripherals reset.
- * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB1RSTR1, Periphs);
-}
-
-/**
- * @brief Release APB1 peripherals reset.
- * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
- * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
- * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB1RSTR2, Periphs);
-}
-
-/**
- * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
- * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
- * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1SMENR1, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
- * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
- * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
- * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1SMENR2, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
- * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
- * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
- * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB1SMENR1, Periphs);
-}
-
-/**
- * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
- * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
- * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
- * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
- * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
- * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB1SMENR2, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
- * @{
- */
-
-/**
- * @brief Enable APB2 peripherals clock.
- * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB2 peripheral clock is enabled or not
- * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) {
- return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
- * @brief Disable APB2 peripherals clock.
- * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
- * @brief Force APB2 peripherals reset.
- * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) {
- SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Release APB2 peripherals reset.
- * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
- * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR SPI4SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR TIM20SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
- * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) {
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2SMENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
- * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR SPI4SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR TIM20SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
- * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) {
- CLEAR_BIT(RCC->APB2SMENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_BUS_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_bus.h
+ * @author MCD Application Team
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective
+ peripheral enabling should be taken into account in order to manage the
+ peripheral read/write from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has
+ been inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_BUS_H
+#define STM32G4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
+#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
+#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
+#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
+#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
+#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
+#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
+#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
+#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
+#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
+#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
+#define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSRAMSMEN
+#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
+#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
+#if defined(ADC345_COMMON)
+#define LL_AHB2_GRP1_PERIPH_ADC345 RCC_AHB2ENR_ADC345EN
+#endif /* ADC345_COMMON */
+#define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
+#if defined(DAC2)
+#define LL_AHB2_GRP1_PERIPH_DAC2 RCC_AHB2ENR_DAC2EN
+#endif /* DAC2 */
+#define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
+#if defined(DAC4)
+#define LL_AHB2_GRP1_PERIPH_DAC4 RCC_AHB2ENR_DAC4EN
+#endif /* DAC4 */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
+#endif /* AES */
+#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#if defined(FMC_Bank1_R)
+#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1_R */
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
+#endif /* TIM5 */
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
+#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
+#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
+#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
+#if defined(FDCAN1)
+#define LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
+#endif /* FDCAN1 */
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
+#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
+#if defined(I2C4)
+#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
+#endif /* I2C4 */
+#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
+#endif /* SPI4 */
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#if defined(TIM20)
+#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
+#endif /* TIM20 */
+#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
+#endif /* HRTIM1 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMAMMUXEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMAMUXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) {
+ return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMAMUXEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) {
+ SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB1SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+ * @{
+ */
+
+/**
+ * @brief Enable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR ADC345EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR DAC2EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR DAC3EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR DAC4EN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB2 peripheral clock is enabled or not
+ * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR ADC345EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR DAC2EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR DAC3EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR DAC4EN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) {
+ return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR ADC345EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR DAC2EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR DAC3EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR DAC4EN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR ADC345RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR DAC2RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR DAC3RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR DAC4RST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) {
+ SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR ADC345RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR DAC2RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR DAC3RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR DAC4RST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR CCMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR CCMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB2SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+ * @{
+ */
+
+/**
+ * @brief Enable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB3 peripheral clock is enabled or not
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) {
+ return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) {
+ SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) {
+ CLEAR_BIT(RCC->AHB3SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) {
+ return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) {
+ return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB1ENR1, Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB1ENR2, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) {
+ SET_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
+ * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
+ * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) {
+ SET_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1SMENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1SMENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB1SMENR1, Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB1SMENR2, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) {
+ return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) {
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SPI4SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM20SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) {
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SPI4SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM20SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) {
+ CLEAR_BIT(RCC->APB2SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_BUS_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h
index 0cfa5fa..8f6239d 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h
@@ -1,705 +1,705 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL CORTEX driver contains a set of generic APIs that can be
- used by user:
- (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
- functions
- (+) Low power mode configuration (SCB register of Cortex-MCU)
- (+) MPU API to configure and enable regions
- (+) API to access to MCU info (CPUID register)
- (+) API to enable fault handler (SHCSR accesses)
-
- @endverbatim
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_CORTEX_H
-#define __STM32G4xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-/** @defgroup CORTEX_LL CORTEX
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
- * @{
- */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 \
- 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK \
- SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. \
- */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
- * @{
- */
-#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM \
- SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
- * @{
- */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE \
- 0x00000000U /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI \
- MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, \
- NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT \
- MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default \
- memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF \
- (MPU_CTRL_HFNMIENA_Msk | \
- MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
- * @{
- */
-#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
- * @{
- */
-#define LL_MPU_REGION_SIZE_32B \
- (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B \
- (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B \
- (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B \
- (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B \
- (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB \
- (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB \
- (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB \
- (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB \
- (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB \
- (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB \
- (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB \
- (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB \
- (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB \
- (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB \
- (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB \
- (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB \
- (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB \
- (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB \
- (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB \
- (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB \
- (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB \
- (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB \
- (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB \
- (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB \
- (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB \
- (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB \
- (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB \
- (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
- * @{
- */
-#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW \
- (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO \
- (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user \
- program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS \
- (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO \
- (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO \
- (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
- * @{
- */
-#define LL_MPU_TEX_LEVEL0 \
- (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits \
- */
-#define LL_MPU_TEX_LEVEL1 \
- (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits \
- */
-#define LL_MPU_TEX_LEVEL2 \
- (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits \
- */
-#define LL_MPU_TEX_LEVEL4 \
- (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits \
- */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
- * @{
- */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE \
- 0x00U /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE \
- MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
- * @{
- */
-#define LL_MPU_ACCESS_SHAREABLE \
- MPU_RASR_S_Msk /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE \
- 0x00U /*!< Not Shareable memory attribute \
- */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
- * @{
- */
-#define LL_MPU_ACCESS_CACHEABLE \
- MPU_RASR_C_Msk /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE \
- 0x00U /*!< Not Cacheable memory attribute \
- */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
- * @{
- */
-#define LL_MPU_ACCESS_BUFFERABLE \
- MPU_RASR_B_Msk /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE \
- 0x00U /*!< Not Bufferable memory attribute */
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
- * @{
- */
-
-/**
- * @brief This function checks if the Systick counter flag is active or not.
- * @note It can be used in timeout function on application side.
- * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) {
- return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) ==
- (SysTick_CTRL_COUNTFLAG_Msk))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configures the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) {
- if (Source == LL_SYSTICK_CLKSOURCE_HCLK) {
- SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- } else {
- CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
-}
-
-/**
- * @brief Get the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) {
- return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
- * @brief Enable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void) {
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Disable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void) {
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Checks if the SYSTICK interrupt is enabled or disabled.
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) {
- return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) ==
- (SysTick_CTRL_TICKINT_Msk))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
- * @{
- */
-
-/**
- * @brief Processor uses sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleep(void) {
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Processor uses deep sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) {
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Configures sleep-on-exit when returning from Handler mode to Thread
- * mode.
- * @note Setting this bit to 1 enables an interrupt-driven application to
- * avoid returning to an empty main application.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) {
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Do not sleep when returning to Thread mode.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) {
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enabled events and all interrupts, including disabled interrupts, can
- * wakeup the processor.
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) {
- /* Set SEVEONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Only enabled interrupts or events can wakeup the processor, disabled
- * interrupts are excluded
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) {
- /* Clear SEVEONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
- * @{
- */
-
-/**
- * @brief Enable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) {
- /* Enable the system handler fault */
- SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @brief Disable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) {
- /* Disable the system handler fault */
- CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
- * @{
- */
-
-/**
- * @brief Get Implementer code
- * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
- * @retval Value should be equal to 0x41 for ARM
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) {
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >>
- SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
- * @brief Get Variant number (The r value in the rnpn product revision
- * identifier)
- * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
- * @retval Value between 0 and 255 (0x0: revision 0)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) {
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >>
- SCB_CPUID_VARIANT_Pos);
-}
-
-/**
- * @brief Get Architecture number
- * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
- * @retval Value should be equal to 0xF for Cortex-M4 devices
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) {
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >>
- SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
- * @brief Get Part number
- * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
- * @retval Value should be equal to 0xC24 for Cortex-M4
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) {
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >>
- SCB_CPUID_PARTNO_Pos);
-}
-
-/**
- * @brief Get Revision number (The p value in the rnpn product revision
- * identifier, indicates patch release)
- * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
- * @retval Value between 0 and 255 (0x1: patch 1)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) {
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >>
- SCB_CPUID_REVISION_Pos);
-}
-
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
- * @{
- */
-
-/**
- * @brief Enable MPU with input options
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
- * @param Options This parameter can be one of the following values:
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
- * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
- * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) {
- /* Enable the MPU*/
- WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
- /* Ensure MPU settings take effects */
- __DSB();
- /* Sequence instruction fetches using update settings */
- __ISB();
-}
-
-/**
- * @brief Disable MPU
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Disable(void) {
- /* Make sure outstanding transfers are done */
- __DMB();
- /* Disable MPU*/
- WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
- * @brief Check if MPU is enabled or not
- * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) {
- return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable a MPU region
- * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) {
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Enable the MPU region */
- SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @brief Configure and enable a region
- * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
- * MPU_RASR XN LL_MPU_ConfigRegion\n
- * MPU_RASR AP LL_MPU_ConfigRegion\n
- * MPU_RASR S LL_MPU_ConfigRegion\n
- * MPU_RASR C LL_MPU_ConfigRegion\n
- * MPU_RASR B LL_MPU_ConfigRegion\n
- * MPU_RASR SIZE LL_MPU_ConfigRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @param Address Value of region base address
- * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and
- * Max_Data = 0xFF
- * @param Attributes This parameter can be a combination of the following
- * values:
- * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or
- * @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref
- * LL_MPU_REGION_SIZE_512B or @ref LL_MPU_REGION_SIZE_1KB or @ref
- * LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref
- * LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB or @ref
- * LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref
- * LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref
- * LL_MPU_REGION_SIZE_512KB or @ref LL_MPU_REGION_SIZE_1MB or @ref
- * LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref
- * LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB or @ref
- * LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref
- * LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref
- * LL_MPU_REGION_SIZE_512MB or @ref LL_MPU_REGION_SIZE_1GB or @ref
- * LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
- * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or
- * @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS or @ref
- * LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
- * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref
- * LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
- * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref
- * LL_MPU_INSTRUCTION_ACCESS_DISABLE
- * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
- * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
- * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref
- * LL_MPU_ACCESS_NOT_BUFFERABLE
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region,
- uint32_t SubRegionDisable,
- uint32_t Address,
- uint32_t Attributes) {
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Set base address */
- WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
- /* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes |
- (SubRegionDisable << MPU_RASR_SRD_Pos)));
-}
-
-/**
- * @brief Disable a region
- * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
- * MPU_RASR ENABLE LL_MPU_DisableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) {
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Disable the MPU region */
- CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @}
- */
-
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_CORTEX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_CORTEX_H
+#define __STM32G4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 \
+ 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK \
+ SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM \
+ SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE \
+ 0x00000000U /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI \
+ MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, \
+ NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT \
+ MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default \
+ memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF \
+ (MPU_CTRL_HFNMIENA_Msk | \
+ MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B \
+ (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B \
+ (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B \
+ (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B \
+ (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B \
+ (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB \
+ (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB \
+ (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB \
+ (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB \
+ (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB \
+ (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB \
+ (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB \
+ (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB \
+ (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB \
+ (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB \
+ (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB \
+ (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB \
+ (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB \
+ (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB \
+ (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB \
+ (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB \
+ (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB \
+ (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB \
+ (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB \
+ (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB \
+ (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB \
+ (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB \
+ (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB \
+ (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW \
+ (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO \
+ (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user \
+ program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS \
+ (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO \
+ (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO \
+ (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 \
+ (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits \
+ */
+#define LL_MPU_TEX_LEVEL1 \
+ (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits \
+ */
+#define LL_MPU_TEX_LEVEL2 \
+ (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits \
+ */
+#define LL_MPU_TEX_LEVEL4 \
+ (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE \
+ 0x00U /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE \
+ MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE \
+ MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE \
+ 0x00U /*!< Not Shareable memory attribute \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE \
+ MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE \
+ 0x00U /*!< Not Cacheable memory attribute \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE \
+ MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE \
+ 0x00U /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) {
+ return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) ==
+ (SysTick_CTRL_COUNTFLAG_Msk))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) {
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK) {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ } else {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) {
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void) {
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void) {
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) {
+ return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) ==
+ (SysTick_CTRL_TICKINT_Msk))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void) {
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) {
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread
+ * mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to
+ * avoid returning to an empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) {
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) {
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can
+ * wakeup the processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) {
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled
+ * interrupts are excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) {
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) {
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) {
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) {
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >>
+ SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision
+ * identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x0: revision 0)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) {
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >>
+ SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Architecture number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
+ * @retval Value should be equal to 0xF for Cortex-M4 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) {
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >>
+ SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC24 for Cortex-M4
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) {
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >>
+ SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision
+ * identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) {
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >>
+ SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) {
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void) {
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) {
+ return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) {
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and
+ * Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following
+ * values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or
+ * @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref
+ * LL_MPU_REGION_SIZE_512B or @ref LL_MPU_REGION_SIZE_1KB or @ref
+ * LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref
+ * LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB or @ref
+ * LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref
+ * LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref
+ * LL_MPU_REGION_SIZE_512KB or @ref LL_MPU_REGION_SIZE_1MB or @ref
+ * LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref
+ * LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB or @ref
+ * LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref
+ * LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref
+ * LL_MPU_REGION_SIZE_512MB or @ref LL_MPU_REGION_SIZE_1GB or @ref
+ * LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or
+ * @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS or @ref
+ * LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref
+ * LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref
+ * LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref
+ * LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region,
+ uint32_t SubRegionDisable,
+ uint32_t Address,
+ uint32_t Attributes) {
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes |
+ (SubRegionDisable << MPU_RASR_SRD_Pos)));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) {
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_CORTEX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h
index 41c5f17..8259747 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h
@@ -1,783 +1,783 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_crs.h
- * @author MCD Application Team
- * @brief Header file of CRS LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_CRS_H
-#define __STM32G4xx_LL_CRS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(CRS)
-
-/** @defgroup CRS_LL CRS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
- * @{
- */
-
-/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_CRS_ReadReg function
- * @{
- */
-#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
-#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
-#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
-#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
-#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
-#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
-#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_CRS_ReadReg and
- * LL_CRS_WriteReg functions
- * @{
- */
-#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
-#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
-#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
-#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
- * @{
- */
-#define LL_CRS_SYNC_DIV_1 \
- ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
-#define LL_CRS_SYNC_DIV_2 \
- CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 \
- */
-#define LL_CRS_SYNC_DIV_4 \
- CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 \
- */
-#define LL_CRS_SYNC_DIV_8 \
- (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 \
- */
-#define LL_CRS_SYNC_DIV_16 \
- CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
-#define LL_CRS_SYNC_DIV_32 \
- (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 \
- */
-#define LL_CRS_SYNC_DIV_64 \
- (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 \
- */
-#define LL_CRS_SYNC_DIV_128 \
- CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
- * @{
- */
-#define LL_CRS_SYNC_SOURCE_GPIO \
- ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
-#define LL_CRS_SYNC_SOURCE_LSE \
- CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
-#define LL_CRS_SYNC_SOURCE_USB \
- CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
- * @{
- */
-#define LL_CRS_SYNC_POLARITY_RISING \
- ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
-#define LL_CRS_SYNC_POLARITY_FALLING \
- CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
- * @{
- */
-#define LL_CRS_FREQ_ERROR_DIR_UP \
- ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above \
- the target */
-#define LL_CRS_FREQ_ERROR_DIR_DOWN \
- ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency \
- is below the target */
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
- * @{
- */
-/**
- * @brief Reset value of the RELOAD field
- * @note The reset value of the RELOAD field corresponds to a target frequency
- * of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from
- * USB)
- */
-#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
-
-/**
- * @brief Reset value of Frequency error limit.
- */
-#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
-
-/**
- * @brief Reset value of the HSI48 Calibration field
- * @note The default value is 64, which corresponds to the middle of the
- * trimming interval. The trimming step is specified in the product datasheet.
- * A higher TRIM value corresponds to a higher output frequency
- */
-#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
- * @{
- */
-
-/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in CRS register
- * @param __INSTANCE__ CRS Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in CRS register
- * @param __INSTANCE__ CRS Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload
- * Exported_Macros_Calculate_Reload
- * @{
- */
-
-/**
- * @brief Macro to calculate reload value to be set in CRS register according
- * to target and sync frequencies
- * @note The RELOAD value should be selected according to the ratio between
- * the target frequency and the frequency of the synchronization source
- * after prescaling. It is then decreased by one in order to reach the expected
- * synchronization on the zero value. The formula is the following:
- * RELOAD = (fTARGET / fSYNC) -1
- * @param __FTARGET__ Target frequency (value in Hz)
- * @param __FSYNC__ Synchronization signal frequency (value in Hz)
- * @retval Reload value (in Hz)
- */
-#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) \
- (((__FTARGET__) / (__FSYNC__)) - 1U)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
- * @{
- */
-
-/** @defgroup CRS_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable Frequency error counter
- * @note When this bit is set, the CRS_CFGR register is write-protected and
- * cannot be modified
- * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) {
- SET_BIT(CRS->CR, CRS_CR_CEN);
-}
-
-/**
- * @brief Disable Frequency error counter
- * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) {
- CLEAR_BIT(CRS->CR, CRS_CR_CEN);
-}
-
-/**
- * @brief Check if Frequency error counter is enabled or not
- * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) {
- return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable Automatic trimming counter
- * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) {
- SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
-}
-
-/**
- * @brief Disable Automatic trimming counter
- * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) {
- CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
-}
-
-/**
- * @brief Check if Automatic trimming is enabled or not
- * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) {
- return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set HSI48 oscillator smooth trimming
- * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware
- * and is read-only
- * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
- * @param Value a number between Min_Data = 0 and Max_Data = 63
- * @note Default value can be set thanks to @ref
- * LL_CRS_HSI48CALIBRATION_DEFAULT
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) {
- MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
-}
-
-/**
- * @brief Get HSI48 oscillator smooth trimming
- * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
- * @retval a number between Min_Data = 0 and Max_Data = 63
- */
-__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) {
- return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
-}
-
-/**
- * @brief Set counter reload value
- * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
- * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
- * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
- * Otherwise it can be calculated in using macro @ref
- * __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) {
- MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
-}
-
-/**
- * @brief Get counter reload value
- * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
- * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) {
- return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-}
-
-/**
- * @brief Set frequency error limit
- * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
- * @param Value a number between Min_Data = 0 and Max_Data = 255
- * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) {
- MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
-}
-
-/**
- * @brief Get frequency error limit
- * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
- * @retval A number between Min_Data = 0 and Max_Data = 255
- */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) {
- return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
-}
-
-/**
- * @brief Set division factor for SYNC signal
- * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
- * @param Divider This parameter can be one of the following values:
- * @arg @ref LL_CRS_SYNC_DIV_1
- * @arg @ref LL_CRS_SYNC_DIV_2
- * @arg @ref LL_CRS_SYNC_DIV_4
- * @arg @ref LL_CRS_SYNC_DIV_8
- * @arg @ref LL_CRS_SYNC_DIV_16
- * @arg @ref LL_CRS_SYNC_DIV_32
- * @arg @ref LL_CRS_SYNC_DIV_64
- * @arg @ref LL_CRS_SYNC_DIV_128
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) {
- MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
-}
-
-/**
- * @brief Get division factor for SYNC signal
- * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRS_SYNC_DIV_1
- * @arg @ref LL_CRS_SYNC_DIV_2
- * @arg @ref LL_CRS_SYNC_DIV_4
- * @arg @ref LL_CRS_SYNC_DIV_8
- * @arg @ref LL_CRS_SYNC_DIV_16
- * @arg @ref LL_CRS_SYNC_DIV_32
- * @arg @ref LL_CRS_SYNC_DIV_64
- * @arg @ref LL_CRS_SYNC_DIV_128
- */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) {
- return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
-}
-
-/**
- * @brief Set SYNC signal source
- * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
- * @arg @ref LL_CRS_SYNC_SOURCE_LSE
- * @arg @ref LL_CRS_SYNC_SOURCE_USB
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) {
- MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
-}
-
-/**
- * @brief Get SYNC signal source
- * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
- * @arg @ref LL_CRS_SYNC_SOURCE_LSE
- * @arg @ref LL_CRS_SYNC_SOURCE_USB
- */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) {
- return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
-}
-
-/**
- * @brief Set input polarity for the SYNC signal source
- * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_CRS_SYNC_POLARITY_RISING
- * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) {
- MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
-}
-
-/**
- * @brief Get input polarity for the SYNC signal source
- * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRS_SYNC_POLARITY_RISING
- * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
- */
-__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) {
- return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
-}
-
-/**
- * @brief Configure CRS for the synchronization
- * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
- * CFGR RELOAD LL_CRS_ConfigSynchronization\n
- * CFGR FELIM LL_CRS_ConfigSynchronization\n
- * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
- * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
- * CFGR SYNCPOL LL_CRS_ConfigSynchronization
- * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
- * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
- * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
- * @param Settings This parameter can be a combination of the following values:
- * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref
- * LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or
- * @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref
- * LL_CRS_SYNC_DIV_128
- * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or
- * @ref LL_CRS_SYNC_SOURCE_USB
- * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref
- * LL_CRS_SYNC_POLARITY_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_ConfigSynchronization(
- uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
- uint32_t ReloadValue, uint32_t Settings) {
- MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
- MODIFY_REG(CRS->CFGR,
- CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV |
- CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
- ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
- * @{
- */
-
-/**
- * @brief Generate software SYNC event
- * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) {
- SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
- * @brief Get the frequency error direction latched in the time of the last
- * SYNC event
- * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
- * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
- */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) {
- return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
- * @brief Get the frequency error counter value latched in the time of the last
- * SYNC event
- * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
- * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) {
- return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if SYNC event OK signal occurred or not
- * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if SYNC warning signal occurred or not
- * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Synchronization or trimming error signal occurred or not
- * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if Expected SYNC signal occurred or not
- * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if SYNC error signal occurred or not
- * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if SYNC missed error signal occurred or not
- * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Trimming overflow or underflow occurred or not
- * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) {
- return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Clear the SYNC event OK flag
- * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) {
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-}
-
-/**
- * @brief Clear the SYNC warning flag
- * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) {
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-}
-
-/**
- * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
- * the ERR flag
- * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) {
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-}
-
-/**
- * @brief Clear Expected SYNC flag
- * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) {
- WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRS_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable SYNC event OK interrupt
- * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) {
- SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
-}
-
-/**
- * @brief Disable SYNC event OK interrupt
- * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) {
- CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
-}
-
-/**
- * @brief Check if SYNC event OK interrupt is enabled or not
- * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) {
- return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable SYNC warning interrupt
- * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) {
- SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
-}
-
-/**
- * @brief Disable SYNC warning interrupt
- * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) {
- CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
-}
-
-/**
- * @brief Check if SYNC warning interrupt is enabled or not
- * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) {
- return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable Synchronization or trimming error interrupt
- * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) {
- SET_BIT(CRS->CR, CRS_CR_ERRIE);
-}
-
-/**
- * @brief Disable Synchronization or trimming error interrupt
- * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) {
- CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
-}
-
-/**
- * @brief Check if Synchronization or trimming error interrupt is enabled or
- * not
- * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) {
- return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable Expected SYNC interrupt
- * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) {
- SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
-}
-
-/**
- * @brief Disable Expected SYNC interrupt
- * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
- * @retval None
- */
-__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) {
- CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
-}
-
-/**
- * @brief Check if Expected SYNC interrupt is enabled or not
- * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) {
- return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_CRS_DeInit(void);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(CRS) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_CRS_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_crs.h
+ * @author MCD Application Team
+ * @brief Header file of CRS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_CRS_H
+#define __STM32G4xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+ * @{
+ */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_CRS_ReadReg function
+ * @{
+ */
+#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_CRS_ReadReg and
+ * LL_CRS_WriteReg functions
+ * @{
+ */
+#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+ * @{
+ */
+#define LL_CRS_SYNC_DIV_1 \
+ ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2 \
+ CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 \
+ */
+#define LL_CRS_SYNC_DIV_4 \
+ CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 \
+ */
+#define LL_CRS_SYNC_DIV_8 \
+ (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 \
+ */
+#define LL_CRS_SYNC_DIV_16 \
+ CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32 \
+ (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 \
+ */
+#define LL_CRS_SYNC_DIV_64 \
+ (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 \
+ */
+#define LL_CRS_SYNC_DIV_128 \
+ CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+ * @{
+ */
+#define LL_CRS_SYNC_SOURCE_GPIO \
+ ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE \
+ CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB \
+ CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+ * @{
+ */
+#define LL_CRS_SYNC_POLARITY_RISING \
+ ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING \
+ CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+ * @{
+ */
+#define LL_CRS_FREQ_ERROR_DIR_UP \
+ ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above \
+ the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN \
+ ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency \
+ is below the target */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+ * @{
+ */
+/**
+ * @brief Reset value of the RELOAD field
+ * @note The reset value of the RELOAD field corresponds to a target frequency
+ * of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from
+ * USB)
+ */
+#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
+
+/**
+ * @brief Reset value of Frequency error limit.
+ */
+#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
+
+/**
+ * @brief Reset value of the HSI48 Calibration field
+ * @note The default value is 64, which corresponds to the middle of the
+ * trimming interval. The trimming step is specified in the product datasheet.
+ * A higher TRIM value corresponds to a higher output frequency
+ */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+ * @{
+ */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRS register
+ * @param __INSTANCE__ CRS Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRS register
+ * @param __INSTANCE__ CRS Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload
+ * Exported_Macros_Calculate_Reload
+ * @{
+ */
+
+/**
+ * @brief Macro to calculate reload value to be set in CRS register according
+ * to target and sync frequencies
+ * @note The RELOAD value should be selected according to the ratio between
+ * the target frequency and the frequency of the synchronization source
+ * after prescaling. It is then decreased by one in order to reach the expected
+ * synchronization on the zero value. The formula is the following:
+ * RELOAD = (fTARGET / fSYNC) -1
+ * @param __FTARGET__ Target frequency (value in Hz)
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)
+ * @retval Reload value (in Hz)
+ */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) \
+ (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+ * @{
+ */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable Frequency error counter
+ * @note When this bit is set, the CRS_CFGR register is write-protected and
+ * cannot be modified
+ * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) {
+ SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+ * @brief Disable Frequency error counter
+ * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) {
+ CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+ * @brief Check if Frequency error counter is enabled or not
+ * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) {
+ return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Automatic trimming counter
+ * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) {
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+ * @brief Disable Automatic trimming counter
+ * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) {
+ CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+ * @brief Check if Automatic trimming is enabled or not
+ * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) {
+ return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set HSI48 oscillator smooth trimming
+ * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware
+ * and is read-only
+ * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
+ * @param Value a number between Min_Data = 0 and Max_Data = 63
+ * @note Default value can be set thanks to @ref
+ * LL_CRS_HSI48CALIBRATION_DEFAULT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) {
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+ * @brief Get HSI48 oscillator smooth trimming
+ * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
+ * @retval a number between Min_Data = 0 and Max_Data = 63
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) {
+ return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+ * @brief Set counter reload value
+ * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
+ * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+ * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+ * Otherwise it can be calculated in using macro @ref
+ * __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) {
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+ * @brief Get counter reload value
+ * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
+ * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) {
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+ * @brief Set frequency error limit
+ * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
+ * @param Value a number between Min_Data = 0 and Max_Data = 255
+ * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) {
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+ * @brief Get frequency error limit
+ * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
+ * @retval A number between Min_Data = 0 and Max_Data = 255
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) {
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+ * @brief Set division factor for SYNC signal
+ * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1
+ * @arg @ref LL_CRS_SYNC_DIV_2
+ * @arg @ref LL_CRS_SYNC_DIV_4
+ * @arg @ref LL_CRS_SYNC_DIV_8
+ * @arg @ref LL_CRS_SYNC_DIV_16
+ * @arg @ref LL_CRS_SYNC_DIV_32
+ * @arg @ref LL_CRS_SYNC_DIV_64
+ * @arg @ref LL_CRS_SYNC_DIV_128
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) {
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+ * @brief Get division factor for SYNC signal
+ * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1
+ * @arg @ref LL_CRS_SYNC_DIV_2
+ * @arg @ref LL_CRS_SYNC_DIV_4
+ * @arg @ref LL_CRS_SYNC_DIV_8
+ * @arg @ref LL_CRS_SYNC_DIV_16
+ * @arg @ref LL_CRS_SYNC_DIV_32
+ * @arg @ref LL_CRS_SYNC_DIV_64
+ * @arg @ref LL_CRS_SYNC_DIV_128
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) {
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+ * @brief Set SYNC signal source
+ * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+ * @arg @ref LL_CRS_SYNC_SOURCE_LSE
+ * @arg @ref LL_CRS_SYNC_SOURCE_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) {
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+ * @brief Get SYNC signal source
+ * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+ * @arg @ref LL_CRS_SYNC_SOURCE_LSE
+ * @arg @ref LL_CRS_SYNC_SOURCE_USB
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) {
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+ * @brief Set input polarity for the SYNC signal source
+ * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING
+ * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) {
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+ * @brief Get input polarity for the SYNC signal source
+ * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING
+ * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) {
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+ * @brief Configure CRS for the synchronization
+ * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
+ * CFGR RELOAD LL_CRS_ConfigSynchronization\n
+ * CFGR FELIM LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCPOL LL_CRS_ConfigSynchronization
+ * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+ * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+ * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
+ * @param Settings This parameter can be a combination of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref
+ * LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or
+ * @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref
+ * LL_CRS_SYNC_DIV_128
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or
+ * @ref LL_CRS_SYNC_SOURCE_USB
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref
+ * LL_CRS_SYNC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(
+ uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
+ uint32_t ReloadValue, uint32_t Settings) {
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+ MODIFY_REG(CRS->CFGR,
+ CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV |
+ CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+ ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+ * @{
+ */
+
+/**
+ * @brief Generate software SYNC event
+ * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) {
+ SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+ * @brief Get the frequency error direction latched in the time of the last
+ * SYNC event
+ * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+ * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) {
+ return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+ * @brief Get the frequency error counter value latched in the time of the last
+ * SYNC event
+ * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
+ * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) {
+ return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if SYNC event OK signal occurred or not
+ * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if SYNC warning signal occurred or not
+ * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Synchronization or trimming error signal occurred or not
+ * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Expected SYNC signal occurred or not
+ * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if SYNC error signal occurred or not
+ * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if SYNC missed error signal occurred or not
+ * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Trimming overflow or underflow occurred or not
+ * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) {
+ return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Clear the SYNC event OK flag
+ * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) {
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+ * @brief Clear the SYNC warning flag
+ * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) {
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+ * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+ * the ERR flag
+ * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) {
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+ * @brief Clear Expected SYNC flag
+ * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) {
+ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable SYNC event OK interrupt
+ * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) {
+ SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+ * @brief Disable SYNC event OK interrupt
+ * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) {
+ CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+ * @brief Check if SYNC event OK interrupt is enabled or not
+ * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) {
+ return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable SYNC warning interrupt
+ * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) {
+ SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+ * @brief Disable SYNC warning interrupt
+ * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) {
+ CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+ * @brief Check if SYNC warning interrupt is enabled or not
+ * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) {
+ return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable Synchronization or trimming error interrupt
+ * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) {
+ SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+ * @brief Disable Synchronization or trimming error interrupt
+ * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) {
+ CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+ * @brief Check if Synchronization or trimming error interrupt is enabled or
+ * not
+ * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) {
+ return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Expected SYNC interrupt
+ * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) {
+ SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+ * @brief Disable Expected SYNC interrupt
+ * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) {
+ CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+ * @brief Check if Expected SYNC interrupt is enabled or not
+ * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) {
+ return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRS) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_CRS_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h
index 065eb28..b14e508 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h
@@ -1,2820 +1,2820 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_DMA_H
-#define __STM32G4xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-#include "stm32g4xx_ll_dmamux.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(DMA1) || defined(DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
- * @{
- */
-/* Array used to get the DMA channel register offset versus channel index
- * LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] = {
- (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
-#if defined(DMA1_Channel7)
- ,
- (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
-#endif /* DMA1_Channel7 */
-#if defined(DMA1_Channel8)
- ,
- (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
-#endif /* DMA1_Channel8 */
-};
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Constants DMA Private Constants
- * @{
- */
-/* Define used to get CSELR register offset */
-#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
-
-/* Defines used for the bit position in the register and perform offsets */
-#define DMA_POSITION_CSELR_CXS \
- POSITION_VAL(DMA_CSELR_C1S << ((Channel - 1U) * 4U))
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
- * @{
- */
-typedef struct {
- uint32_t
- PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA
- transfer or as Source base address in case of
- memory to memory transfer direction.
-
- This parameter must be a value between
- Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t
- MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA
- transfer or as Destination base address in case
- of memory to memory transfer direction.
-
- This parameter must be a value between
- Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory
- to peripheral, from memory to memory or from peripheral
- to memory. This parameter can be a value of @ref
- DMA_LL_EC_DIRECTION
-
- This feature can be modified afterwards using unitary
- function @ref LL_DMA_SetDataTransferDirection(). */
-
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref DMA_LL_EC_MODE
- @note: The circular buffer mode cannot be used if the
- memory to memory data transfer direction is configured on
- the selected Channel
-
- This feature can be modified afterwards using unitary
- function @ref LL_DMA_SetMode(). */
-
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address
- or Source address in case of memory to
- memory transfer direction is incremented or
- not. This parameter can be a value of @ref
- DMA_LL_EC_PERIPH
-
- This feature can be modified afterwards
- using unitary function @ref
- LL_DMA_SetPeriphIncMode(). */
-
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or
- Destination address in case of memory to
- memory transfer direction is incremented or
- not. This parameter can be a value of @ref
- DMA_LL_EC_MEMORY
-
- This feature can be modified afterwards
- using unitary function @ref
- LL_DMA_SetMemoryIncMode(). */
-
- uint32_t
- PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment
- or Source data size alignment (byte, half word,
- word) in case of memory to memory transfer
- direction. This parameter can be a value of
- @ref DMA_LL_EC_PDATAALIGN
-
- This feature can be modified afterwards using
- unitary function @ref LL_DMA_SetPeriphSize().
- */
-
- uint32_t
- MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or
- Destination data size alignment (byte, half
- word, word) in case of memory to memory
- transfer direction. This parameter can be a
- value of @ref DMA_LL_EC_MDATAALIGN
-
- This feature can be modified afterwards using
- unitary function @ref LL_DMA_SetMemorySize().
- */
-
- uint32_t
- NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set
- in PeripheralSize or MemorySize parameters depending in the
- transfer direction. This parameter must be a value between
- Min_Data = 0 and Max_Data = 0x0000FFFF
-
- This feature can be modified afterwards using unitary
- function @ref LL_DMA_SetDataLength(). */
-
- uint32_t PeriphRequest; /*!< Specifies the peripheral request.
- This parameter can be a value of @ref
- DMAMUX_LL_EC_REQUEST
-
- This feature can be modified afterwards using
- unitary function @ref LL_DMA_SetPeriphRequest(). */
-
- uint32_t
- Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
- This feature can be modified afterwards using unitary
- function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
- * @{
- */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_DMA_WriteReg function
- * @{
- */
-#define LL_DMA_IFCR_CGIF1 \
- DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
-#define LL_DMA_IFCR_CTCIF1 \
- DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1 \
- DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_IFCR_CTEIF1 \
- DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_IFCR_CGIF2 \
- DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
-#define LL_DMA_IFCR_CTCIF2 \
- DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2 \
- DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_IFCR_CTEIF2 \
- DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_IFCR_CGIF3 \
- DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
-#define LL_DMA_IFCR_CTCIF3 \
- DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3 \
- DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_IFCR_CTEIF3 \
- DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_IFCR_CGIF4 \
- DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
-#define LL_DMA_IFCR_CTCIF4 \
- DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4 \
- DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_IFCR_CTEIF4 \
- DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_IFCR_CGIF5 \
- DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
-#define LL_DMA_IFCR_CTCIF5 \
- DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5 \
- DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_IFCR_CTEIF5 \
- DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_IFCR_CGIF6 \
- DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
-#define LL_DMA_IFCR_CTCIF6 \
- DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6 \
- DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_IFCR_CTEIF6 \
- DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
-#if defined(DMA1_Channel7)
-#define LL_DMA_IFCR_CGIF7 \
- DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
-#define LL_DMA_IFCR_CTCIF7 \
- DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7 \
- DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_IFCR_CTEIF7 \
- DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
-#endif /* DMA1_Channel7 */
-#if defined(DMA1_Channel8)
-#define LL_DMA_IFCR_CGIF8 \
- DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
-#define LL_DMA_IFCR_CTCIF8 \
- DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF8 \
- DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
-#define LL_DMA_IFCR_CTEIF8 \
- DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
-#endif /* DMA1_Channel8 */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_DMA_ReadReg function
- * @{
- */
-#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
-#define LL_DMA_ISR_TCIF1 \
- DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
-#define LL_DMA_ISR_TCIF2 \
- DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
-#define LL_DMA_ISR_TCIF3 \
- DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
-#define LL_DMA_ISR_TCIF4 \
- DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
-#define LL_DMA_ISR_TCIF5 \
- DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
-#define LL_DMA_ISR_TCIF6 \
- DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
-#if defined(DMA1_Channel7)
-#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
-#define LL_DMA_ISR_TCIF7 \
- DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
-#endif /* DMA1_Channel7 */
-#if defined(DMA1_Channel8)
-#define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
-#define LL_DMA_ISR_TCIF8 \
- DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag \
- */
-#define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
-#define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
-#endif /* DMA1_Channel8 */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_DMA_ReadReg and
- * LL_DMA_WriteReg functions
- * @{
- */
-#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
-#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
- * @{
- */
-#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
-#if defined(DMA1_Channel7)
-#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
-#endif /* DMA1_Channel7 */
-#if defined(DMA1_Channel8)
-#define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */
-#endif /* DMA1_Channel8 */
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL \
- 0xFFFF0000U /*!< DMA Channel all (used only for function @ref \
- LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
- * @{
- */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY \
- 0x00000000U /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH \
- DMA_CCR_DIR /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY \
- DMA_CCR_MEM2MEM /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
- * @{
- */
-#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
-#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
- * @{
- */
-#define LL_DMA_PERIPH_INCREMENT \
- DMA_CCR_PINC /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT \
- 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
- * @{
- */
-#define LL_DMA_MEMORY_INCREMENT \
- DMA_CCR_MINC /*!< Memory increment mode Enable */
-#define LL_DMA_MEMORY_NOINCREMENT \
- 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
- * @{
- */
-#define LL_DMA_PDATAALIGN_BYTE \
- 0x00000000U /*!< Peripheral data alignment : Byte */
-#define LL_DMA_PDATAALIGN_HALFWORD \
- DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD \
- DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
- * @{
- */
-#define LL_DMA_MDATAALIGN_BYTE \
- 0x00000000U /*!< Memory data alignment : Byte */
-#define LL_DMA_MDATAALIGN_HALFWORD \
- DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD \
- DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
- * @{
- */
-#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
-#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
-#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
- * @{
- */
-/**
- * @brief Convert DMAx_Channely into DMAx
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval DMAx
- */
-#if defined(DMA1_Channel8)
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
- (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ? DMA2 : DMA1)
-#else
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
- (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
-#endif /* DMA1_Channel8 */
-/**
- * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval LL_DMA_CHANNEL_y
- */
-#if defined(DMA1_Channel8)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
- (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) \
- ? LL_DMA_CHANNEL_1 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) \
- ? LL_DMA_CHANNEL_1 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) \
- ? LL_DMA_CHANNEL_2 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) \
- ? LL_DMA_CHANNEL_2 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) \
- ? LL_DMA_CHANNEL_3 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) \
- ? LL_DMA_CHANNEL_3 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) \
- ? LL_DMA_CHANNEL_4 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) \
- ? LL_DMA_CHANNEL_4 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) \
- ? LL_DMA_CHANNEL_5 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) \
- ? LL_DMA_CHANNEL_5 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) \
- ? LL_DMA_CHANNEL_6 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) \
- ? LL_DMA_CHANNEL_6 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) \
- ? LL_DMA_CHANNEL_7 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) \
- ? LL_DMA_CHANNEL_7 \
- : LL_DMA_CHANNEL_8)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
- (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) \
- ? LL_DMA_CHANNEL_1 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) \
- ? LL_DMA_CHANNEL_1 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) \
- ? LL_DMA_CHANNEL_2 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) \
- ? LL_DMA_CHANNEL_2 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) \
- ? LL_DMA_CHANNEL_3 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) \
- ? LL_DMA_CHANNEL_3 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) \
- ? LL_DMA_CHANNEL_4 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) \
- ? LL_DMA_CHANNEL_4 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) \
- ? LL_DMA_CHANNEL_5 \
- : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) \
- ? LL_DMA_CHANNEL_5 \
- : LL_DMA_CHANNEL_6)
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
- * @param __DMA_INSTANCE__ DMAx
- * @param __CHANNEL__ LL_DMA_CHANNEL_y
- * @retval DMAx_Channely
- */
-#if defined(DMA1_Channel8)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
- ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
- ? DMA1_Channel1 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
- ? DMA2_Channel1 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
- ? DMA1_Channel2 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
- ? DMA2_Channel2 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
- ? DMA1_Channel3 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
- ? DMA2_Channel3 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
- ? DMA1_Channel4 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
- ? DMA2_Channel4 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
- ? DMA1_Channel5 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
- ? DMA2_Channel5 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
- ? DMA1_Channel6 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
- ? DMA2_Channel6 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
- ? DMA1_Channel7 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
- ? DMA2_Channel7 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
- ? DMA1_Channel8 \
- : DMA2_Channel8)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
- ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
- ? DMA1_Channel1 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
- ? DMA2_Channel1 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
- ? DMA1_Channel2 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
- ? DMA2_Channel2 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
- ? DMA1_Channel3 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
- ? DMA2_Channel3 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
- ? DMA1_Channel4 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
- ? DMA2_Channel4 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
- ? DMA1_Channel5 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
- ? DMA2_Channel5 \
- : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
- ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
- ? DMA1_Channel6 \
- : DMA2_Channel6)
-#endif /* DMA1_Channel8 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable DMA channel.
- * @rmtoll CCR EN LL_DMA_EnableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_EN);
-}
-
-/**
- * @brief Disable DMA channel.
- * @rmtoll CCR EN LL_DMA_DisableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_EN);
-}
-
-/**
- * @brief Check if DMA channel is enabled or disabled.
- * @rmtoll CCR EN LL_DMA_IsEnabledChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (
- (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_EN) == (DMA_CCR_EN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configure all parameters link to DMA transfer.
- * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
- * CCR MEM2MEM LL_DMA_ConfigTransfer\n
- * CCR CIRC LL_DMA_ConfigTransfer\n
- * CCR PINC LL_DMA_ConfigTransfer\n
- * CCR MINC LL_DMA_ConfigTransfer\n
- * CCR PSIZE LL_DMA_ConfigTransfer\n
- * CCR MSIZE LL_DMA_ConfigTransfer\n
- * CCR PL LL_DMA_ConfigTransfer
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param Configuration This parameter must be a combination of all the
- * following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
- * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD
- * or @ref LL_DMA_PDATAALIGN_WORD
- * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD
- * or @ref LL_DMA_MDATAALIGN_WORD
- * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref
- * LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel,
- uint32_t Configuration) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC |
- DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
- Configuration);
-}
-
-/**
- * @brief Set Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_SetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t Direction) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
- * @brief Get Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_GetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
- * @brief Set DMA mode circular or normal.
- * @note The circular buffer mode cannot be used if the memory-to-memory
- * data transfer is configured on the selected Channel.
- * @rmtoll CCR CIRC LL_DMA_SetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel,
- uint32_t Mode) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_CIRC, Mode);
-}
-
-/**
- * @brief Get DMA mode circular or normal.
- * @rmtoll CCR CIRC LL_DMA_GetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_CIRC));
-}
-
-/**
- * @brief Set Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param PeriphOrM2MSrcIncMode This parameter can be one of the following
- * values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t PeriphOrM2MSrcIncMode) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_PINC, PeriphOrM2MSrcIncMode);
-}
-
-/**
- * @brief Get Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_PINC));
-}
-
-/**
- * @brief Set Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param MemoryOrM2MDstIncMode This parameter can be one of the following
- * values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t MemoryOrM2MDstIncMode) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_MINC, MemoryOrM2MDstIncMode);
-}
-
-/**
- * @brief Get Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_MINC));
-}
-
-/**
- * @brief Set Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param PeriphOrM2MSrcDataSize This parameter can be one of the following
- * values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel,
- uint32_t PeriphOrM2MSrcDataSize) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize);
-}
-
-/**
- * @brief Get Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_PSIZE));
-}
-
-/**
- * @brief Set Memory size.
- * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param MemoryOrM2MDstDataSize This parameter can be one of the following
- * values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel,
- uint32_t MemoryOrM2MDstDataSize) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_MSIZE, MemoryOrM2MDstDataSize);
-}
-
-/**
- * @brief Get Memory size.
- * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_MSIZE));
-}
-
-/**
- * @brief Set Channel priority level.
- * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param Priority This parameter can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t Priority) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_PL, Priority);
-}
-
-/**
- * @brief Get Channel priority level.
- * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_PL));
-}
-
-/**
- * @brief Set Number of data to transfer.
- * @note This action has no effect if
- * channel is enabled.
- * @rmtoll CNDTR NDT LL_DMA_SetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel,
- uint32_t NbData) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CNDTR,
- DMA_CNDTR_NDT, NbData);
-}
-
-/**
- * @brief Get Number of data to transfer.
- * @note Once the channel is enabled, the return value indicate the
- * remaining bytes to be transmitted.
- * @rmtoll CNDTR NDT LL_DMA_GetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CNDTR,
- DMA_CNDTR_NDT));
-}
-
-/**
- * @brief Configure the Source and Destination addresses.
- * @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register
- * address (LL_PPP_DMA_GetRegAddr).
- * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
- * CMAR MA LL_DMA_ConfigAddresses
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel,
- uint32_t SrcAddress,
- uint32_t DstAddress,
- uint32_t Direction) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
-
- /* Direction Memory to Periph */
- if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CMAR,
- SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CPAR,
- DstAddress);
- }
- /* Direction Periph to Memory and Memory to Memory */
- else {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CPAR,
- SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CMAR,
- DstAddress);
- }
-}
-
-/**
- * @brief Set the Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t MemoryAddress) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CMAR,
- MemoryAddress);
-}
-
-/**
- * @brief Set the Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t PeriphAddress) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CPAR,
- PeriphAddress);
-}
-
-/**
- * @brief Get Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_REG(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CMAR));
-}
-
-/**
- * @brief Get Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_REG(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CPAR));
-}
-
-/**
- * @brief Set the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t MemoryAddress) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CPAR,
- MemoryAddress);
-}
-
-/**
- * @brief Set the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t MemoryAddress) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CMAR,
- MemoryAddress);
-}
-
-/**
- * @brief Get the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_REG(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CPAR));
-}
-
-/**
- * @brief Get the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (READ_REG(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CMAR));
-}
-
-/**
- * @brief Set DMA request for DMA instance on Channel x.
- * @note Please refer to Reference Manual to get the available mapping of
- * Request value link to Channel Selection.
- * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
- * CSELR C2S LL_DMA_SetPeriphRequest\n
- * CSELR C3S LL_DMA_SetPeriphRequest\n
- * CSELR C4S LL_DMA_SetPeriphRequest\n
- * CSELR C5S LL_DMA_SetPeriphRequest\n
- * CSELR C6S LL_DMA_SetPeriphRequest\n
- * CSELR C7S LL_DMA_SetPeriphRequest
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @param PeriphRequest This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_MEM2MEM
- * @arg @ref LL_DMAMUX_REQ_GENERATOR0
- * @arg @ref LL_DMAMUX_REQ_GENERATOR1
- * @arg @ref LL_DMAMUX_REQ_GENERATOR2
- * @arg @ref LL_DMAMUX_REQ_GENERATOR3
- * @arg @ref LL_DMAMUX_REQ_ADC1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM6_UP
- * @arg @ref LL_DMAMUX_REQ_TIM7_UP
- * @arg @ref LL_DMAMUX_REQ_SPI1_RX
- * @arg @ref LL_DMAMUX_REQ_SPI1_TX
- * @arg @ref LL_DMAMUX_REQ_SPI2_RX
- * @arg @ref LL_DMAMUX_REQ_SPI2_TX
- * @arg @ref LL_DMAMUX_REQ_SPI3_RX
- * @arg @ref LL_DMAMUX_REQ_SPI3_TX
- * @arg @ref LL_DMAMUX_REQ_I2C1_RX
- * @arg @ref LL_DMAMUX_REQ_I2C1_TX
- * @arg @ref LL_DMAMUX_REQ_I2C2_RX
- * @arg @ref LL_DMAMUX_REQ_I2C2_TX
- * @arg @ref LL_DMAMUX_REQ_I2C3_RX
- * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_TX
- * @arg @ref LL_DMAMUX_REQ_USART1_RX
- * @arg @ref LL_DMAMUX_REQ_USART1_TX
- * @arg @ref LL_DMAMUX_REQ_USART2_RX
- * @arg @ref LL_DMAMUX_REQ_USART2_TX
- * @arg @ref LL_DMAMUX_REQ_USART3_RX
- * @arg @ref LL_DMAMUX_REQ_USART3_TX
- * @arg @ref LL_DMAMUX_REQ_UART4_RX
- * @arg @ref LL_DMAMUX_REQ_UART4_TX
- * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
- * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
- * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
- * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
- * @arg @ref LL_DMAMUX_REQ_ADC2
- * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
- * @arg @ref LL_DMAMUX_REQ_QSPI (*)
- * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM1_UP
- * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM1_COM
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM8_UP
- * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM8_COM
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM2_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM3_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM4_UP
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM15_UP
- * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM15_COM
- * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM16_UP
- * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM17_UP
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
- * @arg @ref LL_DMAMUX_REQ_AES_IN
- * @arg @ref LL_DMAMUX_REQ_AES_OUT
- * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
- * @arg @ref LL_DMAMUX_REQ_SAI1_A
- * @arg @ref LL_DMAMUX_REQ_SAI1_B
- * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
- * @arg @ref LL_DMAMUX_REQ_FMAC_READ
- * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
- * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
- * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
- * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx,
- uint32_t Channel,
- uint32_t PeriphRequest) {
- uint32_t dmamux_ccr_offset =
- ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
- MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR,
- DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
-}
-
-/**
- * @brief Get DMA request for DMA instance on Channel x.
- * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
- * CSELR C2S LL_DMA_GetPeriphRequest\n
- * CSELR C3S LL_DMA_GetPeriphRequest\n
- * CSELR C4S LL_DMA_GetPeriphRequest\n
- * CSELR C5S LL_DMA_GetPeriphRequest\n
- * CSELR C6S LL_DMA_GetPeriphRequest\n
- * CSELR C7S LL_DMA_GetPeriphRequest
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_MEM2MEM
- * @arg @ref LL_DMAMUX_REQ_GENERATOR0
- * @arg @ref LL_DMAMUX_REQ_GENERATOR1
- * @arg @ref LL_DMAMUX_REQ_GENERATOR2
- * @arg @ref LL_DMAMUX_REQ_GENERATOR3
- * @arg @ref LL_DMAMUX_REQ_ADC1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM6_UP
- * @arg @ref LL_DMAMUX_REQ_TIM7_UP
- * @arg @ref LL_DMAMUX_REQ_SPI1_RX
- * @arg @ref LL_DMAMUX_REQ_SPI1_TX
- * @arg @ref LL_DMAMUX_REQ_SPI2_RX
- * @arg @ref LL_DMAMUX_REQ_SPI2_TX
- * @arg @ref LL_DMAMUX_REQ_SPI3_RX
- * @arg @ref LL_DMAMUX_REQ_SPI3_TX
- * @arg @ref LL_DMAMUX_REQ_I2C1_RX
- * @arg @ref LL_DMAMUX_REQ_I2C1_TX
- * @arg @ref LL_DMAMUX_REQ_I2C2_RX
- * @arg @ref LL_DMAMUX_REQ_I2C2_TX
- * @arg @ref LL_DMAMUX_REQ_I2C3_RX
- * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_TX
- * @arg @ref LL_DMAMUX_REQ_USART1_RX
- * @arg @ref LL_DMAMUX_REQ_USART1_TX
- * @arg @ref LL_DMAMUX_REQ_USART2_RX
- * @arg @ref LL_DMAMUX_REQ_USART2_TX
- * @arg @ref LL_DMAMUX_REQ_USART3_RX
- * @arg @ref LL_DMAMUX_REQ_USART3_TX
- * @arg @ref LL_DMAMUX_REQ_UART4_RX
- * @arg @ref LL_DMAMUX_REQ_UART4_TX
- * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
- * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
- * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
- * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
- * @arg @ref LL_DMAMUX_REQ_ADC2
- * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
- * @arg @ref LL_DMAMUX_REQ_QSPI (*)
- * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM1_UP
- * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM1_COM
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM8_UP
- * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM8_COM
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM2_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM3_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM4_UP
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM15_UP
- * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM15_COM
- * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM16_UP
- * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM17_UP
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
- * @arg @ref LL_DMAMUX_REQ_AES_IN
- * @arg @ref LL_DMAMUX_REQ_AES_OUT
- * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
- * @arg @ref LL_DMAMUX_REQ_SAI1_A
- * @arg @ref LL_DMAMUX_REQ_SAI1_B
- * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
- * @arg @ref LL_DMAMUX_REQ_FMAC_READ
- * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
- * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
- * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
- * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
- * (*) Not on all G4 devices
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dmamux_ccr_offset =
- ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
- return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR,
- DMAMUX_CxCR_DMAREQ_ID));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Channel 1 global interrupt flag.
- * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 2 global interrupt flag.
- * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 3 global interrupt flag.
- * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 4 global interrupt flag.
- * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 5 global interrupt flag.
- * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 6 global interrupt flag.
- * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Get Channel 7 global interrupt flag.
- * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Get Channel 8 global interrupt flag.
- * @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Get Channel 1 transfer complete flag.
- * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 2 transfer complete flag.
- * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 3 transfer complete flag.
- * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 4 transfer complete flag.
- * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 5 transfer complete flag.
- * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 6 transfer complete flag.
- * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Get Channel 7 transfer complete flag.
- * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Get Channel 8 transfer complete flag.
- * @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Get Channel 1 half transfer flag.
- * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 2 half transfer flag.
- * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 3 half transfer flag.
- * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 4 half transfer flag.
- * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 5 half transfer flag.
- * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 6 half transfer flag.
- * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Get Channel 7 half transfer flag.
- * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Get Channel 8 half transfer flag.
- * @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Get Channel 1 transfer error flag.
- * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 2 transfer error flag.
- * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 3 transfer error flag.
- * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 4 transfer error flag.
- * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 5 transfer error flag.
- * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get Channel 6 transfer error flag.
- * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Get Channel 7 transfer error flag.
- * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Get Channel 8 transfer error flag.
- * @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) {
- return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Clear Channel 1 global interrupt flag.
- * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
- LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
- * @brief Clear Channel 2 global interrupt flag.
- * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
- LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
- * @brief Clear Channel 3 global interrupt flag.
- * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
- LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
- * @brief Clear Channel 4 global interrupt flag.
- * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
- LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
- * @brief Clear Channel 5 global interrupt flag.
- * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
- LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-/**
- * @brief Clear Channel 6 global interrupt flag.
- * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
- LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Clear Channel 7 global interrupt flag.
- * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
- LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Clear Channel 8 global interrupt flag.
- * @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
- Instead clear specific flags transfer complete, half transfer & transfer
- error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
- LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
- * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Clear Channel 1 transfer complete flag.
- * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer complete flag.
- * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer complete flag.
- * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer complete flag.
- * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer complete flag.
- * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer complete flag.
- * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Clear Channel 7 transfer complete flag.
- * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Clear Channel 8 transfer complete flag.
- * @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Clear Channel 1 half transfer flag.
- * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
- * @brief Clear Channel 2 half transfer flag.
- * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
- * @brief Clear Channel 3 half transfer flag.
- * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
- * @brief Clear Channel 4 half transfer flag.
- * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
- * @brief Clear Channel 5 half transfer flag.
- * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-/**
- * @brief Clear Channel 6 half transfer flag.
- * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Clear Channel 7 half transfer flag.
- * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Clear Channel 8 half transfer flag.
- * @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @brief Clear Channel 1 transfer error flag.
- * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer error flag.
- * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer error flag.
- * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer error flag.
- * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer error flag.
- * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer error flag.
- * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-
-#if defined(DMA1_Channel7)
-/**
- * @brief Clear Channel 7 transfer error flag.
- * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-#endif /* DMA1_Channel7 */
-
-#if defined(DMA1_Channel8)
-/**
- * @brief Clear Channel 8 transfer error flag.
- * @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) {
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
-}
-#endif /* DMA1_Channel8 */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
- * @{
- */
-/**
- * @brief Enable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_TCIE);
-}
-
-/**
- * @brief Enable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_HTIE);
-}
-
-/**
- * @brief Enable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_TEIE);
-}
-
-/**
- * @brief Disable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_TCIE);
-}
-
-/**
- * @brief Disable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_HTIE);
-}
-
-/**
- * @brief Disable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
- CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_TEIE);
-}
-
-/**
- * @brief Check if Transfer complete Interrupt is enabled.
- * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (
- (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_TCIE) == (DMA_CCR_TCIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Half transfer Interrupt is enabled.
- * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (
- (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_HTIE) == (DMA_CCR_HTIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Transfer error Interrupt is enabled.
- * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- * @arg @ref LL_DMA_CHANNEL_8 (*)
- * (*) Not on all G4 devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx,
- uint32_t Channel) {
- uint32_t dma_base_addr = (uint32_t)DMAx;
- return (
- (READ_BIT(((DMA_Channel_TypeDef *)((
- uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
- ->CCR,
- DMA_CCR_TEIE) == (DMA_CCR_TEIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel,
- LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_DMA_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_DMA_H
+#define __STM32G4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+#include "stm32g4xx_ll_dmamux.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(DMA1) || defined(DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA channel register offset versus channel index
+ * LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] = {
+ (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
+#if defined(DMA1_Channel7)
+ ,
+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+#endif /* DMA1_Channel7 */
+#if defined(DMA1_Channel8)
+ ,
+ (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
+#endif /* DMA1_Channel8 */
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+ * @{
+ */
+/* Define used to get CSELR register offset */
+#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define DMA_POSITION_CSELR_CXS \
+ POSITION_VAL(DMA_CSELR_C1S << ((Channel - 1U) * 4U))
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct {
+ uint32_t
+ PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA
+ transfer or as Source base address in case of
+ memory to memory transfer direction.
+
+ This parameter must be a value between
+ Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t
+ MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA
+ transfer or as Destination base address in case
+ of memory to memory transfer direction.
+
+ This parameter must be a value between
+ Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory
+ to peripheral, from memory to memory or from peripheral
+ to memory. This parameter can be a value of @ref
+ DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the
+ memory to memory data transfer direction is configured on
+ the selected Channel
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address
+ or Source address in case of memory to
+ memory transfer direction is incremented or
+ not. This parameter can be a value of @ref
+ DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards
+ using unitary function @ref
+ LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or
+ Destination address in case of memory to
+ memory transfer direction is incremented or
+ not. This parameter can be a value of @ref
+ DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards
+ using unitary function @ref
+ LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t
+ PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment
+ or Source data size alignment (byte, half word,
+ word) in case of memory to memory transfer
+ direction. This parameter can be a value of
+ @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_DMA_SetPeriphSize().
+ */
+
+ uint32_t
+ MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or
+ Destination data size alignment (byte, half
+ word, word) in case of memory to memory
+ transfer direction. This parameter can be a
+ value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_DMA_SetMemorySize().
+ */
+
+ uint32_t
+ NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set
+ in PeripheralSize or MemorySize parameters depending in the
+ transfer direction. This parameter must be a value between
+ Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DMA_SetDataLength(). */
+
+ uint32_t PeriphRequest; /*!< Specifies the peripheral request.
+ This parameter can be a value of @ref
+ DMAMUX_LL_EC_REQUEST
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+ uint32_t
+ Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_WriteReg function
+ * @{
+ */
+#define LL_DMA_IFCR_CGIF1 \
+ DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
+#define LL_DMA_IFCR_CTCIF1 \
+ DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1 \
+ DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_IFCR_CTEIF1 \
+ DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_IFCR_CGIF2 \
+ DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
+#define LL_DMA_IFCR_CTCIF2 \
+ DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2 \
+ DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_IFCR_CTEIF2 \
+ DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_IFCR_CGIF3 \
+ DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
+#define LL_DMA_IFCR_CTCIF3 \
+ DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3 \
+ DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_IFCR_CTEIF3 \
+ DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_IFCR_CGIF4 \
+ DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
+#define LL_DMA_IFCR_CTCIF4 \
+ DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4 \
+ DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_IFCR_CTEIF4 \
+ DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_IFCR_CGIF5 \
+ DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
+#define LL_DMA_IFCR_CTCIF5 \
+ DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5 \
+ DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_IFCR_CTEIF5 \
+ DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_IFCR_CGIF6 \
+ DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
+#define LL_DMA_IFCR_CTCIF6 \
+ DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6 \
+ DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_IFCR_CTEIF6 \
+ DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
+#if defined(DMA1_Channel7)
+#define LL_DMA_IFCR_CGIF7 \
+ DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
+#define LL_DMA_IFCR_CTCIF7 \
+ DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7 \
+ DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_IFCR_CTEIF7 \
+ DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
+#endif /* DMA1_Channel7 */
+#if defined(DMA1_Channel8)
+#define LL_DMA_IFCR_CGIF8 \
+ DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
+#define LL_DMA_IFCR_CTCIF8 \
+ DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF8 \
+ DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
+#define LL_DMA_IFCR_CTEIF8 \
+ DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
+#endif /* DMA1_Channel8 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_ReadReg function
+ * @{
+ */
+#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
+#define LL_DMA_ISR_TCIF1 \
+ DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
+#define LL_DMA_ISR_TCIF2 \
+ DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
+#define LL_DMA_ISR_TCIF3 \
+ DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
+#define LL_DMA_ISR_TCIF4 \
+ DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
+#define LL_DMA_ISR_TCIF5 \
+ DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
+#define LL_DMA_ISR_TCIF6 \
+ DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
+#if defined(DMA1_Channel7)
+#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
+#define LL_DMA_ISR_TCIF7 \
+ DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
+#endif /* DMA1_Channel7 */
+#if defined(DMA1_Channel8)
+#define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
+#define LL_DMA_ISR_TCIF8 \
+ DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag \
+ */
+#define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
+#define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
+#endif /* DMA1_Channel8 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and
+ * LL_DMA_WriteReg functions
+ * @{
+ */
+#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
+#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
+#if defined(DMA1_Channel7)
+#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
+#endif /* DMA1_Channel7 */
+#if defined(DMA1_Channel8)
+#define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */
+#endif /* DMA1_Channel8 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL \
+ 0xFFFF0000U /*!< DMA Channel all (used only for function @ref \
+ LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY \
+ 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH \
+ DMA_CCR_DIR /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY \
+ DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+ * @{
+ */
+#define LL_DMA_PERIPH_INCREMENT \
+ DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT \
+ 0x00000000U /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+ * @{
+ */
+#define LL_DMA_MEMORY_INCREMENT \
+ DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define LL_DMA_MEMORY_NOINCREMENT \
+ 0x00000000U /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE \
+ 0x00000000U /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD \
+ DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD \
+ DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE \
+ 0x00000000U /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD \
+ DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD \
+ DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+/**
+ * @brief Convert DMAx_Channely into DMAx
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval DMAx
+ */
+#if defined(DMA1_Channel8)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+ (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ? DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+ (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
+#endif /* DMA1_Channel8 */
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval LL_DMA_CHANNEL_y
+ */
+#if defined(DMA1_Channel8)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) \
+ ? LL_DMA_CHANNEL_1 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) \
+ ? LL_DMA_CHANNEL_1 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) \
+ ? LL_DMA_CHANNEL_2 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) \
+ ? LL_DMA_CHANNEL_2 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) \
+ ? LL_DMA_CHANNEL_3 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) \
+ ? LL_DMA_CHANNEL_3 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) \
+ ? LL_DMA_CHANNEL_4 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) \
+ ? LL_DMA_CHANNEL_4 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) \
+ ? LL_DMA_CHANNEL_5 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) \
+ ? LL_DMA_CHANNEL_5 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) \
+ ? LL_DMA_CHANNEL_6 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) \
+ ? LL_DMA_CHANNEL_6 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) \
+ ? LL_DMA_CHANNEL_7 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) \
+ ? LL_DMA_CHANNEL_7 \
+ : LL_DMA_CHANNEL_8)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) \
+ ? LL_DMA_CHANNEL_1 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) \
+ ? LL_DMA_CHANNEL_1 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) \
+ ? LL_DMA_CHANNEL_2 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) \
+ ? LL_DMA_CHANNEL_2 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) \
+ ? LL_DMA_CHANNEL_3 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) \
+ ? LL_DMA_CHANNEL_3 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) \
+ ? LL_DMA_CHANNEL_4 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) \
+ ? LL_DMA_CHANNEL_4 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) \
+ ? LL_DMA_CHANNEL_5 \
+ : ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) \
+ ? LL_DMA_CHANNEL_5 \
+ : LL_DMA_CHANNEL_6)
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y
+ * @retval DMAx_Channely
+ */
+#if defined(DMA1_Channel8)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+ ? DMA1_Channel1 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+ ? DMA2_Channel1 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+ ? DMA1_Channel2 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+ ? DMA2_Channel2 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+ ? DMA1_Channel3 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+ ? DMA2_Channel3 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+ ? DMA1_Channel4 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+ ? DMA2_Channel4 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+ ? DMA1_Channel5 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+ ? DMA2_Channel5 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
+ ? DMA1_Channel6 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
+ ? DMA2_Channel6 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
+ ? DMA1_Channel7 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
+ ? DMA2_Channel7 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
+ ? DMA1_Channel8 \
+ : DMA2_Channel8)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+ ? DMA1_Channel1 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+ ? DMA2_Channel1 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+ ? DMA1_Channel2 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+ ? DMA2_Channel2 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+ ? DMA1_Channel3 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+ ? DMA2_Channel3 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+ ? DMA1_Channel4 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+ ? DMA2_Channel4 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+ ? DMA1_Channel5 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+ ? DMA2_Channel5 \
+ : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
+ ? DMA1_Channel6 \
+ : DMA2_Channel6)
+#endif /* DMA1_Channel8 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA channel.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable DMA channel.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_EN);
+}
+
+/**
+ * @brief Check if DMA channel is enabled or disabled.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (
+ (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_EN) == (DMA_CCR_EN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configure all parameters link to DMA transfer.
+ * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
+ * CCR MEM2MEM LL_DMA_ConfigTransfer\n
+ * CCR CIRC LL_DMA_ConfigTransfer\n
+ * CCR PINC LL_DMA_ConfigTransfer\n
+ * CCR MINC LL_DMA_ConfigTransfer\n
+ * CCR PSIZE LL_DMA_ConfigTransfer\n
+ * CCR MSIZE LL_DMA_ConfigTransfer\n
+ * CCR PL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param Configuration This parameter must be a combination of all the
+ * following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD
+ * or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD
+ * or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref
+ * LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t Configuration) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC |
+ DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t Direction) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+ * @brief Set DMA mode circular or normal.
+ * @note The circular buffer mode cannot be used if the memory-to-memory
+ * data transfer is configured on the selected Channel.
+ * @rmtoll CCR CIRC LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t Mode) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_CIRC, Mode);
+}
+
+/**
+ * @brief Get DMA mode circular or normal.
+ * @rmtoll CCR CIRC LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_CIRC));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param PeriphOrM2MSrcIncMode This parameter can be one of the following
+ * values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t PeriphOrM2MSrcIncMode) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_PINC, PeriphOrM2MSrcIncMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param MemoryOrM2MDstIncMode This parameter can be one of the following
+ * values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t MemoryOrM2MDstIncMode) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_MINC, MemoryOrM2MDstIncMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param PeriphOrM2MSrcDataSize This parameter can be one of the following
+ * values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t PeriphOrM2MSrcDataSize) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param MemoryOrM2MDstDataSize This parameter can be one of the following
+ * values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t MemoryOrM2MDstDataSize) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_MSIZE, MemoryOrM2MDstDataSize);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_MSIZE));
+}
+
+/**
+ * @brief Set Channel priority level.
+ * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t Priority) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_PL, Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @note This action has no effect if
+ * channel is enabled.
+ * @rmtoll CNDTR NDT LL_DMA_SetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t NbData) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CNDTR,
+ DMA_CNDTR_NDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @note Once the channel is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @rmtoll CNDTR NDT LL_DMA_GetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CNDTR,
+ DMA_CNDTR_NDT));
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @note Each IP using DMA provides an API to get directly the register
+ * address (LL_PPP_DMA_GetRegAddr).
+ * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
+ * CMAR MA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel,
+ uint32_t SrcAddress,
+ uint32_t DstAddress,
+ uint32_t Direction) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CMAR,
+ SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CPAR,
+ DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CPAR,
+ SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CMAR,
+ DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t MemoryAddress) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CMAR,
+ MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t PeriphAddress) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CPAR,
+ PeriphAddress);
+}
+
+/**
+ * @brief Get Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CMAR));
+}
+
+/**
+ * @brief Get Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CPAR));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t MemoryAddress) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CPAR,
+ MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t MemoryAddress) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CMAR,
+ MemoryAddress);
+}
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CPAR));
+}
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CMAR));
+}
+
+/**
+ * @brief Set DMA request for DMA instance on Channel x.
+ * @note Please refer to Reference Manual to get the available mapping of
+ * Request value link to Channel Selection.
+ * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
+ * CSELR C2S LL_DMA_SetPeriphRequest\n
+ * CSELR C3S LL_DMA_SetPeriphRequest\n
+ * CSELR C4S LL_DMA_SetPeriphRequest\n
+ * CSELR C5S LL_DMA_SetPeriphRequest\n
+ * CSELR C6S LL_DMA_SetPeriphRequest\n
+ * CSELR C7S LL_DMA_SetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @param PeriphRequest This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_ADC2
+ * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+ * @arg @ref LL_DMAMUX_REQ_QSPI (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_FMAC_READ
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx,
+ uint32_t Channel,
+ uint32_t PeriphRequest) {
+ uint32_t dmamux_ccr_offset =
+ ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR,
+ DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
+}
+
+/**
+ * @brief Get DMA request for DMA instance on Channel x.
+ * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
+ * CSELR C2S LL_DMA_GetPeriphRequest\n
+ * CSELR C3S LL_DMA_GetPeriphRequest\n
+ * CSELR C4S LL_DMA_GetPeriphRequest\n
+ * CSELR C5S LL_DMA_GetPeriphRequest\n
+ * CSELR C6S LL_DMA_GetPeriphRequest\n
+ * CSELR C7S LL_DMA_GetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_ADC2
+ * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+ * @arg @ref LL_DMAMUX_REQ_QSPI (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_FMAC_READ
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+ * (*) Not on all G4 devices
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dmamux_ccr_offset =
+ ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
+ return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR,
+ DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Channel 1 global interrupt flag.
+ * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 global interrupt flag.
+ * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 global interrupt flag.
+ * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 global interrupt flag.
+ * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 global interrupt flag.
+ * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 global interrupt flag.
+ * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Get Channel 7 global interrupt flag.
+ * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Get Channel 8 global interrupt flag.
+ * @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Get Channel 1 transfer complete flag.
+ * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 transfer complete flag.
+ * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 transfer complete flag.
+ * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 transfer complete flag.
+ * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 transfer complete flag.
+ * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 transfer complete flag.
+ * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Get Channel 7 transfer complete flag.
+ * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Get Channel 8 transfer complete flag.
+ * @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Get Channel 1 half transfer flag.
+ * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 half transfer flag.
+ * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 half transfer flag.
+ * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 half transfer flag.
+ * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 half transfer flag.
+ * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 half transfer flag.
+ * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
+}
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Get Channel 7 half transfer flag.
+ * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Get Channel 8 half transfer flag.
+ * @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Get Channel 1 transfer error flag.
+ * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 transfer error flag.
+ * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 transfer error flag.
+ * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 transfer error flag.
+ * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 transfer error flag.
+ * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 transfer error flag.
+ * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Get Channel 7 transfer error flag.
+ * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Get Channel 8 transfer error flag.
+ * @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) {
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Clear Channel 1 global interrupt flag.
+ * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
+ LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+ * @brief Clear Channel 2 global interrupt flag.
+ * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
+ LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+ * @brief Clear Channel 3 global interrupt flag.
+ * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
+ LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+ * @brief Clear Channel 4 global interrupt flag.
+ * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
+ LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+ * @brief Clear Channel 5 global interrupt flag.
+ * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
+ LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+ * @brief Clear Channel 6 global interrupt flag.
+ * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
+ LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Clear Channel 7 global interrupt flag.
+ * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
+ LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Clear Channel 8 global interrupt flag.
+ * @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
+ LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Clear Channel 1 transfer complete flag.
+ * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer complete flag.
+ * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer complete flag.
+ * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer complete flag.
+ * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer complete flag.
+ * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer complete flag.
+ * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Clear Channel 7 transfer complete flag.
+ * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Clear Channel 8 transfer complete flag.
+ * @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Clear Channel 1 half transfer flag.
+ * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Channel 2 half transfer flag.
+ * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Channel 3 half transfer flag.
+ * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Channel 4 half transfer flag.
+ * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Channel 5 half transfer flag.
+ * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Channel 6 half transfer flag.
+ * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Clear Channel 7 half transfer flag.
+ * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Clear Channel 8 half transfer flag.
+ * @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @brief Clear Channel 1 transfer error flag.
+ * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer error flag.
+ * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer error flag.
+ * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer error flag.
+ * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer error flag.
+ * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer error flag.
+ * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+#if defined(DMA1_Channel7)
+/**
+ * @brief Clear Channel 7 transfer error flag.
+ * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined(DMA1_Channel8)
+/**
+ * @brief Clear Channel 8 transfer error flag.
+ * @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) {
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr +
+ CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete Interrupt is enabled.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (
+ (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_TCIE) == (DMA_CCR_TCIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Half transfer Interrupt is enabled.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (
+ (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_HTIE) == (DMA_CCR_HTIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Transfer error Interrupt is enabled.
+ * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7 (*)
+ * @arg @ref LL_DMA_CHANNEL_8 (*)
+ * (*) Not on all G4 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx,
+ uint32_t Channel) {
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (
+ (READ_BIT(((DMA_Channel_TypeDef *)((
+ uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))
+ ->CCR,
+ DMA_CCR_TEIE) == (DMA_CCR_TEIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel,
+ LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_DMA_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h
index dae777f..8275c27 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h
@@ -1,2291 +1,2291 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_dmamux.h
- * @author MCD Application Team
- * @brief Header file of DMAMUX LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_DMAMUX_H
-#define __STM32G4xx_LL_DMAMUX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(DMAMUX1)
-
-/** @defgroup DMAMUX_LL DMAMUX
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
- * @{
- */
-/* Define used to get DMAMUX CCR register size */
-#define DMAMUX_CCR_SIZE 0x00000004U
-
-/* Define used to get DMAMUX RGCR register size */
-#define DMAMUX_RGCR_SIZE 0x00000004U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Private_Macros DMAMUX Private Macros
- * @{
- */
-#define UNUSED(X) (void)X
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
- * @{
- */
-/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
- * @{
- */
-#define LL_DMAMUX_CFR_CSOF0 \
- DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
-#define LL_DMAMUX_CFR_CSOF1 \
- DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
-#define LL_DMAMUX_CFR_CSOF2 \
- DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
-#define LL_DMAMUX_CFR_CSOF3 \
- DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
-#define LL_DMAMUX_CFR_CSOF4 \
- DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
-#define LL_DMAMUX_CFR_CSOF5 \
- DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
-#define LL_DMAMUX_CFR_CSOF6 \
- DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
-#define LL_DMAMUX_CFR_CSOF7 \
- DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
-#define LL_DMAMUX_CFR_CSOF8 \
- DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
-#define LL_DMAMUX_CFR_CSOF9 \
- DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
-#define LL_DMAMUX_CFR_CSOF10 \
- DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
-#define LL_DMAMUX_CFR_CSOF11 \
- DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
-#define LL_DMAMUX_CFR_CSOF12 \
- DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
-#define LL_DMAMUX_CFR_CSOF13 \
- DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
-#define LL_DMAMUX_CFR_CSOF14 \
- DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
-#define LL_DMAMUX_CFR_CSOF15 \
- DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
-#define LL_DMAMUX_RGCFR_RGCOF0 \
- DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF1 \
- DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF2 \
- DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF3 \
- DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
- * @{
- */
-#define LL_DMAMUX_CSR_SOF0 \
- DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
-#define LL_DMAMUX_CSR_SOF1 \
- DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
-#define LL_DMAMUX_CSR_SOF2 \
- DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
-#define LL_DMAMUX_CSR_SOF3 \
- DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
-#define LL_DMAMUX_CSR_SOF4 \
- DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
-#define LL_DMAMUX_CSR_SOF5 \
- DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
-#define LL_DMAMUX_CSR_SOF6 \
- DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
-#define LL_DMAMUX_CSR_SOF7 \
- DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
-#define LL_DMAMUX_CSR_SOF8 \
- DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
-#define LL_DMAMUX_CSR_SOF9 \
- DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
-#define LL_DMAMUX_CSR_SOF10 \
- DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
-#define LL_DMAMUX_CSR_SOF11 \
- DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
-#define LL_DMAMUX_CSR_SOF12 \
- DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
-#define LL_DMAMUX_CSR_SOF13 \
- DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
-#define LL_DMAMUX_CSR_SOF14 \
- DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
-#define LL_DMAMUX_CSR_SOF15 \
- DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
-#define LL_DMAMUX_RGSR_RGOF0 \
- DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF1 \
- DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF2 \
- DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF3 \
- DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_DMA_ReadReg and
- * LL_DMAMUX_WriteReg functions
- * @{
- */
-#define LL_DMAMUX_CCR_SOIE \
- DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
-#define LL_DMAMUX_RGCR_RGOIE \
- DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
- * @{
- */
-#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< Memory to memory transfer */
-#define LL_DMAMUX_REQ_GENERATOR0 \
- 0x00000001U /*!< DMAMUX request generator 0 \
- */
-#define LL_DMAMUX_REQ_GENERATOR1 \
- 0x00000002U /*!< DMAMUX request generator 1 \
- */
-#define LL_DMAMUX_REQ_GENERATOR2 \
- 0x00000003U /*!< DMAMUX request generator 2 \
- */
-#define LL_DMAMUX_REQ_GENERATOR3 \
- 0x00000004U /*!< DMAMUX request generator 3 \
- */
-#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */
-#define LL_DMAMUX_REQ_DAC1_CH1 0x00000006U /*!< DMAMUX DAC1 CH1 request */
-#define LL_DMAMUX_REQ_DAC1_CH2 0x00000007U /*!< DMAMUX DAC1 CH2 request */
-#define LL_DMAMUX_REQ_TIM6_UP 0x00000008U /*!< DMAMUX TIM6 UP request */
-#define LL_DMAMUX_REQ_TIM7_UP 0x00000009U /*!< DMAMUX TIM7 UP request */
-#define LL_DMAMUX_REQ_SPI1_RX 0x0000000AU /*!< DMAMUX SPI1 RX request */
-#define LL_DMAMUX_REQ_SPI1_TX 0x0000000BU /*!< DMAMUX SPI1 TX request */
-#define LL_DMAMUX_REQ_SPI2_RX 0x0000000CU /*!< DMAMUX SPI2 RX request */
-#define LL_DMAMUX_REQ_SPI2_TX 0x0000000DU /*!< DMAMUX SPI2 TX request */
-#define LL_DMAMUX_REQ_SPI3_RX 0x0000000EU /*!< DMAMUX SPI3 RX request */
-#define LL_DMAMUX_REQ_SPI3_TX 0x0000000FU /*!< DMAMUX SPI3 TX request */
-#define LL_DMAMUX_REQ_I2C1_RX 0x00000010U /*!< DMAMUX I2C1 RX request */
-#define LL_DMAMUX_REQ_I2C1_TX 0x00000011U /*!< DMAMUX I2C1 TX request */
-#define LL_DMAMUX_REQ_I2C2_RX 0x00000012U /*!< DMAMUX I2C2 RX request */
-#define LL_DMAMUX_REQ_I2C2_TX 0x00000013U /*!< DMAMUX I2C2 TX request */
-#define LL_DMAMUX_REQ_I2C3_RX 0x00000014U /*!< DMAMUX I2C3 RX request */
-#define LL_DMAMUX_REQ_I2C3_TX 0x00000015U /*!< DMAMUX I2C3 TX request */
-#define LL_DMAMUX_REQ_I2C4_RX 0x00000016U /*!< DMAMUX I2C4 RX request */
-#define LL_DMAMUX_REQ_I2C4_TX 0x00000017U /*!< DMAMUX I2C4 TX request */
-#define LL_DMAMUX_REQ_USART1_RX 0x00000018U /*!< DMAMUX USART1 RX request */
-#define LL_DMAMUX_REQ_USART1_TX 0x00000019U /*!< DMAMUX USART1 TX request */
-#define LL_DMAMUX_REQ_USART2_RX 0x0000001AU /*!< DMAMUX USART2 RX request */
-#define LL_DMAMUX_REQ_USART2_TX 0x0000001BU /*!< DMAMUX USART2 TX request */
-#define LL_DMAMUX_REQ_USART3_RX 0x0000001CU /*!< DMAMUX USART3 RX request */
-#define LL_DMAMUX_REQ_USART3_TX 0x0000001DU /*!< DMAMUX USART3 TX request */
-#define LL_DMAMUX_REQ_UART4_RX 0x0000001EU /*!< DMAMUX UART4 RX request */
-#define LL_DMAMUX_REQ_UART4_TX 0x0000001FU /*!< DMAMUX UART4 TX request */
-#define LL_DMAMUX_REQ_UART5_RX 0x00000020U /*!< DMAMUX UART5 RX request */
-#define LL_DMAMUX_REQ_UART5_TX 0x00000021U /*!< DMAMUX UART5 TX request */
-#define LL_DMAMUX_REQ_LPUART1_RX 0x00000022U /*!< DMAMUX LPUART1 RX request */
-#define LL_DMAMUX_REQ_LPUART1_TX 0x00000023U /*!< DMAMUX LPUART1 TX request */
-#define LL_DMAMUX_REQ_ADC2 0x00000024U /*!< DMAMUX ADC2 request */
-#define LL_DMAMUX_REQ_ADC3 0x00000025U /*!< DMAMUX ADC3 request */
-#define LL_DMAMUX_REQ_ADC4 0x00000026U /*!< DMAMUX ADC4 request */
-#define LL_DMAMUX_REQ_ADC5 0x00000027U /*!< DMAMUX ADC5 request */
-#define LL_DMAMUX_REQ_QSPI 0x00000028U /*!< DMAMUX QSPI request */
-#define LL_DMAMUX_REQ_DAC2_CH1 0x00000029U /*!< DMAMUX DAC2 CH1 request */
-#define LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU /*!< DMAMUX TIM1 CH1 request */
-#define LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU /*!< DMAMUX TIM1 CH2 request */
-#define LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU /*!< DMAMUX TIM1 CH3 request */
-#define LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU /*!< DMAMUX TIM1 CH4 request */
-#define LL_DMAMUX_REQ_TIM1_UP 0x0000002EU /*!< DMAMUX TIM1 UP request */
-#define LL_DMAMUX_REQ_TIM1_TRIG 0x0000002FU /*!< DMAMUX TIM1 TRIG request */
-#define LL_DMAMUX_REQ_TIM1_COM 0x00000030U /*!< DMAMUX TIM1 COM request */
-#define LL_DMAMUX_REQ_TIM8_CH1 0x00000031U /*!< DMAMUX TIM8 CH1 request */
-#define LL_DMAMUX_REQ_TIM8_CH2 0x00000032U /*!< DMAMUX TIM8 CH2 request */
-#define LL_DMAMUX_REQ_TIM8_CH3 0x00000033U /*!< DMAMUX TIM8 CH3 request */
-#define LL_DMAMUX_REQ_TIM8_CH4 0x00000034U /*!< DMAMUX TIM8 CH4 request */
-#define LL_DMAMUX_REQ_TIM8_UP 0x00000035U /*!< DMAMUX TIM8 UP request */
-#define LL_DMAMUX_REQ_TIM8_TRIG 0x00000036U /*!< DMAMUX TIM8 TRIG request */
-#define LL_DMAMUX_REQ_TIM8_COM 0x00000037U /*!< DMAMUX TIM8 COM request */
-#define LL_DMAMUX_REQ_TIM2_CH1 0x00000038U /*!< DMAMUX TIM2 CH1 request */
-#define LL_DMAMUX_REQ_TIM2_CH2 0x00000039U /*!< DMAMUX TIM2 CH2 request */
-#define LL_DMAMUX_REQ_TIM2_CH3 0x0000003AU /*!< DMAMUX TIM2 CH3 request */
-#define LL_DMAMUX_REQ_TIM2_CH4 0x0000003BU /*!< DMAMUX TIM2 CH4 request */
-#define LL_DMAMUX_REQ_TIM2_UP 0x0000003CU /*!< DMAMUX TIM2 UP request */
-#define LL_DMAMUX_REQ_TIM3_CH1 0x0000003DU /*!< DMAMUX TIM3 CH1 request */
-#define LL_DMAMUX_REQ_TIM3_CH2 0x0000003EU /*!< DMAMUX TIM3 CH2 request */
-#define LL_DMAMUX_REQ_TIM3_CH3 0x0000003FU /*!< DMAMUX TIM3 CH3 request */
-#define LL_DMAMUX_REQ_TIM3_CH4 0x00000040U /*!< DMAMUX TIM3 CH4 request */
-#define LL_DMAMUX_REQ_TIM3_UP 0x00000041U /*!< DMAMUX TIM3 UP request */
-#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000042U /*!< DMAMUX TIM3 TRIG request */
-#define LL_DMAMUX_REQ_TIM4_CH1 0x00000043U /*!< DMAMUX TIM4 CH1 request */
-#define LL_DMAMUX_REQ_TIM4_CH2 0x00000044U /*!< DMAMUX TIM4 CH2 request */
-#define LL_DMAMUX_REQ_TIM4_CH3 0x00000045U /*!< DMAMUX TIM4 CH3 request */
-#define LL_DMAMUX_REQ_TIM4_CH4 0x00000046U /*!< DMAMUX TIM4 CH4 request */
-#define LL_DMAMUX_REQ_TIM4_UP 0x00000047U /*!< DMAMUX TIM4 UP request */
-#define LL_DMAMUX_REQ_TIM5_CH1 0x00000048U /*!< DMAMUX TIM5 CH1 request */
-#define LL_DMAMUX_REQ_TIM5_CH2 0x00000049U /*!< DMAMUX TIM5 CH2 request */
-#define LL_DMAMUX_REQ_TIM5_CH3 0x0000004AU /*!< DMAMUX TIM5 CH3 request */
-#define LL_DMAMUX_REQ_TIM5_CH4 0x0000004BU /*!< DMAMUX TIM5 CH4 request */
-#define LL_DMAMUX_REQ_TIM5_UP 0x0000004CU /*!< DMAMUX TIM5 UP request */
-#define LL_DMAMUX_REQ_TIM5_TRIG 0x0000004DU /*!< DMAMUX TIM5 TRIG request */
-#define LL_DMAMUX_REQ_TIM15_CH1 0x0000004EU /*!< DMAMUX TIM15 CH1 request */
-#define LL_DMAMUX_REQ_TIM15_UP 0x0000004FU /*!< DMAMUX TIM15 UP request */
-#define LL_DMAMUX_REQ_TIM15_TRIG 0x00000050U /*!< DMAMUX TIM15 TRIG request */
-#define LL_DMAMUX_REQ_TIM15_COM 0x00000051U /*!< DMAMUX TIM15 COM request */
-#define LL_DMAMUX_REQ_TIM16_CH1 0x00000052U /*!< DMAMUX TIM16 CH1 request */
-#define LL_DMAMUX_REQ_TIM16_UP 0x00000053U /*!< DMAMUX TIM16 UP request */
-#define LL_DMAMUX_REQ_TIM17_CH1 0x00000054U /*!< DMAMUX TIM17 CH1 request */
-#define LL_DMAMUX_REQ_TIM17_UP 0x00000055U /*!< DMAMUX TIM17 UP request */
-#define LL_DMAMUX_REQ_TIM20_CH1 0x00000056U /*!< DMAMUX TIM20 CH1 request */
-#define LL_DMAMUX_REQ_TIM20_CH2 0x00000057U /*!< DMAMUX TIM20 CH2 request */
-#define LL_DMAMUX_REQ_TIM20_CH3 0x00000058U /*!< DMAMUX TIM20 CH3 request */
-#define LL_DMAMUX_REQ_TIM20_CH4 0x00000059U /*!< DMAMUX TIM20 CH4 request */
-#define LL_DMAMUX_REQ_TIM20_UP 0x0000005AU /*!< DMAMUX TIM20 UP request */
-#define LL_DMAMUX_REQ_AES_IN 0x0000005BU /*!< DMAMUX AES_IN request */
-#define LL_DMAMUX_REQ_AES_OUT 0x0000005CU /*!< DMAMUX AES_OUT request */
-#define LL_DMAMUX_REQ_TIM20_TRIG 0x0000005DU /*!< DMAMUX TIM20 TRIG request */
-#define LL_DMAMUX_REQ_TIM20_COM 0x0000005EU /*!< DMAMUX TIM20 COM request */
-#define LL_DMAMUX_REQ_HRTIM1_M 0x0000005FU /*!< DMAMUX HRTIM M request */
-#define LL_DMAMUX_REQ_HRTIM1_A 0x00000060U /*!< DMAMUX HRTIM A request */
-#define LL_DMAMUX_REQ_HRTIM1_B 0x00000061U /*!< DMAMUX HRTIM B request */
-#define LL_DMAMUX_REQ_HRTIM1_C 0x00000062U /*!< DMAMUX HRTIM C request */
-#define LL_DMAMUX_REQ_HRTIM1_D 0x00000063U /*!< DMAMUX HRTIM D request */
-#define LL_DMAMUX_REQ_HRTIM1_E 0x00000064U /*!< DMAMUX HRTIM E request */
-#define LL_DMAMUX_REQ_HRTIM1_F 0x00000065U /*!< DMAMUX HRTIM F request */
-#define LL_DMAMUX_REQ_DAC3_CH1 0x00000066U /*!< DMAMUX DAC3 CH1 request */
-#define LL_DMAMUX_REQ_DAC3_CH2 0x00000067U /*!< DMAMUX DAC3 CH2 request */
-#define LL_DMAMUX_REQ_DAC4_CH1 0x00000068U /*!< DMAMUX DAC4 CH1 request */
-#define LL_DMAMUX_REQ_DAC4_CH2 0x00000069U /*!< DMAMUX DAC4 CH2 request */
-#define LL_DMAMUX_REQ_SPI4_RX 0x0000006AU /*!< DMAMUX SPI4 RX request */
-#define LL_DMAMUX_REQ_SPI4_TX 0x0000006BU /*!< DMAMUX SPI4 TX request */
-#define LL_DMAMUX_REQ_SAI1_A 0x0000006CU /*!< DMAMUX SAI1 A request */
-#define LL_DMAMUX_REQ_SAI1_B 0x0000006DU /*!< DMAMUX SAI1 B request */
-#define LL_DMAMUX_REQ_FMAC_READ 0x0000006EU /*!< DMAMUX FMAC READ request */
-#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU /*!< DMAMUX FMAC WRITE request */
-#define LL_DMAMUX_REQ_CORDIC_READ \
- 0x00000070U /*!< DMAMUX CORDIC READ request \
- */
-#define LL_DMAMUX_REQ_CORDIC_WRITE \
- 0x00000071U /*!< DMAMUX CORDIC WRITE request*/
-#define LL_DMAMUX_REQ_UCPD1_RX 0x00000072U /*!< DMAMUX USBPD1_RX request */
-#define LL_DMAMUX_REQ_UCPD1_TX 0x00000073U /*!< DMAMUX USBPD1_TX request */
-
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
- * @{
- */
-#define LL_DMAMUX_CHANNEL_0 \
- 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
-#define LL_DMAMUX_CHANNEL_1 \
- 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
-#define LL_DMAMUX_CHANNEL_2 \
- 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
-#define LL_DMAMUX_CHANNEL_3 \
- 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
-#define LL_DMAMUX_CHANNEL_4 \
- 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
-#define LL_DMAMUX_CHANNEL_5 \
- 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
-#define LL_DMAMUX_CHANNEL_6 \
- 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
-#define LL_DMAMUX_CHANNEL_7 \
- 0x00000007U /*!< DMAMUX Channel 7 connected to DMA1 Channel 8 */
-#define LL_DMAMUX_CHANNEL_8 \
- 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 1 */
-#define LL_DMAMUX_CHANNEL_9 \
- 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 2 */
-#define LL_DMAMUX_CHANNEL_10 \
- 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 3 */
-#define LL_DMAMUX_CHANNEL_11 \
- 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */
-#define LL_DMAMUX_CHANNEL_12 \
- 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */
-#define LL_DMAMUX_CHANNEL_13 \
- 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */
-#define LL_DMAMUX_CHANNEL_14 \
- 0x0000000EU /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */
-#define LL_DMAMUX_CHANNEL_15 \
- 0x0000000FU /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
- * @{
- */
-#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
-#define LL_DMAMUX_SYNC_POL_RISING \
- DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
-#define LL_DMAMUX_SYNC_POL_FALLING \
- DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
-#define LL_DMAMUX_SYNC_POL_RISING_FALLING \
- (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on \
- rising and falling edge */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
- * @{
- */
-#define LL_DMAMUX_SYNC_EXTI_LINE0 \
- 0x00000000U /*!< Synchronization signal from EXTI Line0 */
-#define LL_DMAMUX_SYNC_EXTI_LINE1 \
- DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
-#define LL_DMAMUX_SYNC_EXTI_LINE2 \
- DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
-#define LL_DMAMUX_SYNC_EXTI_LINE3 \
- (DMAMUX_CxCR_SYNC_ID_1 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
-#define LL_DMAMUX_SYNC_EXTI_LINE4 \
- DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
-#define LL_DMAMUX_SYNC_EXTI_LINE5 \
- (DMAMUX_CxCR_SYNC_ID_2 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
-#define LL_DMAMUX_SYNC_EXTI_LINE6 \
- (DMAMUX_CxCR_SYNC_ID_2 | \
- DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
-#define LL_DMAMUX_SYNC_EXTI_LINE7 \
- (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
-#define LL_DMAMUX_SYNC_EXTI_LINE8 \
- DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
-#define LL_DMAMUX_SYNC_EXTI_LINE9 \
- (DMAMUX_CxCR_SYNC_ID_3 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
-#define LL_DMAMUX_SYNC_EXTI_LINE10 \
- (DMAMUX_CxCR_SYNC_ID_3 | \
- DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
-#define LL_DMAMUX_SYNC_EXTI_LINE11 \
- (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
-#define LL_DMAMUX_SYNC_EXTI_LINE12 \
- (DMAMUX_CxCR_SYNC_ID_3 | \
- DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
-#define LL_DMAMUX_SYNC_EXTI_LINE13 \
- (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */
-#define LL_DMAMUX_SYNC_EXTI_LINE14 \
- (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | \
- DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */
-#define LL_DMAMUX_SYNC_EXTI_LINE15 \
- (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
-#define LL_DMAMUX_SYNC_DMAMUX_CH0 \
- DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event \
- */
-#define LL_DMAMUX_SYNC_DMAMUX_CH1 \
- (DMAMUX_CxCR_SYNC_ID_4 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 \
- Event */
-#define LL_DMAMUX_SYNC_DMAMUX_CH2 \
- (DMAMUX_CxCR_SYNC_ID_4 | \
- DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 \
- Event */
-#define LL_DMAMUX_SYNC_DMAMUX_CH3 \
- (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | \
- DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 \
- Event */
-#define LL_DMAMUX_SYNC_LPTIM1_OUT \
- (DMAMUX_CxCR_SYNC_ID_4 | \
- DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
- * @{
- */
-#define LL_DMAMUX_REQ_GEN_0 0x00000000U
-#define LL_DMAMUX_REQ_GEN_1 0x00000001U
-#define LL_DMAMUX_REQ_GEN_2 0x00000002U
-#define LL_DMAMUX_REQ_GEN_3 0x00000003U
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal
- * Generation Polarity
- * @{
- */
-#define LL_DMAMUX_REQ_GEN_NO_EVENT \
- 0x00000000U /*!< No external DMA request generation */
-#define LL_DMAMUX_REQ_GEN_POL_RISING \
- DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising \
- edge */
-#define LL_DMAMUX_REQ_GEN_POL_FALLING \
- DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling \
- edge */
-#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING \
- (DMAMUX_RGxCR_GPOL_0 | \
- DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and \
- falling edge */
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
- * @{
- */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 \
- 0x00000000U /*!< Request signal generation from EXTI Line0 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 \
- DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 \
- DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 \
- (DMAMUX_RGxCR_SIG_ID_1 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 \
- DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 \
- (DMAMUX_RGxCR_SIG_ID_2 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 \
- (DMAMUX_RGxCR_SIG_ID_2 | \
- DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 \
- (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 \
- DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 \
- (DMAMUX_RGxCR_SIG_ID_3 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 \
- (DMAMUX_RGxCR_SIG_ID_3 | \
- DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 \
- (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 \
- (DMAMUX_RGxCR_SIG_ID_3 | \
- DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 \
- (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 \
- (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | \
- DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 \
- (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 \
- DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 \
- Event */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 \
- (DMAMUX_RGxCR_SIG_ID_4 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 \
- Event */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 \
- (DMAMUX_RGxCR_SIG_ID_4 | \
- DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 \
- Event */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 \
- (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | \
- DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 \
- Event */
-#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT \
- (DMAMUX_RGxCR_SIG_ID_4 | \
- DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
- * @{
- */
-/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in DMAMUX register
- * @param __INSTANCE__ DMAMUX Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DMAMUX register
- * @param __INSTANCE__ DMAMUX Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
- * @{
- */
-
-/** @defgroup DMAMUX_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Set DMAMUX request ID for DMAMUX Channel x.
- * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
- * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
- * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @param Request This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_MEM2MEM
- * @arg @ref LL_DMAMUX_REQ_GENERATOR0
- * @arg @ref LL_DMAMUX_REQ_GENERATOR1
- * @arg @ref LL_DMAMUX_REQ_GENERATOR2
- * @arg @ref LL_DMAMUX_REQ_GENERATOR3
- * @arg @ref LL_DMAMUX_REQ_ADC1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM6_UP
- * @arg @ref LL_DMAMUX_REQ_TIM7_UP
- * @arg @ref LL_DMAMUX_REQ_SPI1_RX
- * @arg @ref LL_DMAMUX_REQ_SPI1_TX
- * @arg @ref LL_DMAMUX_REQ_SPI2_RX
- * @arg @ref LL_DMAMUX_REQ_SPI2_TX
- * @arg @ref LL_DMAMUX_REQ_SPI3_RX
- * @arg @ref LL_DMAMUX_REQ_SPI3_TX
- * @arg @ref LL_DMAMUX_REQ_I2C1_RX
- * @arg @ref LL_DMAMUX_REQ_I2C1_TX
- * @arg @ref LL_DMAMUX_REQ_I2C2_RX
- * @arg @ref LL_DMAMUX_REQ_I2C2_TX
- * @arg @ref LL_DMAMUX_REQ_I2C3_RX
- * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_TX
- * @arg @ref LL_DMAMUX_REQ_USART1_RX
- * @arg @ref LL_DMAMUX_REQ_USART1_TX
- * @arg @ref LL_DMAMUX_REQ_USART2_RX
- * @arg @ref LL_DMAMUX_REQ_USART2_TX
- * @arg @ref LL_DMAMUX_REQ_USART3_RX
- * @arg @ref LL_DMAMUX_REQ_USART3_TX
- * @arg @ref LL_DMAMUX_REQ_UART4_RX
- * @arg @ref LL_DMAMUX_REQ_UART4_TX
- * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
- * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
- * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
- * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
- * @arg @ref LL_DMAMUX_REQ_ADC2
- * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
- * @arg @ref LL_DMAMUX_REQ_QSPI (*)
- * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM1_UP
- * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM1_COM
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM8_UP
- * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM8_COM
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM2_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM3_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM4_UP
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM15_UP
- * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM15_COM
- * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM16_UP
- * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM17_UP
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
- * @arg @ref LL_DMAMUX_REQ_AES_IN
- * @arg @ref LL_DMAMUX_REQ_AES_OUT
- * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
- * @arg @ref LL_DMAMUX_REQ_SAI1_A
- * @arg @ref LL_DMAMUX_REQ_SAI1_B
- * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
- * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
- * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
- * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
- * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
- * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
- * (*) Not on all G4 devices
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel,
- uint32_t Request) {
- (void)(DMAMUXx);
- MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
-}
-
-/**
- * @brief Get DMAMUX request ID for DMAMUX Channel x.
- * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
- * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
- * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * (*) Not on all G4 devices
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_MEM2MEM
- * @arg @ref LL_DMAMUX_REQ_GENERATOR0
- * @arg @ref LL_DMAMUX_REQ_GENERATOR0
- * @arg @ref LL_DMAMUX_REQ_GENERATOR1
- * @arg @ref LL_DMAMUX_REQ_GENERATOR2
- * @arg @ref LL_DMAMUX_REQ_GENERATOR3
- * @arg @ref LL_DMAMUX_REQ_ADC1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM6_UP
- * @arg @ref LL_DMAMUX_REQ_TIM7_UP
- * @arg @ref LL_DMAMUX_REQ_SPI1_RX
- * @arg @ref LL_DMAMUX_REQ_SPI1_TX
- * @arg @ref LL_DMAMUX_REQ_SPI2_RX
- * @arg @ref LL_DMAMUX_REQ_SPI2_TX
- * @arg @ref LL_DMAMUX_REQ_SPI3_RX
- * @arg @ref LL_DMAMUX_REQ_SPI3_TX
- * @arg @ref LL_DMAMUX_REQ_I2C1_RX
- * @arg @ref LL_DMAMUX_REQ_I2C1_TX
- * @arg @ref LL_DMAMUX_REQ_I2C2_RX
- * @arg @ref LL_DMAMUX_REQ_I2C2_TX
- * @arg @ref LL_DMAMUX_REQ_I2C3_RX
- * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_I2C4_TX
- * @arg @ref LL_DMAMUX_REQ_USART1_RX
- * @arg @ref LL_DMAMUX_REQ_USART1_TX
- * @arg @ref LL_DMAMUX_REQ_USART2_RX
- * @arg @ref LL_DMAMUX_REQ_USART2_TX
- * @arg @ref LL_DMAMUX_REQ_USART3_RX
- * @arg @ref LL_DMAMUX_REQ_USART3_TX
- * @arg @ref LL_DMAMUX_REQ_UART4_RX
- * @arg @ref LL_DMAMUX_REQ_UART4_TX
- * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
- * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
- * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
- * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
- * @arg @ref LL_DMAMUX_REQ_ADC2
- * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
- * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
- * @arg @ref LL_DMAMUX_REQ_QSPI (*)
- * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM1_UP
- * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM1_COM
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM8_UP
- * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM8_COM
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM2_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM3_UP
- * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
- * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
- * @arg @ref LL_DMAMUX_REQ_TIM4_UP
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
- * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM15_UP
- * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
- * @arg @ref LL_DMAMUX_REQ_TIM15_COM
- * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM16_UP
- * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
- * @arg @ref LL_DMAMUX_REQ_TIM17_UP
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
- * @arg @ref LL_DMAMUX_REQ_AES_IN
- * @arg @ref LL_DMAMUX_REQ_AES_OUT
- * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
- * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
- * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
- * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
- * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
- * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
- * @arg @ref LL_DMAMUX_REQ_SAI1_A
- * @arg @ref LL_DMAMUX_REQ_SAI1_B
- * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
- * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
- * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
- * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
- * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
- * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
- * (*) Not on all G4 devices
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel) {
- (void)(DMAMUXx);
- return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR,
- DMAMUX_CxCR_DMAREQ_ID));
-}
-
-/**
- * @brief Set the number of DMA request that will be autorized after a
- * synchronization event and/or the number of DMA request needed to generate an
- * event.
- * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @param RequestNb This parameter must be a value between Min_Data = 1 and
- * Max_Data = 32.
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel,
- uint32_t RequestNb) {
- (void)(DMAMUXx);
- MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ,
- ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
-}
-
-/**
- * @brief Get the number of DMA request that will be autorized after a
- * synchronization event and/or the number of DMA request needed to generate an
- * event.
- * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval Between Min_Data = 1 and Max_Data = 32
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR,
- DMAMUX_CxCR_NBREQ)) >>
- DMAMUX_CxCR_NBREQ_Pos) +
- 1U);
-}
-
-/**
- * @brief Set the polarity of the signal on which the DMA request is
- * synchronized.
- * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
- * @arg @ref LL_DMAMUX_SYNC_POL_RISING
- * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
- * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel,
- uint32_t Polarity) {
- (void)(DMAMUXx);
- MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
-}
-
-/**
- * @brief Get the polarity of the signal on which the DMA request is
- * synchronized.
- * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
- * @arg @ref LL_DMAMUX_SYNC_POL_RISING
- * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
- * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- return (
- uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
-}
-
-/**
- * @brief Enable the Event Generation on DMAMUX channel x.
- * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
-}
-
-/**
- * @brief Disable the Event Generation on DMAMUX channel x.
- * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
-}
-
-/**
- * @brief Check if the Event Generation on DMAMUX channel x is enabled or
- * disabled.
- * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) ==
- (DMAMUX_CxCR_EGE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable the synchronization mode.
- * @rmtoll CxCR SE LL_DMAMUX_EnableSync
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel) {
- (void)(DMAMUXx);
- SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
-}
-
-/**
- * @brief Disable the synchronization mode.
- * @rmtoll CxCR SE LL_DMAMUX_DisableSync
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel) {
- (void)(DMAMUXx);
- CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
-}
-
-/**
- * @brief Check if the synchronization mode is enabled or disabled.
- * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) ==
- (DMAMUX_CxCR_SE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
- * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @param SyncID This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
- * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel, uint32_t SyncID) {
- (void)(DMAMUXx);
- MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
-}
-
-/**
- * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
- * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
- * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
- * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
- * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel) {
- (void)(DMAMUXx);
- return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR,
- DMAMUX_CxCR_SYNC_ID));
-}
-
-/**
- * @brief Enable the Request Generator.
- * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t RequestGenChannel) {
- (void)(DMAMUXx);
- SET_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GE);
-}
-
-/**
- * @brief Disable the Request Generator.
- * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
- (void)(DMAMUXx);
- CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GE);
-}
-
-/**
- * @brief Check if the Request Generator is enabled or disabled.
- * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
- (void)(DMAMUXx);
- return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set the polarity of the signal on which the DMA request is generated.
- * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
- * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
- * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
- * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
- uint32_t Polarity) {
- UNUSED(DMAMUXx);
- MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GPOL, Polarity);
-}
-
-/**
- * @brief Get the polarity of the signal on which the DMA request is generated.
- * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
- * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
- * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
- * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
- UNUSED(DMAMUXx);
- return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GPOL));
-}
-
-/**
- * @brief Set the number of DMA request that will be autorized after a
- * generation event.
- * @note This field can only be written when Generator is disabled.
- * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @param RequestNb This parameter must be a value between Min_Data = 1 and
- * Max_Data = 32.
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t RequestGenChannel,
- uint32_t RequestNb) {
- UNUSED(DMAMUXx);
- MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
-}
-
-/**
- * @brief Get the number of DMA request that will be autorized after a
- * generation event.
- * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval Between Min_Data = 1 and Max_Data = 32
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_GNBREQ) >>
- DMAMUX_RGxCR_GNBREQ_Pos) +
- 1U);
-}
-
-/**
- * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation
- * Trigger Event Channel x.
- * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @param RequestSignalID This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
- * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
- uint32_t RequestSignalID) {
- UNUSED(DMAMUXx);
- MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_SIG_ID, RequestSignalID);
-}
-
-/**
- * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
- * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
- * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
- * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
- * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
- UNUSED(DMAMUXx);
- return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_SIG_ID));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 0.
- * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) ==
- (DMAMUX_CSR_SOF0))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 1.
- * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) ==
- (DMAMUX_CSR_SOF1))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 2.
- * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) ==
- (DMAMUX_CSR_SOF2))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 3.
- * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) ==
- (DMAMUX_CSR_SOF3))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 4.
- * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) ==
- (DMAMUX_CSR_SOF4))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 5.
- * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) ==
- (DMAMUX_CSR_SOF5))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 6.
- * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) ==
- (DMAMUX_CSR_SOF6))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 7.
- * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) ==
- (DMAMUX_CSR_SOF7))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 8.
- * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) ==
- (DMAMUX_CSR_SOF8))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 9.
- * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) ==
- (DMAMUX_CSR_SOF9))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 10.
- * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) ==
- (DMAMUX_CSR_SOF10))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 11.
- * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) ==
- (DMAMUX_CSR_SOF11))
- ? 1UL
- : 0UL);
-}
-
-#if defined(DMAMUX_CSR_SOF12)
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 12.
- * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) ==
- (DMAMUX_CSR_SOF12))
- ? 1UL
- : 0UL);
-}
-#endif /* DMAMUX_CSR_SOF12 */
-
-#if defined(DMAMUX_CSR_SOF13)
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 13.
- * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) ==
- (DMAMUX_CSR_SOF13))
- ? 1UL
- : 0UL);
-}
-#endif /* DMAMUX_CSR_SOF13 */
-
-#if defined(DMAMUX_CSR_SOF14)
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 14.
- * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO14
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF14) ==
- (DMAMUX_CSR_SOF14))
- ? 1UL
- : 0UL);
-}
-#endif /* DMAMUX_CSR_SOF14 */
-
-#if defined(DMAMUX_CSR_SOF15)
-/**
- * @brief Get Synchronization Event Overrun Flag Channel 15.
- * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO15
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF15) ==
- (DMAMUX_CSR_SOF15))
- ? 1UL
- : 0UL);
-}
-#endif /* DMAMUX_CSR_SOF15 */
-
-/**
- * @brief Get Request Generator 0 Trigger Event Overrun Flag.
- * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) ==
- (DMAMUX_RGSR_OF0))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Request Generator 1 Trigger Event Overrun Flag.
- * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) ==
- (DMAMUX_RGSR_OF1))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Request Generator 2 Trigger Event Overrun Flag.
- * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) ==
- (DMAMUX_RGSR_OF2))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get Request Generator 3 Trigger Event Overrun Flag.
- * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) ==
- (DMAMUX_RGSR_OF3))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 0.
- * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 1.
- * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 2.
- * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 3.
- * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 4.
- * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 5.
- * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 6.
- * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 7.
- * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 8.
- * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 9.
- * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 10.
- * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
-}
-
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 11.
- * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
-}
-
-#if defined(DMAMUX_CFR_CSOF12)
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 12.
- * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
-}
-#endif /* DMAMUX_CFR_CSOF12 */
-
-#if defined(DMAMUX_CFR_CSOF13)
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 13.
- * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
-}
-#endif /* DMAMUX_CFR_CSOF13 */
-
-#if defined(DMAMUX_CFR_CSOF14)
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 14.
- * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF14);
-}
-#endif /* DMAMUX_CFR_CSOF14 */
-
-#if defined(DMAMUX_CFR_CSOF15)
-/**
- * @brief Clear Synchronization Event Overrun Flag Channel 15.
- * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF15);
-}
-#endif /* DMAMUX_CFR_CSOF15 */
-
-/**
- * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
- * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
-}
-
-/**
- * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
- * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
-}
-
-/**
- * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
- * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
-}
-
-/**
- * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
- * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
- * @param DMAMUXx DMAMUXx DMAMUXx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
- UNUSED(DMAMUXx);
- SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel
- * x.
- * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel) {
- (void)(DMAMUXx);
- SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
-}
-
-/**
- * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel
- * x.
- * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t Channel) {
- (void)(DMAMUXx);
- CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
-}
-
-/**
- * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX
- * channel x is enabled or disabled.
- * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
- * @param DMAMUXx DMAMUXx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_CHANNEL_0
- * @arg @ref LL_DMAMUX_CHANNEL_1
- * @arg @ref LL_DMAMUX_CHANNEL_2
- * @arg @ref LL_DMAMUX_CHANNEL_3
- * @arg @ref LL_DMAMUX_CHANNEL_4
- * @arg @ref LL_DMAMUX_CHANNEL_5
- * @arg @ref LL_DMAMUX_CHANNEL_6
- * @arg @ref LL_DMAMUX_CHANNEL_7
- * @arg @ref LL_DMAMUX_CHANNEL_8
- * @arg @ref LL_DMAMUX_CHANNEL_9
- * @arg @ref LL_DMAMUX_CHANNEL_10
- * @arg @ref LL_DMAMUX_CHANNEL_11
- * @arg @ref LL_DMAMUX_CHANNEL_12
- * @arg @ref LL_DMAMUX_CHANNEL_13
- * @arg @ref LL_DMAMUX_CHANNEL_14
- * @arg @ref LL_DMAMUX_CHANNEL_15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
- (void)(DMAMUXx);
- return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) ==
- (DMAMUX_CxCR_SOIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable the Request Generation Trigger Event Overrun Interrupt on
- * DMAMUX channel x.
- * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t RequestGenChannel) {
- UNUSED(DMAMUXx);
- SET_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_OIE);
-}
-
-/**
- * @brief Disable the Request Generation Trigger Event Overrun Interrupt on
- * DMAMUX channel x.
- * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval None
- */
-__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx,
- uint32_t RequestGenChannel) {
- UNUSED(DMAMUXx);
- CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_OIE);
-}
-
-/**
- * @brief Check if the Request Generation Trigger Event Overrun Interrupt on
- * DMAMUX channel x is enabled or disabled.
- * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
- * @param DMAMUXx DMAMUXx Instance
- * @param RequestGenChannel This parameter can be one of the following values:
- * @arg @ref LL_DMAMUX_REQ_GEN_0
- * @arg @ref LL_DMAMUX_REQ_GEN_1
- * @arg @ref LL_DMAMUX_REQ_GEN_2
- * @arg @ref LL_DMAMUX_REQ_GEN_3
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(
- DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
- UNUSED(DMAMUXx);
- return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
- uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
- (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
- ->RGCR,
- DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMAMUX1 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_DMAMUX_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_dmamux.h
+ * @author MCD Application Team
+ * @brief Header file of DMAMUX LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_DMAMUX_H
+#define __STM32G4xx_LL_DMAMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(DMAMUX1)
+
+/** @defgroup DMAMUX_LL DMAMUX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
+ * @{
+ */
+/* Define used to get DMAMUX CCR register size */
+#define DMAMUX_CCR_SIZE 0x00000004U
+
+/* Define used to get DMAMUX RGCR register size */
+#define DMAMUX_RGCR_SIZE 0x00000004U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Macros DMAMUX Private Macros
+ * @{
+ */
+#define UNUSED(X) (void)X
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
+ * @{
+ */
+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
+ * @{
+ */
+#define LL_DMAMUX_CFR_CSOF0 \
+ DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
+#define LL_DMAMUX_CFR_CSOF1 \
+ DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
+#define LL_DMAMUX_CFR_CSOF2 \
+ DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
+#define LL_DMAMUX_CFR_CSOF3 \
+ DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
+#define LL_DMAMUX_CFR_CSOF4 \
+ DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
+#define LL_DMAMUX_CFR_CSOF5 \
+ DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
+#define LL_DMAMUX_CFR_CSOF6 \
+ DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
+#define LL_DMAMUX_CFR_CSOF7 \
+ DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
+#define LL_DMAMUX_CFR_CSOF8 \
+ DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
+#define LL_DMAMUX_CFR_CSOF9 \
+ DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
+#define LL_DMAMUX_CFR_CSOF10 \
+ DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
+#define LL_DMAMUX_CFR_CSOF11 \
+ DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
+#define LL_DMAMUX_CFR_CSOF12 \
+ DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
+#define LL_DMAMUX_CFR_CSOF13 \
+ DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
+#define LL_DMAMUX_CFR_CSOF14 \
+ DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
+#define LL_DMAMUX_CFR_CSOF15 \
+ DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
+#define LL_DMAMUX_RGCFR_RGCOF0 \
+ DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF1 \
+ DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF2 \
+ DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF3 \
+ DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
+ * @{
+ */
+#define LL_DMAMUX_CSR_SOF0 \
+ DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
+#define LL_DMAMUX_CSR_SOF1 \
+ DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
+#define LL_DMAMUX_CSR_SOF2 \
+ DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
+#define LL_DMAMUX_CSR_SOF3 \
+ DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
+#define LL_DMAMUX_CSR_SOF4 \
+ DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
+#define LL_DMAMUX_CSR_SOF5 \
+ DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
+#define LL_DMAMUX_CSR_SOF6 \
+ DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
+#define LL_DMAMUX_CSR_SOF7 \
+ DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
+#define LL_DMAMUX_CSR_SOF8 \
+ DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
+#define LL_DMAMUX_CSR_SOF9 \
+ DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
+#define LL_DMAMUX_CSR_SOF10 \
+ DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
+#define LL_DMAMUX_CSR_SOF11 \
+ DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
+#define LL_DMAMUX_CSR_SOF12 \
+ DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
+#define LL_DMAMUX_CSR_SOF13 \
+ DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
+#define LL_DMAMUX_CSR_SOF14 \
+ DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
+#define LL_DMAMUX_CSR_SOF15 \
+ DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
+#define LL_DMAMUX_RGSR_RGOF0 \
+ DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF1 \
+ DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF2 \
+ DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF3 \
+ DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and
+ * LL_DMAMUX_WriteReg functions
+ * @{
+ */
+#define LL_DMAMUX_CCR_SOIE \
+ DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
+#define LL_DMAMUX_RGCR_RGOIE \
+ DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
+ * @{
+ */
+#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< Memory to memory transfer */
+#define LL_DMAMUX_REQ_GENERATOR0 \
+ 0x00000001U /*!< DMAMUX request generator 0 \
+ */
+#define LL_DMAMUX_REQ_GENERATOR1 \
+ 0x00000002U /*!< DMAMUX request generator 1 \
+ */
+#define LL_DMAMUX_REQ_GENERATOR2 \
+ 0x00000003U /*!< DMAMUX request generator 2 \
+ */
+#define LL_DMAMUX_REQ_GENERATOR3 \
+ 0x00000004U /*!< DMAMUX request generator 3 \
+ */
+#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */
+#define LL_DMAMUX_REQ_DAC1_CH1 0x00000006U /*!< DMAMUX DAC1 CH1 request */
+#define LL_DMAMUX_REQ_DAC1_CH2 0x00000007U /*!< DMAMUX DAC1 CH2 request */
+#define LL_DMAMUX_REQ_TIM6_UP 0x00000008U /*!< DMAMUX TIM6 UP request */
+#define LL_DMAMUX_REQ_TIM7_UP 0x00000009U /*!< DMAMUX TIM7 UP request */
+#define LL_DMAMUX_REQ_SPI1_RX 0x0000000AU /*!< DMAMUX SPI1 RX request */
+#define LL_DMAMUX_REQ_SPI1_TX 0x0000000BU /*!< DMAMUX SPI1 TX request */
+#define LL_DMAMUX_REQ_SPI2_RX 0x0000000CU /*!< DMAMUX SPI2 RX request */
+#define LL_DMAMUX_REQ_SPI2_TX 0x0000000DU /*!< DMAMUX SPI2 TX request */
+#define LL_DMAMUX_REQ_SPI3_RX 0x0000000EU /*!< DMAMUX SPI3 RX request */
+#define LL_DMAMUX_REQ_SPI3_TX 0x0000000FU /*!< DMAMUX SPI3 TX request */
+#define LL_DMAMUX_REQ_I2C1_RX 0x00000010U /*!< DMAMUX I2C1 RX request */
+#define LL_DMAMUX_REQ_I2C1_TX 0x00000011U /*!< DMAMUX I2C1 TX request */
+#define LL_DMAMUX_REQ_I2C2_RX 0x00000012U /*!< DMAMUX I2C2 RX request */
+#define LL_DMAMUX_REQ_I2C2_TX 0x00000013U /*!< DMAMUX I2C2 TX request */
+#define LL_DMAMUX_REQ_I2C3_RX 0x00000014U /*!< DMAMUX I2C3 RX request */
+#define LL_DMAMUX_REQ_I2C3_TX 0x00000015U /*!< DMAMUX I2C3 TX request */
+#define LL_DMAMUX_REQ_I2C4_RX 0x00000016U /*!< DMAMUX I2C4 RX request */
+#define LL_DMAMUX_REQ_I2C4_TX 0x00000017U /*!< DMAMUX I2C4 TX request */
+#define LL_DMAMUX_REQ_USART1_RX 0x00000018U /*!< DMAMUX USART1 RX request */
+#define LL_DMAMUX_REQ_USART1_TX 0x00000019U /*!< DMAMUX USART1 TX request */
+#define LL_DMAMUX_REQ_USART2_RX 0x0000001AU /*!< DMAMUX USART2 RX request */
+#define LL_DMAMUX_REQ_USART2_TX 0x0000001BU /*!< DMAMUX USART2 TX request */
+#define LL_DMAMUX_REQ_USART3_RX 0x0000001CU /*!< DMAMUX USART3 RX request */
+#define LL_DMAMUX_REQ_USART3_TX 0x0000001DU /*!< DMAMUX USART3 TX request */
+#define LL_DMAMUX_REQ_UART4_RX 0x0000001EU /*!< DMAMUX UART4 RX request */
+#define LL_DMAMUX_REQ_UART4_TX 0x0000001FU /*!< DMAMUX UART4 TX request */
+#define LL_DMAMUX_REQ_UART5_RX 0x00000020U /*!< DMAMUX UART5 RX request */
+#define LL_DMAMUX_REQ_UART5_TX 0x00000021U /*!< DMAMUX UART5 TX request */
+#define LL_DMAMUX_REQ_LPUART1_RX 0x00000022U /*!< DMAMUX LPUART1 RX request */
+#define LL_DMAMUX_REQ_LPUART1_TX 0x00000023U /*!< DMAMUX LPUART1 TX request */
+#define LL_DMAMUX_REQ_ADC2 0x00000024U /*!< DMAMUX ADC2 request */
+#define LL_DMAMUX_REQ_ADC3 0x00000025U /*!< DMAMUX ADC3 request */
+#define LL_DMAMUX_REQ_ADC4 0x00000026U /*!< DMAMUX ADC4 request */
+#define LL_DMAMUX_REQ_ADC5 0x00000027U /*!< DMAMUX ADC5 request */
+#define LL_DMAMUX_REQ_QSPI 0x00000028U /*!< DMAMUX QSPI request */
+#define LL_DMAMUX_REQ_DAC2_CH1 0x00000029U /*!< DMAMUX DAC2 CH1 request */
+#define LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU /*!< DMAMUX TIM1 CH1 request */
+#define LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU /*!< DMAMUX TIM1 CH2 request */
+#define LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU /*!< DMAMUX TIM1 CH3 request */
+#define LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU /*!< DMAMUX TIM1 CH4 request */
+#define LL_DMAMUX_REQ_TIM1_UP 0x0000002EU /*!< DMAMUX TIM1 UP request */
+#define LL_DMAMUX_REQ_TIM1_TRIG 0x0000002FU /*!< DMAMUX TIM1 TRIG request */
+#define LL_DMAMUX_REQ_TIM1_COM 0x00000030U /*!< DMAMUX TIM1 COM request */
+#define LL_DMAMUX_REQ_TIM8_CH1 0x00000031U /*!< DMAMUX TIM8 CH1 request */
+#define LL_DMAMUX_REQ_TIM8_CH2 0x00000032U /*!< DMAMUX TIM8 CH2 request */
+#define LL_DMAMUX_REQ_TIM8_CH3 0x00000033U /*!< DMAMUX TIM8 CH3 request */
+#define LL_DMAMUX_REQ_TIM8_CH4 0x00000034U /*!< DMAMUX TIM8 CH4 request */
+#define LL_DMAMUX_REQ_TIM8_UP 0x00000035U /*!< DMAMUX TIM8 UP request */
+#define LL_DMAMUX_REQ_TIM8_TRIG 0x00000036U /*!< DMAMUX TIM8 TRIG request */
+#define LL_DMAMUX_REQ_TIM8_COM 0x00000037U /*!< DMAMUX TIM8 COM request */
+#define LL_DMAMUX_REQ_TIM2_CH1 0x00000038U /*!< DMAMUX TIM2 CH1 request */
+#define LL_DMAMUX_REQ_TIM2_CH2 0x00000039U /*!< DMAMUX TIM2 CH2 request */
+#define LL_DMAMUX_REQ_TIM2_CH3 0x0000003AU /*!< DMAMUX TIM2 CH3 request */
+#define LL_DMAMUX_REQ_TIM2_CH4 0x0000003BU /*!< DMAMUX TIM2 CH4 request */
+#define LL_DMAMUX_REQ_TIM2_UP 0x0000003CU /*!< DMAMUX TIM2 UP request */
+#define LL_DMAMUX_REQ_TIM3_CH1 0x0000003DU /*!< DMAMUX TIM3 CH1 request */
+#define LL_DMAMUX_REQ_TIM3_CH2 0x0000003EU /*!< DMAMUX TIM3 CH2 request */
+#define LL_DMAMUX_REQ_TIM3_CH3 0x0000003FU /*!< DMAMUX TIM3 CH3 request */
+#define LL_DMAMUX_REQ_TIM3_CH4 0x00000040U /*!< DMAMUX TIM3 CH4 request */
+#define LL_DMAMUX_REQ_TIM3_UP 0x00000041U /*!< DMAMUX TIM3 UP request */
+#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000042U /*!< DMAMUX TIM3 TRIG request */
+#define LL_DMAMUX_REQ_TIM4_CH1 0x00000043U /*!< DMAMUX TIM4 CH1 request */
+#define LL_DMAMUX_REQ_TIM4_CH2 0x00000044U /*!< DMAMUX TIM4 CH2 request */
+#define LL_DMAMUX_REQ_TIM4_CH3 0x00000045U /*!< DMAMUX TIM4 CH3 request */
+#define LL_DMAMUX_REQ_TIM4_CH4 0x00000046U /*!< DMAMUX TIM4 CH4 request */
+#define LL_DMAMUX_REQ_TIM4_UP 0x00000047U /*!< DMAMUX TIM4 UP request */
+#define LL_DMAMUX_REQ_TIM5_CH1 0x00000048U /*!< DMAMUX TIM5 CH1 request */
+#define LL_DMAMUX_REQ_TIM5_CH2 0x00000049U /*!< DMAMUX TIM5 CH2 request */
+#define LL_DMAMUX_REQ_TIM5_CH3 0x0000004AU /*!< DMAMUX TIM5 CH3 request */
+#define LL_DMAMUX_REQ_TIM5_CH4 0x0000004BU /*!< DMAMUX TIM5 CH4 request */
+#define LL_DMAMUX_REQ_TIM5_UP 0x0000004CU /*!< DMAMUX TIM5 UP request */
+#define LL_DMAMUX_REQ_TIM5_TRIG 0x0000004DU /*!< DMAMUX TIM5 TRIG request */
+#define LL_DMAMUX_REQ_TIM15_CH1 0x0000004EU /*!< DMAMUX TIM15 CH1 request */
+#define LL_DMAMUX_REQ_TIM15_UP 0x0000004FU /*!< DMAMUX TIM15 UP request */
+#define LL_DMAMUX_REQ_TIM15_TRIG 0x00000050U /*!< DMAMUX TIM15 TRIG request */
+#define LL_DMAMUX_REQ_TIM15_COM 0x00000051U /*!< DMAMUX TIM15 COM request */
+#define LL_DMAMUX_REQ_TIM16_CH1 0x00000052U /*!< DMAMUX TIM16 CH1 request */
+#define LL_DMAMUX_REQ_TIM16_UP 0x00000053U /*!< DMAMUX TIM16 UP request */
+#define LL_DMAMUX_REQ_TIM17_CH1 0x00000054U /*!< DMAMUX TIM17 CH1 request */
+#define LL_DMAMUX_REQ_TIM17_UP 0x00000055U /*!< DMAMUX TIM17 UP request */
+#define LL_DMAMUX_REQ_TIM20_CH1 0x00000056U /*!< DMAMUX TIM20 CH1 request */
+#define LL_DMAMUX_REQ_TIM20_CH2 0x00000057U /*!< DMAMUX TIM20 CH2 request */
+#define LL_DMAMUX_REQ_TIM20_CH3 0x00000058U /*!< DMAMUX TIM20 CH3 request */
+#define LL_DMAMUX_REQ_TIM20_CH4 0x00000059U /*!< DMAMUX TIM20 CH4 request */
+#define LL_DMAMUX_REQ_TIM20_UP 0x0000005AU /*!< DMAMUX TIM20 UP request */
+#define LL_DMAMUX_REQ_AES_IN 0x0000005BU /*!< DMAMUX AES_IN request */
+#define LL_DMAMUX_REQ_AES_OUT 0x0000005CU /*!< DMAMUX AES_OUT request */
+#define LL_DMAMUX_REQ_TIM20_TRIG 0x0000005DU /*!< DMAMUX TIM20 TRIG request */
+#define LL_DMAMUX_REQ_TIM20_COM 0x0000005EU /*!< DMAMUX TIM20 COM request */
+#define LL_DMAMUX_REQ_HRTIM1_M 0x0000005FU /*!< DMAMUX HRTIM M request */
+#define LL_DMAMUX_REQ_HRTIM1_A 0x00000060U /*!< DMAMUX HRTIM A request */
+#define LL_DMAMUX_REQ_HRTIM1_B 0x00000061U /*!< DMAMUX HRTIM B request */
+#define LL_DMAMUX_REQ_HRTIM1_C 0x00000062U /*!< DMAMUX HRTIM C request */
+#define LL_DMAMUX_REQ_HRTIM1_D 0x00000063U /*!< DMAMUX HRTIM D request */
+#define LL_DMAMUX_REQ_HRTIM1_E 0x00000064U /*!< DMAMUX HRTIM E request */
+#define LL_DMAMUX_REQ_HRTIM1_F 0x00000065U /*!< DMAMUX HRTIM F request */
+#define LL_DMAMUX_REQ_DAC3_CH1 0x00000066U /*!< DMAMUX DAC3 CH1 request */
+#define LL_DMAMUX_REQ_DAC3_CH2 0x00000067U /*!< DMAMUX DAC3 CH2 request */
+#define LL_DMAMUX_REQ_DAC4_CH1 0x00000068U /*!< DMAMUX DAC4 CH1 request */
+#define LL_DMAMUX_REQ_DAC4_CH2 0x00000069U /*!< DMAMUX DAC4 CH2 request */
+#define LL_DMAMUX_REQ_SPI4_RX 0x0000006AU /*!< DMAMUX SPI4 RX request */
+#define LL_DMAMUX_REQ_SPI4_TX 0x0000006BU /*!< DMAMUX SPI4 TX request */
+#define LL_DMAMUX_REQ_SAI1_A 0x0000006CU /*!< DMAMUX SAI1 A request */
+#define LL_DMAMUX_REQ_SAI1_B 0x0000006DU /*!< DMAMUX SAI1 B request */
+#define LL_DMAMUX_REQ_FMAC_READ 0x0000006EU /*!< DMAMUX FMAC READ request */
+#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU /*!< DMAMUX FMAC WRITE request */
+#define LL_DMAMUX_REQ_CORDIC_READ \
+ 0x00000070U /*!< DMAMUX CORDIC READ request \
+ */
+#define LL_DMAMUX_REQ_CORDIC_WRITE \
+ 0x00000071U /*!< DMAMUX CORDIC WRITE request*/
+#define LL_DMAMUX_REQ_UCPD1_RX 0x00000072U /*!< DMAMUX USBPD1_RX request */
+#define LL_DMAMUX_REQ_UCPD1_TX 0x00000073U /*!< DMAMUX USBPD1_TX request */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
+ * @{
+ */
+#define LL_DMAMUX_CHANNEL_0 \
+ 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
+#define LL_DMAMUX_CHANNEL_1 \
+ 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
+#define LL_DMAMUX_CHANNEL_2 \
+ 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
+#define LL_DMAMUX_CHANNEL_3 \
+ 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
+#define LL_DMAMUX_CHANNEL_4 \
+ 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
+#define LL_DMAMUX_CHANNEL_5 \
+ 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
+#define LL_DMAMUX_CHANNEL_6 \
+ 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
+#define LL_DMAMUX_CHANNEL_7 \
+ 0x00000007U /*!< DMAMUX Channel 7 connected to DMA1 Channel 8 */
+#define LL_DMAMUX_CHANNEL_8 \
+ 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 1 */
+#define LL_DMAMUX_CHANNEL_9 \
+ 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 2 */
+#define LL_DMAMUX_CHANNEL_10 \
+ 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 3 */
+#define LL_DMAMUX_CHANNEL_11 \
+ 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */
+#define LL_DMAMUX_CHANNEL_12 \
+ 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */
+#define LL_DMAMUX_CHANNEL_13 \
+ 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */
+#define LL_DMAMUX_CHANNEL_14 \
+ 0x0000000EU /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */
+#define LL_DMAMUX_CHANNEL_15 \
+ 0x0000000FU /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
+ * @{
+ */
+#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
+#define LL_DMAMUX_SYNC_POL_RISING \
+ DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
+#define LL_DMAMUX_SYNC_POL_FALLING \
+ DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
+#define LL_DMAMUX_SYNC_POL_RISING_FALLING \
+ (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on \
+ rising and falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
+ * @{
+ */
+#define LL_DMAMUX_SYNC_EXTI_LINE0 \
+ 0x00000000U /*!< Synchronization signal from EXTI Line0 */
+#define LL_DMAMUX_SYNC_EXTI_LINE1 \
+ DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
+#define LL_DMAMUX_SYNC_EXTI_LINE2 \
+ DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
+#define LL_DMAMUX_SYNC_EXTI_LINE3 \
+ (DMAMUX_CxCR_SYNC_ID_1 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
+#define LL_DMAMUX_SYNC_EXTI_LINE4 \
+ DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
+#define LL_DMAMUX_SYNC_EXTI_LINE5 \
+ (DMAMUX_CxCR_SYNC_ID_2 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
+#define LL_DMAMUX_SYNC_EXTI_LINE6 \
+ (DMAMUX_CxCR_SYNC_ID_2 | \
+ DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
+#define LL_DMAMUX_SYNC_EXTI_LINE7 \
+ (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
+#define LL_DMAMUX_SYNC_EXTI_LINE8 \
+ DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
+#define LL_DMAMUX_SYNC_EXTI_LINE9 \
+ (DMAMUX_CxCR_SYNC_ID_3 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
+#define LL_DMAMUX_SYNC_EXTI_LINE10 \
+ (DMAMUX_CxCR_SYNC_ID_3 | \
+ DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
+#define LL_DMAMUX_SYNC_EXTI_LINE11 \
+ (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
+#define LL_DMAMUX_SYNC_EXTI_LINE12 \
+ (DMAMUX_CxCR_SYNC_ID_3 | \
+ DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
+#define LL_DMAMUX_SYNC_EXTI_LINE13 \
+ (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */
+#define LL_DMAMUX_SYNC_EXTI_LINE14 \
+ (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | \
+ DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */
+#define LL_DMAMUX_SYNC_EXTI_LINE15 \
+ (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
+#define LL_DMAMUX_SYNC_DMAMUX_CH0 \
+ DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event \
+ */
+#define LL_DMAMUX_SYNC_DMAMUX_CH1 \
+ (DMAMUX_CxCR_SYNC_ID_4 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 \
+ Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH2 \
+ (DMAMUX_CxCR_SYNC_ID_4 | \
+ DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 \
+ Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH3 \
+ (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | \
+ DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 \
+ Event */
+#define LL_DMAMUX_SYNC_LPTIM1_OUT \
+ (DMAMUX_CxCR_SYNC_ID_4 | \
+ DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
+ * @{
+ */
+#define LL_DMAMUX_REQ_GEN_0 0x00000000U
+#define LL_DMAMUX_REQ_GEN_1 0x00000001U
+#define LL_DMAMUX_REQ_GEN_2 0x00000002U
+#define LL_DMAMUX_REQ_GEN_3 0x00000003U
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal
+ * Generation Polarity
+ * @{
+ */
+#define LL_DMAMUX_REQ_GEN_NO_EVENT \
+ 0x00000000U /*!< No external DMA request generation */
+#define LL_DMAMUX_REQ_GEN_POL_RISING \
+ DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising \
+ edge */
+#define LL_DMAMUX_REQ_GEN_POL_FALLING \
+ DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling \
+ edge */
+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING \
+ (DMAMUX_RGxCR_GPOL_0 | \
+ DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and \
+ falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
+ * @{
+ */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 \
+ 0x00000000U /*!< Request signal generation from EXTI Line0 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 \
+ DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 \
+ DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 \
+ (DMAMUX_RGxCR_SIG_ID_1 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 \
+ DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 \
+ (DMAMUX_RGxCR_SIG_ID_2 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 \
+ (DMAMUX_RGxCR_SIG_ID_2 | \
+ DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 \
+ (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 \
+ DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 \
+ (DMAMUX_RGxCR_SIG_ID_3 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 \
+ (DMAMUX_RGxCR_SIG_ID_3 | \
+ DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 \
+ (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 \
+ (DMAMUX_RGxCR_SIG_ID_3 | \
+ DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 \
+ (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 \
+ (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | \
+ DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 \
+ (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 \
+ DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 \
+ Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 \
+ (DMAMUX_RGxCR_SIG_ID_4 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 \
+ Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 \
+ (DMAMUX_RGxCR_SIG_ID_4 | \
+ DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 \
+ Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 \
+ (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | \
+ DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 \
+ Event */
+#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT \
+ (DMAMUX_RGxCR_SIG_ID_4 | \
+ DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
+ * @{
+ */
+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMAMUX register
+ * @param __INSTANCE__ DMAMUX Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMAMUX register
+ * @param __INSTANCE__ DMAMUX Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAMUX_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Set DMAMUX request ID for DMAMUX Channel x.
+ * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
+ * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
+ * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_ADC2
+ * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+ * @arg @ref LL_DMAMUX_REQ_QSPI (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+ * (*) Not on all G4 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel,
+ uint32_t Request) {
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+ * @brief Get DMAMUX request ID for DMAMUX Channel x.
+ * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
+ * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
+ * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * (*) Not on all G4 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_ADC2
+ * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+ * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+ * @arg @ref LL_DMAMUX_REQ_QSPI (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+ * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+ * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+ * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+ * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+ * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+ * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+ * (*) Not on all G4 devices
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel) {
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR,
+ DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+ * @brief Set the number of DMA request that will be autorized after a
+ * synchronization event and/or the number of DMA request needed to generate an
+ * event.
+ * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @param RequestNb This parameter must be a value between Min_Data = 1 and
+ * Max_Data = 32.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel,
+ uint32_t RequestNb) {
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ,
+ ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
+}
+
+/**
+ * @brief Get the number of DMA request that will be autorized after a
+ * synchronization event and/or the number of DMA request needed to generate an
+ * event.
+ * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval Between Min_Data = 1 and Max_Data = 32
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR,
+ DMAMUX_CxCR_NBREQ)) >>
+ DMAMUX_CxCR_NBREQ_Pos) +
+ 1U);
+}
+
+/**
+ * @brief Set the polarity of the signal on which the DMA request is
+ * synchronized.
+ * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING
+ * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel,
+ uint32_t Polarity) {
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
+}
+
+/**
+ * @brief Get the polarity of the signal on which the DMA request is
+ * synchronized.
+ * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING
+ * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ return (
+ uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
+}
+
+/**
+ * @brief Enable the Event Generation on DMAMUX channel x.
+ * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+ * @brief Disable the Event Generation on DMAMUX channel x.
+ * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+ * @brief Check if the Event Generation on DMAMUX channel x is enabled or
+ * disabled.
+ * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) ==
+ (DMAMUX_CxCR_EGE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable the synchronization mode.
+ * @rmtoll CxCR SE LL_DMAMUX_EnableSync
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel) {
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+ * @brief Disable the synchronization mode.
+ * @rmtoll CxCR SE LL_DMAMUX_DisableSync
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel) {
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+ * @brief Check if the synchronization mode is enabled or disabled.
+ * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) ==
+ (DMAMUX_CxCR_SE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
+ * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @param SyncID This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel, uint32_t SyncID) {
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
+}
+
+/**
+ * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
+ * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel) {
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR,
+ DMAMUX_CxCR_SYNC_ID));
+}
+
+/**
+ * @brief Enable the Request Generator.
+ * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t RequestGenChannel) {
+ (void)(DMAMUXx);
+ SET_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GE);
+}
+
+/**
+ * @brief Disable the Request Generator.
+ * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
+ (void)(DMAMUXx);
+ CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GE);
+}
+
+/**
+ * @brief Check if the Request Generator is enabled or disabled.
+ * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
+ (void)(DMAMUXx);
+ return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set the polarity of the signal on which the DMA request is generated.
+ * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
+ uint32_t Polarity) {
+ UNUSED(DMAMUXx);
+ MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GPOL, Polarity);
+}
+
+/**
+ * @brief Get the polarity of the signal on which the DMA request is generated.
+ * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
+ UNUSED(DMAMUXx);
+ return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GPOL));
+}
+
+/**
+ * @brief Set the number of DMA request that will be autorized after a
+ * generation event.
+ * @note This field can only be written when Generator is disabled.
+ * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @param RequestNb This parameter must be a value between Min_Data = 1 and
+ * Max_Data = 32.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t RequestGenChannel,
+ uint32_t RequestNb) {
+ UNUSED(DMAMUXx);
+ MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
+}
+
+/**
+ * @brief Get the number of DMA request that will be autorized after a
+ * generation event.
+ * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval Between Min_Data = 1 and Max_Data = 32
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_GNBREQ) >>
+ DMAMUX_RGxCR_GNBREQ_Pos) +
+ 1U);
+}
+
+/**
+ * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation
+ * Trigger Event Channel x.
+ * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @param RequestSignalID This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
+ uint32_t RequestSignalID) {
+ UNUSED(DMAMUXx);
+ MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_SIG_ID, RequestSignalID);
+}
+
+/**
+ * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
+ * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
+ UNUSED(DMAMUXx);
+ return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_SIG_ID));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 0.
+ * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) ==
+ (DMAMUX_CSR_SOF0))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 1.
+ * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) ==
+ (DMAMUX_CSR_SOF1))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 2.
+ * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) ==
+ (DMAMUX_CSR_SOF2))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 3.
+ * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) ==
+ (DMAMUX_CSR_SOF3))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 4.
+ * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) ==
+ (DMAMUX_CSR_SOF4))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 5.
+ * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) ==
+ (DMAMUX_CSR_SOF5))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 6.
+ * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) ==
+ (DMAMUX_CSR_SOF6))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 7.
+ * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) ==
+ (DMAMUX_CSR_SOF7))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 8.
+ * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) ==
+ (DMAMUX_CSR_SOF8))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 9.
+ * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) ==
+ (DMAMUX_CSR_SOF9))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 10.
+ * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) ==
+ (DMAMUX_CSR_SOF10))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 11.
+ * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) ==
+ (DMAMUX_CSR_SOF11))
+ ? 1UL
+ : 0UL);
+}
+
+#if defined(DMAMUX_CSR_SOF12)
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 12.
+ * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) ==
+ (DMAMUX_CSR_SOF12))
+ ? 1UL
+ : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF12 */
+
+#if defined(DMAMUX_CSR_SOF13)
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 13.
+ * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) ==
+ (DMAMUX_CSR_SOF13))
+ ? 1UL
+ : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF13 */
+
+#if defined(DMAMUX_CSR_SOF14)
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 14.
+ * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO14
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF14) ==
+ (DMAMUX_CSR_SOF14))
+ ? 1UL
+ : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF14 */
+
+#if defined(DMAMUX_CSR_SOF15)
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 15.
+ * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO15
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF15) ==
+ (DMAMUX_CSR_SOF15))
+ ? 1UL
+ : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF15 */
+
+/**
+ * @brief Get Request Generator 0 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) ==
+ (DMAMUX_RGSR_OF0))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 1 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) ==
+ (DMAMUX_RGSR_OF1))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 2 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) ==
+ (DMAMUX_RGSR_OF2))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 3 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) ==
+ (DMAMUX_RGSR_OF3))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 0.
+ * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 1.
+ * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 2.
+ * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 3.
+ * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 4.
+ * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 5.
+ * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 6.
+ * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 7.
+ * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 8.
+ * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 9.
+ * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 10.
+ * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 11.
+ * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
+}
+
+#if defined(DMAMUX_CFR_CSOF12)
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 12.
+ * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
+}
+#endif /* DMAMUX_CFR_CSOF12 */
+
+#if defined(DMAMUX_CFR_CSOF13)
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 13.
+ * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
+}
+#endif /* DMAMUX_CFR_CSOF13 */
+
+#if defined(DMAMUX_CFR_CSOF14)
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 14.
+ * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF14);
+}
+#endif /* DMAMUX_CFR_CSOF14 */
+
+#if defined(DMAMUX_CFR_CSOF15)
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 15.
+ * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF15);
+}
+#endif /* DMAMUX_CFR_CSOF15 */
+
+/**
+ * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
+}
+
+/**
+ * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
+}
+
+/**
+ * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
+}
+
+/**
+ * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) {
+ UNUSED(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel
+ * x.
+ * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel) {
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+ * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel
+ * x.
+ * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t Channel) {
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+ * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX
+ * channel x is enabled or disabled.
+ * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @arg @ref LL_DMAMUX_CHANNEL_14
+ * @arg @ref LL_DMAMUX_CHANNEL_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) {
+ (void)(DMAMUXx);
+ return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) ==
+ (DMAMUX_CxCR_SOIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable the Request Generation Trigger Event Overrun Interrupt on
+ * DMAMUX channel x.
+ * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t RequestGenChannel) {
+ UNUSED(DMAMUXx);
+ SET_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_OIE);
+}
+
+/**
+ * @brief Disable the Request Generation Trigger Event Overrun Interrupt on
+ * DMAMUX channel x.
+ * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx,
+ uint32_t RequestGenChannel) {
+ UNUSED(DMAMUXx);
+ CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_OIE);
+}
+
+/**
+ * @brief Check if the Request Generation Trigger Event Overrun Interrupt on
+ * DMAMUX channel x is enabled or disabled.
+ * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(
+ DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) {
+ UNUSED(DMAMUXx);
+ return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
+ (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))
+ ->RGCR,
+ DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMAMUX1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_DMAMUX_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h
index a40c6e2..0d8fdfb 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h
@@ -1,1392 +1,1392 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_EXTI_H
-#define __STM32G4xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
- * @{
- */
-typedef struct {
- uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled
- for Lines in range 0 to 31 This parameter can be any
- combination of @ref EXTI_LL_EC_LINE */
-
- uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled
- for Lines in range 32 to 63 This parameter can be any
- combination of @ref EXTI_LL_EC_LINE */
-
- FunctionalState
- LineCommand; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-
- uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
- uint8_t
- Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
- * @{
- */
-#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
-#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
-#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
-#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
-#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
-#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
-#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
-#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
-#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
-#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
-#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
-#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
-#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
-#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
-#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
-#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
-#if defined(EXTI_IMR1_IM16)
-#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
-#endif /* EXTI_IMR1_IM16 */
-#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
-#if defined(EXTI_IMR1_IM18)
-#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
-#endif /* EXTI_IMR1_IM18 */
-#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
-#if defined(EXTI_IMR1_IM20)
-#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
-#endif /* EXTI_IMR1_IM20 */
-#if defined(EXTI_IMR1_IM21)
-#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
-#endif /* EXTI_IMR1_IM21 */
-#if defined(EXTI_IMR1_IM22)
-#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
-#endif /* EXTI_IMR1_IM22 */
-#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
-#if defined(EXTI_IMR1_IM24)
-#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
-#endif /* EXTI_IMR1_IM24 */
-#if defined(EXTI_IMR1_IM25)
-#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
-#endif /* EXTI_IMR1_IM25 */
-#if defined(EXTI_IMR1_IM26)
-#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */
-#endif /* EXTI_IMR1_IM26 */
-#if defined(EXTI_IMR1_IM27)
-#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */
-#endif /* EXTI_IMR1_IM27 */
-#if defined(EXTI_IMR1_IM28)
-#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
-#endif /* EXTI_IMR1_IM28 */
-#if defined(EXTI_IMR1_IM29)
-#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
-#endif /* EXTI_IMR1_IM29 */
-#if defined(EXTI_IMR1_IM30)
-#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
-#endif /* EXTI_IMR1_IM30 */
-#if defined(EXTI_IMR1_IM31)
-#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
-#endif /* EXTI_IMR1_IM31 */
-#define LL_EXTI_LINE_ALL_0_31 \
- EXTI_IMR1_IM /*!< All Extended line not \
- reserved*/
-
-#if defined(EXTI_IMR2_IM32)
-#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
-#endif /* EXTI_IMR2_IM32 */
-#if defined(EXTI_IMR2_IM33)
-#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
-#endif /* EXTI_IMR2_IM33 */
-#if defined(EXTI_IMR2_IM34)
-#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
-#endif /* EXTI_IMR2_IM34 */
-#if defined(EXTI_IMR2_IM35)
-#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
-#endif /* EXTI_IMR2_IM35 */
-#if defined(EXTI_IMR2_IM36)
-#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
-#endif /* EXTI_IMR2_IM36 */
-#if defined(EXTI_IMR2_IM37)
-#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
-#endif /* EXTI_IMR2_IM37 */
-#if defined(EXTI_IMR2_IM38)
-#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
-#endif /* EXTI_IMR2_IM38 */
-#if defined(EXTI_IMR2_IM39)
-#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
-#endif /* EXTI_IMR2_IM39 */
-#if defined(EXTI_IMR2_IM40)
-#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
-#endif /* EXTI_IMR2_IM40 */
-#if defined(EXTI_IMR2_IM41)
-#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */
-#endif /* EXTI_IMR2_IM41 */
-#if defined(EXTI_IMR2_IM42)
-#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */
-#endif /* EXTI_IMR2_IM42 */
-#define LL_EXTI_LINE_ALL_32_63 \
- EXTI_IMR2_IM /*!< All Extended line not reserved*/
-
-#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
- * @{
- */
-#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
- * @{
- */
-#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING \
- ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
- * @}
- */
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in EXTI register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) \
- WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in EXTI register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) {
- SET_BIT(EXTI->IMR1, ExtiLine);
-}
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
- * @note The reset value for the direct lines (lines from 32 to 34, line
- * 39) is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35 (*)
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_42(*)
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) {
- SET_BIT(EXTI->IMR2, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->IMR1, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
- * @note The reset value for the direct lines (lines from 32 to 34, line
- * 39) is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35 (*)
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_42(*)
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->IMR2, ExtiLine);
-}
-
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range
- * 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range
- * 32 to 63
- * @note The reset value for the direct lines (lines from 32 to 34, line
- * 39) is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35 (*)
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_42(*)
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @note (*): Available in some devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) {
- SET_BIT(EXTI->EMR1, ExtiLine);
-}
-
-/**
- * @brief Enable ExtiLine Event request for Lines in range 32 to 63
- * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35 (*)
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_42(*)
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) {
- SET_BIT(EXTI->EMR2, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->EMR1, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Event request for Lines in range 32 to 63
- * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35 (*)
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_42(*)
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->EMR2, ExtiLine);
-}
-
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to
- * 31
- * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32
- * to 63
- * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35 (*)
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_42(*)
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @note (*): Available in some devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) {
- SET_BIT(EXTI->RTSR1, ExtiLine);
-}
-
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) {
- SET_BIT(EXTI->RTSR2, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->RTSR1, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->RTSR2, ExtiLine);
-}
-
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
- * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) {
- SET_BIT(EXTI->FTSR1, ExtiLine);
-}
-
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) {
- SET_BIT(EXTI->FTSR2, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt
- * line. In this case, both generate a trigger condition.
- * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->FTSR1, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt
- * line. In this case, both generate a trigger condition.
- * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) {
- CLEAR_BIT(EXTI->FTSR2, ExtiLine);
-}
-
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
- * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management
- * Software_Interrupt_Management
- * @{
- */
-
-/**
- * @brief Generate a software Interrupt Event for Lines in range 0 to 31
- * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1
- * to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR1
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) {
- SET_BIT(EXTI->SWIER1, ExtiLine);
-}
-
-/**
- * @brief Generate a software Interrupt Event for Lines in range 32 to 63
- * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1
- * to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR2
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) {
- SET_BIT(EXTI->SWIER2, ExtiLine);
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
- * @{
- */
-
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) {
- return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval @note This bit is set when the selected edge event arrives on the
- * interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) {
- return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
-}
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval @note This bit is set when the selected edge event arrives on the
- * interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) {
- return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
-}
-
-/**
- * @brief Clear ExtLine Flags for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31 (*)
- * @note (*): Available in some devices
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) {
- WRITE_REG(EXTI->PR1, ExtiLine);
-}
-
-/**
- * @brief Clear ExtLine Flags for Lines in range 32 to 63
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32 (*)
- * @arg @ref LL_EXTI_LINE_33 (*)
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_40
- * @arg @ref LL_EXTI_LINE_41
- * @note (*): Available in some devices
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) {
- WRITE_REG(EXTI->PR2, ExtiLine);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* EXTI */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_EXTI_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_EXTI_H
+#define __STM32G4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct {
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled
+ for Lines in range 0 to 31 This parameter can be any
+ combination of @ref EXTI_LL_EC_LINE */
+
+ uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled
+ for Lines in range 32 to 63 This parameter can be any
+ combination of @ref EXTI_LL_EC_LINE */
+
+ FunctionalState
+ LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t
+ Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR1_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
+#endif /* EXTI_IMR1_IM16 */
+#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR1_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
+#endif /* EXTI_IMR1_IM18 */
+#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
+#if defined(EXTI_IMR1_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
+#endif /* EXTI_IMR1_IM20 */
+#if defined(EXTI_IMR1_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
+#endif /* EXTI_IMR1_IM21 */
+#if defined(EXTI_IMR1_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
+#endif /* EXTI_IMR1_IM22 */
+#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
+#if defined(EXTI_IMR1_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
+#endif /* EXTI_IMR1_IM24 */
+#if defined(EXTI_IMR1_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
+#endif /* EXTI_IMR1_IM25 */
+#if defined(EXTI_IMR1_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */
+#endif /* EXTI_IMR1_IM26 */
+#if defined(EXTI_IMR1_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */
+#endif /* EXTI_IMR1_IM27 */
+#if defined(EXTI_IMR1_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
+#endif /* EXTI_IMR1_IM28 */
+#if defined(EXTI_IMR1_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
+#endif /* EXTI_IMR1_IM29 */
+#if defined(EXTI_IMR1_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
+#endif /* EXTI_IMR1_IM30 */
+#if defined(EXTI_IMR1_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
+#endif /* EXTI_IMR1_IM31 */
+#define LL_EXTI_LINE_ALL_0_31 \
+ EXTI_IMR1_IM /*!< All Extended line not \
+ reserved*/
+
+#if defined(EXTI_IMR2_IM32)
+#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
+#endif /* EXTI_IMR2_IM32 */
+#if defined(EXTI_IMR2_IM33)
+#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
+#endif /* EXTI_IMR2_IM33 */
+#if defined(EXTI_IMR2_IM34)
+#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
+#endif /* EXTI_IMR2_IM34 */
+#if defined(EXTI_IMR2_IM35)
+#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
+#endif /* EXTI_IMR2_IM35 */
+#if defined(EXTI_IMR2_IM36)
+#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
+#endif /* EXTI_IMR2_IM36 */
+#if defined(EXTI_IMR2_IM37)
+#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
+#endif /* EXTI_IMR2_IM37 */
+#if defined(EXTI_IMR2_IM38)
+#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
+#endif /* EXTI_IMR2_IM38 */
+#if defined(EXTI_IMR2_IM39)
+#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
+#endif /* EXTI_IMR2_IM39 */
+#if defined(EXTI_IMR2_IM40)
+#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
+#endif /* EXTI_IMR2_IM40 */
+#if defined(EXTI_IMR2_IM41)
+#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */
+#endif /* EXTI_IMR2_IM41 */
+#if defined(EXTI_IMR2_IM42)
+#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */
+#endif /* EXTI_IMR2_IM42 */
+#define LL_EXTI_LINE_ALL_32_63 \
+ EXTI_IMR2_IM /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING \
+ ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) \
+ WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) {
+ SET_BIT(EXTI->IMR1, ExtiLine);
+}
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35 (*)
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @arg @ref LL_EXTI_LINE_42(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) {
+ SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35 (*)
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @arg @ref LL_EXTI_LINE_42(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range
+ * 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range
+ * 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35 (*)
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @arg @ref LL_EXTI_LINE_42(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) {
+ SET_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35 (*)
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @arg @ref LL_EXTI_LINE_42(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) {
+ SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35 (*)
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @arg @ref LL_EXTI_LINE_42(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to
+ * 31
+ * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32
+ * to 63
+ * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35 (*)
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @arg @ref LL_EXTI_LINE_42(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) {
+ SET_BIT(EXTI->RTSR1, ExtiLine);
+}
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) {
+ SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) {
+ SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) {
+ SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt
+ * line. In this case, both generate a trigger condition.
+ * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt
+ * line. In this case, both generate a trigger condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) {
+ CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management
+ * Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1
+ * to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) {
+ SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 32 to 63
+ * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1
+ * to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) {
+ SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) {
+ return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the
+ * interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) {
+ return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval @note This bit is set when the selected edge event arrives on the
+ * interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) {
+ return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) {
+ WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32 (*)
+ * @arg @ref LL_EXTI_LINE_33 (*)
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_40
+ * @arg @ref LL_EXTI_LINE_41
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) {
+ WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_EXTI_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h
index 8feee89..902a4d9 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h
@@ -1,1027 +1,1027 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_GPIO_H
-#define STM32G4xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(GPIOA) || defined(GPIOB) || defined(GPIOC) || defined(GPIOD) || \
- defined(GPIOE) || defined(GPIOF) || defined(GPIOG)
-
-/** @defgroup GPIO_LL GPIO
- * @{
- */
-/** MISRA C:2012 deviation rule has been granted for following rules:
- * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
- * which may be out of array bounds [..,UNKNOWN] in following APIs:
- * LL_GPIO_GetAFPin_0_7
- * LL_GPIO_SetAFPin_0_7
- * LL_GPIO_SetAFPin_8_15
- * LL_GPIO_GetAFPin_8_15
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
- * @{
- */
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
- * @{
- */
-
-/**
- * @brief LL GPIO Init Structure definition
- */
-typedef struct {
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
- GPIO HW configuration can be modified afterwards using
- unitary function @ref LL_GPIO_SetPinMode().*/
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
- GPIO HW configuration can be modified afterwards using
- unitary function @ref LL_GPIO_SetPinSpeed().*/
-
- uint32_t
- OutputType; /*!< Specifies the operating output type for the selected
- pins. This parameter can be a value of @ref
- GPIO_LL_EC_OUTPUT.
-
- GPIO HW configuration can be modified afterwards using
- unitary function @ref LL_GPIO_SetPinOutputType().*/
-
- uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected
- pins. This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
- GPIO HW configuration can be modified afterwards using
- unitary function @ref LL_GPIO_SetPinPull().*/
-
- uint32_t
- Alternate; /*!< Specifies the Peripheral to be connected to the selected
- pins. This parameter can be a value of @ref GPIO_LL_EC_AF.
-
- GPIO HW configuration can be modified afterwards using
- unitary function @ref LL_GPIO_SetAFPin_0_7() and
- LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
- * @{
- */
-#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL \
- (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | GPIO_BSRR_BS3 | \
- GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | \
- GPIO_BSRR_BS8 | GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
- GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
- GPIO_BSRR_BS15) /*!< Select all pins */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
- * @{
- */
-#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE \
- GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
- * @{
- */
-#define LL_GPIO_OUTPUT_PUSHPULL \
- (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN \
- GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
- * @{
- */
-#define LL_GPIO_SPEED_FREQ_LOW \
- (0x00000000U) /*!< Select I/O low output speed */
-#define LL_GPIO_SPEED_FREQ_MEDIUM \
- GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH \
- GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH \
- GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
-/**
- * @}
- */
-#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
-#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
-#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
-#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
- * @{
- */
-#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
- * @{
- */
-#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
- * @{
- */
-
-/**
- * @brief Configure gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Input mode, General purpose output, Alternate
- * function mode or Analog.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll MODER MODEy LL_GPIO_SetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin,
- uint32_t Mode) {
- MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)),
- (Mode << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Input mode, General purpose output, Alternate
- * function mode or Analog.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll MODER MODEy LL_GPIO_GetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) {
- return (uint32_t)(READ_BIT(GPIOx->MODER,
- (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >>
- (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @param OutputType This parameter can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx,
- uint32_t PinMask,
- uint32_t OutputType) {
- MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
- * @brief Return gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx,
- uint32_t Pin) {
- return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
-}
-
-/**
- * @brief Configure gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Speed This parameter can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin,
- uint32_t Speed) {
- MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
- (Speed << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx,
- uint32_t Pin) {
- return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0
- << (POSITION_VAL(Pin) * 2U))) >>
- (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio pull-up or pull-down for a dedicated pin on a
- * dedicated port.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Pull This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PULL_NO
- * @arg @ref LL_GPIO_PULL_UP
- * @arg @ref LL_GPIO_PULL_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin,
- uint32_t Pull) {
- MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)),
- (Pull << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated
- * port
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_PULL_NO
- * @arg @ref LL_GPIO_PULL_UP
- * @arg @ref LL_GPIO_PULL_DOWN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) {
- return (uint32_t)(READ_BIT(GPIOx->PUPDR,
- (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >>
- (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for
- * a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @param Alternate This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin,
- uint32_t Alternate) {
- MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
- (Alternate << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a
- * dedicated port.
- * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx,
- uint32_t Pin) {
- return (uint32_t)(READ_BIT(GPIOx->AFR[0],
- (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >>
- (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for
- * a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Alternate This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin,
- uint32_t Alternate) {
- MODIFY_REG(GPIOx->AFR[1],
- (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
- (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
-}
-
-/**
- * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a
- * dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx,
- uint32_t Pin) {
- return (uint32_t)(READ_BIT(
- GPIOx->AFR[1],
- (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >>
- (POSITION_VAL(Pin >> 8U) * 4U));
-}
-
-/**
- * @brief Lock configuration of several pins for a dedicated port.
- * @note When the lock sequence has been applied on a port bit, the
- * value of this port bit can no longer be modified until the
- * next reset.
- * @note Each lock bit freezes a specific configuration register
- * (control and alternate function registers).
- * @rmtoll LCKR LCKK LL_GPIO_LockPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) {
- __IO uint32_t temp;
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
- WRITE_REG(GPIOx->LCKR, PinMask);
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
- /* Read LCKR register. This read is mandatory to complete key lock sequence */
- temp = READ_REG(GPIOx->LCKR);
- (void)temp;
-}
-
-/**
- * @brief Return 1 if all pins passed as parameter, of a dedicated port, are
- * locked. else Return 0.
- * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx,
- uint32_t PinMask) {
- return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Return 1 if one of the pin of a dedicated port is locked. else return
- * 0.
- * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
- * @param GPIOx GPIO Port
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) {
- return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
- * @{
- */
-
-/**
- * @brief Return full input data register value for a dedicated port.
- * @rmtoll IDR IDy LL_GPIO_ReadInputPort
- * @param GPIOx GPIO Port
- * @retval Input data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) {
- return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high
- * or low.
- * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx,
- uint32_t PinMask) {
- return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Write output data register for the port.
- * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
- * @param GPIOx GPIO Port
- * @param PortValue Level value for each pin of the port
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx,
- uint32_t PortValue) {
- WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
- * @brief Return full output data register value for a dedicated port.
- * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
- * @param GPIOx GPIO Port
- * @retval Output data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) {
- return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high
- * or low.
- * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx,
- uint32_t PinMask) {
- return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set several pins to high level on dedicated gpio port.
- * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx,
- uint32_t PinMask) {
- WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
- * @brief Set several pins to low level on dedicated gpio port.
- * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx,
- uint32_t PinMask) {
- WRITE_REG(GPIOx->BRR, PinMask);
-}
-
-/**
- * @brief Toggle data value for several pin of dedicated port.
- * @rmtoll ODR ODy LL_GPIO_TogglePin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) {
- uint32_t odr = READ_REG(GPIOx->ODR);
- WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx,
- LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined \
- (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_GPIO_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_GPIO_H
+#define STM32G4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(GPIOA) || defined(GPIOB) || defined(GPIOC) || defined(GPIOD) || \
+ defined(GPIOE) || defined(GPIOF) || defined(GPIOG)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+ * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
+ * which may be out of array bounds [..,UNKNOWN] in following APIs:
+ * LL_GPIO_GetAFPin_0_7
+ * LL_GPIO_SetAFPin_0_7
+ * LL_GPIO_SetAFPin_8_15
+ * LL_GPIO_GetAFPin_8_15
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct {
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using
+ unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using
+ unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t
+ OutputType; /*!< Specifies the operating output type for the selected
+ pins. This parameter can be a value of @ref
+ GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using
+ unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected
+ pins. This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using
+ unitary function @ref LL_GPIO_SetPinPull().*/
+
+ uint32_t
+ Alternate; /*!< Specifies the Peripheral to be connected to the selected
+ pins. This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+ GPIO HW configuration can be modified afterwards using
+ unitary function @ref LL_GPIO_SetAFPin_0_7() and
+ LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL \
+ (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | GPIO_BSRR_BS3 | \
+ GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | \
+ GPIO_BSRR_BS8 | GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+ GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+ GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE \
+ GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL \
+ (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN \
+ GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_SPEED_FREQ_LOW \
+ (0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM \
+ GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH \
+ GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH \
+ GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
+/**
+ * @}
+ */
+#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+ * @{
+ */
+#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate
+ * function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin,
+ uint32_t Mode) {
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)),
+ (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate
+ * function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) {
+ return (uint32_t)(READ_BIT(GPIOx->MODER,
+ (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >>
+ (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx,
+ uint32_t PinMask,
+ uint32_t OutputType) {
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx,
+ uint32_t Pin) {
+ return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin,
+ uint32_t Speed) {
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx,
+ uint32_t Pin) {
+ return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0
+ << (POSITION_VAL(Pin) * 2U))) >>
+ (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a
+ * dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin,
+ uint32_t Pull) {
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)),
+ (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated
+ * port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) {
+ return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >>
+ (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for
+ * a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin,
+ uint32_t Alternate) {
+ MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a
+ * dedicated port.
+ * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx,
+ uint32_t Pin) {
+ return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >>
+ (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for
+ * a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin,
+ uint32_t Alternate) {
+ MODIFY_REG(GPIOx->AFR[1],
+ (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a
+ * dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx,
+ uint32_t Pin) {
+ return (uint32_t)(READ_BIT(
+ GPIOx->AFR[1],
+ (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >>
+ (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) {
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ WRITE_REG(GPIOx->LCKR, PinMask);
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ /* Read LCKR register. This read is mandatory to complete key lock sequence */
+ temp = READ_REG(GPIOx->LCKR);
+ (void)temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are
+ * locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx,
+ uint32_t PinMask) {
+ return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return
+ * 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) {
+ return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) {
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high
+ * or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx,
+ uint32_t PinMask) {
+ return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx,
+ uint32_t PortValue) {
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) {
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high
+ * or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx,
+ uint32_t PinMask) {
+ return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx,
+ uint32_t PinMask) {
+ WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx,
+ uint32_t PinMask) {
+ WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) {
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx,
+ LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined \
+ (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_GPIO_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h
new file mode 100644
index 0000000..b1db9d2
--- /dev/null
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h
@@ -0,0 +1,339 @@
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_IWDG_H
+#define STM32G4xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+ * @{
+ */
+#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE \
+ 0x00005555U /*!< IWDG KR Write Access Enable */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE \
+ 0x00000000U /*!< IWDG KR Write Access Disable */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_IWDG_ReadReg function
+ * @{
+ */
+#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU \
+ IWDG_SR_RVU /*!< Watchdog counter reload value update \
+ */
+#define LL_IWDG_SR_WVU \
+ IWDG_SR_WVU /*!< Watchdog counter window value update \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
+ * @{
+ */
+#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
+#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
+#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
+#define LL_IWDG_PRESCALER_32 \
+ (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
+#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
+#define LL_IWDG_PRESCALER_128 \
+ (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256 \
+ (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Start the Independent Watchdog
+ * @note Except if the hardware watchdog option is selected
+ * @rmtoll KR KEY LL_IWDG_Enable
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) {
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * @rmtoll KR KEY LL_IWDG_ReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) {
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) {
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) {
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+ * @brief Select the prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_SetPrescaler
+ * @param IWDGx IWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx,
+ uint32_t Prescaler) {
+ WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+ * @brief Get the selected prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_GetPrescaler
+ * @param IWDGx IWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) {
+ return (READ_REG(IWDGx->PR));
+}
+
+/**
+ * @brief Specify the IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_SetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx,
+ uint32_t Counter) {
+ WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+ * @brief Get the specified IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_GetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) {
+ return (READ_REG(IWDGx->RLR));
+}
+
+/**
+ * @brief Specify high limit of the window value to be compared to the
+ * down-counter.
+ * @rmtoll WINR WIN LL_IWDG_SetWindow
+ * @param IWDGx IWDG Instance
+ * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) {
+ WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+ * @brief Get the high limit of the window value specified.
+ * @rmtoll WINR WIN LL_IWDG_GetWindow
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) {
+ return (READ_REG(IWDGx->WINR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if flag Prescaler Value Update is set or not
+ * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) {
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if flag Reload Value Update is set or not
+ * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) {
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if flag Window Value Update is set or not
+ * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) {
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if all flags Prescaler, Reload & Window Value Update are reset
+ * or not
+ * @rmtoll SR PVU LL_IWDG_IsReady\n
+ * SR RVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady
+ * @param IWDGx IWDG Instance
+ * @retval State of bits (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) {
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U)
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* IWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_IWDG_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
index 9cdcc48..9c72915 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
@@ -1,2707 +1,2767 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_lpuart.h
- * @author MCD Application Team
- * @brief Header file of LPUART LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_LPUART_H
-#define STM32G4xx_LL_LPUART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(LPUART1)
-
-/** @defgroup LPUART_LL LPUART
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
- * @{
- */
-/* Array used to get the LPUART prescaler division decimal values versus @ref
- * LPUART_LL_EC_PRESCALER values */
-static const uint16_t LPUART_PRESCALER_TAB[] = {
- (uint16_t)1, (uint16_t)2, (uint16_t)4, (uint16_t)6,
- (uint16_t)8, (uint16_t)10, (uint16_t)12, (uint16_t)16,
- (uint16_t)32, (uint16_t)64, (uint16_t)128, (uint16_t)256};
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
- * @{
- */
-/* Defines used in Baud Rate related macros and corresponding register setting
- * computation */
-#define LPUART_LPUARTDIV_FREQ_MUL 256U
-#define LPUART_BRR_MASK 0x000FFFFFU
-#define LPUART_BRR_MIN_VALUE 0x00000300U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
- * @{
- */
-
-/**
- * @brief LL LPUART Init Structure definition
- */
-typedef struct {
- uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the
- communication baud rate. This parameter can be a
- value of @ref LPUART_LL_EC_PRESCALER.
-
- This feature can be modified afterwards using
- unitary function @ref LL_LPUART_SetPrescaler().*/
-
- uint32_t
- BaudRate; /*!< This field defines expected LPUART communication baud rate.
-
- This feature can be modified afterwards using unitary
- function @ref LL_LPUART_SetBaudRate().*/
-
- uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or
- received in a frame. This parameter can be a value of
- @ref LPUART_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary
- function @ref LL_LPUART_SetDataWidth().*/
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref
- LPUART_LL_EC_STOPBITS.
-
- This feature can be modified afterwards using unitary
- function @ref LL_LPUART_SetStopBitsLength().*/
-
- uint32_t
- Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref LPUART_LL_EC_PARITY.
-
- This feature can be modified afterwards using unitary
- function @ref LL_LPUART_SetParity().*/
-
- uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit
- mode is enabled or disabled. This parameter can
- be a value of @ref LPUART_LL_EC_DIRECTION.
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_LPUART_SetTransferDirection().*/
-
- uint32_t
- HardwareFlowControl; /*!< Specifies whether the hardware flow control mode
- is enabled or disabled. This parameter can be a
- value of @ref LPUART_LL_EC_HWCONTROL.
-
- This feature can be modified afterwards using
- unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
-
-} LL_LPUART_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
- * @{
- */
-
-/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_LPUART_WriteReg function
- * @{
- */
-#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
-#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
-#define LL_LPUART_ICR_NCF \
- USART_ICR_NECF /*!< Noise error detected clear flag \
- */
-#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
-#define LL_LPUART_ICR_IDLECF \
- USART_ICR_IDLECF /*!< Idle line detected clear flag */
-#define LL_LPUART_ICR_TCCF \
- USART_ICR_TCCF /*!< Transmission complete clear flag */
-#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
-#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
-#define LL_LPUART_ICR_WUCF \
- USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_LPUART_ReadReg function
- * @{
- */
-#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
-#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
-#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
-#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
-#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
-#define LL_LPUART_ISR_RXNE_RXFNE \
- USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
-#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
-#define LL_LPUART_ISR_TXE_TXFNF \
- USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full \
- flag*/
-#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
-#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
-#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
-#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
-#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
-#define LL_LPUART_ISR_RWU \
- USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
-#define LL_LPUART_ISR_TEACK \
- USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
-#define LL_LPUART_ISR_REACK \
- USART_ISR_REACK /*!< Receive enable acknowledge flag */
-#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
-#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
-#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
-#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_LPUART_ReadReg and
- * LL_LPUART_WriteReg functions
- * @{
- */
-#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_LPUART_CR1_RXNEIE_RXFNEIE \
- USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty \
- interrupt enable */
-#define LL_LPUART_CR1_TCIE \
- USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_LPUART_CR1_TXEIE_TXFNFIE \
- USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO \
- not full interrupt enable */
-#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_LPUART_CR1_CMIE \
- USART_CR1_CMIE /*!< Character match interrupt enable */
-#define LL_LPUART_CR1_TXFEIE \
- USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
-#define LL_LPUART_CR1_RXFFIE \
- USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
-#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#define LL_LPUART_CR3_WUFIE \
- USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
-#define LL_LPUART_CR3_TXFTIE \
- USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
-#define LL_LPUART_CR3_RXFTIE \
- USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
- * @{
- */
-#define LL_LPUART_FIFOTHRESHOLD_1_8 \
- 0x00000000U /*!< FIFO reaches 1/8 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_1_4 \
- 0x00000001U /*!< FIFO reaches 1/4 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_1_2 \
- 0x00000002U /*!< FIFO reaches 1/2 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_3_4 \
- 0x00000003U /*!< FIFO reaches 3/4 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_7_8 \
- 0x00000004U /*!< FIFO reaches 7/8 of its depth */
-#define LL_LPUART_FIFOTHRESHOLD_8_8 \
- 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_DIRECTION Direction
- * @{
- */
-#define LL_LPUART_DIRECTION_NONE \
- 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_LPUART_DIRECTION_RX \
- USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_LPUART_DIRECTION_TX \
- USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_LPUART_DIRECTION_TX_RX \
- (USART_CR1_TE | USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_PARITY Parity Control
- * @{
- */
-#define LL_LPUART_PARITY_NONE \
- 0x00000000U /*!< Parity control disabled */
-#define LL_LPUART_PARITY_EVEN \
- USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_LPUART_PARITY_ODD \
- (USART_CR1_PCE | \
- USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
- * @{
- */
-#define LL_LPUART_WAKEUP_IDLELINE \
- 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
-#define LL_LPUART_WAKEUP_ADDRESSMARK \
- USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_LPUART_DATAWIDTH_7B \
- USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits \
- */
-#define LL_LPUART_DATAWIDTH_8B \
- 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_9B \
- USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits \
- */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
- * @{
- */
-#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
-#define LL_LPUART_PRESCALER_DIV2 \
- (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
-#define LL_LPUART_PRESCALER_DIV4 \
- (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
-#define LL_LPUART_PRESCALER_DIV6 \
- (USART_PRESC_PRESCALER_1 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
-#define LL_LPUART_PRESCALER_DIV8 \
- (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
-#define LL_LPUART_PRESCALER_DIV10 \
- (USART_PRESC_PRESCALER_2 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
-#define LL_LPUART_PRESCALER_DIV12 \
- (USART_PRESC_PRESCALER_2 | \
- USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
-#define LL_LPUART_PRESCALER_DIV16 \
- (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
-#define LL_LPUART_PRESCALER_DIV32 \
- (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
-#define LL_LPUART_PRESCALER_DIV64 \
- (USART_PRESC_PRESCALER_3 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
-#define LL_LPUART_PRESCALER_DIV128 \
- (USART_PRESC_PRESCALER_3 | \
- USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
-#define LL_LPUART_PRESCALER_DIV256 \
- (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
- * @{
- */
-#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
- * @{
- */
-#define LL_LPUART_TXRX_STANDARD \
- 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_LPUART_TXRX_SWAPPED \
- (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
- * @{
- */
-#define LL_LPUART_RXPIN_LEVEL_STANDARD \
- 0x00000000U /*!< RX pin signal works using the standard logic levels */
-#define LL_LPUART_RXPIN_LEVEL_INVERTED \
- (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
- * @{
- */
-#define LL_LPUART_TXPIN_LEVEL_STANDARD \
- 0x00000000U /*!< TX pin signal works using the standard logic levels */
-#define LL_LPUART_TXPIN_LEVEL_INVERTED \
- (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
- * @{
- */
-#define LL_LPUART_BINARY_LOGIC_POSITIVE \
- 0x00000000U /*!< Logical data from the data register are send/received \
- in positive/direct logic. (1=H, 0=L) */
-#define LL_LPUART_BINARY_LOGIC_NEGATIVE \
- USART_CR2_DATAINV /*!< Logical data from the data register are send/received \
- in negative/inverse logic. (1=L, 0=H). \
- The parity bit is also inverted. */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_BITORDER Bit Order
- * @{
- */
-#define LL_LPUART_BITORDER_LSBFIRST \
- 0x00000000U /*!< data is transmitted/received with data bit 0 first, \
- following the start bit */
-#define LL_LPUART_BITORDER_MSBFIRST \
- USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, \
- following the start bit */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
- * @{
- */
-#define LL_LPUART_ADDRESS_DETECT_4B \
- 0x00000000U /*!< 4-bit address detection method selected */
-#define LL_LPUART_ADDRESS_DETECT_7B \
- USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method \
- selected */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
- * @{
- */
-#define LL_LPUART_HWCONTROL_NONE \
- 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_LPUART_HWCONTROL_RTS \
- USART_CR3_RTSE /*!< RTS output enabled, data is only requested \
- when there is space in the receive buffer */
-#define LL_LPUART_HWCONTROL_CTS \
- USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted \
- when the nCTS input is asserted (tied to 0)*/
-#define LL_LPUART_HWCONTROL_RTS_CTS \
- (USART_CR3_RTSE | \
- USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
- * @{
- */
-#define LL_LPUART_WAKEUP_ON_ADDRESS \
- 0x00000000U /*!< Wake up active on address match */
-#define LL_LPUART_WAKEUP_ON_STARTBIT \
- USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
-#define LL_LPUART_WAKEUP_ON_RXNE \
- (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
- * @{
- */
-#define LL_LPUART_DE_POLARITY_HIGH \
- 0x00000000U /*!< DE signal is active high \
- */
-#define LL_LPUART_DE_POLARITY_LOW \
- USART_CR3_DEP /*!< DE signal is active low \
- */
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
- * @{
- */
-#define LL_LPUART_DMA_REG_DATA_TRANSMIT \
- 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_LPUART_DMA_REG_DATA_RECEIVE \
- 0x00000001U /*!< Get address of data register used for reception */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
- * @{
- */
-
-/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in LPUART register
- * @param __INSTANCE__ LPUART Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in LPUART register
- * @param __INSTANCE__ LPUART Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
- * @{
- */
-
-/**
- * @brief Compute LPUARTDIV value according to Peripheral Clock and
- * expected Baud Rate (20-bit value of LPUARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
- * @param __PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_LPUART_PRESCALER_DIV1
- * @arg @ref LL_LPUART_PRESCALER_DIV2
- * @arg @ref LL_LPUART_PRESCALER_DIV4
- * @arg @ref LL_LPUART_PRESCALER_DIV6
- * @arg @ref LL_LPUART_PRESCALER_DIV8
- * @arg @ref LL_LPUART_PRESCALER_DIV10
- * @arg @ref LL_LPUART_PRESCALER_DIV12
- * @arg @ref LL_LPUART_PRESCALER_DIV16
- * @arg @ref LL_LPUART_PRESCALER_DIV32
- * @arg @ref LL_LPUART_PRESCALER_DIV64
- * @arg @ref LL_LPUART_PRESCALER_DIV128
- * @arg @ref LL_LPUART_PRESCALER_DIV256
- * @param __BAUDRATE__ Baud Rate value to achieve
- * @retval LPUARTDIV value to be used for BRR register filling
- */
-#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
- (uint32_t)( \
- (((((uint64_t)(__PERIPHCLK__) / \
- (uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * \
- LPUART_LPUARTDIV_FREQ_MUL) + \
- (uint32_t)((__BAUDRATE__) / 2U)) / \
- (__BAUDRATE__)) & \
- LPUART_BRR_MASK)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
- * @{
- */
-
-/** @defgroup LPUART_LL_EF_Configuration Configuration functions
- * @{
- */
-
-/**
- * @brief LPUART Enable
- * @rmtoll CR1 UE LL_LPUART_Enable
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief LPUART Disable
- * @note When LPUART is disabled, LPUART prescalers and outputs are stopped
- * immediately, and current operations are discarded. The configuration of the
- * LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their
- * default values.
- * @note In order to go into low-power mode without generating errors on the
- * line, the TE bit must be reset before and the software must wait for the TC
- * bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests
- * are also reset when UE = 0 so the DMA channel must be disabled before
- * resetting the UE bit.
- * @rmtoll CR1 UE LL_LPUART_Disable
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief Indicate if LPUART is enabled
- * @rmtoll CR1 UE LL_LPUART_IsEnabled
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief FIFO Mode Enable
- * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
- * @brief FIFO Mode Disable
- * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
- * @brief Indicate if FIFO Mode is enabled
- * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configure TX FIFO Threshold
- * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
- * @param LPUARTx LPUART Instance
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx,
- uint32_t Threshold) {
- ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG,
- Threshold << USART_CR3_TXFTCFG_Pos);
-}
-
-/**
- * @brief Return TX FIFO Threshold Configuration
- * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >>
- USART_CR3_TXFTCFG_Pos);
-}
-
-/**
- * @brief Configure RX FIFO Threshold
- * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
- * @param LPUARTx LPUART Instance
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx,
- uint32_t Threshold) {
- ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG,
- Threshold << USART_CR3_RXFTCFG_Pos);
-}
-
-/**
- * @brief Return RX FIFO Threshold Configuration
- * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >>
- USART_CR3_RXFTCFG_Pos);
-}
-
-/**
- * @brief Configure TX and RX FIFOs Threshold
- * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
- * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
- * @param LPUARTx LPUART Instance
- * @param TXThreshold This parameter can be one of the following values:
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
- * @param RXThreshold This parameter can be one of the following values:
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx,
- uint32_t TXThreshold,
- uint32_t RXThreshold) {
- ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG,
- (TXThreshold << USART_CR3_TXFTCFG_Pos) |
- (RXThreshold << USART_CR3_RXFTCFG_Pos));
-}
-
-/**
- * @brief LPUART enabled in STOP Mode
- * @note When this function is enabled, LPUART is able to wake up the MCU from
- * Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
- * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
-}
-
-/**
- * @brief LPUART disabled in STOP Mode
- * @note When this function is disabled, LPUART is not able to wake up the MCU
- * from Stop mode
- * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
-}
-
-/**
- * @brief Indicate if LPUART is enabled in STOP Mode
- * (able to wake up MCU from Stop mode or not)
- * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Receiver Enable (Receiver is enabled and begins searching for a start
- * bit)
- * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Receiver Disable
- * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Transmitter Enable
- * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Transmitter Disable
- * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Configure simultaneously enabled/disabled states
- * of Transmitter and Receiver
- * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
- * CR1 TE LL_LPUART_SetTransferDirection
- * @param LPUARTx LPUART Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_LPUART_DIRECTION_NONE
- * @arg @ref LL_LPUART_DIRECTION_RX
- * @arg @ref LL_LPUART_DIRECTION_TX
- * @arg @ref LL_LPUART_DIRECTION_TX_RX
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetTransferDirection(
- USART_TypeDef *LPUARTx, uint32_t TransferDirection) {
- ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE,
- TransferDirection);
-}
-
-/**
- * @brief Return enabled/disabled states of Transmitter and Receiver
- * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
- * CR1 TE LL_LPUART_GetTransferDirection
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_DIRECTION_NONE
- * @arg @ref LL_LPUART_DIRECTION_RX
- * @arg @ref LL_LPUART_DIRECTION_TX
- * @arg @ref LL_LPUART_DIRECTION_TX_RX
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
- * @brief Configure Parity (enabled/disabled and parity mode if enabled)
- * @note This function selects if hardware parity control (generation and
- * detection) is enabled or disabled. When the parity control is enabled (Odd or
- * Even), computed parity bit is inserted at the MSB position (depending on data
- * width) and parity is checked on the received data.
- * @rmtoll CR1 PS LL_LPUART_SetParity\n
- * CR1 PCE LL_LPUART_SetParity
- * @param LPUARTx LPUART Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_LPUART_PARITY_NONE
- * @arg @ref LL_LPUART_PARITY_EVEN
- * @arg @ref LL_LPUART_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx,
- uint32_t Parity) {
- MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
- * @brief Return Parity configuration (enabled/disabled and parity mode if
- * enabled)
- * @rmtoll CR1 PS LL_LPUART_GetParity\n
- * CR1 PCE LL_LPUART_GetParity
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_PARITY_NONE
- * @arg @ref LL_LPUART_PARITY_EVEN
- * @arg @ref LL_LPUART_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
- * @brief Set Receiver Wake Up method from Mute mode.
- * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
- * @param LPUARTx LPUART Instance
- * @param Method This parameter can be one of the following values:
- * @arg @ref LL_LPUART_WAKEUP_IDLELINE
- * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx,
- uint32_t Method) {
- MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
- * @brief Return Receiver Wake Up method from Mute mode
- * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_WAKEUP_IDLELINE
- * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
- * @brief Set Word length (nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M LL_LPUART_SetDataWidth
- * @param LPUARTx LPUART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_LPUART_DATAWIDTH_7B
- * @arg @ref LL_LPUART_DATAWIDTH_8B
- * @arg @ref LL_LPUART_DATAWIDTH_9B
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx,
- uint32_t DataWidth) {
- MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
- * @brief Return Word length (i.e. nb of data bits, excluding start and stop
- * bits)
- * @rmtoll CR1 M LL_LPUART_GetDataWidth
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_DATAWIDTH_7B
- * @arg @ref LL_LPUART_DATAWIDTH_8B
- * @arg @ref LL_LPUART_DATAWIDTH_9B
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
-}
-
-/**
- * @brief Allow switch between Mute Mode and Active mode
- * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
-}
-
-/**
- * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
- * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
-}
-
-/**
- * @brief Indicate if switch between Mute Mode and Active mode is allowed
- * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configure Clock source prescaler for baudrate generator and
- * oversampling
- * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
- * @param LPUARTx LPUART Instance
- * @param PrescalerValue This parameter can be one of the following values:
- * @arg @ref LL_LPUART_PRESCALER_DIV1
- * @arg @ref LL_LPUART_PRESCALER_DIV2
- * @arg @ref LL_LPUART_PRESCALER_DIV4
- * @arg @ref LL_LPUART_PRESCALER_DIV6
- * @arg @ref LL_LPUART_PRESCALER_DIV8
- * @arg @ref LL_LPUART_PRESCALER_DIV10
- * @arg @ref LL_LPUART_PRESCALER_DIV12
- * @arg @ref LL_LPUART_PRESCALER_DIV16
- * @arg @ref LL_LPUART_PRESCALER_DIV32
- * @arg @ref LL_LPUART_PRESCALER_DIV64
- * @arg @ref LL_LPUART_PRESCALER_DIV128
- * @arg @ref LL_LPUART_PRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx,
- uint32_t PrescalerValue) {
- MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
-}
-
-/**
- * @brief Retrieve the Clock source prescaler for baudrate generator and
- * oversampling
- * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_PRESCALER_DIV1
- * @arg @ref LL_LPUART_PRESCALER_DIV2
- * @arg @ref LL_LPUART_PRESCALER_DIV4
- * @arg @ref LL_LPUART_PRESCALER_DIV6
- * @arg @ref LL_LPUART_PRESCALER_DIV8
- * @arg @ref LL_LPUART_PRESCALER_DIV10
- * @arg @ref LL_LPUART_PRESCALER_DIV12
- * @arg @ref LL_LPUART_PRESCALER_DIV16
- * @arg @ref LL_LPUART_PRESCALER_DIV32
- * @arg @ref LL_LPUART_PRESCALER_DIV64
- * @arg @ref LL_LPUART_PRESCALER_DIV128
- * @arg @ref LL_LPUART_PRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
-}
-
-/**
- * @brief Set the length of the stop bits
- * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
- * @param LPUARTx LPUART Instance
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_LPUART_STOPBITS_1
- * @arg @ref LL_LPUART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx,
- uint32_t StopBits) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Retrieve the length of the stop bits
- * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_STOPBITS_1
- * @arg @ref LL_LPUART_STOPBITS_2
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
-}
-
-/**
- * @brief Configure Character frame format (Datawidth, Parity control, Stop
- * Bits)
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Data Width configuration using @ref LL_LPUART_SetDataWidth()
- * function
- * - Parity Control and mode configuration using @ref
- * LL_LPUART_SetParity() function
- * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength()
- * function
- * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
- * CR1 PCE LL_LPUART_ConfigCharacter\n
- * CR1 M LL_LPUART_ConfigCharacter\n
- * CR2 STOP LL_LPUART_ConfigCharacter
- * @param LPUARTx LPUART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_LPUART_DATAWIDTH_7B
- * @arg @ref LL_LPUART_DATAWIDTH_8B
- * @arg @ref LL_LPUART_DATAWIDTH_9B
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_LPUART_PARITY_NONE
- * @arg @ref LL_LPUART_PARITY_EVEN
- * @arg @ref LL_LPUART_PARITY_ODD
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_LPUART_STOPBITS_1
- * @arg @ref LL_LPUART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx,
- uint32_t DataWidth,
- uint32_t Parity,
- uint32_t StopBits) {
- MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M,
- Parity | DataWidth);
- MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Configure TX/RX pins swapping setting.
- * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
- * @param LPUARTx LPUART Instance
- * @param SwapConfig This parameter can be one of the following values:
- * @arg @ref LL_LPUART_TXRX_STANDARD
- * @arg @ref LL_LPUART_TXRX_SWAPPED
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx,
- uint32_t SwapConfig) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
- * @brief Retrieve TX/RX pins swapping configuration.
- * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_TXRX_STANDARD
- * @arg @ref LL_LPUART_TXRX_SWAPPED
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
- * @brief Configure RX pin active level logic
- * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
- * @param LPUARTx LPUART Instance
- * @param PinInvMethod This parameter can be one of the following values:
- * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
- * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx,
- uint32_t PinInvMethod) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
- * @brief Retrieve RX pin active level logic configuration
- * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
- * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
- * @brief Configure TX pin active level logic
- * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
- * @param LPUARTx LPUART Instance
- * @param PinInvMethod This parameter can be one of the following values:
- * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
- * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx,
- uint32_t PinInvMethod) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
- * @brief Retrieve TX pin active level logic configuration
- * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
- * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
- * @brief Configure Binary data logic.
- *
- * @note Allow to define how Logical data from the data register are
- * send/received : either in positive/direct logic (1=H, 0=L) or in
- * negative/inverse logic (1=L, 0=H)
- * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
- * @param LPUARTx LPUART Instance
- * @param DataLogic This parameter can be one of the following values:
- * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
- * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx,
- uint32_t DataLogic) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
- * @brief Retrieve Binary data configuration
- * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
- * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
- * @brief Configure transfer bit order (either Less or Most Significant Bit
- * First)
- * @note MSB First means data is transmitted/received with the MSB first,
- * following the start bit. LSB First means data is transmitted/received with
- * data bit 0 first, following the start bit.
- * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
- * @param LPUARTx LPUART Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_LPUART_BITORDER_LSBFIRST
- * @arg @ref LL_LPUART_BITORDER_MSBFIRST
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx,
- uint32_t BitOrder) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
- * @brief Return transfer bit order (either Less or Most Significant Bit First)
- * @note MSB First means data is transmitted/received with the MSB first,
- * following the start bit. LSB First means data is transmitted/received with
- * data bit 0 first, following the start bit.
- * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_BITORDER_LSBFIRST
- * @arg @ref LL_LPUART_BITORDER_MSBFIRST
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
- * @brief Set Address of the LPUART node.
- * @note This is used in multiprocessor communication during Mute mode or Stop
- * mode, for wake up with address mark detection.
- * @note 4bits address node is used when 4-bit Address Detection is selected
- * in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit
- * Address Detection is selected in ADDM7. (This is used in multiprocessor
- * communication during Mute mode or Stop mode, for wake up with 7-bit address
- * mark detection. The MSB of the character sent by the transmitter should be
- * equal to 1. It may also be used for character detection during normal
- * reception, Mute mode inactive (for example, end of block detection in ModBus
- * protocol). In this case, the whole received character (8-bit) is compared to
- * the ADD[7:0] value and CMF flag is set on match)
- * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
- * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
- * @param LPUARTx LPUART Instance
- * @param AddressLen This parameter can be one of the following values:
- * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
- * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
- * @param NodeAddress 4 or 7 bit Address of the LPUART node.
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx,
- uint32_t AddressLen,
- uint32_t NodeAddress) {
- MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
- (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
- * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
- * @note If 4-bit Address Detection is selected in ADDM7,
- * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not
- * relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0)
- * of returned value are relevant (b31-b8 are not relevant)
- * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
- * @param LPUARTx LPUART Instance
- * @retval Address of the LPUART node (Value between Min_Data=0 and
- * Max_Data=255)
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
- * @brief Return Length of Node Address used in Address Detection mode (7-bit
- * or 4-bit)
- * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
- * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
- * @brief Enable RTS HW Flow Control
- * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Disable RTS HW Flow Control
- * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Enable CTS HW Flow Control
- * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Disable CTS HW Flow Control
- * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Configure HW Flow Control mode (both CTS and RTS)
- * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
- * CR3 CTSE LL_LPUART_SetHWFlowCtrl
- * @param LPUARTx LPUART Instance
- * @param HardwareFlowControl This parameter can be one of the following
- * values:
- * @arg @ref LL_LPUART_HWCONTROL_NONE
- * @arg @ref LL_LPUART_HWCONTROL_RTS
- * @arg @ref LL_LPUART_HWCONTROL_CTS
- * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx,
- uint32_t HardwareFlowControl) {
- MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE,
- HardwareFlowControl);
-}
-
-/**
- * @brief Return HW Flow Control configuration (both CTS and RTS)
- * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
- * CR3 CTSE LL_LPUART_GetHWFlowCtrl
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_HWCONTROL_NONE
- * @arg @ref LL_LPUART_HWCONTROL_RTS
- * @arg @ref LL_LPUART_HWCONTROL_CTS
- * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
- * @brief Enable Overrun detection
- * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Disable Overrun detection
- * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Indicate if Overrun detection is enabled
- * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
- * @param LPUARTx LPUART Instance
- * @param Type This parameter can be one of the following values:
- * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
- * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
- * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx,
- uint32_t Type) {
- MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
- * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
- * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
- * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
-}
-
-/**
- * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
- *
- * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
- * according to used Peripheral Clock and expected Baud Rate values
- * @note Peripheral clock and Baud Rate values provided as function parameters
- * should be valid (Baud rate value != 0).
- * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
- * a care should be taken when generating high baud rates using high
- * PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x
- * BaudRate].
- * @rmtoll BRR BRR LL_LPUART_SetBaudRate
- * @param LPUARTx LPUART Instance
- * @param PeriphClk Peripheral Clock
- * @param PrescalerValue This parameter can be one of the following values:
- * @arg @ref LL_LPUART_PRESCALER_DIV1
- * @arg @ref LL_LPUART_PRESCALER_DIV2
- * @arg @ref LL_LPUART_PRESCALER_DIV4
- * @arg @ref LL_LPUART_PRESCALER_DIV6
- * @arg @ref LL_LPUART_PRESCALER_DIV8
- * @arg @ref LL_LPUART_PRESCALER_DIV10
- * @arg @ref LL_LPUART_PRESCALER_DIV12
- * @arg @ref LL_LPUART_PRESCALER_DIV16
- * @arg @ref LL_LPUART_PRESCALER_DIV32
- * @arg @ref LL_LPUART_PRESCALER_DIV64
- * @arg @ref LL_LPUART_PRESCALER_DIV128
- * @arg @ref LL_LPUART_PRESCALER_DIV256
- * @param BaudRate Baud Rate
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx,
- uint32_t PeriphClk,
- uint32_t PrescalerValue,
- uint32_t BaudRate) {
- if (BaudRate != 0U) {
- LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
- }
-}
-
-/**
- * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR
- * register (full BRR content), and to used Peripheral Clock values
- * @note In case of non-initialized or invalid value stored in BRR register,
- * value 0 will be returned.
- * @rmtoll BRR BRR LL_LPUART_GetBaudRate
- * @param LPUARTx LPUART Instance
- * @param PeriphClk Peripheral Clock
- * @param PrescalerValue This parameter can be one of the following values:
- * @arg @ref LL_LPUART_PRESCALER_DIV1
- * @arg @ref LL_LPUART_PRESCALER_DIV2
- * @arg @ref LL_LPUART_PRESCALER_DIV4
- * @arg @ref LL_LPUART_PRESCALER_DIV6
- * @arg @ref LL_LPUART_PRESCALER_DIV8
- * @arg @ref LL_LPUART_PRESCALER_DIV10
- * @arg @ref LL_LPUART_PRESCALER_DIV12
- * @arg @ref LL_LPUART_PRESCALER_DIV16
- * @arg @ref LL_LPUART_PRESCALER_DIV32
- * @arg @ref LL_LPUART_PRESCALER_DIV64
- * @arg @ref LL_LPUART_PRESCALER_DIV128
- * @arg @ref LL_LPUART_PRESCALER_DIV256
- * @retval Baud Rate
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx,
- uint32_t PeriphClk,
- uint32_t PrescalerValue) {
- uint32_t lpuartdiv;
- uint32_t brrresult;
- uint32_t periphclkpresc =
- (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
-
- lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
-
- if (lpuartdiv >= LPUART_BRR_MIN_VALUE) {
- brrresult =
- (uint32_t)(((uint64_t)(periphclkpresc)*LPUART_LPUARTDIV_FREQ_MUL) /
- lpuartdiv);
- } else {
- brrresult = 0x0UL;
- }
-
- return (brrresult);
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions
- * related to Half Duplex feature
- * @{
- */
-
-/**
- * @brief Enable Single Wire Half-Duplex mode
- * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Disable Single Wire Half-Duplex mode
- * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to
- * Driver Enable feature
- * @{
- */
-
-/**
- * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5
- * bits ([4:0] bits).
- * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
- * @param LPUARTx LPUART Instance
- * @param Time Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx,
- uint32_t Time) {
- MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
- * @brief Return DEDT (Driver Enable De-Assertion Time)
- * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
- * @param LPUARTx LPUART Instance
- * @retval Time value expressed on 5 bits ([4:0] bits) : c
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >>
- USART_CR1_DEDT_Pos);
-}
-
-/**
- * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5
- * bits ([4:0] bits).
- * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
- * @param LPUARTx LPUART Instance
- * @param Time Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx,
- uint32_t Time) {
- MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
- * @brief Return DEAT (Driver Enable Assertion Time)
- * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
- * @param LPUARTx LPUART Instance
- * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between
- * Min_Data=0 and Max_Data=31
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >>
- USART_CR1_DEAT_Pos);
-}
-
-/**
- * @brief Enable Driver Enable (DE) Mode
- * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
-}
-
-/**
- * @brief Disable Driver Enable (DE) Mode
- * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
-}
-
-/**
- * @brief Indicate if Driver Enable (DE) Mode is enabled
- * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Select Driver Enable Polarity
- * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
- * @param LPUARTx LPUART Instance
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_LPUART_DE_POLARITY_HIGH
- * @arg @ref LL_LPUART_DE_POLARITY_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx,
- uint32_t Polarity) {
- MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
- * @brief Return Driver Enable Polarity
- * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
- * @param LPUARTx LPUART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_LPUART_DE_POLARITY_HIGH
- * @arg @ref LL_LPUART_DE_POLARITY_LOW
- */
-__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) {
- return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if the LPUART Parity Error Flag is set or not
- * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Framing Error Flag is set or not
- * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Noise error detected Flag is set or not
- * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the LPUART OverRun Error Flag is set or not
- * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART IDLE line detected Flag is set or not
- * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL
- : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
-
-/**
- * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty
- * Flag is set or not
- * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) {
- return (
- (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Transmission Complete Flag is set or not
- * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
-
-/**
- * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO
- * Not Full Flag is set or not
- * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART CTS interrupt Flag is set or not
- * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART CTS Flag is set or not
- * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Busy Flag is set or not
- * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Character Match Flag is set or not
- * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Send Break Flag is set or not
- * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
- * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
- * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
- * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
- * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART TX FIFO Empty Flag is set or not
- * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART RX FIFO Full Flag is set or not
- * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
- * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
- * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Clear Parity Error Flag
- * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
-}
-
-/**
- * @brief Clear Framing Error Flag
- * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
-}
-
-/**
- * @brief Clear Noise detected Flag
- * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
-}
-
-/**
- * @brief Clear OverRun Error Flag
- * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
- * @brief Clear IDLE line detected Flag
- * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
- * @brief Clear Transmission Complete Flag
- * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
-}
-
-/**
- * @brief Clear CTS Interrupt Flag
- * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
- * @brief Clear Character Match Flag
- * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
- * @brief Clear Wake Up from stop mode Flag
- * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) {
- WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
-
-/**
- * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
- * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
- * @brief Enable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
-
-/**
- * @brief Enable TX Empty and TX FIFO Not Full Interrupt
- * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
- * @brief Enable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Enable Character Match Interrupt
- * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
- * @brief Enable TX FIFO Empty Interrupt
- * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
- * @brief Enable RX FIFO Full Interrupt
- * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
- * @brief Enable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
- * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
- * NF=1 in the LPUARTx_ISR register).
- * - 0: Interrupt is inhibited
- * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the
- * LPUARTx_ISR register.
- * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Enable CTS Interrupt
- * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Enable Wake Up from Stop Mode Interrupt
- * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
- * @brief Enable TX FIFO Threshold Interrupt
- * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
- * @brief Enable RX FIFO Threshold Interrupt
- * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
- * @brief Disable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
-
-/**
- * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
- * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
- * @brief Disable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
-
-/**
- * @brief Disable TX Empty and TX FIFO Not Full Interrupt
- * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
- * @brief Disable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Disable Character Match Interrupt
- * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
- * @brief Disable TX FIFO Empty Interrupt
- * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
- * @brief Disable RX FIFO Full Interrupt
- * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
- * @brief Disable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
- * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
- * NF=1 in the LPUARTx_ISR register).
- * - 0: Interrupt is inhibited
- * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the
- * LPUARTx_ISR register.
- * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Disable CTS Interrupt
- * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Disable Wake Up from Stop Mode Interrupt
- * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
- * @brief Disable TX FIFO Threshold Interrupt
- * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
- * @brief Disable RX FIFO Threshold Interrupt
- * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
- * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
- * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE))
- ? 1UL
- : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
-
-/**
- * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty
- * Interrupt is enabled or disabled.
- * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) ==
- (USART_CR1_RXNEIE_RXFNEIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Transmission Complete Interrupt is enabled or
- * disabled.
- * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL
- : 0UL);
-}
-
-/* Legacy define */
-#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
-
-/**
- * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is
- * enabled or disabled
- * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) ==
- (USART_CR1_TXEIE_TXFNFIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
- * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
- * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
- * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
- * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Error Interrupt is enabled or disabled.
- * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
- * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or
- * disabled.
- * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
- * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
- * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
- * @{
- */
-
-/**
- * @brief Enable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Disable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for reception
- * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) {
- ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Disable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) {
- ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for transmission
- * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable DMA Disabling on Reception Error
- * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
- * @brief Disable DMA Disabling on Reception Error
- * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) {
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
- * @brief Indicate if DMA Disabling on Reception Error is disabled
- * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
- * @param LPUARTx LPUART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) {
- return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get the LPUART data register address used for DMA transfer
- * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
- * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
- * @param LPUARTx LPUART Instance
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
- * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx,
- uint32_t Direction) {
- uint32_t data_reg_addr;
-
- if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) {
- /* return address of TDR register */
- data_reg_addr = (uint32_t) & (LPUARTx->TDR);
- } else {
- /* return address of RDR register */
- data_reg_addr = (uint32_t) & (LPUARTx->RDR);
- }
-
- return data_reg_addr;
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 8 bits)
- * @rmtoll RDR RDR LL_LPUART_ReceiveData8
- * @param LPUARTx LPUART Instance
- * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) {
- return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 9 bits)
- * @rmtoll RDR RDR LL_LPUART_ReceiveData9
- * @param LPUARTx LPUART Instance
- * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
- */
-__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) {
- return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
- * @rmtoll TDR TDR LL_LPUART_TransmitData8
- * @param LPUARTx LPUART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx,
- uint8_t Value) {
- LPUARTx->TDR = Value;
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
- * @rmtoll TDR TDR LL_LPUART_TransmitData9
- * @param LPUARTx LPUART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0x1FF
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx,
- uint16_t Value) {
- LPUARTx->TDR = Value & 0x1FFUL;
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPUART_LL_EF_Execution Execution
- * @{
- */
-
-/**
- * @brief Request Break sending
- * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
- * @brief Put LPUART in mute mode and set the RWU flag
- * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
- * @brief Request a Receive Data and FIFO flush
- * @note Allows to discard the received data without reading them, and avoid
- * an overrun condition.
- * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) {
- SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx,
- LL_LPUART_InitTypeDef *LPUART_InitStruct);
-void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* LPUART1 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_LPUART_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_lpuart.h
+ * @author MCD Application Team
+ * @brief Header file of LPUART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_LPUART_H
+#define STM32G4xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+ * @{
+ */
+/* Array used to get the LPUART prescaler division decimal values versus @ref
+ * LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] = {
+ (uint16_t)1, (uint16_t)2, (uint16_t)4, (uint16_t)6,
+ (uint16_t)8, (uint16_t)10, (uint16_t)12, (uint16_t)16,
+ (uint16_t)32, (uint16_t)64, (uint16_t)128, (uint16_t)256};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+ * @{
+ */
+/* Defines used in Baud Rate related macros and corresponding register setting
+ * computation */
+#define LPUART_LPUARTDIV_FREQ_MUL 256U
+#define LPUART_BRR_MASK 0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE 0x00000300U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL LPUART Init Structure definition
+ */
+typedef struct {
+ uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the
+ communication baud rate. This parameter can be a
+ value of @ref LPUART_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_LPUART_SetPrescaler().*/
+
+ uint32_t
+ BaudRate; /*!< This field defines expected LPUART communication baud rate.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or
+ received in a frame. This parameter can be a value of
+ @ref LPUART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref
+ LPUART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetStopBitsLength().*/
+
+ uint32_t
+ Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit
+ mode is enabled or disabled. This parameter can
+ be a value of @ref LPUART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using
+ unitary function @ref
+ LL_LPUART_SetTransferDirection().*/
+
+ uint32_t
+ HardwareFlowControl; /*!< Specifies whether the hardware flow control mode
+ is enabled or disabled. This parameter can be a
+ value of @ref LPUART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+ * @{
+ */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_LPUART_WriteReg function
+ * @{
+ */
+#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF \
+ USART_ICR_NECF /*!< Noise error detected clear flag \
+ */
+#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF \
+ USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF \
+ USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF \
+ USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_LPUART_ReadReg function
+ * @{
+ */
+#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE \
+ USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF \
+ USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full \
+ flag*/
+#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_LPUART_ISR_RWU \
+ USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK \
+ USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK \
+ USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_LPUART_ReadReg and
+ * LL_LPUART_WriteReg functions
+ * @{
+ */
+#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE \
+ USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty \
+ interrupt enable */
+#define LL_LPUART_CR1_TCIE \
+ USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE \
+ USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO \
+ not full interrupt enable */
+#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_LPUART_CR1_CMIE \
+ USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE \
+ USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE \
+ USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE \
+ USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE \
+ USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE \
+ USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+ * @{
+ */
+#define LL_LPUART_FIFOTHRESHOLD_1_8 \
+ 0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4 \
+ 0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2 \
+ 0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4 \
+ 0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8 \
+ 0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8 \
+ 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+ * @{
+ */
+#define LL_LPUART_DIRECTION_NONE \
+ 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX \
+ USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX \
+ USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX \
+ (USART_CR1_TE | USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_LPUART_PARITY_NONE \
+ 0x00000000U /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN \
+ USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD \
+ (USART_CR1_PCE | \
+ USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_LPUART_WAKEUP_IDLELINE \
+ 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK \
+ USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_LPUART_DATAWIDTH_7B \
+ USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits \
+ */
+#define LL_LPUART_DATAWIDTH_8B \
+ 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B \
+ USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+ * @{
+ */
+#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_LPUART_PRESCALER_DIV2 \
+ (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_LPUART_PRESCALER_DIV4 \
+ (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_LPUART_PRESCALER_DIV6 \
+ (USART_PRESC_PRESCALER_1 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_LPUART_PRESCALER_DIV8 \
+ (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_LPUART_PRESCALER_DIV10 \
+ (USART_PRESC_PRESCALER_2 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12 \
+ (USART_PRESC_PRESCALER_2 | \
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16 \
+ (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32 \
+ (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64 \
+ (USART_PRESC_PRESCALER_3 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 \
+ (USART_PRESC_PRESCALER_3 | \
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 \
+ (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_LPUART_TXRX_STANDARD \
+ 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED \
+ (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD \
+ 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED \
+ (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD \
+ 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED \
+ (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE \
+ 0x00000000U /*!< Logical data from the data register are send/received \
+ in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE \
+ USART_CR2_DATAINV /*!< Logical data from the data register are send/received \
+ in negative/inverse logic. (1=L, 0=H). \
+ The parity bit is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_LPUART_BITORDER_LSBFIRST \
+ 0x00000000U /*!< data is transmitted/received with data bit 0 first, \
+ following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST \
+ USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, \
+ following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_LPUART_ADDRESS_DETECT_4B \
+ 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B \
+ USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method \
+ selected */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_LPUART_HWCONTROL_NONE \
+ 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS \
+ USART_CR3_RTSE /*!< RTS output enabled, data is only requested \
+ when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS \
+ USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted \
+ when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS \
+ (USART_CR3_RTSE | \
+ USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+ * @{
+ */
+#define LL_LPUART_WAKEUP_ON_ADDRESS \
+ 0x00000000U /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT \
+ USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE \
+ (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_LPUART_DE_POLARITY_HIGH \
+ 0x00000000U /*!< DE signal is active high \
+ */
+#define LL_LPUART_DE_POLARITY_LOW \
+ USART_CR3_DEP /*!< DE signal is active low \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT \
+ 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE \
+ 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+ * @{
+ */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in LPUART register
+ * @param __INSTANCE__ LPUART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in LPUART register
+ * @param __INSTANCE__ LPUART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+ * @{
+ */
+
+/**
+ * @brief Compute LPUARTDIV value according to Peripheral Clock and
+ * expected Baud Rate (20-bit value of LPUARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @param __BAUDRATE__ Baud Rate value to achieve
+ * @retval LPUARTDIV value to be used for BRR register filling
+ */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (uint32_t)( \
+ (((((uint64_t)(__PERIPHCLK__) / \
+ (uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * \
+ LPUART_LPUARTDIV_FREQ_MUL) + \
+ (uint32_t)((__BAUDRATE__) / 2U)) / \
+ (__BAUDRATE__)) & \
+ LPUART_BRR_MASK)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+ * @{
+ */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief LPUART Enable
+ * @rmtoll CR1 UE LL_LPUART_Enable
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief LPUART Disable
+ * @note When LPUART is disabled, LPUART prescalers and outputs are stopped
+ * immediately, and current operations are discarded. The configuration of the
+ * LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their
+ * default values.
+ * @note In order to go into low-power mode without generating errors on the
+ * line, the TE bit must be reset before and the software must wait for the TC
+ * bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests
+ * are also reset when UE = 0 so the DMA channel must be disabled before
+ * resetting the UE bit.
+ * @rmtoll CR1 UE LL_LPUART_Disable
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if LPUART is enabled
+ * @rmtoll CR1 UE LL_LPUART_IsEnabled
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief FIFO Mode Enable
+ * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief FIFO Mode Disable
+ * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief Indicate if FIFO Mode is enabled
+ * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configure TX FIFO Threshold
+ * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx,
+ uint32_t Threshold) {
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG,
+ Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Return TX FIFO Threshold Configuration
+ * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >>
+ USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure RX FIFO Threshold
+ * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx,
+ uint32_t Threshold) {
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG,
+ Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Return RX FIFO Threshold Configuration
+ * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >>
+ USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure TX and RX FIFOs Threshold
+ * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
+ * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
+ * @param LPUARTx LPUART Instance
+ * @param TXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @param RXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx,
+ uint32_t TXThreshold,
+ uint32_t RXThreshold) {
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG,
+ (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+ * @brief LPUART enabled in STOP Mode
+ * @note When this function is enabled, LPUART is able to wake up the MCU from
+ * Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
+ * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief LPUART disabled in STOP Mode
+ * @note When this function is disabled, LPUART is not able to wake up the MCU
+ * from Stop mode
+ * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if LPUART is enabled in STOP Mode
+ * (able to wake up MCU from Stop mode or not)
+ * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start
+ * bit)
+ * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
+ * CR1 TE LL_LPUART_SetTransferDirection
+ * @param LPUARTx LPUART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DIRECTION_NONE
+ * @arg @ref LL_LPUART_DIRECTION_RX
+ * @arg @ref LL_LPUART_DIRECTION_TX
+ * @arg @ref LL_LPUART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(
+ USART_TypeDef *LPUARTx, uint32_t TransferDirection) {
+ ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE,
+ TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
+ * CR1 TE LL_LPUART_GetTransferDirection
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_DIRECTION_NONE
+ * @arg @ref LL_LPUART_DIRECTION_RX
+ * @arg @ref LL_LPUART_DIRECTION_TX
+ * @arg @ref LL_LPUART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled)
+ * @note This function selects if hardware parity control (generation and
+ * detection) is enabled or disabled. When the parity control is enabled (Odd or
+ * Even), computed parity bit is inserted at the MSB position (depending on data
+ * width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_LPUART_SetParity\n
+ * CR1 PCE LL_LPUART_SetParity
+ * @param LPUARTx LPUART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PARITY_NONE
+ * @arg @ref LL_LPUART_PARITY_EVEN
+ * @arg @ref LL_LPUART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx,
+ uint32_t Parity) {
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if
+ * enabled)
+ * @rmtoll CR1 PS LL_LPUART_GetParity\n
+ * CR1 PCE LL_LPUART_GetParity
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_PARITY_NONE
+ * @arg @ref LL_LPUART_PARITY_EVEN
+ * @arg @ref LL_LPUART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
+ * @param LPUARTx LPUART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_WAKEUP_IDLELINE
+ * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx,
+ uint32_t Method) {
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_WAKEUP_IDLELINE
+ * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_LPUART_SetDataWidth
+ * @param LPUARTx LPUART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DATAWIDTH_7B
+ * @arg @ref LL_LPUART_DATAWIDTH_8B
+ * @arg @ref LL_LPUART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx,
+ uint32_t DataWidth) {
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop
+ * bits)
+ * @rmtoll CR1 M LL_LPUART_GetDataWidth
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_DATAWIDTH_7B
+ * @arg @ref LL_LPUART_DATAWIDTH_8B
+ * @arg @ref LL_LPUART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configure Clock source prescaler for baudrate generator and
+ * oversampling
+ * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
+ * @param LPUARTx LPUART Instance
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx,
+ uint32_t PrescalerValue) {
+ MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Retrieve the Clock source prescaler for baudrate generator and
+ * oversampling
+ * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
+ * @param LPUARTx LPUART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_STOPBITS_1
+ * @arg @ref LL_LPUART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx,
+ uint32_t StopBits) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_STOPBITS_1
+ * @arg @ref LL_LPUART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop
+ * Bits)
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Data Width configuration using @ref LL_LPUART_SetDataWidth()
+ * function
+ * - Parity Control and mode configuration using @ref
+ * LL_LPUART_SetParity() function
+ * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength()
+ * function
+ * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
+ * CR1 PCE LL_LPUART_ConfigCharacter\n
+ * CR1 M LL_LPUART_ConfigCharacter\n
+ * CR2 STOP LL_LPUART_ConfigCharacter
+ * @param LPUARTx LPUART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DATAWIDTH_7B
+ * @arg @ref LL_LPUART_DATAWIDTH_8B
+ * @arg @ref LL_LPUART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PARITY_NONE
+ * @arg @ref LL_LPUART_PARITY_EVEN
+ * @arg @ref LL_LPUART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_STOPBITS_1
+ * @arg @ref LL_LPUART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx,
+ uint32_t DataWidth,
+ uint32_t Parity,
+ uint32_t StopBits) {
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M,
+ Parity | DataWidth);
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
+ * @param LPUARTx LPUART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_TXRX_STANDARD
+ * @arg @ref LL_LPUART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx,
+ uint32_t SwapConfig) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_TXRX_STANDARD
+ * @arg @ref LL_LPUART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx,
+ uint32_t PinInvMethod) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx,
+ uint32_t PinInvMethod) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ *
+ * @note Allow to define how Logical data from the data register are
+ * send/received : either in positive/direct logic (1=H, 0=L) or in
+ * negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
+ * @param LPUARTx LPUART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx,
+ uint32_t DataLogic) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit
+ * First)
+ * @note MSB First means data is transmitted/received with the MSB first,
+ * following the start bit. LSB First means data is transmitted/received with
+ * data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
+ * @param LPUARTx LPUART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_BITORDER_LSBFIRST
+ * @arg @ref LL_LPUART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx,
+ uint32_t BitOrder) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first,
+ * following the start bit. LSB First means data is transmitted/received with
+ * data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_BITORDER_LSBFIRST
+ * @arg @ref LL_LPUART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Set Address of the LPUART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop
+ * mode, for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected
+ * in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit
+ * Address Detection is selected in ADDM7. (This is used in multiprocessor
+ * communication during Mute mode or Stop mode, for wake up with 7-bit address
+ * mark detection. The MSB of the character sent by the transmitter should be
+ * equal to 1. It may also be used for character detection during normal
+ * reception, Mute mode inactive (for example, end of block detection in ModBus
+ * protocol). In this case, the whole received character (8-bit) is compared to
+ * the ADD[7:0] value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
+ * @param LPUARTx LPUART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the LPUART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx,
+ uint32_t AddressLen,
+ uint32_t NodeAddress) {
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not
+ * relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0)
+ * of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
+ * @param LPUARTx LPUART Instance
+ * @retval Address of the LPUART node (Value between Min_Data=0 and
+ * Max_Data=255)
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit
+ * or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+ * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_LPUART_SetHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @param HardwareFlowControl This parameter can be one of the following
+ * values:
+ * @arg @ref LL_LPUART_HWCONTROL_NONE
+ * @arg @ref LL_LPUART_HWCONTROL_RTS
+ * @arg @ref LL_LPUART_HWCONTROL_CTS
+ * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx,
+ uint32_t HardwareFlowControl) {
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE,
+ HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_LPUART_GetHWFlowCtrl
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_HWCONTROL_NONE
+ * @arg @ref LL_LPUART_HWCONTROL_RTS
+ * @arg @ref LL_LPUART_HWCONTROL_CTS
+ * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
+ * @param LPUARTx LPUART Instance
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx,
+ uint32_t Type) {
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+ * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+ * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
+ *
+ * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock and expected Baud Rate values
+ * @note Peripheral clock and Baud Rate values provided as function parameters
+ * should be valid (Baud rate value != 0).
+ * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+ * a care should be taken when generating high baud rates using high
+ * PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x
+ * BaudRate].
+ * @rmtoll BRR BRR LL_LPUART_SetBaudRate
+ * @param LPUARTx LPUART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx,
+ uint32_t PeriphClk,
+ uint32_t PrescalerValue,
+ uint32_t BaudRate) {
+ if (BaudRate != 0U) {
+ LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR
+ * register (full BRR content), and to used Peripheral Clock values
+ * @note In case of non-initialized or invalid value stored in BRR register,
+ * value 0 will be returned.
+ * @rmtoll BRR BRR LL_LPUART_GetBaudRate
+ * @param LPUARTx LPUART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_PRESCALER_DIV1
+ * @arg @ref LL_LPUART_PRESCALER_DIV2
+ * @arg @ref LL_LPUART_PRESCALER_DIV4
+ * @arg @ref LL_LPUART_PRESCALER_DIV6
+ * @arg @ref LL_LPUART_PRESCALER_DIV8
+ * @arg @ref LL_LPUART_PRESCALER_DIV10
+ * @arg @ref LL_LPUART_PRESCALER_DIV12
+ * @arg @ref LL_LPUART_PRESCALER_DIV16
+ * @arg @ref LL_LPUART_PRESCALER_DIV32
+ * @arg @ref LL_LPUART_PRESCALER_DIV64
+ * @arg @ref LL_LPUART_PRESCALER_DIV128
+ * @arg @ref LL_LPUART_PRESCALER_DIV256
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx,
+ uint32_t PeriphClk,
+ uint32_t PrescalerValue) {
+ uint32_t lpuartdiv;
+ uint32_t brrresult;
+ uint32_t periphclkpresc =
+ (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+ lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+ if (lpuartdiv >= LPUART_BRR_MIN_VALUE) {
+ brrresult =
+ (uint32_t)(((uint64_t)(periphclkpresc)*LPUART_LPUARTDIV_FREQ_MUL) /
+ lpuartdiv);
+ } else {
+ brrresult = 0x0UL;
+ }
+
+ return (brrresult);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions
+ * related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to
+ * Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5
+ * bits ([4:0] bits).
+ * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
+ * @param LPUARTx LPUART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx,
+ uint32_t Time) {
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
+ * @param LPUARTx LPUART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : c
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >>
+ USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5
+ * bits ([4:0] bits).
+ * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
+ * @param LPUARTx LPUART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx,
+ uint32_t Time) {
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
+ * @param LPUARTx LPUART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between
+ * Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >>
+ USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
+ * @param LPUARTx LPUART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DE_POLARITY_HIGH
+ * @arg @ref LL_LPUART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx,
+ uint32_t Polarity) {
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
+ * @param LPUARTx LPUART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPUART_DE_POLARITY_HIGH
+ * @arg @ref LL_LPUART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) {
+ return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the LPUART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Noise error detected Flag is set or not
+ * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL
+ : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_RXNE \
+ LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty
+ * Flag is set or not
+ * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) {
+ return (
+ (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_TXE \
+ LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO
+ * Not Full Flag is set or not
+ * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART CTS interrupt Flag is set or not
+ * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART CTS Flag is set or not
+ * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
+ * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART TX FIFO Empty Flag is set or not
+ * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART RX FIFO Full Flag is set or not
+ * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
+ * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
+ * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise detected Flag
+ * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @brief Clear Wake Up from stop mode Flag
+ * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) {
+ WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_EnableIT_RXNE \
+ LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_EnableIT_TXE \
+ LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Enable TX Empty and TX FIFO Not Full Interrupt
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable TX FIFO Empty Interrupt
+ * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Enable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
+ * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
+ * NF=1 in the LPUARTx_ISR register).
+ * - 0: Interrupt is inhibited
+ * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the
+ * LPUARTx_ISR register.
+ * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable Wake Up from Stop Mode Interrupt
+ * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+ * @brief Enable TX FIFO Threshold Interrupt
+ * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Enable RX FIFO Threshold Interrupt
+ * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_DisableIT_RXNE \
+ LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_DisableIT_TXE \
+ LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Disable TX Empty and TX FIFO Not Full Interrupt
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable TX FIFO Empty Interrupt
+ * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Disable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
+ * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
+ * NF=1 in the LPUARTx_ISR register).
+ * - 0: Interrupt is inhibited
+ * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the
+ * LPUARTx_ISR register.
+ * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable Wake Up from Stop Mode Interrupt
+ * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+ * @brief Disable TX FIFO Threshold Interrupt
+ * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Disable RX FIFO Threshold Interrupt
+ * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE))
+ ? 1UL
+ : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_RXNE \
+ LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty
+ * Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) ==
+ (USART_CR1_RXNEIE_RXFNEIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Transmission Complete Interrupt is enabled or
+ * disabled.
+ * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL
+ : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_TXE \
+ LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is
+ * enabled or disabled
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) ==
+ (USART_CR1_TXEIE_TXFNFIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+ * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+ * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
+ * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or
+ * disabled.
+ * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+ * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+ * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) {
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) {
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) {
+ CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
+ * @param LPUARTx LPUART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) {
+ return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get the LPUART data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
+ * @param LPUARTx LPUART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx,
+ uint32_t Direction) {
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) & (LPUARTx->TDR);
+ } else {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) & (LPUARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_LPUART_ReceiveData8
+ * @param LPUARTx LPUART Instance
+ * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) {
+ return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_LPUART_ReceiveData9
+ * @param LPUARTx LPUART Instance
+ * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) {
+ return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_LPUART_TransmitData8
+ * @param LPUARTx LPUART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx,
+ uint8_t Value) {
+ LPUARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_LPUART_TransmitData9
+ * @param LPUARTx LPUART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx,
+ uint16_t Value) {
+ LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put LPUART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+ * @brief Request a Receive Data and FIFO flush
+ * @note Allows to discard the received data without reading them, and avoid
+ * an overrun condition.
+ * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+ * @brief Request a Transmit data FIFO flush
+ * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled.
+ * This also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) {
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx,
+ const LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPUART1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_LPUART_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h
index c976ecb..474cb15 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h
@@ -1,1527 +1,1529 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_PWR_H
-#define STM32G4xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_PWR_WriteReg function
- * @{
- */
-#define LL_PWR_SCR_CSBF PWR_SCR_CSBF
-#define LL_PWR_SCR_CWUF PWR_SCR_CWUF
-#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
-#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
-#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
-#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
-#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_PWR_ReadReg function
- * @{
- */
-#define LL_PWR_SR1_WUFI PWR_SR1_WUFI
-#define LL_PWR_SR1_SBF PWR_SR1_SBF
-#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
-#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
-#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
-#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
-#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
-#if defined(PWR_SR2_PVMO4)
-#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
-#endif /* PWR_SR2_PVMO4 */
-#if defined(PWR_SR2_PVMO3)
-#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
-#endif /* PWR_SR2_PVMO3 */
-#if defined(PWR_SR2_PVMO2)
-#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
-#endif /* PWR_SR2_PVMO2 */
-#if defined(PWR_SR2_PVMO1)
-#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
-#endif /* PWR_SR2_PVMO1 */
-#define LL_PWR_SR2_PVDO PWR_SR2_PVDO
-#define LL_PWR_SR2_VOSF PWR_SR2_VOSF
-#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
-#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
- * @{
- */
-#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
-#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
- * @{
- */
-#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
-#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
-#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
-#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
- * @{
- */
-#if defined(PWR_CR2_PVME1)
-#define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
-#endif
-#if defined(PWR_CR2_PVME2)
-#define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
-#endif
-#if defined(PWR_CR2_PVME3)
-#define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
-#endif
-#if defined(PWR_CR2_PVME4)
-#define LL_PWR_PVM_VDDA_OPAMP_DAC \
- (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
-#endif
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
- * @{
- */
-#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
-#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
-#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
-#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
-#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
-#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
-#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
-#define LL_PWR_PVDLEVEL_7 \
- (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to \
- VREFINT) */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
- * @{
- */
-#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
-#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
-#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
-#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
-#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
- * @{
- */
-#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
-#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GPIO GPIO
- * @{
- */
-#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
-#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
-#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
-#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
-#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
-#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
-#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
- * @{
- */
-#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
-#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
-#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
-#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
-#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
-#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
-#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
-#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
-#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
-#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
-#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
-#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
-#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
-#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
-#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
-#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in PWR register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in PWR register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Switch the regulator from main mode to low-power mode
- * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) {
- SET_BIT(PWR->CR1, PWR_CR1_LPR);
-}
-
-/**
- * @brief Switch the regulator from low-power mode to main mode
- * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) {
- CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
-}
-
-/**
- * @brief Check if the regulator is in low-power mode
- * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
-
- return ((temp == (PWR_CR1_LPR)) ? 1U : 0U);
-}
-
-/**
- * @brief Switch from run main mode to run low-power mode.
- * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) {
- LL_PWR_EnableLowPowerRunMode();
-}
-
-/**
- * @brief Switch from run main mode to low-power mode.
- * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) {
- LL_PWR_DisableLowPowerRunMode();
-}
-
-/**
- * @brief Set the main internal regulator output voltage
- * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
- * @param VoltageScaling This parameter can be one of the following values:
- * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
- * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) {
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
-}
-
-/**
- * @brief Get the main internal regulator output voltage
- * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
- * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
- */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) {
- return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
-}
-
-#if defined(PWR_CR5_R1MODE)
-/**
- * @brief Enable main regulator voltage range 1 boost mode
- * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) {
- CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
-}
-
-/**
- * @brief Disable main regulator voltage range 1 boost mode
- * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) {
- SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
-}
-
-/**
- * @brief Check if the main regulator voltage range 1 boost mode is enabled
- * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
- * @retval Inverted state of bit (0 or 1).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
-
- return ((temp == (0U)) ? 1U : 0U);
-}
-#endif /* PWR_CR5_R1MODE */
-
-/**
- * @brief Enable access to the backup domain
- * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) {
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain
- * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) {
- CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
- * @brief Check if the backup domain is enabled
- * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
-
- return ((temp == (PWR_CR1_DBP)) ? 1U : 0U);
-}
-
-/**
- * @brief Set Low-Power mode
- * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
- * @param LowPowerMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP0
- * @arg @ref LL_PWR_MODE_STOP1
- * @arg @ref LL_PWR_MODE_STANDBY
- * @arg @ref LL_PWR_MODE_SHUTDOWN
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) {
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
-}
-
-/**
- * @brief Get Low-Power mode
- * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP0
- * @arg @ref LL_PWR_MODE_STOP1
- * @arg @ref LL_PWR_MODE_STANDBY
- * @arg @ref LL_PWR_MODE_SHUTDOWN
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) {
- return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
-}
-
-#if defined(PWR_CR3_UCPD_STDBY)
-/**
- * @brief Enable the USB Type-C and Power Delivery memorization in Standby
- * mode.
- * @note This function must be called just before entering Standby mode.
- * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) {
- SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
-}
-
-/**
- * @brief Disable the USB Type-C and Power Delivery memorization in Standby
- * mode.
- * @note This function must be called after exiting Standby mode and before
- * any UCPD configuration update.
- * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
-}
-
-/**
- * @brief Check the USB Type-C and Power Delivery Standby mode memorization
- * state.
- * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) {
- return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY))
- ? 1UL
- : 0UL);
-}
-#endif /* PWR_CR3_UCPD_STDBY */
-
-#if defined(PWR_CR3_UCPD_DBDIS)
-/**
- * @brief Enable the USB Type-C and power delivery dead battery pull-down
- * behavior on UCPD CC1 and CC2 pins.
- * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
- * which may have a pull-down effect on CC1 and CC2 pins. It is
- * recommended to disable it in all cases, either to stop this pull-down or to
- * hand over control to the UCPD (which should therefore be initialized before
- * doing the disable).
- * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
-}
-
-/**
- * @brief Disable the USB Type-C and power delivery dead battery pull-down
- * behavior on UCPD CC1 and CC2 pins.
- * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
- * which may have a pull-down effect on CC1 and CC2 pins. It is
- * recommended to disable it in all cases, either to stop this pull-down or to
- * hand over control to the UCPD (which should therefore be initialized before
- * doing the disable).
- * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) {
- SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
-}
-
-/**
- * @brief Check the USB Type-C and power delivery dead battery pull-down
- * behavior on UCPD CC1 and CC2 pins.
- * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
- * which may have a pull-down effect on CC1 and CC2 pins. It is
- * recommended to disable it in all cases, either to stop this pull-down or to
- * hand over control to the UCPD (which should therefore be initialized before
- * doing the disable).
- * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
- * @retval State of feature (1 : enabled; 0 : disabled).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) {
- return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))
- ? 0UL
- : 1UL);
-}
-#endif /* PWR_CR3_UCPD_DBDIS */
-
-#if defined(PWR_CR2_USV)
-/**
- * @brief Enable VDDUSB supply
- * @rmtoll CR2 USV LL_PWR_EnableVddUSB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableVddUSB(void) {
- SET_BIT(PWR->CR2, PWR_CR2_USV);
-}
-
-/**
- * @brief Disable VDDUSB supply
- * @rmtoll CR2 USV LL_PWR_DisableVddUSB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableVddUSB(void) {
- CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
-}
-
-/**
- * @brief Check if VDDUSB supply is enabled
- * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
-
- return ((temp == (PWR_CR2_USV)) ? 1U : 0U);
-}
-#endif
-
-#if defined(PWR_CR2_IOSV)
-/**
- * @brief Enable VDDIO2 supply
- * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableVddIO2(void) {
- SET_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-/**
- * @brief Disable VDDIO2 supply
- * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableVddIO2(void) {
- CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-/**
- * @brief Check if VDDIO2 supply is enabled
- * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
-
- return ((temp == (PWR_CR2_IOSV)) ? 1U : 0U);
-}
-#endif
-
-/**
- * @brief Enable the Power Voltage Monitoring on a peripheral
- * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
- * CR2 PVME2 LL_PWR_EnablePVM\n
- * CR2 PVME3 LL_PWR_EnablePVM\n
- * CR2 PVME4 LL_PWR_EnablePVM
- * @param PeriphVoltage This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
- * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
- * @arg @ref LL_PWR_PVM_VDDA_ADC
- * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) {
- SET_BIT(PWR->CR2, PeriphVoltage);
-}
-
-/**
- * @brief Disable the Power Voltage Monitoring on a peripheral
- * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
- * CR2 PVME2 LL_PWR_DisablePVM\n
- * CR2 PVME3 LL_PWR_DisablePVM\n
- * CR2 PVME4 LL_PWR_DisablePVM
- * @param PeriphVoltage This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
- * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
- * @arg @ref LL_PWR_PVM_VDDA_ADC
- * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) {
- CLEAR_BIT(PWR->CR2, PeriphVoltage);
-}
-
-/**
- * @brief Check if Power Voltage Monitoring is enabled on a peripheral
- * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
- * CR2 PVME2 LL_PWR_IsEnabledPVM\n
- * CR2 PVME3 LL_PWR_IsEnabledPVM\n
- * CR2 PVME4 LL_PWR_IsEnabledPVM
- * @param PeriphVoltage This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
- * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
- * @arg @ref LL_PWR_PVM_VDDA_ADC
- * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
- *
- * (*) value not defined in all devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR2, PeriphVoltage);
-
- return ((temp == (PeriphVoltage)) ? 1U : 0U);
-}
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage
- * Detector
- * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
- * @param PVDLevel This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) {
- MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
-}
-
-/**
- * @brief Get the voltage threshold detection
- * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) {
- return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
-}
-
-/**
- * @brief Enable Power Voltage Detector
- * @rmtoll CR2 PVDE LL_PWR_EnablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePVD(void) { SET_BIT(PWR->CR2, PWR_CR2_PVDE); }
-
-/**
- * @brief Disable Power Voltage Detector
- * @rmtoll CR2 PVDE LL_PWR_DisablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePVD(void) {
- CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
-}
-
-/**
- * @brief Check if Power Voltage Detector is enabled
- * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
-
- return ((temp == (PWR_CR2_PVDE)) ? 1U : 0U);
-}
-
-/**
- * @brief Enable Internal Wake-up line
- * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableInternWU(void) {
- SET_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-/**
- * @brief Disable Internal Wake-up line
- * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableInternWU(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-/**
- * @brief Check if Internal Wake-up line is enabled
- * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) {
- return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable pull-up and pull-down configuration
- * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) {
- SET_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-/**
- * @brief Disable pull-up and pull-down configuration
- * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-/**
- * @brief Check if pull-up and pull-down configuration is enabled
- * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
-
- return ((temp == (PWR_CR3_APC)) ? 1U : 0U);
-}
-
-/**
- * @brief Enable SRAM2 content retention in Standby mode
- * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) {
- SET_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-/**
- * @brief Disable SRAM2 content retention in Standby mode
- * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-/**
- * @brief Check if SRAM2 content retention in Standby mode is enabled
- * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
-
- return ((temp == (PWR_CR3_RRS)) ? 1U : 0U);
-}
-
-/**
- * @brief Enable the WakeUp PINx functionality
- * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
- * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
- * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
- * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
- * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
- * @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) {
- SET_BIT(PWR->CR3, WakeUpPin);
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality
- * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
- * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
- * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
- * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
- * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
- * @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) {
- CLEAR_BIT(PWR->CR3, WakeUpPin);
-}
-
-/**
- * @brief Check if the WakeUp PINx functionality is enabled
- * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
- * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
- * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
- * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
- * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
- * @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR3, WakeUpPin);
-
- return ((temp == (WakeUpPin)) ? 1U : 0U);
-}
-
-/**
- * @brief Set the resistor impedance
- * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
- * @param Resistor This parameter can be one of the following values:
- * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
- * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) {
- MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
-}
-
-/**
- * @brief Get the resistor impedance
- * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
- * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
- */
-__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) {
- return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
-}
-
-/**
- * @brief Enable battery charging
- * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) {
- SET_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-/**
- * @brief Disable battery charging
- * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) {
- CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-/**
- * @brief Check if battery charging is enabled
- * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
-
- return ((temp == (PWR_CR4_VBE)) ? 1U : 0U);
-}
-
-/**
- * @brief Set the Wake-Up pin polarity low for the event detection
- * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
- * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
- * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
- * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
- * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
- * @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) {
- SET_BIT(PWR->CR4, WakeUpPin);
-}
-
-/**
- * @brief Set the Wake-Up pin polarity high for the event detection
- * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
- * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
- * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
- * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
- * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
- * @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) {
- CLEAR_BIT(PWR->CR4, WakeUpPin);
-}
-
-/**
- * @brief Get the Wake-Up pin polarity for the event detection
- * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
- * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
- * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
- * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
- * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
- * @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) {
- uint32_t temp;
- temp = READ_BIT(PWR->CR4, WakeUpPin);
-
- return ((temp == (WakeUpPin)) ? 1U : 0U);
-}
-
-/**
- * @brief Enable GPIO pull-up state in Standby and Shutdown modes
- * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
- * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
- * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
- * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
- * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
- * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
- * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
- * @param GPIO This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_A
- * @arg @ref LL_PWR_GPIO_B
- * @arg @ref LL_PWR_GPIO_C
- * @arg @ref LL_PWR_GPIO_D
- * @arg @ref LL_PWR_GPIO_E
- * @arg @ref LL_PWR_GPIO_F
- * @arg @ref LL_PWR_GPIO_G
- *
- * (*) value not defined in all devices
- * @param GPIONumber This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_BIT_0
- * @arg @ref LL_PWR_GPIO_BIT_1
- * @arg @ref LL_PWR_GPIO_BIT_2
- * @arg @ref LL_PWR_GPIO_BIT_3
- * @arg @ref LL_PWR_GPIO_BIT_4
- * @arg @ref LL_PWR_GPIO_BIT_5
- * @arg @ref LL_PWR_GPIO_BIT_6
- * @arg @ref LL_PWR_GPIO_BIT_7
- * @arg @ref LL_PWR_GPIO_BIT_8
- * @arg @ref LL_PWR_GPIO_BIT_9
- * @arg @ref LL_PWR_GPIO_BIT_10
- * @arg @ref LL_PWR_GPIO_BIT_11
- * @arg @ref LL_PWR_GPIO_BIT_12
- * @arg @ref LL_PWR_GPIO_BIT_13
- * @arg @ref LL_PWR_GPIO_BIT_14
- * @arg @ref LL_PWR_GPIO_BIT_15
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber) {
- SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
-}
-
-/**
- * @brief Disable GPIO pull-up state in Standby and Shutdown modes
- * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
- * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
- * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
- * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
- * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
- * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
- * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
- * @param GPIO This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_A
- * @arg @ref LL_PWR_GPIO_B
- * @arg @ref LL_PWR_GPIO_C
- * @arg @ref LL_PWR_GPIO_D
- * @arg @ref LL_PWR_GPIO_E
- * @arg @ref LL_PWR_GPIO_F
- * @arg @ref LL_PWR_GPIO_G
- *
- * (*) value not defined in all devices
- * @param GPIONumber This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_BIT_0
- * @arg @ref LL_PWR_GPIO_BIT_1
- * @arg @ref LL_PWR_GPIO_BIT_2
- * @arg @ref LL_PWR_GPIO_BIT_3
- * @arg @ref LL_PWR_GPIO_BIT_4
- * @arg @ref LL_PWR_GPIO_BIT_5
- * @arg @ref LL_PWR_GPIO_BIT_6
- * @arg @ref LL_PWR_GPIO_BIT_7
- * @arg @ref LL_PWR_GPIO_BIT_8
- * @arg @ref LL_PWR_GPIO_BIT_9
- * @arg @ref LL_PWR_GPIO_BIT_10
- * @arg @ref LL_PWR_GPIO_BIT_11
- * @arg @ref LL_PWR_GPIO_BIT_12
- * @arg @ref LL_PWR_GPIO_BIT_13
- * @arg @ref LL_PWR_GPIO_BIT_14
- * @arg @ref LL_PWR_GPIO_BIT_15
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber) {
- CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
-}
-
-/**
- * @brief Check if GPIO pull-up state is enabled
- * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
- * @param GPIO This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_A
- * @arg @ref LL_PWR_GPIO_B
- * @arg @ref LL_PWR_GPIO_C
- * @arg @ref LL_PWR_GPIO_D
- * @arg @ref LL_PWR_GPIO_E
- * @arg @ref LL_PWR_GPIO_F
- * @arg @ref LL_PWR_GPIO_G
- *
- * (*) value not defined in all devices
- * @param GPIONumber This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_BIT_0
- * @arg @ref LL_PWR_GPIO_BIT_1
- * @arg @ref LL_PWR_GPIO_BIT_2
- * @arg @ref LL_PWR_GPIO_BIT_3
- * @arg @ref LL_PWR_GPIO_BIT_4
- * @arg @ref LL_PWR_GPIO_BIT_5
- * @arg @ref LL_PWR_GPIO_BIT_6
- * @arg @ref LL_PWR_GPIO_BIT_7
- * @arg @ref LL_PWR_GPIO_BIT_8
- * @arg @ref LL_PWR_GPIO_BIT_9
- * @arg @ref LL_PWR_GPIO_BIT_10
- * @arg @ref LL_PWR_GPIO_BIT_11
- * @arg @ref LL_PWR_GPIO_BIT_12
- * @arg @ref LL_PWR_GPIO_BIT_13
- * @arg @ref LL_PWR_GPIO_BIT_14
- * @arg @ref LL_PWR_GPIO_BIT_15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber) {
- return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable GPIO pull-down state in Standby and Shutdown modes
- * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
- * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
- * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
- * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
- * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
- * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
- * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
- * @param GPIO This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_A
- * @arg @ref LL_PWR_GPIO_B
- * @arg @ref LL_PWR_GPIO_C
- * @arg @ref LL_PWR_GPIO_D
- * @arg @ref LL_PWR_GPIO_E
- * @arg @ref LL_PWR_GPIO_F
- * @arg @ref LL_PWR_GPIO_G
- *
- * (*) value not defined in all devices
- * @param GPIONumber This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_BIT_0
- * @arg @ref LL_PWR_GPIO_BIT_1
- * @arg @ref LL_PWR_GPIO_BIT_2
- * @arg @ref LL_PWR_GPIO_BIT_3
- * @arg @ref LL_PWR_GPIO_BIT_4
- * @arg @ref LL_PWR_GPIO_BIT_5
- * @arg @ref LL_PWR_GPIO_BIT_6
- * @arg @ref LL_PWR_GPIO_BIT_7
- * @arg @ref LL_PWR_GPIO_BIT_8
- * @arg @ref LL_PWR_GPIO_BIT_9
- * @arg @ref LL_PWR_GPIO_BIT_10
- * @arg @ref LL_PWR_GPIO_BIT_11
- * @arg @ref LL_PWR_GPIO_BIT_12
- * @arg @ref LL_PWR_GPIO_BIT_13
- * @arg @ref LL_PWR_GPIO_BIT_14
- * @arg @ref LL_PWR_GPIO_BIT_15
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber) {
- SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
-}
-
-/**
- * @brief Disable GPIO pull-down state in Standby and Shutdown modes
- * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
- * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
- * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
- * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
- * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
- * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
- * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
- * @param GPIO This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_A
- * @arg @ref LL_PWR_GPIO_B
- * @arg @ref LL_PWR_GPIO_C
- * @arg @ref LL_PWR_GPIO_D
- * @arg @ref LL_PWR_GPIO_E
- * @arg @ref LL_PWR_GPIO_F
- * @arg @ref LL_PWR_GPIO_G
- *
- * (*) value not defined in all devices
- * @param GPIONumber This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_BIT_0
- * @arg @ref LL_PWR_GPIO_BIT_1
- * @arg @ref LL_PWR_GPIO_BIT_2
- * @arg @ref LL_PWR_GPIO_BIT_3
- * @arg @ref LL_PWR_GPIO_BIT_4
- * @arg @ref LL_PWR_GPIO_BIT_5
- * @arg @ref LL_PWR_GPIO_BIT_6
- * @arg @ref LL_PWR_GPIO_BIT_7
- * @arg @ref LL_PWR_GPIO_BIT_8
- * @arg @ref LL_PWR_GPIO_BIT_9
- * @arg @ref LL_PWR_GPIO_BIT_10
- * @arg @ref LL_PWR_GPIO_BIT_11
- * @arg @ref LL_PWR_GPIO_BIT_12
- * @arg @ref LL_PWR_GPIO_BIT_13
- * @arg @ref LL_PWR_GPIO_BIT_14
- * @arg @ref LL_PWR_GPIO_BIT_15
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber) {
- CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
-}
-
-/**
- * @brief Check if GPIO pull-down state is enabled
- * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
- * @param GPIO This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_A
- * @arg @ref LL_PWR_GPIO_B
- * @arg @ref LL_PWR_GPIO_C
- * @arg @ref LL_PWR_GPIO_D
- * @arg @ref LL_PWR_GPIO_E
- * @arg @ref LL_PWR_GPIO_F
- * @arg @ref LL_PWR_GPIO_G
- *
- * (*) value not defined in all devices
- * @param GPIONumber This parameter can be one of the following values:
- * @arg @ref LL_PWR_GPIO_BIT_0
- * @arg @ref LL_PWR_GPIO_BIT_1
- * @arg @ref LL_PWR_GPIO_BIT_2
- * @arg @ref LL_PWR_GPIO_BIT_3
- * @arg @ref LL_PWR_GPIO_BIT_4
- * @arg @ref LL_PWR_GPIO_BIT_5
- * @arg @ref LL_PWR_GPIO_BIT_6
- * @arg @ref LL_PWR_GPIO_BIT_7
- * @arg @ref LL_PWR_GPIO_BIT_8
- * @arg @ref LL_PWR_GPIO_BIT_9
- * @arg @ref LL_PWR_GPIO_BIT_10
- * @arg @ref LL_PWR_GPIO_BIT_11
- * @arg @ref LL_PWR_GPIO_BIT_12
- * @arg @ref LL_PWR_GPIO_BIT_13
- * @arg @ref LL_PWR_GPIO_BIT_14
- * @arg @ref LL_PWR_GPIO_BIT_15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber) {
- return (
- (READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Internal Wake-up line Flag
- * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
-
- return ((temp == (PWR_SR1_WUFI)) ? 1U : 0U);
-}
-
-/**
- * @brief Get Stand-By Flag
- * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
-
- return ((temp == (PWR_SR1_SBF)) ? 1U : 0U);
-}
-
-/**
- * @brief Get Wake-up Flag 5
- * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
-
- return ((temp == (PWR_SR1_WUF5)) ? 1U : 0U);
-}
-
-/**
- * @brief Get Wake-up Flag 4
- * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
-
- return ((temp == (PWR_SR1_WUF4)) ? 1U : 0U);
-}
-
-/**
- * @brief Get Wake-up Flag 3
- * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
-
- return ((temp == (PWR_SR1_WUF3)) ? 1U : 0U);
-}
-
-/**
- * @brief Get Wake-up Flag 2
- * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
-
- return ((temp == (PWR_SR1_WUF2)) ? 1U : 0U);
-}
-
-/**
- * @brief Get Wake-up Flag 1
- * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
-
- return ((temp == (PWR_SR1_WUF1)) ? 1U : 0U);
-}
-
-/**
- * @brief Clear Stand-By Flag
- * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
-}
-
-/**
- * @brief Clear Wake-up Flags
- * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
-}
-
-/**
- * @brief Clear Wake-up Flag 5
- * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
-}
-
-/**
- * @brief Clear Wake-up Flag 4
- * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
-}
-
-/**
- * @brief Clear Wake-up Flag 3
- * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
-}
-
-/**
- * @brief Clear Wake-up Flag 2
- * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
-}
-
-/**
- * @brief Clear Wake-up Flag 1
- * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) {
- WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
-}
-
-/**
- * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
- * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
-
- return ((temp == (PWR_SR2_PVMO4)) ? 1U : 0U);
-}
-
-/**
- * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
- * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
-
- return ((temp == (PWR_SR2_PVMO3)) ? 1U : 0U);
-}
-
-#if defined(PWR_SR2_PVMO2)
-/**
- * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
- * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
-
- return ((temp == (PWR_SR2_PVMO2)) ? 1U : 0U);
-}
-#endif /* PWR_SR2_PVMO2 */
-
-#if defined(PWR_SR2_PVMO1)
-/**
- * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
- * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
-
- return ((temp == (PWR_SR2_PVMO1)) ? 1U : 0U);
-}
-#endif /* PWR_SR2_PVMO1 */
-
-/**
- * @brief Indicate whether VDD voltage is below or above the selected PVD
- * threshold
- * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
-
- return ((temp == (PWR_SR2_PVDO)) ? 1U : 0U);
-}
-
-/**
- * @brief Indicate whether the regulator is ready in the selected voltage range
- * or if its output voltage is still changing to the required voltage level
- * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
-
- return ((temp == (PWR_SR2_VOSF)) ? 1U : 0U);
-}
-
-/**
- * @brief Indicate whether the regulator is ready in main mode or is in
- * low-power mode
- * @note: Take care, return value "0" means the regulator is ready. Return
- * value "1" means the output voltage range is still changing.
- * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
-
- return ((temp == (PWR_SR2_REGLPF)) ? 1U : 0U);
-}
-
-/**
- * @brief Indicate whether or not the low-power regulator is ready
- * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) {
- uint32_t temp;
- temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
-
- return ((temp == (PWR_SR2_REGLPS)) ? 1U : 0U);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_PWR_DeInit(void);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
- * @{
- */
-/* Old functions name kept for legacy purpose, to be replaced by the */
-/* current functions name. */
-#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
-#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
-#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
-#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
-#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
-#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
-#define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
-#define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
-#define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
-#define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
-#define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(PWR) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_PWR_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_PWR_H
+#define STM32G4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_SCR_CSBF PWR_SCR_CSBF
+#define LL_PWR_SCR_CWUF PWR_SCR_CWUF
+#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
+#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
+#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
+#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
+#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_SR1_WUFI PWR_SR1_WUFI
+#define LL_PWR_SR1_SBF PWR_SR1_SBF
+#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
+#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
+#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
+#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
+#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
+#if defined(PWR_SR2_PVMO4)
+#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
+#endif /* PWR_SR2_PVMO4 */
+#if defined(PWR_SR2_PVMO3)
+#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
+#endif /* PWR_SR2_PVMO3 */
+#if defined(PWR_SR2_PVMO2)
+#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
+#endif /* PWR_SR2_PVMO2 */
+#if defined(PWR_SR2_PVMO1)
+#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
+#endif /* PWR_SR2_PVMO1 */
+#define LL_PWR_SR2_PVDO PWR_SR2_PVDO
+#define LL_PWR_SR2_VOSF PWR_SR2_VOSF
+#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
+#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
+ * @{
+ */
+#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
+ * @{
+ */
+#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
+#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
+#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
+#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
+ * @{
+ */
+#if defined(PWR_CR2_PVME1)
+#define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
+#endif
+#if defined(PWR_CR2_PVME2)
+#define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
+#endif
+#if defined(PWR_CR2_PVME3)
+#define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
+#endif
+#if defined(PWR_CR2_PVME4)
+#define LL_PWR_PVM_VDDA_OPAMP_DAC \
+ (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
+#define LL_PWR_PVDLEVEL_7 \
+ (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to \
+ VREFINT) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
+#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
+#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
+#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
+#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
+ * @{
+ */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GPIO GPIO
+ * @{
+ */
+#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
+#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
+#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
+#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
+#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
+#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
+#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
+ * @{
+ */
+#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
+#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
+#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
+#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
+#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
+#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
+#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
+#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
+#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
+#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
+#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
+#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
+#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
+#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
+#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
+#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Switch the regulator from main mode to low-power mode
+ * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) {
+ SET_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+ * @brief Switch the regulator from low-power mode to main mode
+ * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) {
+ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+ * @brief Check if the regulator is in low-power mode
+ * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
+
+ return ((temp == (PWR_CR1_LPR)) ? 1U : 0U);
+}
+
+/**
+ * @brief Switch from run main mode to run low-power mode.
+ * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) {
+ LL_PWR_EnableLowPowerRunMode();
+}
+
+/**
+ * @brief Switch from run main mode to low-power mode.
+ * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) {
+ LL_PWR_DisableLowPowerRunMode();
+}
+
+/**
+ * @brief Set the main internal regulator output voltage
+ * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
+ * @param VoltageScaling This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) {
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
+}
+
+/**
+ * @brief Get the main internal regulator output voltage
+ * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) {
+ return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
+}
+
+#if defined(PWR_CR5_R1MODE)
+/**
+ * @brief Enable main regulator voltage range 1 boost mode
+ * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) {
+ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+}
+
+/**
+ * @brief Disable main regulator voltage range 1 boost mode
+ * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) {
+ SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+}
+
+/**
+ * @brief Check if the main regulator voltage range 1 boost mode is enabled
+ * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
+
+ return ((temp == (0U)) ? 1U : 0U);
+}
+#endif /* PWR_CR5_R1MODE */
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) {
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) {
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
+
+ return ((temp == (PWR_CR1_DBP)) ? 1U : 0U);
+}
+
+/**
+ * @brief Set Low-Power mode
+ * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP0
+ * @arg @ref LL_PWR_MODE_STOP1
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @arg @ref LL_PWR_MODE_SHUTDOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) {
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
+}
+
+/**
+ * @brief Get Low-Power mode
+ * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP0
+ * @arg @ref LL_PWR_MODE_STOP1
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @arg @ref LL_PWR_MODE_SHUTDOWN
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) {
+ return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
+}
+
+#if defined(PWR_CR3_UCPD_STDBY)
+/**
+ * @brief Enable the USB Type-C and Power Delivery memorization in Standby
+ * mode.
+ * @note This function must be called just before entering Standby mode.
+ * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+
+/**
+ * @brief Disable the USB Type-C and Power Delivery memorization in Standby
+ * mode.
+ * @note This function must be called after exiting Standby mode and before
+ * any UCPD configuration update.
+ * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+
+/**
+ * @brief Check the USB Type-C and Power Delivery Standby mode memorization
+ * state.
+ * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) {
+ return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY))
+ ? 1UL
+ : 0UL);
+}
+#endif /* PWR_CR3_UCPD_STDBY */
+
+#if defined(PWR_CR3_UCPD_DBDIS)
+/**
+ * @brief Enable the USB Type-C and power delivery dead battery pull-down
+ * behavior on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is
+ * recommended to disable it in all cases, either to stop this pull-down or to
+ * hand over control to the UCPD (which should therefore be initialized before
+ * doing the disable).
+ * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+
+/**
+ * @brief Disable the USB Type-C and power delivery dead battery pull-down
+ * behavior on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is
+ * recommended to disable it in all cases, either to stop this pull-down or to
+ * hand over control to the UCPD (which should therefore be initialized before
+ * doing the disable).
+ * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+
+/**
+ * @brief Check the USB Type-C and power delivery dead battery pull-down
+ * behavior on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is
+ * recommended to disable it in all cases, either to stop this pull-down or to
+ * hand over control to the UCPD (which should therefore be initialized before
+ * doing the disable).
+ * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
+ * @retval State of feature (1 : enabled; 0 : disabled).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) {
+ return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))
+ ? 0UL
+ : 1UL);
+}
+#endif /* PWR_CR3_UCPD_DBDIS */
+
+#if defined(PWR_CR2_USV)
+/**
+ * @brief Enable VDDUSB supply
+ * @rmtoll CR2 USV LL_PWR_EnableVddUSB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVddUSB(void) {
+ SET_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+ * @brief Disable VDDUSB supply
+ * @rmtoll CR2 USV LL_PWR_DisableVddUSB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVddUSB(void) {
+ CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+ * @brief Check if VDDUSB supply is enabled
+ * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
+
+ return ((temp == (PWR_CR2_USV)) ? 1U : 0U);
+}
+#endif
+
+#if defined(PWR_CR2_IOSV)
+/**
+ * @brief Enable VDDIO2 supply
+ * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVddIO2(void) {
+ SET_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+ * @brief Disable VDDIO2 supply
+ * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVddIO2(void) {
+ CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+ * @brief Check if VDDIO2 supply is enabled
+ * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
+
+ return ((temp == (PWR_CR2_IOSV)) ? 1U : 0U);
+}
+#endif
+
+/**
+ * @brief Enable the Power Voltage Monitoring on a peripheral
+ * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
+ * CR2 PVME2 LL_PWR_EnablePVM\n
+ * CR2 PVME3 LL_PWR_EnablePVM\n
+ * CR2 PVME4 LL_PWR_EnablePVM
+ * @param PeriphVoltage This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
+ * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
+ * @arg @ref LL_PWR_PVM_VDDA_ADC
+ * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) {
+ SET_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+ * @brief Disable the Power Voltage Monitoring on a peripheral
+ * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
+ * CR2 PVME2 LL_PWR_DisablePVM\n
+ * CR2 PVME3 LL_PWR_DisablePVM\n
+ * CR2 PVME4 LL_PWR_DisablePVM
+ * @param PeriphVoltage This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
+ * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
+ * @arg @ref LL_PWR_PVM_VDDA_ADC
+ * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) {
+ CLEAR_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+ * @brief Check if Power Voltage Monitoring is enabled on a peripheral
+ * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
+ * CR2 PVME2 LL_PWR_IsEnabledPVM\n
+ * CR2 PVME3 LL_PWR_IsEnabledPVM\n
+ * CR2 PVME4 LL_PWR_IsEnabledPVM
+ * @param PeriphVoltage This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
+ * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
+ * @arg @ref LL_PWR_PVM_VDDA_ADC
+ * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
+ *
+ * (*) value not defined in all devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR2, PeriphVoltage);
+
+ return ((temp == (PeriphVoltage)) ? 1U : 0U);
+}
+
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage
+ * Detector
+ * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) {
+ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) {
+ return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR2 PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void) { SET_BIT(PWR->CR2, PWR_CR2_PVDE); }
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR2 PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void) {
+ CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
+
+ return ((temp == (PWR_CR2_PVDE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable Internal Wake-up line
+ * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableInternWU(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+ * @brief Disable Internal Wake-up line
+ * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableInternWU(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+ * @brief Check if Internal Wake-up line is enabled
+ * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) {
+ return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable pull-up and pull-down configuration
+ * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+ * @brief Disable pull-up and pull-down configuration
+ * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+ * @brief Check if pull-up and pull-down configuration is enabled
+ * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
+
+ return ((temp == (PWR_CR3_APC)) ? 1U : 0U);
+}
+
+#if defined(SRAM2_BASE)
+/**
+ * @brief Enable SRAM2 content retention in Standby mode
+ * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+ * @brief Disable SRAM2 content retention in Standby mode
+ * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+ * @brief Check if SRAM2 content retention in Standby mode is enabled
+ * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
+
+ return ((temp == (PWR_CR3_RRS)) ? 1U : 0U);
+}
+
+#endif /* SRAM2_BASE */
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) {
+ SET_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) {
+ CLEAR_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR3, WakeUpPin);
+
+ return ((temp == (WakeUpPin)) ? 1U : 0U);
+}
+
+/**
+ * @brief Set the resistor impedance
+ * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
+ * @param Resistor This parameter can be one of the following values:
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+ * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) {
+ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
+}
+
+/**
+ * @brief Get the resistor impedance
+ * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+ * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) {
+ return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
+}
+
+/**
+ * @brief Enable battery charging
+ * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) {
+ SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+ * @brief Disable battery charging
+ * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) {
+ CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+ * @brief Check if battery charging is enabled
+ * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
+
+ return ((temp == (PWR_CR4_VBE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Set the Wake-Up pin polarity low for the event detection
+ * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) {
+ SET_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+ * @brief Set the Wake-Up pin polarity high for the event detection
+ * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) {
+ CLEAR_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+ * @brief Get the Wake-Up pin polarity for the event detection
+ * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->CR4, WakeUpPin);
+
+ return ((temp == (WakeUpPin)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable GPIO pull-up state in Standby and Shutdown modes
+ * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F
+ * @arg @ref LL_PWR_GPIO_G
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+ * @brief Disable GPIO pull-up state in Standby and Shutdown modes
+ * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F
+ * @arg @ref LL_PWR_GPIO_G
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+ * @brief Check if GPIO pull-up state is enabled
+ * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F
+ * @arg @ref LL_PWR_GPIO_G
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable GPIO pull-down state in Standby and Shutdown modes
+ * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F
+ * @arg @ref LL_PWR_GPIO_G
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
+}
+
+/**
+ * @brief Disable GPIO pull-down state in Standby and Shutdown modes
+ * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F
+ * @arg @ref LL_PWR_GPIO_G
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
+}
+
+/**
+ * @brief Check if GPIO pull-down state is enabled
+ * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F
+ * @arg @ref LL_PWR_GPIO_G
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ return (
+ (READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Internal Wake-up line Flag
+ * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
+
+ return ((temp == (PWR_SR1_WUFI)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Stand-By Flag
+ * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
+
+ return ((temp == (PWR_SR1_SBF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wake-up Flag 5
+ * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
+
+ return ((temp == (PWR_SR1_WUF5)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wake-up Flag 4
+ * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
+
+ return ((temp == (PWR_SR1_WUF4)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wake-up Flag 3
+ * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
+
+ return ((temp == (PWR_SR1_WUF3)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wake-up Flag 2
+ * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
+
+ return ((temp == (PWR_SR1_WUF2)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get Wake-up Flag 1
+ * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
+
+ return ((temp == (PWR_SR1_WUF1)) ? 1U : 0U);
+}
+
+/**
+ * @brief Clear Stand-By Flag
+ * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
+}
+
+/**
+ * @brief Clear Wake-up Flag 5
+ * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
+}
+
+/**
+ * @brief Clear Wake-up Flag 4
+ * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
+}
+
+/**
+ * @brief Clear Wake-up Flag 3
+ * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
+}
+
+/**
+ * @brief Clear Wake-up Flag 2
+ * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
+}
+
+/**
+ * @brief Clear Wake-up Flag 1
+ * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) {
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
+}
+
+/**
+ * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
+ * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
+
+ return ((temp == (PWR_SR2_PVMO4)) ? 1U : 0U);
+}
+
+/**
+ * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
+ * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
+
+ return ((temp == (PWR_SR2_PVMO3)) ? 1U : 0U);
+}
+
+#if defined(PWR_SR2_PVMO2)
+/**
+ * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
+ * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
+
+ return ((temp == (PWR_SR2_PVMO2)) ? 1U : 0U);
+}
+#endif /* PWR_SR2_PVMO2 */
+
+#if defined(PWR_SR2_PVMO1)
+/**
+ * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
+ * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
+
+ return ((temp == (PWR_SR2_PVMO1)) ? 1U : 0U);
+}
+#endif /* PWR_SR2_PVMO1 */
+
+/**
+ * @brief Indicate whether VDD voltage is below or above the selected PVD
+ * threshold
+ * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
+
+ return ((temp == (PWR_SR2_PVDO)) ? 1U : 0U);
+}
+
+/**
+ * @brief Indicate whether the regulator is ready in the selected voltage range
+ * or if its output voltage is still changing to the required voltage level
+ * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
+
+ return ((temp == (PWR_SR2_VOSF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Indicate whether the regulator is ready in main mode or is in
+ * low-power mode
+ * @note: Take care, return value "0" means the regulator is ready. Return
+ * value "1" means the output voltage range is still changing.
+ * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
+
+ return ((temp == (PWR_SR2_REGLPF)) ? 1U : 0U);
+}
+
+/**
+ * @brief Indicate whether or not the low-power regulator is ready
+ * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) {
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
+
+ return ((temp == (PWR_SR2_REGLPS)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
+ * @{
+ */
+/* Old functions name kept for legacy purpose, to be replaced by the */
+/* current functions name. */
+#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
+#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
+#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
+#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
+#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
+#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
+#define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
+#define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
+#define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
+#define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
+#define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_PWR_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h
index 8fc9ac2..c51d34e 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h
@@ -1,3264 +1,3287 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_RCC_H
-#define STM32G4xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Constants RCC Private Constants
- * @{
- */
-/* Defines used to perform offsets*/
-/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
-#define RCC_OFFSET_CCIPR 0U
-#define RCC_OFFSET_CCIPR2 0x14U
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
- * @{
- */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
- * @{
- */
-
-/**
- * @brief RCC Clocks Frequency Structure
- */
-typedef struct {
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
- * @brief Defines used to adapt values of different oscillators
- * @note These values could be modified in the user environment according to
- * HW set-up.
- * @{
- */
-#if !defined(HSE_VALUE)
-#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined(HSI_VALUE)
-#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined(LSE_VALUE)
-#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined(LSI_VALUE)
-#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-
-#if !defined(HSI48_VALUE)
-#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
-#endif /* HSI48_VALUE */
-
-#if !defined(EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE \
- 48000U /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz \
- */
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_RCC_WriteReg function
- * @{
- */
-#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CICR_HSI48RDYC \
- RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
-#define LL_RCC_CICR_LSECSSC \
- RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
-#define LL_RCC_CICR_CSSC \
- RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RCC_ReadReg function
- * @{
- */
-#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIFR_HSI48RDYF \
- RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
-#define LL_RCC_CIFR_LSECSSF \
- RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
-#define LL_RCC_CIFR_CSSF \
- RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
-#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
-#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF \
- RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF \
- RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag \
- */
-#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RCC_ReadReg and
- * LL_RCC_WriteReg functions
- * @{
- */
-#define LL_RCC_CIER_LSIRDYIE \
- RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIER_LSERDYIE \
- RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIER_HSIRDYIE \
- RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIER_HSERDYIE \
- RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIER_PLLRDYIE \
- RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIER_HSI48RDYIE \
- RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
-#define LL_RCC_CIER_LSECSSIE \
- RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable \
- */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
- * @{
- */
-#define LL_RCC_LSEDRIVE_LOW \
- 0x00000000U /*!< Xtal mode lower driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMLOW \
- RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMHIGH \
- RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
-#define LL_RCC_LSEDRIVE_HIGH \
- RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
- * @{
- */
-#define LL_RCC_LSCO_CLKSOURCE_LSI \
- 0x00000000U /*!< LSI selection for low speed clock */
-#define LL_RCC_LSCO_CLKSOURCE_LSE \
- RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_HSI \
- RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE \
- RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL \
- RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI \
- RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE \
- RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL \
- RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
- * @{
- */
-#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 \
- RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 \
- */
-#define LL_RCC_SYSCLK_DIV_256 \
- RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 \
- */
-#define LL_RCC_SYSCLK_DIV_512 \
- RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 \
- */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
- * @{
- */
-#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
- * @{
- */
-#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
- * @{
- */
-#define LL_RCC_MCO1SOURCE_NOCLOCK \
- 0x00000000U /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK \
- RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSI \
- (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source \
- */
-#define LL_RCC_MCO1SOURCE_HSE \
- RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_PLLCLK \
- (RCC_CFGR_MCOSEL_0 | \
- RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSI \
- (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSE \
- (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1 | \
- RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSI48 \
- RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
- * @{
- */
-#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
-#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
-#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
-#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
-#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
- * @{
- */
-#define LL_RCC_PERIPH_FREQUENCY_NO \
- 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA \
- 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source
- * selection
- * @{
- */
-#define LL_RCC_USART1_CLKSOURCE_PCLK2 \
- (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_SYSCLK \
- ((RCC_CCIPR_USART1SEL << 16U) | \
- RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_HSI \
- ((RCC_CCIPR_USART1SEL << 16U) | \
- RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_LSE \
- ((RCC_CCIPR_USART1SEL << 16U) | \
- RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
-#define LL_RCC_USART2_CLKSOURCE_PCLK1 \
- (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_SYSCLK \
- ((RCC_CCIPR_USART2SEL << 16U) | \
- RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_HSI \
- ((RCC_CCIPR_USART2SEL << 16U) | \
- RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_LSE \
- ((RCC_CCIPR_USART2SEL << 16U) | \
- RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
-#define LL_RCC_USART3_CLKSOURCE_PCLK1 \
- (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_SYSCLK \
- ((RCC_CCIPR_USART3SEL << 16U) | \
- RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_HSI \
- ((RCC_CCIPR_USART3SEL << 16U) | \
- RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_LSE \
- ((RCC_CCIPR_USART3SEL << 16U) | \
- RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
- * @{
- */
-#if defined(RCC_CCIPR_UART4SEL)
-#define LL_RCC_UART4_CLKSOURCE_PCLK1 \
- (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
-#define LL_RCC_UART4_CLKSOURCE_SYSCLK \
- ((RCC_CCIPR_UART4SEL << 16U) | \
- RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
-#define LL_RCC_UART4_CLKSOURCE_HSI \
- ((RCC_CCIPR_UART4SEL << 16U) | \
- RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
-#define LL_RCC_UART4_CLKSOURCE_LSE \
- ((RCC_CCIPR_UART4SEL << 16U) | \
- RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
-#endif /* RCC_CCIPR_UART4SEL */
-#if defined(RCC_CCIPR_UART5SEL)
-#define LL_RCC_UART5_CLKSOURCE_PCLK1 \
- (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
-#define LL_RCC_UART5_CLKSOURCE_SYSCLK \
- ((RCC_CCIPR_UART5SEL << 16U) | \
- RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
-#define LL_RCC_UART5_CLKSOURCE_HSI \
- ((RCC_CCIPR_UART5SEL << 16U) | \
- RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
-#define LL_RCC_UART5_CLKSOURCE_LSE \
- ((RCC_CCIPR_UART5SEL << 16U) | \
- RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
-#endif /* RCC_CCIPR_UART5SEL */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source
- * selection
- * @{
- */
-#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 \
- 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
-#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK \
- RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
-#define LL_RCC_LPUART1_CLKSOURCE_HSI \
- RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
-#define LL_RCC_LPUART1_CLKSOURCE_LSE \
- RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
- * @{
- */
-#define LL_RCC_I2C1_CLKSOURCE_PCLK1 \
- ( \
- (RCC_OFFSET_CCIPR << 24U) | \
- (RCC_CCIPR_I2C1SEL_Pos \
- << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_SYSCLK \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C1SEL_0 >> \
- RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_HSI \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C1SEL_1 >> \
- RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_PCLK1 \
- ( \
- (RCC_OFFSET_CCIPR << 24U) | \
- (RCC_CCIPR_I2C2SEL_Pos \
- << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_SYSCLK \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C2SEL_0 >> \
- RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_HSI \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C2SEL_1 >> \
- RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_PCLK1 \
- ( \
- (RCC_OFFSET_CCIPR << 24U) | \
- (RCC_CCIPR_I2C3SEL_Pos \
- << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_SYSCLK \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C3SEL_0 >> \
- RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_HSI \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C3SEL_1 >> \
- RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
-#if defined(RCC_CCIPR2_I2C4SEL)
-#define LL_RCC_I2C4_CLKSOURCE_PCLK1 \
- ( \
- (RCC_OFFSET_CCIPR2 << 24U) | \
- (RCC_CCIPR2_I2C4SEL_Pos \
- << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
-#define LL_RCC_I2C4_CLKSOURCE_SYSCLK \
- ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | \
- (RCC_CCIPR2_I2C4SEL_0 >> \
- RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
-#define LL_RCC_I2C4_CLKSOURCE_HSI \
- ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | \
- (RCC_CCIPR2_I2C4SEL_1 >> \
- RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
-#endif /* RCC_CCIPR2_I2C4SEL */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source
- * selection
- * @{
- */
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 \
- 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock source */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI \
- RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock used as LPTIM1 clock source */
-#define LL_RCC_LPTIM1_CLKSOURCE_HSI \
- RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock used as LPTIM1 clock source */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE \
- RCC_CCIPR_LPTIM1SEL /*!< LSE clock used as LPTIM1 clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
- * @{
- */
-#define LL_RCC_SAI1_CLKSOURCE_SYSCLK \
- 0x00000000U /*!< System clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PLL \
- RCC_CCIPR_SAI1SEL_0 /*!< PLL clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PIN \
- RCC_CCIPR_SAI1SEL_1 /*!< EXT clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_HSI \
- (RCC_CCIPR_SAI1SEL_0 | \
- RCC_CCIPR_SAI1SEL_1) /*!< HSI clock used as SAI1 clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
- * @{
- */
-#define LL_RCC_I2S_CLKSOURCE_SYSCLK \
- 0x00000000U /*!< System clock used as I2S clock source */
-#define LL_RCC_I2S_CLKSOURCE_PLL \
- RCC_CCIPR_I2S23SEL_0 /*!< PLL clock used as I2S clock source */
-#define LL_RCC_I2S_CLKSOURCE_PIN \
- RCC_CCIPR_I2S23SEL_1 /*!< EXT clock used as I2S clock source */
-#define LL_RCC_I2S_CLKSOURCE_HSI \
- (RCC_CCIPR_I2S23SEL_0 | \
- RCC_CCIPR_I2S23SEL_1) /*!< HSI clock used as I2S clock source */
-/**
- * @}
- */
-
-#if defined(FDCAN1)
-/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
- * @{
- */
-#define LL_RCC_FDCAN_CLKSOURCE_HSE \
- 0x00000000U /*!< HSE clock used as FDCAN clock source */
-#define LL_RCC_FDCAN_CLKSOURCE_PLL \
- RCC_CCIPR_FDCANSEL_0 /*!< PLL clock used as FDCAN clock source */
-#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 \
- RCC_CCIPR_FDCANSEL_1 /*!< PCLK1 clock used as FDCAN clock source */
-/**
- * @}
- */
-#endif /* FDCAN1 */
-
-/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
- * @{
- */
-#define LL_RCC_RNG_CLKSOURCE_HSI48 \
- 0x00000000U /*!< HSI48 clock used as RNG clock source */
-#define LL_RCC_RNG_CLKSOURCE_PLL \
- RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
- * @{
- */
-#define LL_RCC_USB_CLKSOURCE_HSI48 \
- 0x00000000U /*!< HSI48 clock used as USB clock source */
-#define LL_RCC_USB_CLKSOURCE_PLL \
- RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
- * @{
- */
-#define LL_RCC_ADC12_CLKSOURCE_NONE \
- ( \
- (RCC_OFFSET_CCIPR << 24U) | \
- (RCC_CCIPR_ADC12SEL_Pos \
- << 16U)) /*!< No clock used as ADC12 clock source */
-#define LL_RCC_ADC12_CLKSOURCE_PLL \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | \
- (RCC_CCIPR_ADC12SEL_0 >> \
- RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */
-#define LL_RCC_ADC12_CLKSOURCE_SYSCLK \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | \
- (RCC_CCIPR_ADC12SEL_1 >> \
- RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */
-#if defined(RCC_CCIPR_ADC345SEL)
-#define LL_RCC_ADC345_CLKSOURCE_NONE \
- ((RCC_OFFSET_CCIPR << 24U) | \
- (RCC_CCIPR_ADC345SEL_Pos \
- << 16U)) /*!< No clock used as ADC345 clock source */
-#define LL_RCC_ADC345_CLKSOURCE_PLL \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | \
- (RCC_CCIPR_ADC345SEL_0 >> \
- RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
-#define LL_RCC_ADC345_CLKSOURCE_SYSCLK \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | \
- (RCC_CCIPR_ADC345SEL_1 >> \
- RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
-#endif /* RCC_CCIPR_ADC345SEL */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
- * @{
- */
-#define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK \
- 0x00000000U /*!< SYSCLK used as QuadSPI clock source */
-#define LL_RCC_QUADSPI_CLKSOURCE_HSI \
- RCC_CCIPR2_QSPISEL_0 /*!< HSI used as QuadSPI clock source */
-#define LL_RCC_QUADSPI_CLKSOURCE_PLL \
- RCC_CCIPR2_QSPISEL_1 /*!< PLL used as QuadSPI clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
- * @{
- */
-#define LL_RCC_USART1_CLKSOURCE \
- RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
-#define LL_RCC_USART2_CLKSOURCE \
- RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
-#define LL_RCC_USART3_CLKSOURCE \
- RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
- * @{
- */
-#if defined(RCC_CCIPR_UART4SEL)
-#define LL_RCC_UART4_CLKSOURCE \
- RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
-#endif /* RCC_CCIPR_UART4SEL */
-#if defined(RCC_CCIPR_UART5SEL)
-#define LL_RCC_UART5_CLKSOURCE \
- RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
-#endif /* RCC_CCIPR_UART5SEL */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
- * @{
- */
-#define LL_RCC_LPUART1_CLKSOURCE \
- RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
- * @{
- */
-#define LL_RCC_I2C1_CLKSOURCE \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C1SEL >> \
- RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
-#define LL_RCC_I2C2_CLKSOURCE \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C2SEL >> \
- RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
-#define LL_RCC_I2C3_CLKSOURCE \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | \
- (RCC_CCIPR_I2C3SEL >> \
- RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
-#if defined(RCC_CCIPR2_I2C4SEL)
-#define LL_RCC_I2C4_CLKSOURCE \
- ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | \
- (RCC_CCIPR2_I2C4SEL >> \
- RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
-#endif /* RCC_CCIPR2_I2C4SEL */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
- * @{
- */
-#define LL_RCC_LPTIM1_CLKSOURCE \
- RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
- * @{
- */
-#define LL_RCC_SAI1_CLKSOURCE \
- RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
- * @{
- */
-#define LL_RCC_I2S_CLKSOURCE \
- RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
-/**
- * @}
- */
-
-#if defined(FDCAN1)
-/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
- * @{
- */
-#define LL_RCC_FDCAN_CLKSOURCE \
- RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
-#endif /* FDCAN1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
- * @{
- */
-#define LL_RCC_RNG_CLKSOURCE \
- RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
- * @{
- */
-#define LL_RCC_USB_CLKSOURCE \
- RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
- * @{
- */
-#define LL_RCC_ADC12_CLKSOURCE \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | \
- (RCC_CCIPR_ADC12SEL >> \
- RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */
-#if defined(RCC_CCIPR_ADC345SEL_Pos)
-#define LL_RCC_ADC345_CLKSOURCE \
- ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | \
- (RCC_CCIPR_ADC345SEL >> \
- RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
-#endif /* RCC_CCIPR_ADC345SEL_Pos */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
- * @{
- */
-#define LL_RCC_QUADSPI_CLKSOURCE \
- RCC_CCIPR2_QSPISEL /*!< QuadSPI Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
- * @{
- */
-#define LL_RCC_RTC_CLKSOURCE_NONE \
- 0x00000000U /*!< No clock used as RTC clock \
- */
-#define LL_RCC_RTC_CLKSOURCE_LSE \
- RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI \
- RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 \
- RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
- * @{
- */
-#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
-#define LL_RCC_PLLSOURCE_HSI \
- RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source \
- */
-#define LL_RCC_PLLSOURCE_HSE \
- RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
- * @{
- */
-#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
-#define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0 /*!< PLL division factor by 2 */
-#define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1 /*!< PLL division factor by 3 */
-#define LL_RCC_PLLM_DIV_4 \
- (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 4 */
-#define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2 /*!< PLL division factor by 5 */
-#define LL_RCC_PLLM_DIV_6 \
- (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 6 */
-#define LL_RCC_PLLM_DIV_7 \
- (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 7 */
-#define LL_RCC_PLLM_DIV_8 \
- (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | \
- RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 8 */
-#define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3 /*!< PLL division factor by 9 */
-#define LL_RCC_PLLM_DIV_10 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 10 */
-#define LL_RCC_PLLM_DIV_11 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 11 */
-#define LL_RCC_PLLM_DIV_12 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | \
- RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 12 */
-#define LL_RCC_PLLM_DIV_13 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 13 */
-#define LL_RCC_PLLM_DIV_14 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | \
- RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 14 */
-#define LL_RCC_PLLM_DIV_15 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | \
- RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 15 */
-#define LL_RCC_PLLM_DIV_16 \
- (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | \
- RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
- * @{
- */
-#define LL_RCC_PLLR_DIV_2 \
- 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
-#define LL_RCC_PLLR_DIV_4 \
- (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) \
- by 4 */
-#define LL_RCC_PLLR_DIV_6 \
- (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) \
- by 6 */
-#define LL_RCC_PLLR_DIV_8 \
- (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) \
- by 8 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
- * @{
- */
-#define LL_RCC_PLLP_DIV_2 \
- (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 \
- */
-#define LL_RCC_PLLP_DIV_3 \
- (RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 \
- */
-#define LL_RCC_PLLP_DIV_4 \
- (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 \
- */
-#define LL_RCC_PLLP_DIV_5 \
- (RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 \
- */
-#define LL_RCC_PLLP_DIV_6 \
- (RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 \
- */
-#define LL_RCC_PLLP_DIV_7 \
- (RCC_PLLCFGR_PLLPDIV_2 | RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 \
- */
-#define LL_RCC_PLLP_DIV_8 \
- (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 \
- */
-#define LL_RCC_PLLP_DIV_9 \
- (RCC_PLLCFGR_PLLPDIV_3 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 \
- */
-#define LL_RCC_PLLP_DIV_10 \
- (RCC_PLLCFGR_PLLPDIV_3 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 \
- */
-#define LL_RCC_PLLP_DIV_11 \
- (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 \
- */
-#define LL_RCC_PLLP_DIV_12 \
- (RCC_PLLCFGR_PLLPDIV_3 | \
- RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 \
- */
-#define LL_RCC_PLLP_DIV_13 \
- (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 \
- */
-#define LL_RCC_PLLP_DIV_14 \
- (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 \
- */
-#define LL_RCC_PLLP_DIV_15 \
- (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 \
- */
-#define LL_RCC_PLLP_DIV_16 \
- (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 \
- */
-#define LL_RCC_PLLP_DIV_17 \
- (RCC_PLLCFGR_PLLPDIV_4 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 \
- */
-#define LL_RCC_PLLP_DIV_18 \
- (RCC_PLLCFGR_PLLPDIV_4 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 \
- */
-#define LL_RCC_PLLP_DIV_19 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 \
- */
-#define LL_RCC_PLLP_DIV_20 \
- (RCC_PLLCFGR_PLLPDIV_4 | \
- RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 \
- */
-#define LL_RCC_PLLP_DIV_21 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 \
- */
-#define LL_RCC_PLLP_DIV_22 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 \
- */
-#define LL_RCC_PLLP_DIV_23 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_2 | RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 \
- */
-#define LL_RCC_PLLP_DIV_24 \
- (RCC_PLLCFGR_PLLPDIV_4 | \
- RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 \
- */
-#define LL_RCC_PLLP_DIV_25 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 \
- */
-#define LL_RCC_PLLP_DIV_26 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 \
- */
-#define LL_RCC_PLLP_DIV_27 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 \
- */
-#define LL_RCC_PLLP_DIV_28 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | \
- RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 \
- */
-#define LL_RCC_PLLP_DIV_29 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 \
- */
-#define LL_RCC_PLLP_DIV_30 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 \
- */
-#define LL_RCC_PLLP_DIV_31 \
- (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
- RCC_PLLCFGR_PLLPDIV_1 | \
- RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 \
- */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
- * @{
- */
-#define LL_RCC_PLLQ_DIV_2 \
- 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
-#define LL_RCC_PLLQ_DIV_4 \
- (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
-#define LL_RCC_PLLQ_DIV_6 \
- (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
-#define LL_RCC_PLLQ_DIV_8 \
- (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RCC register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
-
-/**
- * @brief Read a value in RCC register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
- * @{
- */
-
-/**
- * @brief Helper macro to calculate the PLLCLK frequency on system domain
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref
- * LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
- * @param __PLLR__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLR_DIV_2
- * @arg @ref LL_RCC_PLLR_DIV_4
- * @arg @ref LL_RCC_PLLR_DIV_6
- * @arg @ref LL_RCC_PLLR_DIV_8
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
- ((__INPUTFREQ__) * (__PLLN__) / \
- ((((__PLLM__) >> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
- ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
-
-/**
- * @brief Helper macro to calculate the PLLCLK frequency used on ADC domain
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref
- LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
-
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
- * @param __PLLP__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_3
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_5
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_7
- * @arg @ref LL_RCC_PLLP_DIV_8
- * @arg @ref LL_RCC_PLLP_DIV_9
- * @arg @ref LL_RCC_PLLP_DIV_10
- * @arg @ref LL_RCC_PLLP_DIV_11
- * @arg @ref LL_RCC_PLLP_DIV_12
- * @arg @ref LL_RCC_PLLP_DIV_13
- * @arg @ref LL_RCC_PLLP_DIV_14
- * @arg @ref LL_RCC_PLLP_DIV_15
- * @arg @ref LL_RCC_PLLP_DIV_16
- * @arg @ref LL_RCC_PLLP_DIV_17
- * @arg @ref LL_RCC_PLLP_DIV_18
- * @arg @ref LL_RCC_PLLP_DIV_19
- * @arg @ref LL_RCC_PLLP_DIV_20
- * @arg @ref LL_RCC_PLLP_DIV_21
- * @arg @ref LL_RCC_PLLP_DIV_22
- * @arg @ref LL_RCC_PLLP_DIV_23
- * @arg @ref LL_RCC_PLLP_DIV_24
- * @arg @ref LL_RCC_PLLP_DIV_25
- * @arg @ref LL_RCC_PLLP_DIV_26
- * @arg @ref LL_RCC_PLLP_DIV_27
- * @arg @ref LL_RCC_PLLP_DIV_28
- * @arg @ref LL_RCC_PLLP_DIV_29
- * @arg @ref LL_RCC_PLLP_DIV_30
- * @arg @ref LL_RCC_PLLP_DIV_31
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, \
- __PLLP__) \
- ((__INPUTFREQ__) * (__PLLN__) / \
- ((((__PLLM__) >> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
- ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
-
-/**
- * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref
- * LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
- * @param __PLLQ__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLQ_DIV_2
- * @arg @ref LL_RCC_PLLQ_DIV_4
- * @arg @ref LL_RCC_PLLQ_DIV_6
- * @arg @ref LL_RCC_PLLQ_DIV_8
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, \
- __PLLQ__) \
- ((__INPUTFREQ__) * (__PLLN__) / \
- ((((__PLLM__) >> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
- ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
-
-/**
- * @brief Helper macro to calculate the HCLK frequency
- * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
- * @param __AHBPRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval HCLK clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
- ((__SYSCLKFREQ__) >> \
- (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & \
- 0x1FU))
-
-/**
- * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB1PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval PCLK1 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
- ((__HCLKFREQ__) >> \
- (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
-
-/**
- * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB2PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval PCLK2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \
- ((__HCLKFREQ__) >> \
- (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_LL_EF_HSE HSE
- * @{
- */
-
-/**
- * @brief Enable the Clock Security System.
- * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) {
- SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
- * @brief Enable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) {
- SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Disable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) {
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Enable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSEON); }
-
-/**
- * @brief Disable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void) {
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Check if HSE oscillator Ready
- * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) {
- return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_HSI HSI
- * @{
- */
-
-/**
- * @brief Enable HSI even in stop mode
- * @note HSI oscillator is forced ON even in Stop mode
- * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) {
- SET_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
- * @brief Disable HSI in stop mode
- * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) {
- CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
- * @brief Enable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSION); }
-
-/**
- * @brief Disable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void) {
- CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Check if HSI clock is ready
- * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) {
- return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get HSI Calibration value
- * @note When HSITRIM is written, HSICAL is updated with the sum of
- * HSITRIM and the factory trim value
- * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) {
- return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >>
- RCC_ICSCR_HSICAL_Pos);
-}
-
-/**
- * @brief Set HSI Calibration trimming
- * @note user-programmable trimming value that is added to the HSICAL
- * @note Default value is 16, which, when added to the HSICAL value,
- * should trim the HSI to 16 MHz +/- 1 %
- * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
- * @param Value Between Min_Data = 0 and Max_Data = 127
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) {
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
- * @brief Get HSI Calibration trimming
- * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
- * @retval Between Min_Data = 0 and Max_Data = 127
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) {
- return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >>
- RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_HSI48 HSI48
- * @{
- */
-
-/**
- * @brief Enable HSI48
- * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI48_Enable(void) {
- SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
-}
-
-/**
- * @brief Disable HSI48
- * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI48_Disable(void) {
- CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
-}
-
-/**
- * @brief Check if HSI48 oscillator Ready
- * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) {
- return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get HSI48 Calibration value
- * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) {
- return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >>
- RCC_CRRCR_HSI48CAL_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSE LSE
- * @{
- */
-
-/**
- * @brief Enable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void) {
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Disable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Enable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) {
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Disable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Set LSE oscillator drive capability
- * @note The oscillator is in Xtal mode when it is not in bypass mode.
- * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
- * @param LSEDrive This parameter can be one of the following values:
- * @arg @ref LL_RCC_LSEDRIVE_LOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
- * @arg @ref LL_RCC_LSEDRIVE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) {
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
-}
-
-/**
- * @brief Get LSE oscillator drive capability
- * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_LSEDRIVE_LOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
- * @arg @ref LL_RCC_LSEDRIVE_HIGH
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) {
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
-}
-
-/**
- * @brief Enable Clock security system on LSE.
- * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) {
- SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-}
-
-/**
- * @brief Disable Clock security system on LSE.
- * @note Clock security system can be disabled only after a LSE
- * failure detection. In that case it MUST be disabled by software.
- * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-}
-
-/**
- * @brief Check if LSE oscillator Ready
- * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) {
- return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if CSS on LSE failure Detection
- * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) {
- return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSI LSI
- * @{
- */
-
-/**
- * @brief Enable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void) {
- SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Disable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void) {
- CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Check if LSI is Ready
- * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSCO LSCO
- * @{
- */
-
-/**
- * @brief Enable Low speed clock
- * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSCO_Enable(void) {
- SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-}
-
-/**
- * @brief Disable Low speed clock
- * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSCO_Disable(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-}
-
-/**
- * @brief Configure Low speed clock selection
- * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
- * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) {
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
-}
-
-/**
- * @brief Get Low speed clock selection
- * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
- * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
- */
-__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) {
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_System System
- * @{
- */
-
-/**
- * @brief Configure the system clock source
- * @rmtoll CFGR SW LL_RCC_SetSysClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
- * @brief Get the system clock source
- * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) {
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
- * @brief Set AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
- * @brief Set APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
- * @brief Set APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
- * @brief Get AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) {
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
- * @brief Get APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) {
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
- * @brief Get APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) {
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_MCO MCO
- * @{
- */
-
-/**
- * @brief Configure MCOx
- * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
- * CFGR MCOPRE LL_RCC_ConfigMCO
- * @param MCOxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
- * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
- * @arg @ref LL_RCC_MCO1SOURCE_HSI
- * @arg @ref LL_RCC_MCO1SOURCE_HSE
- * @arg @ref LL_RCC_MCO1SOURCE_HSI48
- * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
- * @arg @ref LL_RCC_MCO1SOURCE_LSI
- * @arg @ref LL_RCC_MCO1SOURCE_LSE
- *
- * (*) value not defined in all devices.
- * @param MCOxPrescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1_DIV_1
- * @arg @ref LL_RCC_MCO1_DIV_2
- * @arg @ref LL_RCC_MCO1_DIV_4
- * @arg @ref LL_RCC_MCO1_DIV_8
- * @arg @ref LL_RCC_MCO1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource,
- uint32_t MCOxPrescaler) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE,
- MCOxSource | MCOxPrescaler);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
- * @{
- */
-
-/**
- * @brief Configure USARTx clock source
- * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
- * @param USARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
- * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
- * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
- * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) {
- MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
-}
-
-#if defined(UART4)
-/**
- * @brief Configure UARTx clock source
- * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
- * @param UARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) {
- MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
-}
-#endif /* UART4 */
-
-/**
- * @brief Configure LPUART1x clock source
- * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
- * @param LPUARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
-}
-
-/**
- * @brief Configure I2Cx clock source
- * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
- * @param I2CxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) {
- __IO uint32_t *reg =
- (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
- MODIFY_REG(
- *reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U),
- ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
-}
-
-/**
- * @brief Configure LPTIMx clock source
- * @rmtoll CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
- * @param LPTIMxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
-}
-
-/**
- * @brief Configure SAIx clock source
- * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
- * @param SAIxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
-}
-
-/**
- * @brief Configure I2S clock source
- * @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
- * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
-}
-
-#if defined(FDCAN1)
-/**
- * @brief Configure FDCAN clock source
- * @rmtoll CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
- * @param FDCANxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
-}
-#endif /* FDCAN1 */
-
-/**
- * @brief Configure RNG clock source
- * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
- * @param RNGxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
-}
-
-/**
- * @brief Configure USB clock source
- * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) {
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
-}
-
-/**
- * @brief Configure ADC clock source
- * @rmtoll CCIPR ADC12SEL LL_RCC_SetADCClockSource\n
- * CCIPR ADC345SEL LL_RCC_SetADCClockSource
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
- * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
- * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
- * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) {
- MODIFY_REG(
- RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U),
- ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
-}
-
-#if defined(QUADSPI)
-/**
- * @brief Configure QUADSPI clock source
- * @rmtoll CCIPR2 QSPISEL LL_RCC_SetQUADSPIClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source) {
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
-}
-#endif /* QUADSPI */
-
-/**
- * @brief Get USARTx clock source
- * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
- * @param USARTx This parameter can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE
- * @arg @ref LL_RCC_USART2_CLKSOURCE
- * @arg @ref LL_RCC_USART3_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
- * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
- * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
- * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
-}
-
-#if defined(UART4)
-/**
- * @brief Get UARTx clock source
- * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
- * @param UARTx This parameter can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
-}
-#endif /* UART4 */
-
-/**
- * @brief Get LPUARTx clock source
- * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
- * @param LPUARTx This parameter can be one of the following values:
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
- */
-__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
-}
-
-/**
- * @brief Get I2Cx clock source
- * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
- * @param I2Cx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE
- * @arg @ref LL_RCC_I2C2_CLKSOURCE
- * @arg @ref LL_RCC_I2C3_CLKSOURCE
- * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) {
- __IO const uint32_t *reg =
- (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
- return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >>
- ((I2Cx & 0x001F0000U) >> 16U)) |
- (I2Cx & 0xFFFF0000U));
-}
-
-/**
- * @brief Get LPTIMx clock source
- * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
- * @param LPTIMx This parameter can be one of the following values:
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
- */
-__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
-}
-
-/**
- * @brief Get SAIx clock source
- * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
- * @param SAIx This parameter can be one of the following values:
- * @arg @ref LL_RCC_SAI1_CLKSOURCE
- *
- * (*) value not defined in all devices.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
- * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
-}
-
-/**
- * @brief Get I2Sx clock source
- * @rmtoll CCIPR I2S23SEL LL_RCC_GetI2SClockSource
- * @param I2Sx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
- * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
-}
-
-#if defined(FDCAN1)
-/**
- * @brief Get FDCANx clock source
- * @rmtoll CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
- * @param FDCANx This parameter can be one of the following values:
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
- * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
- * @retval None
- */
-__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
-}
-#endif /* FDCAN1 */
-
-/**
- * @brief Get RNGx clock source
- * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
- * @param RNGx This parameter can be one of the following values:
- * @arg @ref LL_RCC_RNG_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
-}
-
-/**
- * @brief Get USBx clock source
- * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
- * @param USBx This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
-}
-
-/**
- * @brief Get ADCx clock source
- * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
- * @param ADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC12_CLKSOURCE
- * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
- * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
- * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
- * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) {
- return (
- uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >>
- ((ADCx & 0x001F0000U) >> 16U)) |
- (ADCx & 0xFFFF0000U));
-}
-
-#if defined(QUADSPI)
-/**
- * @brief Get QUADSPI clock source
- * @rmtoll CCIPR2 QSPISEL LL_RCC_GetQUADSPIClockSource
- * @param QUADSPIx This parameter can be one of the following values:
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
- * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx) {
- return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
-}
-#endif /* QUADSPI */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_RTC RTC
- * @{
- */
-
-/**
- * @brief Set RTC Clock Source
- * @note Once the RTC clock source has been selected, it cannot be changed
- * anymore unless the Backup domain is reset, or unless a failure is detected on
- * LSE (LSECSSD is set). The BDRST bit can be used to reset them.
- * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) {
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
- * @brief Get RTC Clock Source
- * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) {
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
- * @brief Enable RTC
- * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableRTC(void) {
- SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Disable RTC
- * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableRTC(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Check if RTC has been enabled or not
- * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) {
- return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Force the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) {
- SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @brief Release the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_PLL PLL
- * @{
- */
-
-/**
- * @brief Enable PLL
- * @rmtoll CR PLLON LL_RCC_PLL_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLLON); }
-
-/**
- * @brief Disable PLL
- * @note Cannot be disabled if the PLL clock is used as the system clock
- * @rmtoll CR PLLON LL_RCC_PLL_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void) {
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Check if PLL Ready
- * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) {
- return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Configure PLL used for SYSCLK Domain
- * @note PLL Source and PLLM Divider can be written only when PLL
- * is disabled.
- * @note PLLN/PLLR can be written only when PLL is disabled.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
- * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
- * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_NONE
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLM This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @param PLLN Between Min_Data = 8 and Max_Data = 127
- * @param PLLR This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLR_DIV_2
- * @arg @ref LL_RCC_PLLR_DIV_4
- * @arg @ref LL_RCC_PLLR_DIV_6
- * @arg @ref LL_RCC_PLLR_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM,
- uint32_t PLLN, uint32_t PLLR) {
- MODIFY_REG(RCC->PLLCFGR,
- RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
- RCC_PLLCFGR_PLLR,
- Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
-}
-
-/**
- * @brief Configure PLL used for ADC domain clock
- * @note PLL Source and PLLM Divider can be written only when PLL
- * is disabled.
- * @note PLLN/PLLP can be written only when PLL is disabled.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
- * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
- * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
- * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_NONE
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLM This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @param PLLN Between Min_Data = 8 and Max_Data = 127
- * @param PLLP This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_3
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_5
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_7
- * @arg @ref LL_RCC_PLLP_DIV_8
- * @arg @ref LL_RCC_PLLP_DIV_9
- * @arg @ref LL_RCC_PLLP_DIV_10
- * @arg @ref LL_RCC_PLLP_DIV_11
- * @arg @ref LL_RCC_PLLP_DIV_12
- * @arg @ref LL_RCC_PLLP_DIV_13
- * @arg @ref LL_RCC_PLLP_DIV_14
- * @arg @ref LL_RCC_PLLP_DIV_15
- * @arg @ref LL_RCC_PLLP_DIV_16
- * @arg @ref LL_RCC_PLLP_DIV_17
- * @arg @ref LL_RCC_PLLP_DIV_18
- * @arg @ref LL_RCC_PLLP_DIV_19
- * @arg @ref LL_RCC_PLLP_DIV_20
- * @arg @ref LL_RCC_PLLP_DIV_21
- * @arg @ref LL_RCC_PLLP_DIV_22
- * @arg @ref LL_RCC_PLLP_DIV_23
- * @arg @ref LL_RCC_PLLP_DIV_24
- * @arg @ref LL_RCC_PLLP_DIV_25
- * @arg @ref LL_RCC_PLLP_DIV_26
- * @arg @ref LL_RCC_PLLP_DIV_27
- * @arg @ref LL_RCC_PLLP_DIV_28
- * @arg @ref LL_RCC_PLLP_DIV_29
- * @arg @ref LL_RCC_PLLP_DIV_30
- * @arg @ref LL_RCC_PLLP_DIV_31
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM,
- uint32_t PLLN, uint32_t PLLP) {
- MODIFY_REG(RCC->PLLCFGR,
- RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
- RCC_PLLCFGR_PLLPDIV,
- Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
-}
-
-/**
- * @brief Configure PLL used for 48Mhz domain clock
- * @note PLL Source and PLLM Divider can be written only when PLL,
- * is disabled.
- * @note PLLN/PLLQ can be written only when PLL is disabled.
- * @note This can be selected for USB, RNG
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
- * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
- * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
- * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_NONE
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLM This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @param PLLN Between Min_Data = 8 and Max_Data = 127
- * @param PLLQ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLQ_DIV_2
- * @arg @ref LL_RCC_PLLQ_DIV_4
- * @arg @ref LL_RCC_PLLQ_DIV_6
- * @arg @ref LL_RCC_PLLQ_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM,
- uint32_t PLLN, uint32_t PLLQ) {
- MODIFY_REG(RCC->PLLCFGR,
- RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
- RCC_PLLCFGR_PLLQ,
- Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
-}
-
-/**
- * @brief Configure PLL clock source
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
- * @param PLLSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_NONE
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) {
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
-}
-
-/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_NONE
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) {
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
- * @brief Get Main PLL multiplication factor for VCO
- * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
- * @retval Between Min_Data = 8 and Max_Data = 127
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) {
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos);
-}
-
-/**
- * @brief Get Main PLL division factor for PLLP
- * @note Used for PLLADCCLK (ADC clock)
- * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP\n
- * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_3
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_5
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_7
- * @arg @ref LL_RCC_PLLP_DIV_8
- * @arg @ref LL_RCC_PLLP_DIV_9
- * @arg @ref LL_RCC_PLLP_DIV_10
- * @arg @ref LL_RCC_PLLP_DIV_11
- * @arg @ref LL_RCC_PLLP_DIV_12
- * @arg @ref LL_RCC_PLLP_DIV_13
- * @arg @ref LL_RCC_PLLP_DIV_14
- * @arg @ref LL_RCC_PLLP_DIV_15
- * @arg @ref LL_RCC_PLLP_DIV_16
- * @arg @ref LL_RCC_PLLP_DIV_17
- * @arg @ref LL_RCC_PLLP_DIV_18
- * @arg @ref LL_RCC_PLLP_DIV_19
- * @arg @ref LL_RCC_PLLP_DIV_20
- * @arg @ref LL_RCC_PLLP_DIV_21
- * @arg @ref LL_RCC_PLLP_DIV_22
- * @arg @ref LL_RCC_PLLP_DIV_23
- * @arg @ref LL_RCC_PLLP_DIV_24
- * @arg @ref LL_RCC_PLLP_DIV_25
- * @arg @ref LL_RCC_PLLP_DIV_26
- * @arg @ref LL_RCC_PLLP_DIV_27
- * @arg @ref LL_RCC_PLLP_DIV_28
- * @arg @ref LL_RCC_PLLP_DIV_29
- * @arg @ref LL_RCC_PLLP_DIV_30
- * @arg @ref LL_RCC_PLLP_DIV_31
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) {
- return (uint32_t)((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U)
- ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV)
- : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) ==
- RCC_PLLCFGR_PLLP)
- ? LL_RCC_PLLP_DIV_17
- : LL_RCC_PLLP_DIV_7));
-}
-
-/**
- * @brief Get Main PLL division factor for PLLQ
- * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
- * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLQ_DIV_2
- * @arg @ref LL_RCC_PLLQ_DIV_4
- * @arg @ref LL_RCC_PLLQ_DIV_6
- * @arg @ref LL_RCC_PLLQ_DIV_8
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) {
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
-}
-
-/**
- * @brief Get Main PLL division factor for PLLR
- * @note Used for PLLCLK (system clock)
- * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLR_DIV_2
- * @arg @ref LL_RCC_PLLR_DIV_4
- * @arg @ref LL_RCC_PLLR_DIV_6
- * @arg @ref LL_RCC_PLLR_DIV_8
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) {
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
-}
-
-/**
- * @brief Get Division factor for the main PLL and other PLL
- * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) {
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
-}
-
-/**
- * @brief Enable PLL output mapped on ADC domain clock
- * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void) {
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-
-/**
- * @brief Disable PLL output mapped on ADC domain clock
- * @note Cannot be disabled if the PLL clock is used as the system
- * clock
- * @note In order to save power, when the PLLCLK of the PLL is
- * not used, should be 0
- * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) {
- CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-
-/**
- * @brief Check if PLL output mapped on ADC domain clock is enabled
- * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void) {
- return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable PLL output mapped on 48MHz domain clock
- * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void) {
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
- * @brief Disable PLL output mapped on 48MHz domain clock
- * @note Cannot be disabled if the PLL clock is used as the system
- * clock
- * @note In order to save power, when the PLLCLK of the PLL is
- * not used, should be 0
- * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) {
- CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
- * @brief Check if PLL output mapped on 48MHz domain clock is enabled
- * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void) {
- return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable PLL output mapped on SYSCLK domain
- * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) {
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
-}
-
-/**
- * @brief Disable PLL output mapped on SYSCLK domain
- * @note Cannot be disabled if the PLL clock is used as the system
- * clock
- * @note In order to save power, when the PLLCLK of the PLL is
- * not used, Main PLL should be 0
- * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) {
- CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
-}
-
-/**
- * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
- * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) {
- return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Clear LSI ready interrupt flag
- * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) {
- SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
-}
-
-/**
- * @brief Clear LSE ready interrupt flag
- * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) {
- SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
-}
-
-/**
- * @brief Clear HSI ready interrupt flag
- * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) {
- SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
-}
-
-/**
- * @brief Clear HSE ready interrupt flag
- * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) {
- SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
-}
-
-/**
- * @brief Clear PLL ready interrupt flag
- * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) {
- SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
-}
-
-/**
- * @brief Clear HSI48 ready interrupt flag
- * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) {
- SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
-}
-
-/**
- * @brief Clear Clock security system interrupt flag
- * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) {
- SET_BIT(RCC->CICR, RCC_CICR_CSSC);
-}
-
-/**
- * @brief Clear LSE Clock security system interrupt flag
- * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) {
- SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
-}
-
-/**
- * @brief Check if LSI ready interrupt occurred or not
- * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if LSE ready interrupt occurred or not
- * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if HSI ready interrupt occurred or not
- * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if HSE ready interrupt occurred or not
- * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if PLL ready interrupt occurred or not
- * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if HSI48 ready interrupt occurred or not
- * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Clock security system interrupt occurred or not
- * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if LSE Clock security system interrupt occurred or not
- * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) {
- return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag Independent Watchdog reset is set or not.
- * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag Low Power reset is set or not.
- * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag Option byte reset is set or not.
- * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag Pin reset is set or not.
- * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag Software reset is set or not.
- * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag Window Watchdog reset is set or not.
- * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if RCC flag BOR reset is set or not.
- * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) {
- return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set RMVF bit to clear the reset flags.
- * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void) {
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
- * @{
- */
-
-/**
- * @brief Enable LSI ready interrupt
- * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) {
- SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
- * @brief Enable LSE ready interrupt
- * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) {
- SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
- * @brief Enable HSI ready interrupt
- * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) {
- SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
- * @brief Enable HSE ready interrupt
- * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) {
- SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
- * @brief Enable PLL ready interrupt
- * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) {
- SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
-}
-
-/**
- * @brief Enable HSI48 ready interrupt
- * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) {
- SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-
-/**
- * @brief Enable LSE clock security system interrupt
- * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) {
- SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
-}
-
-/**
- * @brief Disable LSI ready interrupt
- * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
- * @brief Disable LSE ready interrupt
- * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
- * @brief Disable HSI ready interrupt
- * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
- * @brief Disable HSE ready interrupt
- * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
- * @brief Disable PLL ready interrupt
- * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
-}
-
-/**
- * @brief Disable HSI48 ready interrupt
- * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-
-/**
- * @brief Disable LSE clock security system interrupt
- * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) {
- CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
-}
-
-/**
- * @brief Checks if LSI ready interrupt source is enabled or disabled.
- * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Checks if LSE ready interrupt source is enabled or disabled.
- * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Checks if HSI ready interrupt source is enabled or disabled.
- * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Checks if HSE ready interrupt source is enabled or disabled.
- * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Checks if PLL ready interrupt source is enabled or disabled.
- * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
- * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Checks if LSECSS interrupt source is enabled or disabled.
- * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) {
- return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_RCC_DeInit(void);
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency
- * functions
- * @{
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
-#if defined(UART4)
-uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
-#endif /* UART4 */
-uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
-uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
-uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
-uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#if defined(FDCAN1)
-uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
-#endif /* FDCAN1 */
-uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
-#if defined(QUADSPI)
-uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
-#endif /* QUADSPI */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_RCC_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_RCC_H
+#define STM32G4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Defines used to perform offsets*/
+/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
+#define RCC_OFFSET_CCIPR 0U
+#define RCC_OFFSET_CCIPR2 0x14U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct {
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined(HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined(HSI_VALUE)
+#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined(LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined(LSI_VALUE)
+#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined(HSI48_VALUE)
+#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+
+#if !defined(EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE \
+ 48000U /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz \
+ */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CICR_HSI48RDYC \
+ RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
+#define LL_RCC_CICR_LSECSSC \
+ RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
+#define LL_RCC_CICR_CSSC \
+ RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIFR_HSI48RDYF \
+ RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+#define LL_RCC_CIFR_LSECSSF \
+ RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
+#define LL_RCC_CIFR_CSSF \
+ RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF \
+ RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF \
+ RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag \
+ */
+#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and
+ * LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIER_LSIRDYIE \
+ RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIER_LSERDYIE \
+ RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIER_HSIRDYIE \
+ RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSERDYIE \
+ RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIER_PLLRDYIE \
+ RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+#define LL_RCC_CIER_HSI48RDYIE \
+ RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
+#define LL_RCC_CIER_LSECSSIE \
+ RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
+ * @{
+ */
+#define LL_RCC_LSEDRIVE_LOW \
+ 0x00000000U /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW \
+ RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH \
+ RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH \
+ RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
+ * @{
+ */
+#define LL_RCC_LSCO_CLKSOURCE_LSI \
+ 0x00000000U /*!< LSI selection for low speed clock */
+#define LL_RCC_LSCO_CLKSOURCE_LSE \
+ RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_HSI \
+ RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE \
+ RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL \
+ RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI \
+ RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE \
+ RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL \
+ RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 \
+ RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 \
+ */
+#define LL_RCC_SYSCLK_DIV_256 \
+ RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 \
+ */
+#define LL_RCC_SYSCLK_DIV_512 \
+ RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK \
+ 0x00000000U /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK \
+ RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI \
+ (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source \
+ */
+#define LL_RCC_MCO1SOURCE_HSE \
+ RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK \
+ (RCC_CFGR_MCOSEL_0 | \
+ RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI \
+ (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE \
+ (RCC_CFGR_MCOSEL_0 | RCC_CFGR_MCOSEL_1 | \
+ RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI48 \
+ RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
+ * @{
+ */
+#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO \
+ 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA \
+ 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source
+ * selection
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2 \
+ (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK \
+ ((RCC_CCIPR_USART1SEL << 16U) | \
+ RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI \
+ ((RCC_CCIPR_USART1SEL << 16U) | \
+ RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE \
+ ((RCC_CCIPR_USART1SEL << 16U) | \
+ RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1 \
+ (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK \
+ ((RCC_CCIPR_USART2SEL << 16U) | \
+ RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI \
+ ((RCC_CCIPR_USART2SEL << 16U) | \
+ RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE \
+ ((RCC_CCIPR_USART2SEL << 16U) | \
+ RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
+#if defined(RCC_CCIPR_USART3SEL)
+#define LL_RCC_USART3_CLKSOURCE_PCLK1 \
+ (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK \
+ ((RCC_CCIPR_USART3SEL << 16U) | \
+ RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI \
+ ((RCC_CCIPR_USART3SEL << 16U) | \
+ RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE \
+ ((RCC_CCIPR_USART3SEL << 16U) | \
+ RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
+#endif /* RCC_CCIPR_USART3SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
+ * @{
+ */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE_PCLK1 \
+ (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK \
+ ((RCC_CCIPR_UART4SEL << 16U) | \
+ RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI \
+ ((RCC_CCIPR_UART4SEL << 16U) | \
+ RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE \
+ ((RCC_CCIPR_UART4SEL << 16U) | \
+ RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE_PCLK1 \
+ (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK \
+ ((RCC_CCIPR_UART5SEL << 16U) | \
+ RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI \
+ ((RCC_CCIPR_UART5SEL << 16U) | \
+ RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE \
+ ((RCC_CCIPR_UART5SEL << 16U) | \
+ RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source
+ * selection
+ * @{
+ */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 \
+ 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK \
+ RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI \
+ RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE \
+ RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1 \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C1SEL_Pos \
+ << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C1SEL_0 >> \
+ RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C1SEL_1 >> \
+ RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1 \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C2SEL_Pos \
+ << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C2SEL_0 >> \
+ RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C2SEL_1 >> \
+ RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1 \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C3SEL_Pos \
+ << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C3SEL_0 >> \
+ RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C3SEL_1 >> \
+ RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1 \
+ (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | \
+ ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos \
+ << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK \
+ (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | \
+ ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR2_I2C4SEL_0 >> \
+ RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI \
+ (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | \
+ ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR2_I2C4SEL_1 >> \
+ RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source
+ * selection
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 \
+ 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI \
+ RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI \
+ RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE \
+ RCC_CCIPR_LPTIM1SEL /*!< LSE clock used as LPTIM1 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
+ * @{
+ */
+#define LL_RCC_SAI1_CLKSOURCE_SYSCLK \
+ 0x00000000U /*!< System clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL \
+ RCC_CCIPR_SAI1SEL_0 /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN \
+ RCC_CCIPR_SAI1SEL_1 /*!< EXT clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_HSI \
+ (RCC_CCIPR_SAI1SEL_0 | \
+ RCC_CCIPR_SAI1SEL_1) /*!< HSI clock used as SAI1 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE_SYSCLK \
+ 0x00000000U /*!< System clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PLL \
+ RCC_CCIPR_I2S23SEL_0 /*!< PLL clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PIN \
+ RCC_CCIPR_I2S23SEL_1 /*!< EXT clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_HSI \
+ (RCC_CCIPR_I2S23SEL_0 | \
+ RCC_CCIPR_I2S23SEL_1) /*!< HSI clock used as I2S clock source */
+/**
+ * @}
+ */
+
+#if defined(FDCAN1)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
+ * @{
+ */
+#define LL_RCC_FDCAN_CLKSOURCE_HSE \
+ 0x00000000U /*!< HSE clock used as FDCAN clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_PLL \
+ RCC_CCIPR_FDCANSEL_0 /*!< PLL clock used as FDCAN clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 \
+ RCC_CCIPR_FDCANSEL_1 /*!< PCLK1 clock used as FDCAN clock source */
+/**
+ * @}
+ */
+#endif /* FDCAN1 */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
+ * @{
+ */
+#define LL_RCC_RNG_CLKSOURCE_HSI48 \
+ 0x00000000U /*!< HSI48 clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_PLL \
+ RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE_HSI48 \
+ 0x00000000U /*!< HSI48 clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_PLL \
+ RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC12_CLKSOURCE_NONE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC12SEL_Pos \
+ << 16U)) /*!< No clock used as ADC12 clock source */
+#define LL_RCC_ADC12_CLKSOURCE_PLL \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | \
+ (RCC_CCIPR_ADC12SEL_0 >> \
+ RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */
+#define LL_RCC_ADC12_CLKSOURCE_SYSCLK \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | \
+ (RCC_CCIPR_ADC12SEL_1 >> \
+ RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */
+#if defined(RCC_CCIPR_ADC345SEL)
+#define LL_RCC_ADC345_CLKSOURCE_NONE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC345SEL_Pos \
+ << 16U)) /*!< No clock used as ADC345 clock source */
+#define LL_RCC_ADC345_CLKSOURCE_PLL \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | \
+ (RCC_CCIPR_ADC345SEL_0 >> \
+ RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
+#define LL_RCC_ADC345_CLKSOURCE_SYSCLK \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | \
+ (RCC_CCIPR_ADC345SEL_1 >> \
+ RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
+#endif /* RCC_CCIPR_ADC345SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
+ * @{
+ */
+#define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK \
+ 0x00000000U /*!< SYSCLK used as QuadSPI clock source */
+#define LL_RCC_QUADSPI_CLKSOURCE_HSI \
+ RCC_CCIPR2_QSPISEL_0 /*!< HSI used as QuadSPI clock source */
+#define LL_RCC_QUADSPI_CLKSOURCE_PLL \
+ RCC_CCIPR2_QSPISEL_1 /*!< PLL used as QuadSPI clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE \
+ RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
+#define LL_RCC_USART2_CLKSOURCE \
+ RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
+#if defined(RCC_CCIPR_USART3SEL)
+#define LL_RCC_USART3_CLKSOURCE \
+ RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
+#endif /* RCC_CCIPR_USART3SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
+ * @{
+ */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE \
+ RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE \
+ RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
+ * @{
+ */
+#define LL_RCC_LPUART1_CLKSOURCE \
+ RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C1SEL >> \
+ RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
+#define LL_RCC_I2C2_CLKSOURCE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C2SEL >> \
+ RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#if defined(RCC_CCIPR_I2C3SEL)
+#define LL_RCC_I2C3_CLKSOURCE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | \
+ (RCC_CCIPR_I2C3SEL >> \
+ RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#endif /* RCC_CCIPR_I2C3SEL */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE \
+ (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | \
+ ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | \
+ (RCC_CCIPR2_I2C4SEL >> \
+ RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE \
+ RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
+ * @{
+ */
+#define LL_RCC_SAI1_CLKSOURCE \
+ RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE \
+ RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
+/**
+ * @}
+ */
+
+#if defined(FDCAN1)
+/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
+ * @{
+ */
+#define LL_RCC_FDCAN_CLKSOURCE \
+ RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
+#endif /* FDCAN1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
+ * @{
+ */
+#define LL_RCC_RNG_CLKSOURCE \
+ RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE \
+ RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
+ * @{
+ */
+#define LL_RCC_ADC12_CLKSOURCE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | \
+ (RCC_CCIPR_ADC12SEL >> \
+ RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */
+#if defined(RCC_CCIPR_ADC345SEL_Pos)
+#define LL_RCC_ADC345_CLKSOURCE \
+ (((uint32_t)RCC_OFFSET_CCIPR << 24U) | \
+ ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | \
+ (RCC_CCIPR_ADC345SEL >> \
+ RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
+#endif /* RCC_CCIPR_ADC345SEL_Pos */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
+ * @{
+ */
+#define LL_RCC_QUADSPI_CLKSOURCE \
+ RCC_CCIPR2_QSPISEL /*!< QuadSPI Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE \
+ 0x00000000U /*!< No clock used as RTC clock \
+ */
+#define LL_RCC_RTC_CLKSOURCE_LSE \
+ RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI \
+ RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 \
+ RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
+#define LL_RCC_PLLSOURCE_HSI \
+ RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source \
+ */
+#define LL_RCC_PLLSOURCE_HSE \
+ RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
+ * @{
+ */
+#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
+#define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0 /*!< PLL division factor by 2 */
+#define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1 /*!< PLL division factor by 3 */
+#define LL_RCC_PLLM_DIV_4 \
+ (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 4 */
+#define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2 /*!< PLL division factor by 5 */
+#define LL_RCC_PLLM_DIV_6 \
+ (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 6 */
+#define LL_RCC_PLLM_DIV_7 \
+ (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 7 */
+#define LL_RCC_PLLM_DIV_8 \
+ (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | \
+ RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 8 */
+#define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3 /*!< PLL division factor by 9 */
+#define LL_RCC_PLLM_DIV_10 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 10 */
+#define LL_RCC_PLLM_DIV_11 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 11 */
+#define LL_RCC_PLLM_DIV_12 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | \
+ RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 12 */
+#define LL_RCC_PLLM_DIV_13 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 13 */
+#define LL_RCC_PLLM_DIV_14 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | \
+ RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 14 */
+#define LL_RCC_PLLM_DIV_15 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | \
+ RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 15 */
+#define LL_RCC_PLLM_DIV_16 \
+ (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | \
+ RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
+ * @{
+ */
+#define LL_RCC_PLLR_DIV_2 \
+ 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_4 \
+ (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) \
+ by 4 */
+#define LL_RCC_PLLR_DIV_6 \
+ (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) \
+ by 6 */
+#define LL_RCC_PLLR_DIV_8 \
+ (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) \
+ by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
+ * @{
+ */
+#define LL_RCC_PLLP_DIV_2 \
+ (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 \
+ */
+#define LL_RCC_PLLP_DIV_3 \
+ (RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 \
+ */
+#define LL_RCC_PLLP_DIV_4 \
+ (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 \
+ */
+#define LL_RCC_PLLP_DIV_5 \
+ (RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 \
+ */
+#define LL_RCC_PLLP_DIV_6 \
+ (RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 \
+ */
+#define LL_RCC_PLLP_DIV_7 \
+ (RCC_PLLCFGR_PLLPDIV_2 | RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 \
+ */
+#define LL_RCC_PLLP_DIV_8 \
+ (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 \
+ */
+#define LL_RCC_PLLP_DIV_9 \
+ (RCC_PLLCFGR_PLLPDIV_3 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 \
+ */
+#define LL_RCC_PLLP_DIV_10 \
+ (RCC_PLLCFGR_PLLPDIV_3 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 \
+ */
+#define LL_RCC_PLLP_DIV_11 \
+ (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 \
+ */
+#define LL_RCC_PLLP_DIV_12 \
+ (RCC_PLLCFGR_PLLPDIV_3 | \
+ RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 \
+ */
+#define LL_RCC_PLLP_DIV_13 \
+ (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 \
+ */
+#define LL_RCC_PLLP_DIV_14 \
+ (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 \
+ */
+#define LL_RCC_PLLP_DIV_15 \
+ (RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 \
+ */
+#define LL_RCC_PLLP_DIV_16 \
+ (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 \
+ */
+#define LL_RCC_PLLP_DIV_17 \
+ (RCC_PLLCFGR_PLLPDIV_4 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 \
+ */
+#define LL_RCC_PLLP_DIV_18 \
+ (RCC_PLLCFGR_PLLPDIV_4 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 \
+ */
+#define LL_RCC_PLLP_DIV_19 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 \
+ */
+#define LL_RCC_PLLP_DIV_20 \
+ (RCC_PLLCFGR_PLLPDIV_4 | \
+ RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 \
+ */
+#define LL_RCC_PLLP_DIV_21 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 \
+ */
+#define LL_RCC_PLLP_DIV_22 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 \
+ */
+#define LL_RCC_PLLP_DIV_23 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_2 | RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 \
+ */
+#define LL_RCC_PLLP_DIV_24 \
+ (RCC_PLLCFGR_PLLPDIV_4 | \
+ RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 \
+ */
+#define LL_RCC_PLLP_DIV_25 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 \
+ */
+#define LL_RCC_PLLP_DIV_26 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 \
+ */
+#define LL_RCC_PLLP_DIV_27 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 \
+ */
+#define LL_RCC_PLLP_DIV_28 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | \
+ RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 \
+ */
+#define LL_RCC_PLLP_DIV_29 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 \
+ */
+#define LL_RCC_PLLP_DIV_30 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 \
+ */
+#define LL_RCC_PLLP_DIV_31 \
+ (RCC_PLLCFGR_PLLPDIV_4 | RCC_PLLCFGR_PLLPDIV_3 | RCC_PLLCFGR_PLLPDIV_2 | \
+ RCC_PLLCFGR_PLLPDIV_1 | \
+ RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
+ * @{
+ */
+#define LL_RCC_PLLQ_DIV_2 \
+ 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_4 \
+ (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_6 \
+ (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_8 \
+ (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency on system domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref
+ * LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
+ ((__INPUTFREQ__) * (__PLLN__) / \
+ ((((__PLLM__) >> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+ ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on ADC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref
+ LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+
+ * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
+ * @param __PLLP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, \
+ __PLLP__) \
+ ((__INPUTFREQ__) * (__PLLN__) / \
+ ((((__PLLM__) >> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+ ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref
+ * LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
+ * @param __PLLQ__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, \
+ __PLLQ__) \
+ ((__INPUTFREQ__) * (__PLLN__) / \
+ ((((__PLLM__) >> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
+
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
+ ((__SYSCLKFREQ__) >> \
+ (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & \
+ 0x1FU))
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
+ ((__HCLKFREQ__) >> \
+ (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \
+ ((__HCLKFREQ__) >> \
+ (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) {
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) {
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) {
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSEON); }
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void) {
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) {
+ return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI even in stop mode
+ * @note HSI oscillator is forced ON even in Stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) {
+ SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+ * @brief Disable HSI in stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) {
+ CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSION); }
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void) {
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) {
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) {
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >>
+ RCC_ICSCR_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value Between Min_Data = 0 and Max_Data = 127
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) {
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0 and Max_Data = 127
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) {
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >>
+ RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+ * @{
+ */
+
+/**
+ * @brief Enable HSI48
+ * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void) {
+ SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+ * @brief Disable HSI48
+ * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void) {
+ CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+ * @brief Check if HSI48 oscillator Ready
+ * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) {
+ return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get HSI48 Calibration value
+ * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) {
+ return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >>
+ RCC_CRRCR_HSI48CAL_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void) {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Set LSE oscillator drive capability
+ * @note The oscillator is in Xtal mode when it is not in bypass mode.
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
+ * @param LSEDrive This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) {
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+ * @brief Get LSE oscillator drive capability
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) {
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+ * @brief Enable Clock security system on LSE.
+ * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Disable Clock security system on LSE.
+ * @note Clock security system can be disabled only after a LSE
+ * failure detection. In that case it MUST be disabled by software.
+ * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) {
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if CSS on LSE failure Detection
+ * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) {
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void) {
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void) {
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSCO LSCO
+ * @{
+ */
+
+/**
+ * @brief Enable Low speed clock
+ * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_Enable(void) {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+ * @brief Disable Low speed clock
+ * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_Disable(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+ * @brief Configure Low speed clock selection
+ * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) {
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
+}
+
+/**
+ * @brief Get Low speed clock selection
+ * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) {
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) {
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) {
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) {
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) {
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
+ * CFGR MCOPRE LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI48
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_LSI
+ * @arg @ref LL_RCC_MCO1SOURCE_LSE
+ *
+ * (*) value not defined in all devices.
+ * @param MCOxPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1_DIV_1
+ * @arg @ref LL_RCC_MCO1_DIV_2
+ * @arg @ref LL_RCC_MCO1_DIV_4
+ * @arg @ref LL_RCC_MCO1_DIV_8
+ * @arg @ref LL_RCC_MCO1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource,
+ uint32_t MCOxPrescaler) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE,
+ MCOxSource | MCOxPrescaler);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+/**
+ * @brief Configure USARTx clock source
+ * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) {
+ MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+}
+
+#if defined(UART4)
+/**
+ * @brief Configure UARTx clock source
+ * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) {
+ MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
+}
+#endif /* UART4 */
+
+/**
+ * @brief Configure LPUART1x clock source
+ * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
+ * @param LPUARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+}
+
+/**
+ * @brief Configure I2Cx clock source
+ * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) {
+ __IO uint32_t *reg =
+ (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
+ MODIFY_REG(
+ *reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U),
+ ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
+}
+
+/**
+ * @brief Configure LPTIMx clock source
+ * @rmtoll CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
+}
+
+#if defined(SAI1)
+/**
+ * @brief Configure SAIx clock source
+ * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
+}
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Configure I2S clock source
+ * @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
+}
+#endif /* SPI_I2S_SUPPORT */
+
+#if defined(FDCAN1)
+/**
+ * @brief Configure FDCAN clock source
+ * @rmtoll CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
+ * @param FDCANxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
+}
+#endif /* FDCAN1 */
+
+/**
+ * @brief Configure RNG clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
+}
+
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) {
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
+}
+
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CCIPR ADC12SEL LL_RCC_SetADCClockSource\n
+ * CCIPR ADC345SEL LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) {
+ MODIFY_REG(
+ RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U),
+ ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
+}
+
+#if defined(QUADSPI)
+/**
+ * @brief Configure QUADSPI clock source
+ * @rmtoll CCIPR2 QSPISEL LL_RCC_SetQUADSPIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source) {
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
+}
+#endif /* QUADSPI */
+
+/**
+ * @brief Get USARTx clock source
+ * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
+ * @param USARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
+}
+
+#if defined(UART4)
+/**
+ * @brief Get UARTx clock source
+ * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
+ * @param UARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
+}
+#endif /* UART4 */
+
+/**
+ * @brief Get LPUARTx clock source
+ * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
+ * @param LPUARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+}
+
+/**
+ * @brief Get I2Cx clock source
+ * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
+ * @param I2Cx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) {
+ __IO const uint32_t *reg =
+ (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
+ return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >>
+ ((I2Cx & 0x001F0000U) >> 16U)) |
+ (I2Cx & 0xFFFF0000U));
+}
+
+/**
+ * @brief Get LPTIMx clock source
+ * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
+ * @param LPTIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
+}
+
+/**
+ * @brief Get SAIx clock source
+ * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
+ * @param SAIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
+}
+
+/**
+ * @brief Get I2Sx clock source
+ * @rmtoll CCIPR I2S23SEL LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
+}
+
+#if defined(FDCAN1)
+/**
+ * @brief Get FDCANx clock source
+ * @rmtoll CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
+ * @param FDCANx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
+}
+#endif /* FDCAN1 */
+
+/**
+ * @brief Get RNGx clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
+ * @param RNGx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
+}
+
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
+}
+
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) {
+ return (
+ uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >>
+ ((ADCx & 0x001F0000U) >> 16U)) |
+ (ADCx & 0xFFFF0000U));
+}
+
+#if defined(QUADSPI)
+/**
+ * @brief Get QUADSPI clock source
+ * @rmtoll CCIPR2 QSPISEL LL_RCC_GetQUADSPIClockSource
+ * @param QUADSPIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx) {
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
+}
+#endif /* QUADSPI */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed
+ * anymore unless the Backup domain is reset, or unless a failure is detected on
+ * LSE (LSECSSD is set). The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) {
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) {
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void) {
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) {
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) {
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLLON); }
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void) {
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) {
+ return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @note PLL Source and PLLM Divider can be written only when PLL
+ * is disabled.
+ * @note PLLN/PLLR can be written only when PLL is disabled.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @param PLLN Between Min_Data = 8 and Max_Data = 127
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM,
+ uint32_t PLLN, uint32_t PLLR) {
+ MODIFY_REG(RCC->PLLCFGR,
+ RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
+ RCC_PLLCFGR_PLLR,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
+}
+
+/**
+ * @brief Configure PLL used for ADC domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL
+ * is disabled.
+ * @note PLLN/PLLP can be written only when PLL is disabled.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
+ * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @param PLLN Between Min_Data = 8 and Max_Data = 127
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM,
+ uint32_t PLLN, uint32_t PLLP) {
+ MODIFY_REG(RCC->PLLCFGR,
+ RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
+ RCC_PLLCFGR_PLLPDIV,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
+}
+
+/**
+ * @brief Configure PLL used for 48Mhz domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * is disabled.
+ * @note PLLN/PLLQ can be written only when PLL is disabled.
+ * @note This can be selected for USB, RNG
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @param PLLN Between Min_Data = 8 and Max_Data = 127
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM,
+ uint32_t PLLN, uint32_t PLLQ) {
+ MODIFY_REG(RCC->PLLCFGR,
+ RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |
+ RCC_PLLCFGR_PLLQ,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
+}
+
+/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) {
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) {
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+ * @brief Get Main PLL multiplication factor for VCO
+ * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
+ * @retval Between Min_Data = 8 and Max_Data = 127
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) {
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos);
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLP
+ * @note Used for PLLADCCLK (ADC clock)
+ * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP\n
+ * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) {
+ return (uint32_t)((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U)
+ ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV)
+ : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) ==
+ RCC_PLLCFGR_PLLP)
+ ? LL_RCC_PLLP_DIV_17
+ : LL_RCC_PLLP_DIV_7));
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
+ * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) {
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLR
+ * @note Used for PLLCLK (system clock)
+ * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) {
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+
+/**
+ * @brief Get Division factor for the main PLL and other PLL
+ * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) {
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+ * @brief Enable PLL output mapped on ADC domain clock
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void) {
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+ * @brief Disable PLL output mapped on ADC domain clock
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLLCLK of the PLL is
+ * not used, should be 0
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) {
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+ * @brief Check if PLL output mapped on ADC domain clock is enabled
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void) {
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable PLL output mapped on 48MHz domain clock
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void) {
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+ * @brief Disable PLL output mapped on 48MHz domain clock
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLLCLK of the PLL is
+ * not used, should be 0
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) {
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+ * @brief Check if PLL output mapped on 48MHz domain clock is enabled
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void) {
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable PLL output mapped on SYSCLK domain
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) {
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+ * @brief Disable PLL output mapped on SYSCLK domain
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLLCLK of the PLL is
+ * not used, Main PLL should be 0
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) {
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+ * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) {
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+/**
+ * @brief Clear HSI48 ready interrupt flag
+ * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_CSSC);
+}
+
+/**
+ * @brief Clear LSE Clock security system interrupt flag
+ * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) {
+ SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if HSI48 ready interrupt occurred or not
+ * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if LSE Clock security system interrupt occurred or not
+ * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) {
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Option byte reset is set or not.
+ * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag BOR reset is set or not.
+ * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) {
+ return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void) {
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+/**
+ * @brief Enable HSI48 ready interrupt
+ * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+ * @brief Enable LSE clock security system interrupt
+ * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) {
+ SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+/**
+ * @brief Disable HSI48 ready interrupt
+ * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+ * @brief Disable LSE clock security system interrupt
+ * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) {
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Checks if LSECSS interrupt source is enabled or disabled.
+ * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) {
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency
+ * functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+#if defined(UART4)
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+#endif /* UART4 */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#if defined(FDCAN1)
+uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+#endif /* FDCAN1 */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+#if defined(QUADSPI)
+uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
+#endif /* QUADSPI */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_RCC_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h
index 6c41772..47ba1c8 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h
@@ -1,2341 +1,2341 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_SPI_H
-#define STM32G4xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4)
-
-/** @defgroup SPI_LL SPI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
- * @{
- */
-
-/**
- * @brief SPI Init structures definition
- */
-typedef struct {
- uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or
- bidirectional data mode. This parameter can be
- a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_SPI_SetTransferDirection().*/
-
- uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_LL_EC_MODE.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetMode().*/
-
- uint32_t
- DataWidth; /*!< Specifies the SPI data width.
- This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetDataWidth().*/
-
- uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref
- SPI_LL_EC_POLARITY.
-
- This feature can be modified afterwards using
- unitary function @ref LL_SPI_SetClockPolarity().*/
-
- uint32_t
- ClockPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetClockPhase().*/
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware
- (NSS pin) or by software using the SSI bit. This parameter
- can be a value of @ref SPI_LL_EC_NSS_MODE.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetNSSMode().*/
-
- uint32_t
- BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
- to configure the transmit and receive SCK clock. This
- parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetBaudRatePrescaler().*/
-
- uint32_t
- BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetTransferBitOrder().*/
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or
- not. This parameter can be a value of @ref
- SPI_LL_EC_CRC_CALCULATION.
-
- This feature can be modified afterwards using
- unitary functions @ref LL_SPI_EnableCRC() and @ref
- LL_SPI_DisableCRC().*/
-
- uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0x00
- and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary
- function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_SPI_ReadReg function
- * @{
- */
-#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
-#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
-#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
-#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
-#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and
- * LL_SPI_WriteReg functions
- * @{
- */
-#define LL_SPI_CR2_RXNEIE \
- SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE \
- SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_SPI_CR2_ERRIE \
- SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_SPI_MODE_MASTER \
- (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
- * @{
- */
-#define LL_SPI_PROTOCOL_MOTOROLA \
- 0x00000000U /*!< Motorola mode. Used as default value */
-#define LL_SPI_PROTOCOL_TI \
- (SPI_CR2_FRF) /*!< TI mode */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_SPI_PHASE_1EDGE \
- 0x00000000U /*!< First clock transition is the first data capture edge */
-#define LL_SPI_PHASE_2EDGE \
- (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge \
- */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
- * @{
- */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2 \
- 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4 \
- (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8 \
- (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16 \
- (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32 \
- (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64 \
- (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128 \
- (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256 \
- (SPI_CR1_BR_2 | SPI_CR1_BR_1 | \
- SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
- * @{
- */
-#define LL_SPI_LSB_FIRST \
- (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST \
- 0x00000000U /*!< Data is transmitted/received with the MSB first */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
- * @{
- */
-#define LL_SPI_FULL_DUPLEX \
- 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX \
- (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
-#define LL_SPI_HALF_DUPLEX_RX \
- (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
-#define LL_SPI_HALF_DUPLEX_TX \
- (SPI_CR1_BIDIMODE | \
- SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
- * @{
- */
-#define LL_SPI_NSS_SOFT \
- (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
-#define LL_SPI_NSS_HARD_INPUT \
- 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
-#define LL_SPI_NSS_HARD_OUTPUT \
- (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in \
- Slave mode as chip select */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_SPI_DATAWIDTH_4BIT \
- (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
-#define LL_SPI_DATAWIDTH_5BIT \
- (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
-#define LL_SPI_DATAWIDTH_6BIT \
- (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
-#define LL_SPI_DATAWIDTH_7BIT \
- (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
-#define LL_SPI_DATAWIDTH_8BIT \
- (SPI_CR2_DS_2 | SPI_CR2_DS_1 | \
- SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
-#define LL_SPI_DATAWIDTH_9BIT \
- (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
-#define LL_SPI_DATAWIDTH_10BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
-#define LL_SPI_DATAWIDTH_11BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
-#define LL_SPI_DATAWIDTH_12BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_1 | \
- SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
-#define LL_SPI_DATAWIDTH_13BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
-#define LL_SPI_DATAWIDTH_14BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_2 | \
- SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
-#define LL_SPI_DATAWIDTH_15BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_2 | \
- SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
-#define LL_SPI_DATAWIDTH_16BIT \
- (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | \
- SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
- * @{
- */
-#define LL_SPI_CRCCALCULATION_DISABLE \
- 0x00000000U /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE \
- (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
- * @{
- */
-#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
-#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
- * @{
- */
-#define LL_SPI_RX_FIFO_TH_HALF \
- 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or \
- equal to 1/2 (16-bit) */
-#define LL_SPI_RX_FIFO_TH_QUARTER \
- (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than \
- or equal to 1/4 (8-bit) */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
- * @{
- */
-#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
-#define LL_SPI_RX_FIFO_QUARTER_FULL \
- (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
-#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
-#define LL_SPI_RX_FIFO_FULL \
- (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
- * @{
- */
-#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
-#define LL_SPI_TX_FIFO_QUARTER_FULL \
- (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
-#define LL_SPI_TX_FIFO_HALF_FULL \
- (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
-#define LL_SPI_TX_FIFO_FULL \
- (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
- * @{
- */
-#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
-#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable SPI peripheral
- * @rmtoll CR1 SPE LL_SPI_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Disable SPI peripheral
- * @note When disabling the SPI, follow the procedure described in the
- * Reference Manual.
- * @rmtoll CR1 SPE LL_SPI_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Check if SPI peripheral is enabled
- * @rmtoll CR1 SPE LL_SPI_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set SPI operation mode to Master or Slave
- * @note This bit should not be changed when communication is ongoing.
- * @rmtoll CR1 MSTR LL_SPI_SetMode\n
- * CR1 SSI LL_SPI_SetMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
- * @brief Get SPI operation mode (Master or Slave)
- * @rmtoll CR1 MSTR LL_SPI_GetMode\n
- * CR1 SSI LL_SPI_GetMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-/**
- * @brief Set serial protocol used
- * @note This bit should be written only when SPI is disabled (SPE = 0) for
- * correct operation.
- * @rmtoll CR2 FRF LL_SPI_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
- * @arg @ref LL_SPI_PROTOCOL_TI
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) {
- MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
-}
-
-/**
- * @brief Get serial protocol used
- * @rmtoll CR2 FRF LL_SPI_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
- * @arg @ref LL_SPI_PROTOCOL_TI
- */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
-}
-
-/**
- * @brief Set clock phase
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
- * @param SPIx SPI Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx,
- uint32_t ClockPhase) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
- * @brief Get clock phase
- * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
- * @brief Set clock polarity
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx,
- uint32_t ClockPolarity) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Get clock polarity
- * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
- * @brief Set baud rate prescaler
- * @note These bits should not be changed when communication is ongoing. SPI
- * BaudRate = fPCLK/Prescaler.
- * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @param BaudRate This parameter can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx,
- uint32_t BaudRate) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
- * @brief Get baud rate prescaler
- * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
- * @brief Set transfer bit order
- * @note This bit should not be changed when communication is ongoing. This
- * bit is not used in SPI TI mode.
- * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
- * @param SPIx SPI Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx,
- uint32_t BitOrder) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
- * @brief Get transfer bit order
- * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
- * @brief Set transfer direction mode
- * @note For Half-Duplex mode, Rx Direction is set by default.
- * In master mode, the MOSI pin is used and in slave mode, the MISO pin
- * is used for Half-Duplex.
- * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
- * CR1 BIDIOE LL_SPI_SetTransferDirection
- * @param SPIx SPI Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx,
- uint32_t TransferDirection) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE,
- TransferDirection);
-}
-
-/**
- * @brief Get transfer direction mode
- * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
- * CR1 BIDIOE LL_SPI_GetTransferDirection
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(
- SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
- * @brief Set frame data width
- * @rmtoll CR2 DS LL_SPI_SetDataWidth
- * @param SPIx SPI Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_4BIT
- * @arg @ref LL_SPI_DATAWIDTH_5BIT
- * @arg @ref LL_SPI_DATAWIDTH_6BIT
- * @arg @ref LL_SPI_DATAWIDTH_7BIT
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_9BIT
- * @arg @ref LL_SPI_DATAWIDTH_10BIT
- * @arg @ref LL_SPI_DATAWIDTH_11BIT
- * @arg @ref LL_SPI_DATAWIDTH_12BIT
- * @arg @ref LL_SPI_DATAWIDTH_13BIT
- * @arg @ref LL_SPI_DATAWIDTH_14BIT
- * @arg @ref LL_SPI_DATAWIDTH_15BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx,
- uint32_t DataWidth) {
- MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
-}
-
-/**
- * @brief Get frame data width
- * @rmtoll CR2 DS LL_SPI_GetDataWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_4BIT
- * @arg @ref LL_SPI_DATAWIDTH_5BIT
- * @arg @ref LL_SPI_DATAWIDTH_6BIT
- * @arg @ref LL_SPI_DATAWIDTH_7BIT
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_9BIT
- * @arg @ref LL_SPI_DATAWIDTH_10BIT
- * @arg @ref LL_SPI_DATAWIDTH_11BIT
- * @arg @ref LL_SPI_DATAWIDTH_12BIT
- * @arg @ref LL_SPI_DATAWIDTH_13BIT
- * @arg @ref LL_SPI_DATAWIDTH_14BIT
- * @arg @ref LL_SPI_DATAWIDTH_15BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
-}
-
-/**
- * @brief Set threshold of RXFIFO that triggers an RXNE event
- * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
- * @param SPIx SPI Instance
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_SPI_RX_FIFO_TH_HALF
- * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx,
- uint32_t Threshold) {
- MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
-}
-
-/**
- * @brief Get threshold of RXFIFO that triggers an RXNE event
- * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_RX_FIFO_TH_HALF
- * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
- * @{
- */
-
-/**
- * @brief Enable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for
- * correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Disable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for
- * correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Check if CRC is enabled
- * @note This bit should be written only when SPI is disabled (SPE = 0) for
- * correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set CRC Length
- * @note This bit should be written only when SPI is disabled (SPE = 0) for
- * correct operation.
- * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
- * @param SPIx SPI Instance
- * @param CRCLength This parameter can be one of the following values:
- * @arg @ref LL_SPI_CRC_8BIT
- * @arg @ref LL_SPI_CRC_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
-}
-
-/**
- * @brief Get CRC Length
- * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_CRC_8BIT
- * @arg @ref LL_SPI_CRC_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
-}
-
-/**
- * @brief Set CRCNext to transfer CRC on the line
- * @note This bit has to be written as soon as the last data is written in the
- * SPIx_DR register.
- * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
- * @brief Set polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
- * @param SPIx SPI Instance
- * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and
- * Max_Data = 0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx,
- uint32_t CRCPoly) {
- WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
- * @brief Get polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data =
- * 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
- * @brief Get Rx CRC
- * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data =
- * 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
- * @brief Get Tx CRC
- * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data =
- * 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
- * @{
- */
-
-/**
- * @brief Set NSS mode
- * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
- * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
- * @param SPIx SPI Instance
- * @param NSS This parameter can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) {
- MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
- * @brief Get NSS mode
- * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) {
- uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
- return (Ssm | Ssoe);
-}
-
-/**
- * @brief Enable NSS pulse management
- * @note This bit should not be changed when communication is ongoing. This
- * bit is not used in SPI TI mode.
- * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
-}
-
-/**
- * @brief Disable NSS pulse management
- * @note This bit should not be changed when communication is ongoing. This
- * bit is not used in SPI TI mode.
- * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
-}
-
-/**
- * @brief Check if NSS pulse is enabled
- * @note This bit should not be changed when communication is ongoing. This
- * bit is not used in SPI TI mode.
- * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get CRC error flag
- * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get mode fault error flag
- * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get busy flag
- * @note The BSY flag is cleared under any one of the following conditions:
- * -When the SPI is correctly disabled
- * -When a fault is detected in Master mode (MODF bit set to 1)
- * -In Master mode, when it finishes a data transmission and no new data is
- * ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least
- * one SPI clock cycle between each data transfer.
- * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get frame format error flag
- * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get FIFO reception Level
- * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_RX_FIFO_EMPTY
- * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
- * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
- * @arg @ref LL_SPI_RX_FIFO_FULL
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
-}
-
-/**
- * @brief Get FIFO Transmission Level
- * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_TX_FIFO_EMPTY
- * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
- * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
- * @arg @ref LL_SPI_TX_FIFO_FULL
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
-}
-
-/**
- * @brief Clear CRC error flag
- * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
- * @brief Clear mode fault error flag
- * @note Clearing this flag is done by a read access to the SPIx_SR
- * register followed by a write access to the SPIx_CR1 register
- * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) {
- __IO uint32_t tmpreg_sr;
- tmpreg_sr = SPIx->SR;
- (void)tmpreg_sr;
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Clear overrun error flag
- * @note Clearing this flag is done by a read access to the SPIx_DR
- * register followed by a read access to the SPIx_SR register
- * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) {
- __IO uint32_t tmpreg;
- tmpreg = SPIx->DR;
- (void)tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @brief Clear frame format error flag
- * @note Clearing this flag is done by reading SPIx_SR register
- * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) {
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error
- * condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Enable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Enable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error
- * condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Disable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Disable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Check if error interrupt is enabled
- * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if Rx buffer not empty interrupt is enabled
- * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set parity of Last DMA reception
- * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
- * @param SPIx SPI Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx,
- uint32_t Parity) {
- MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
-}
-
-/**
- * @brief Get parity configuration for Last DMA reception
- * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
-}
-
-/**
- * @brief Set parity of Last DMA transmission
- * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
- * @param SPIx SPI Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx,
- uint32_t Parity) {
- MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
-}
-
-/**
- * @brief Get parity configuration for Last DMA transmission
- * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
- * @param SPIx SPI Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) {
- return (uint32_t) & (SPIx->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
- * @{
- */
-
-/**
- * @brief Read 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData8
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) {
- return (*((__IO uint8_t *)&SPIx->DR));
-}
-
-/**
- * @brief Read 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) {
- return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Write 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData8
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) {
-#if defined(__GNUC__)
- __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
- *spidr = TxData;
-#else
- *((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
- * @brief Write 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) {
-#if defined(__GNUC__)
- __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
- *spidr = TxData;
-#else
- SPIx->DR = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
- * @{
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct {
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_LL_EC_MODE
-
- This feature can be modified afterwards using unitary
- function @ref LL_I2S_SetTransferMode().*/
-
- uint32_t
- Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
- This feature can be modified afterwards using unitary
- function @ref LL_I2S_SetStandard().*/
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref
- I2S_LL_EC_DATA_FORMAT
-
- This feature can be modified afterwards using
- unitary function @ref LL_I2S_SetDataFormat().*/
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or
- not. This parameter can be a value of @ref
- I2S_LL_EC_MCLK_OUTPUT
-
- This feature can be modified afterwards using
- unitary functions @ref LL_I2S_EnableMasterClock() or
- @ref LL_I2S_DisableMasterClock.*/
-
- uint32_t
- AudioFreq; /*!< Specifies the frequency selected for the I2S
- communication. This parameter can be a value of @ref
- I2S_LL_EC_AUDIO_FREQ
-
- Audio Frequency can be modified afterwards using Reference
- manual formulas to calculate Prescaler Linear, Parity and
- unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref
- LL_I2S_SetPrescalerParity() to set it.*/
-
- uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref
- I2S_LL_EC_POLARITY
-
- This feature can be modified afterwards using
- unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
- * @{
- */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2S_ReadReg function
- * @{
- */
-#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
-#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
-#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
-#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and
- * LL_SPI_WriteReg functions
- * @{
- */
-#define LL_I2S_CR2_RXNEIE \
- LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE \
- LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_I2S_CR2_ERRIE \
- LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
- * @{
- */
-#define LL_I2S_DATAFORMAT_16B \
- 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED \
- (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_24B \
- (SPI_I2SCFGR_CHLEN | \
- SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_32B \
- (SPI_I2SCFGR_CHLEN | \
- SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_I2S_POLARITY_LOW \
- 0x00000000U /*!< Clock steady state is low level \
- */
-#define LL_I2S_POLARITY_HIGH \
- (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
- * @{
- */
-#define LL_I2S_STANDARD_PHILIPS \
- 0x00000000U /*!< I2S standard philips */
-#define LL_I2S_STANDARD_MSB \
- (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
-#define LL_I2S_STANDARD_LSB \
- (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
-#define LL_I2S_STANDARD_PCM_SHORT \
- (SPI_I2SCFGR_I2SSTD_0 | \
- SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG \
- (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | \
- SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
-#define LL_I2S_MODE_SLAVE_RX \
- (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
-#define LL_I2S_MODE_MASTER_TX \
- (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX \
- (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration \
- */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
- * @{
- */
-#define LL_I2S_PRESCALER_PARITY_EVEN \
- 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
-#define LL_I2S_PRESCALER_PARITY_ODD \
- (SPI_I2SPR_ODD >> \
- 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
- * @{
- */
-#define LL_I2S_MCLK_OUTPUT_DISABLE \
- 0x00000000U /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE \
- (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
- * @{
- */
-
-#define LL_I2S_AUDIOFREQ_192K \
- 192000U /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K \
- 96000U /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K \
- 48000U /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K \
- 44100U /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K \
- 32000U /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K \
- 22050U /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K \
- 16000U /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K \
- 11025U /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K \
- 8000U /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT \
- 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Select I2S mode and Enable I2S peripheral
- * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
- * I2SCFGR I2SE LL_I2S_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Disable I2S peripheral
- * @rmtoll I2SCFGR I2SE LL_I2S_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Check if I2S peripheral is enabled
- * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_SetDataFormat
- * @param SPIx SPI Instance
- * @param DataFormat This parameter can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx,
- uint32_t DataFormat) {
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
- * @brief Get I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_GetDataFormat
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR,
- SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
- * @brief Set I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx,
- uint32_t ClockPolarity) {
- SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
- * @brief Get I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
- * @brief Set I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) {
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
- * @brief Get I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR,
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
- * @brief Set I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) {
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
- * @brief Get I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
- * @brief Set I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
- * @param SPIx SPI Instance
- * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx,
- uint8_t PrescalerLinear) {
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
- * @brief Get I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
- * @param SPIx SPI Instance
- * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
- * @brief Set I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
- * @param SPIx SPI Instance
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx,
- uint32_t PrescalerParity) {
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
- * @brief Get I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) {
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
- * @brief Enable the master clock output (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Disable the master clock output (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Check if the master clock output (Pin MCK) is enabled
- * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL
- : 0UL);
-}
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
-/**
- * @brief Enable asynchronous start
- * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) {
- SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-}
-
-/**
- * @brief Disable asynchronous start
- * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) {
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-}
-
-/**
- * @brief Check if asynchronous start is enabled
- * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) {
- return (
- (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN))
- ? 1UL
- : 0UL);
-}
-#endif /* SPI_I2SCFGR_ASTRTEN */
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) {
- return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) {
- return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
- * @brief Get busy flag
- * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) {
- return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) {
- return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
- * @brief Get underrun error flag
- * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get frame format error flag
- * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) {
- return LL_SPI_IsActiveFlag_FRE(SPIx);
-}
-
-/**
- * @brief Get channel side flag.
- * @note 0: Channel Left has to be transmitted or has been received\n
- * 1: Channel Right has to be transmitted or has been received\n
- * It has no significance in PCM mode.
- * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) {
- return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear overrun error flag
- * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) {
- LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
- * @brief Clear underrun error flag
- * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) {
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @brief Clear frame format error flag
- * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) {
- LL_SPI_ClearFlag_FRE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error IT
- * @note This bit controls the generation of an interrupt when an error
- * condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) {
- LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
- * @brief Enable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) {
- LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Enable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) {
- LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
- * @brief Disable error IT
- * @note This bit controls the generation of an interrupt when an error
- * condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) {
- LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
- * @brief Disable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) {
- LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Disable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) {
- LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
- * @brief Check if ERR IT is enabled
- * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) {
- return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
- * @brief Check if RXNE IT is enabled
- * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) {
- return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
- * @brief Check if TXE IT is enabled
- * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) {
- return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) {
- LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) {
- LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) {
- return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) {
- LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) {
- LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) {
- return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
- * @{
- */
-
-/**
- * @brief Read 16-Bits in data register
- * @rmtoll DR DR LL_I2S_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) {
- return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
- * @brief Write 16-Bits in data register
- * @rmtoll DR DR LL_I2S_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) {
- LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear,
- uint32_t PrescalerParity);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) \
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_SPI_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_SPI_H
+#define STM32G4xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct {
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or
+ bidirectional data mode. This parameter can be
+ a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using
+ unitary function @ref
+ LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetMode().*/
+
+ uint32_t
+ DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref
+ SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t
+ ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware
+ (NSS pin) or by software using the SSI bit. This parameter
+ can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref
+ SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the
+ master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t
+ BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or
+ not. This parameter can be a value of @ref
+ SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using
+ unitary functions @ref LL_SPI_EnableCRC() and @ref
+ LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and
+ * LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE \
+ SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE \
+ SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE \
+ SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER \
+ (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ * @{
+ */
+#define LL_SPI_PROTOCOL_MOTOROLA \
+ 0x00000000U /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI \
+ (SPI_CR2_FRF) /*!< TI mode */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE \
+ 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE \
+ (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 \
+ 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 \
+ (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 \
+ (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 \
+ (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 \
+ (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 \
+ (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 \
+ (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 \
+ (SPI_CR1_BR_2 | SPI_CR1_BR_1 | \
+ SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST \
+ (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST \
+ 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX \
+ 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX \
+ (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX \
+ (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX \
+ (SPI_CR1_BIDIMODE | \
+ SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT \
+ (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT \
+ 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT \
+ (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in \
+ Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_4BIT \
+ (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
+#define LL_SPI_DATAWIDTH_5BIT \
+ (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
+#define LL_SPI_DATAWIDTH_6BIT \
+ (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
+#define LL_SPI_DATAWIDTH_7BIT \
+ (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
+#define LL_SPI_DATAWIDTH_8BIT \
+ (SPI_CR2_DS_2 | SPI_CR2_DS_1 | \
+ SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_9BIT \
+ (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
+#define LL_SPI_DATAWIDTH_10BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_1 | \
+ SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_2 | \
+ SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_2 | \
+ SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT \
+ (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | \
+ SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE \
+ 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE \
+ (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+ * @{
+ */
+#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
+#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+ * @{
+ */
+#define LL_SPI_RX_FIFO_TH_HALF \
+ 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or \
+ equal to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER \
+ (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than \
+ or equal to 1/4 (8-bit) */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+ * @{
+ */
+#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL \
+ (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
+#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
+#define LL_SPI_RX_FIFO_FULL \
+ (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+ * @{
+ */
+#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL \
+ (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
+#define LL_SPI_TX_FIFO_HALF_FULL \
+ (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
+#define LL_SPI_TX_FIFO_FULL \
+ (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+ * @{
+ */
+#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the
+ * Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+ * @brief Set serial protocol used
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for
+ * correct operation.
+ * @rmtoll CR2 FRF LL_SPI_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) {
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+ * @brief Get serial protocol used
+ * @rmtoll CR2 FRF LL_SPI_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx,
+ uint32_t ClockPhase) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx,
+ uint32_t ClockPolarity) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI
+ * BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx,
+ uint32_t BaudRate) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This
+ * bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx,
+ uint32_t BitOrder) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin
+ * is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx,
+ uint32_t TransferDirection) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE,
+ TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(
+ SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR2 DS LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx,
+ uint32_t DataWidth) {
+ MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR2 DS LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+ * @brief Set threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx,
+ uint32_t Threshold) {
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+ * @brief Get threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for
+ * correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for
+ * correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for
+ * correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set CRC Length
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for
+ * correct operation.
+ * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
+ * @param SPIx SPI Instance
+ * @param CRCLength This parameter can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+ * @brief Get CRC Length
+ * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the
+ * SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and
+ * Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx,
+ uint32_t CRCPoly) {
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data =
+ * 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data =
+ * 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data =
+ * 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) {
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) {
+ uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @brief Enable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This
+ * bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Disable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This
+ * bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Check if NSS pulse is enabled
+ * @note This bit should not be changed when communication is ongoing. This
+ * bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is
+ * ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least
+ * one SPI clock cycle between each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get FIFO reception Level
+ * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_EMPTY
+ * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_RX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+ * @brief Get FIFO Transmission Level
+ * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_TX_FIFO_EMPTY
+ * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_TX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) {
+ __IO uint32_t tmpreg_sr;
+ tmpreg_sr = SPIx->SR;
+ (void)tmpreg_sr;
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) {
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void)tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @note Clearing this flag is done by reading SPIx_SR register
+ * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) {
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error
+ * condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error
+ * condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set parity of Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx,
+ uint32_t Parity) {
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+}
+
+/**
+ * @brief Set parity of Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx,
+ uint32_t Parity) {
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) {
+ return (uint32_t) & (SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) {
+ return (*((__IO uint8_t *)&SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) {
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) {
+#if defined(__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) {
+#if defined(__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ SPIx->DR = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct {
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t
+ Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_I2S_SetStandard().*/
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref
+ I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_I2S_SetDataFormat().*/
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or
+ not. This parameter can be a value of @ref
+ I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using
+ unitary functions @ref LL_I2S_EnableMasterClock() or
+ @ref LL_I2S_DisableMasterClock.*/
+
+ uint32_t
+ AudioFreq; /*!< Specifies the frequency selected for the I2S
+ communication. This parameter can be a value of @ref
+ I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference
+ manual formulas to calculate Prescaler Linear, Parity and
+ unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref
+ LL_I2S_SetPrescalerParity() to set it.*/
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref
+ I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and
+ * LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE \
+ LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE \
+ LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE \
+ LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B \
+ 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED \
+ (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_24B \
+ (SPI_I2SCFGR_CHLEN | \
+ SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_32B \
+ (SPI_I2SCFGR_CHLEN | \
+ SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW \
+ 0x00000000U /*!< Clock steady state is low level \
+ */
+#define LL_I2S_POLARITY_HIGH \
+ (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS \
+ 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB \
+ (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB \
+ (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT \
+ (SPI_I2SCFGR_I2SSTD_0 | \
+ SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG \
+ (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | \
+ SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX \
+ (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX \
+ (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX \
+ (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN \
+ 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD \
+ (SPI_I2SPR_ODD >> \
+ 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE \
+ 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE \
+ (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K \
+ 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K \
+ 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K \
+ 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K \
+ 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K \
+ 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K \
+ 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K \
+ 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K \
+ 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K \
+ 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT \
+ 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx,
+ uint32_t DataFormat) {
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR,
+ SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx,
+ uint32_t ClockPolarity) {
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) {
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR,
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) {
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx,
+ uint8_t PrescalerLinear) {
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx,
+ uint32_t PrescalerParity) {
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) {
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock output (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock output (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock output (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL
+ : 0UL);
+}
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+/**
+ * @brief Enable asynchronous start
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) {
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+ * @brief Disable asynchronous start
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) {
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+ * @brief Check if asynchronous start is enabled
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) {
+ return (
+ (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN))
+ ? 1UL
+ : 0UL);
+}
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) {
+ return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) {
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) {
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) {
+ LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error
+ * condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) {
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) {
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) {
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error
+ * condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) {
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) {
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) {
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) {
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) {
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) {
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) {
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) {
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) {
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) {
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear,
+ uint32_t PrescalerParity);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) \
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_SPI_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h
index cf7b83c..210d525 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h
@@ -1,1627 +1,1630 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_system.h
- * @author MCD Application Team
- * @brief Header file of SYSTEM LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL SYSTEM driver contains a set of generic APIs that can be
- used by user:
- (+) Some of the FLASH features need to be handled in the SYSTEM file.
- (+) Access to DBGCMU registers
- (+) Access to SYSCFG registers
- (+) Access to VREFBUF registers
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_SYSTEM_H
-#define __STM32G4xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(FLASH) || defined(SYSCFG) || defined(DBGMCU) || defined(VREFBUF)
-
-/** @defgroup SYSTEM_LL SYSTEM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
- * @{
- */
-
-/* Defines used for position in the register */
-#define DBGMCU_REVID_POSITION (uint32_t) POSITION_VAL(DBGMCU_IDCODE_REV_ID)
-
-/**
- * @brief Power-down in Run mode Flash key
- */
-#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
-#define FLASH_PDKEY2 \
- 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 \
- to unlock the RUN_PD bit in FLASH_ACR */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
- * @{
- */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
- * @{
- */
-#define LL_SYSCFG_REMAP_FLASH \
- 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH \
- SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SRAM \
- (SYSCFG_MEMRMP_MEM_MODE_1 | \
- SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
-#if defined(FMC_Bank1_R)
-#define LL_SYSCFG_REMAP_FMC \
- SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at \
- 0x00000000 */
-#endif /* FMC_Bank1_R */
-#define LL_SYSCFG_REMAP_QUADSPI \
- (SYSCFG_MEMRMP_MEM_MODE_2 | \
- SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
-/**
- * @}
- */
-
-#if defined(SYSCFG_MEMRMP_FB_MODE)
-/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
- * @{
- */
-#define LL_SYSCFG_BANKMODE_BANK1 \
- 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) \
- and Flash Bank2 mapped at 0x08040000 (and aliased at \
- 0x00080000) */
-#define LL_SYSCFG_BANKMODE_BANK2 \
- SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased \
- @0x00000000) and Flash Bank1 mapped at 0x08040000 \
- (and aliased at 0x00080000) */
-/**
- * @}
- */
-
-#endif /* SYSCFG_MEMRMP_FB_MODE */
-/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
- * @{
- */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 \
- SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 \
- SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 \
- SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 \
- SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 \
- SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
-#if defined(I2C2)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 \
- SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
-#endif /* I2C2 */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 \
- SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
-#if defined(I2C4)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 \
- SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
-#endif /* I2C4 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
- * @{
- */
-#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
-#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
-#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
-#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
-#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
-#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
-#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
- * @{
- */
-#define LL_SYSCFG_EXTI_LINE0 \
- (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE1 \
- (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE2 \
- (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE3 \
- (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE4 \
- (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE5 \
- (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE6 \
- (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE7 \
- (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE8 \
- (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE9 \
- (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE10 \
- (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE11 \
- (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE12 \
- (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE13 \
- (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE14 \
- (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE15 \
- (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
- * @{
- */
-#define LL_SYSCFG_TIMBREAK_ECC \
- SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal \
- with Break Input of TIM1/8/15/16/17 */
-#define LL_SYSCFG_TIMBREAK_PVD \
- SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection \
- with TIM1/8/15/16/17 Break Input \
- and also the PVDE and PLS bits of the Power Control \
- Interface */
-#define LL_SYSCFG_TIMBREAK_SRAM_PARITY \
- SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal \
- with Break Input of TIM1/8/15/16/17 */
-#define LL_SYSCFG_TIMBREAK_LOCKUP \
- SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 \
- with Break Input of TIM1/15/16/17 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
- * @{
- */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE0 \
- SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE1 \
- SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE2 \
- SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE3 \
- SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE4 \
- SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE5 \
- SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE6 \
- SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE7 \
- SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE8 \
- SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE9 \
- SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
-#if defined(SYSCFG_SWPR_PAGE10)
-#define LL_SYSCFG_CCMSRAMWRP_PAGE10 \
- SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE11 \
- SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE12 \
- SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE13 \
- SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE14 \
- SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE15 \
- SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE16 \
- SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE17 \
- SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE18 \
- SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE19 \
- SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE20 \
- SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE21 \
- SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE22 \
- SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE23 \
- SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE24 \
- SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE25 \
- SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE26 \
- SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE27 \
- SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE28 \
- SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE29 \
- SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE30 \
- SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
-#define LL_SYSCFG_CCMSRAMWRP_PAGE31 \
- SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
-#endif /* SYSCFG_SWPR_PAGE10 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
- * @{
- */
-#define LL_DBGMCU_TRACE_NONE \
- 0x00000000U /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH \
- DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1 \
- (DBGMCU_CR_TRACE_IOEN | \
- DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with \
- a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2 \
- (DBGMCU_CR_TRACE_IOEN | \
- DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with \
- a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4 \
- (DBGMCU_CR_TRACE_IOEN | \
- DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a \
- TRACEDATA size of 4 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP \
- DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when \
- the core is halted*/
-#if defined(TIM3)
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP \
- DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when \
- the core is halted*/
-#endif /* TIM3 */
-#if defined(TIM4)
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP \
- DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when \
- the core is halted*/
-#endif /* TIM4 */
-#if defined(TIM5)
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP \
- DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when \
- the core is halted*/
-#endif /* TIM5 */
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP \
- DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when \
- the core is halted*/
-#if defined(TIM7)
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP \
- DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when \
- the core is halted*/
-#endif /* TIM7 */
-#define LL_DBGMCU_APB1_GRP1_RTC_STOP \
- DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped \
- when the core is halted*/
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP \
- DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is \
- stopped when the core is halted*/
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP \
- DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is \
- stopped when the core is halted*/
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP \
- DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
-#if defined(I2C2)
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP \
- DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
-#endif /* I2C2 */
-#define LL_DBGMCU_APB1_GRP1_I2C3_STOP \
- DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
-#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP \
- DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped \
- when the core is halted*/
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
- * @{
- */
-#if defined(I2C4)
-#define LL_DBGMCU_APB1_GRP2_I2C4_STOP \
- DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
-#endif /* I2C4 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP \
- DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when \
- the core is halted*/
-#if defined(TIM8)
-#define LL_DBGMCU_APB2_GRP1_TIM8_STOP \
- DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when \
- the core is halted*/
-#endif /* TIM8 */
-#define LL_DBGMCU_APB2_GRP1_TIM15_STOP \
- DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when \
- the core is halted*/
-#define LL_DBGMCU_APB2_GRP1_TIM16_STOP \
- DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when \
- the core is halted*/
-#if defined(TIM17)
-#define LL_DBGMCU_APB2_GRP1_TIM17_STOP \
- DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when \
- the core is halted*/
-#endif /* TIM17 */
-#if defined(TIM20)
-#define LL_DBGMCU_APB2_GRP1_TIM20_STOP \
- DBGMCU_APB2FZ_DBG_TIM20_STOP /*!< The counter clock of TIM20 is stopped when \
- the core is halted*/
-#endif /* TIM20 */
-#if defined(HRTIM1)
-#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP \
- DBGMCU_APB2FZ_DBG_HRTIM1_STOP /*!< The counter clock of HRTIM1 is stopped \
- when the core is halted*/
-#endif /* HRTIM1 */
-/**
- * @}
- */
-
-#if defined(VREFBUF)
-/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
- * @{
- */
-#define LL_VREFBUF_VOLTAGE_SCALE0 \
- ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) \
- */
-#define LL_VREFBUF_VOLTAGE_SCALE1 \
- VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
-#define LL_VREFBUF_VOLTAGE_SCALE2 \
- VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
-/**
- * @}
- */
-#endif /* VREFBUF */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
- * @{
- */
-#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
-#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
-#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
-#define LL_FLASH_LATENCY_3 \
- FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states \
- */
-#define LL_FLASH_LATENCY_4 \
- FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states \
- */
-#if defined(FLASH_ACR_LATENCY_5WS)
-#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
-#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
-#define LL_FLASH_LATENCY_7 \
- FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states \
- */
-#define LL_FLASH_LATENCY_8 \
- FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states \
- */
-#define LL_FLASH_LATENCY_9 \
- FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states \
- */
-#define LL_FLASH_LATENCY_10 \
- FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states \
- */
-#define LL_FLASH_LATENCY_11 \
- FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
-#define LL_FLASH_LATENCY_12 \
- FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
-#define LL_FLASH_LATENCY_13 \
- FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
-#define LL_FLASH_LATENCY_14 \
- FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
-#define LL_FLASH_LATENCY_15 \
- FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
-#endif /* FLASH_ACR_LATENCY_5WS */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
- * @{
- */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
- * @{
- */
-
-/**
- * @brief Set memory mapping at address 0x00000000
- * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
- * @param Memory This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_REMAP_FLASH
- * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
- * @arg @ref LL_SYSCFG_REMAP_SRAM
- * @arg @ref LL_SYSCFG_REMAP_FMC (*)
- * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) {
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
-}
-
-/**
- * @brief Get memory mapping at address 0x00000000
- * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_REMAP_FLASH
- * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
- * @arg @ref LL_SYSCFG_REMAP_SRAM
- * @arg @ref LL_SYSCFG_REMAP_FMC (*)
- * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) {
- return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
-}
-
-#if defined(SYSCFG_MEMRMP_FB_MODE)
-/**
- * @brief Select Flash bank mode (Bank flashed at 0x08000000)
- * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
- * @param Bank This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_BANKMODE_BANK1
- * @arg @ref LL_SYSCFG_BANKMODE_BANK2
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) {
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
-}
-
-/**
- * @brief Get Flash bank mode (Bank flashed at 0x08000000)
- * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_BANKMODE_BANK1
- * @arg @ref LL_SYSCFG_BANKMODE_BANK2
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) {
- return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
-}
-#endif /* SYSCFG_MEMRMP_FB_MODE */
-
-/**
- * @brief Enable I/O analog switch voltage booster.
- * @note When voltage booster is enabled, I/O analog switches are supplied
- * by a dedicated voltage booster, from VDD power domain. This is
- * the recommended configuration with low VDDA voltage operation.
- * @note The I/O analog switch voltage booster is relevant for peripherals
- * using I/O in analog input: ADC, COMP, OPAMP.
- * However, COMP and OPAMP inputs have a high impedance and
- * voltage booster do not impact performance significantly.
- * Therefore, the voltage booster is mainly intended for
- * usage with ADC.
- * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
- * @brief Disable I/O analog switch voltage booster.
- * @note When voltage booster is enabled, I/O analog switches are supplied
- * by a dedicated voltage booster, from VDD power domain. This is
- * the recommended configuration with low VDDA voltage operation.
- * @note The I/O analog switch voltage booster is relevant for peripherals
- * using I/O in analog input: ADC, COMP, OPAMP.
- * However, COMP and OPAMP inputs have a high impedance and
- * voltage booster do not impact performance significantly.
- * Therefore, the voltage booster is mainly intended for
- * usage with ADC.
- * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
- * @brief Enable the I2C fast mode plus driving capability.
- * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
- * @param ConfigFastModePlus This parameter can be a combination of the
- * following values:
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) {
- SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
-}
-
-/**
- * @brief Disable the I2C fast mode plus driving capability.
- * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
- * @param ConfigFastModePlus This parameter can be a combination of the
- * following values:
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(
- uint32_t ConfigFastModePlus) {
- CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
-}
-
-/**
- * @brief Enable Floating Point Unit Invalid operation Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
-}
-
-/**
- * @brief Enable Floating Point Unit Divide-by-zero Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
-}
-
-/**
- * @brief Enable Floating Point Unit Underflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
-}
-
-/**
- * @brief Enable Floating Point Unit Overflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
-}
-
-/**
- * @brief Enable Floating Point Unit Input denormal Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
-}
-
-/**
- * @brief Enable Floating Point Unit Inexact Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
-}
-
-/**
- * @brief Disable Floating Point Unit Invalid operation Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
-}
-
-/**
- * @brief Disable Floating Point Unit Divide-by-zero Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
-}
-
-/**
- * @brief Disable Floating Point Unit Underflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
-}
-
-/**
- * @brief Disable Floating Point Unit Overflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
-}
-
-/**
- * @brief Disable Floating Point Unit Input denormal Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
-}
-
-/**
- * @brief Disable Floating Point Unit Inexact Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
-}
-
-/**
- * @brief Check if Floating Point Unit Invalid operation Interrupt source is
- * enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) {
- return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) ==
- (SYSCFG_CFGR1_FPU_IE_0))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is
- * enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) {
- return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) ==
- (SYSCFG_CFGR1_FPU_IE_1))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or
- * disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) {
- return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) ==
- (SYSCFG_CFGR1_FPU_IE_2))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or
- * disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) {
- return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) ==
- (SYSCFG_CFGR1_FPU_IE_3))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Floating Point Unit Input denormal Interrupt source is
- * enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) {
- return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) ==
- (SYSCFG_CFGR1_FPU_IE_4))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or
- * disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) {
- return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) ==
- (SYSCFG_CFGR1_FPU_IE_5))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configure source input for the EXTI external interrupt.
- * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
- * @param Port This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_PORTA
- * @arg @ref LL_SYSCFG_EXTI_PORTB
- * @arg @ref LL_SYSCFG_EXTI_PORTC
- * @arg @ref LL_SYSCFG_EXTI_PORTD
- * @arg @ref LL_SYSCFG_EXTI_PORTE
- * @arg @ref LL_SYSCFG_EXTI_PORTF
- * @arg @ref LL_SYSCFG_EXTI_PORTG
- *
- * (*) value not defined in all devices
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_LINE0
- * @arg @ref LL_SYSCFG_EXTI_LINE1
- * @arg @ref LL_SYSCFG_EXTI_LINE2
- * @arg @ref LL_SYSCFG_EXTI_LINE3
- * @arg @ref LL_SYSCFG_EXTI_LINE4
- * @arg @ref LL_SYSCFG_EXTI_LINE5
- * @arg @ref LL_SYSCFG_EXTI_LINE6
- * @arg @ref LL_SYSCFG_EXTI_LINE7
- * @arg @ref LL_SYSCFG_EXTI_LINE8
- * @arg @ref LL_SYSCFG_EXTI_LINE9
- * @arg @ref LL_SYSCFG_EXTI_LINE10
- * @arg @ref LL_SYSCFG_EXTI_LINE11
- * @arg @ref LL_SYSCFG_EXTI_LINE12
- * @arg @ref LL_SYSCFG_EXTI_LINE13
- * @arg @ref LL_SYSCFG_EXTI_LINE14
- * @arg @ref LL_SYSCFG_EXTI_LINE15
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) {
- MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U),
- Port << (POSITION_VAL((Line >> 16U)) & 0x1FU));
-}
-
-/**
- * @brief Get the configured defined for specific EXTI Line
- * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_LINE0
- * @arg @ref LL_SYSCFG_EXTI_LINE1
- * @arg @ref LL_SYSCFG_EXTI_LINE2
- * @arg @ref LL_SYSCFG_EXTI_LINE3
- * @arg @ref LL_SYSCFG_EXTI_LINE4
- * @arg @ref LL_SYSCFG_EXTI_LINE5
- * @arg @ref LL_SYSCFG_EXTI_LINE6
- * @arg @ref LL_SYSCFG_EXTI_LINE7
- * @arg @ref LL_SYSCFG_EXTI_LINE8
- * @arg @ref LL_SYSCFG_EXTI_LINE9
- * @arg @ref LL_SYSCFG_EXTI_LINE10
- * @arg @ref LL_SYSCFG_EXTI_LINE11
- * @arg @ref LL_SYSCFG_EXTI_LINE12
- * @arg @ref LL_SYSCFG_EXTI_LINE13
- * @arg @ref LL_SYSCFG_EXTI_LINE14
- * @arg @ref LL_SYSCFG_EXTI_LINE15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_PORTA
- * @arg @ref LL_SYSCFG_EXTI_PORTB
- * @arg @ref LL_SYSCFG_EXTI_PORTC
- * @arg @ref LL_SYSCFG_EXTI_PORTD
- * @arg @ref LL_SYSCFG_EXTI_PORTE
- * @arg @ref LL_SYSCFG_EXTI_PORTF
- * @arg @ref LL_SYSCFG_EXTI_PORTG
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) {
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >>
- (POSITION_VAL(Line >> 16U) & 0x1FU));
-}
-
-/**
- * @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This
- * bit is automatically cleared at the end of the CCMSRAM erase operation.)
- * @note This bit is write-protected: setting this bit is possible only after
- * the correct key sequence is written in the SYSCFG_SKR register as described
- * in the Reference Manual.
- * @rmtoll SYSCFG_SCSR CCMER LL_SYSCFG_EnableCCMSRAMErase
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void) {
- /* Starts a hardware CCMSRAM erase operation*/
- SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
-}
-
-/**
- * @brief Check if CCMSRAM erase operation is on going
- * @rmtoll SYSCFG_SCSR CCMBSY LL_SYSCFG_IsCCMSRAMEraseOngoing
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void) {
- return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set connections to TIM1/8/15/16/17 Break inputs
- * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
- * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
- * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
- * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
- * @param Break This parameter can be a combination of the following values:
- * @arg @ref LL_SYSCFG_TIMBREAK_ECC
- * @arg @ref LL_SYSCFG_TIMBREAK_PVD
- * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
- * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) {
- MODIFY_REG(SYSCFG->CFGR2,
- SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL |
- SYSCFG_CFGR2_ECCL,
- Break);
-}
-
-/**
- * @brief Get connections to TIM1/8/15/16/17 Break inputs
- * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
- * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
- * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
- * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
- * @retval Returned value can be can be a combination of the following values:
- * @arg @ref LL_SYSCFG_TIMBREAK_ECC
- * @arg @ref LL_SYSCFG_TIMBREAK_PVD
- * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
- * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) {
- return (uint32_t)(READ_BIT(
- SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL |
- SYSCFG_CFGR2_ECCL));
-}
-
-/**
- * @brief Check if SRAM parity error detected
- * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) {
- return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Clear SRAM parity error flag
- * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) {
- SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
-}
-
-/**
- * @brief Enable CCMSRAM page write protection
- * @note Write protection is cleared only by a system reset
- * @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableCCMSRAMPageWRP
- * @param CCMSRAMWRP This parameter can be a combination of the following
- * values:
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP) {
- SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
-}
-
-/**
- * @brief CCMSRAM page write protection lock prior to erase
- * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockCCMSRAMWRP
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void) {
- /* Writing a wrong key reactivates the write protection */
- WRITE_REG(SYSCFG->SKR, 0x00);
-}
-
-/**
- * @brief CCMSRAM page write protection unlock prior to erase
- * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockCCMSRAMWRP
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void) {
- /* unlock the write protection of the CCMER bit */
- WRITE_REG(SYSCFG->SKR, 0xCA);
- WRITE_REG(SYSCFG->SKR, 0x53);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
- * @{
- */
-
-/**
- * @brief Return the device identifier
- * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
- * @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is
- * 0x6415)
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) {
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
- * @brief Return the device revision identifier
- * @note This field indicates the revision of the device.
- * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) {
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >>
- (DBGMCU_REVID_POSITION & 0x1FU));
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Set Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
- * @param PinAssignment This parameter can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) {
- MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE,
- PinAssignment);
-}
-
-/**
- * @brief Get Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) {
- return (uint32_t)(READ_BIT(DBGMCU->CR,
- DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
- * @brief Freeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) {
- SET_BIT(DBGMCU->APB1FZR1, Periphs);
-}
-
-/**
- * @brief Freeze APB1 peripherals (group2 peripherals)
- * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) {
- SET_BIT(DBGMCU->APB1FZR2, Periphs);
-}
-
-/**
- * @brief Unfreeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) {
- CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
-}
-
-/**
- * @brief Unfreeze APB1 peripherals (group2 peripherals)
- * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) {
- CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
-}
-
-/**
- * @brief Freeze APB2 peripherals
- * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) {
- SET_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
- * @brief Unfreeze APB2 peripherals
- * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) {
- CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
- * @}
- */
-
-#if defined(VREFBUF)
-/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
- * @{
- */
-
-/**
- * @brief Enable Internal voltage reference
- * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_VREFBUF_Enable(void) {
- SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-
-/**
- * @brief Disable Internal voltage reference
- * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_VREFBUF_Disable(void) {
- CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-
-/**
- * @brief Enable high impedance (VREF+pin is high impedance)
- * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
- * @retval None
- */
-__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) {
- SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
-}
-
-/**
- * @brief Disable high impedance (VREF+pin is internally connected to the
- * voltage reference buffer output)
- * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
- * @retval None
- */
-__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) {
- CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
-}
-
-/**
- * @brief Set the Voltage reference scale
- * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
- * @param Scale This parameter can be one of the following values:
- * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
- * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
- * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
- * @retval None
- */
-__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) {
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
-}
-
-/**
- * @brief Get the Voltage reference scale
- * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
- * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
- * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
- */
-__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) {
- return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
-}
-
-/**
- * @brief Check if Voltage reference buffer is ready
- * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) {
- return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get the trimming code for VREFBUF calibration
- * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
- * @retval Between 0 and 0x3F
- */
-__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) {
- return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
-}
-
-/**
- * @brief Set the trimming code for VREFBUF calibration (Tune the internal
- * reference buffer voltage)
- * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
- * @param Value Between 0 and 0x3F
- * @retval None
- */
-__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) {
- WRITE_REG(VREFBUF->CCR, Value);
-}
-
-/**
- * @}
- */
-#endif /* VREFBUF */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
- * @{
- */
-
-/**
- * @brief Set FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
- * @param Latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @arg @ref LL_FLASH_LATENCY_3
- * @arg @ref LL_FLASH_LATENCY_4
- * @arg @ref LL_FLASH_LATENCY_5 (*)
- * @arg @ref LL_FLASH_LATENCY_6 (*)
- * @arg @ref LL_FLASH_LATENCY_7 (*)
- * @arg @ref LL_FLASH_LATENCY_8 (*)
- * @arg @ref LL_FLASH_LATENCY_9 (*)
- * @arg @ref LL_FLASH_LATENCY_10 (*)
- * @arg @ref LL_FLASH_LATENCY_11 (*)
- * @arg @ref LL_FLASH_LATENCY_12 (*)
- * @arg @ref LL_FLASH_LATENCY_13 (*)
- * @arg @ref LL_FLASH_LATENCY_14 (*)
- * @arg @ref LL_FLASH_LATENCY_15 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) {
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
- * @brief Get FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @arg @ref LL_FLASH_LATENCY_3
- * @arg @ref LL_FLASH_LATENCY_4
- * @arg @ref LL_FLASH_LATENCY_5 (*)
- * @arg @ref LL_FLASH_LATENCY_6 (*)
- * @arg @ref LL_FLASH_LATENCY_7 (*)
- * @arg @ref LL_FLASH_LATENCY_8 (*)
- * @arg @ref LL_FLASH_LATENCY_9 (*)
- * @arg @ref LL_FLASH_LATENCY_10 (*)
- * @arg @ref LL_FLASH_LATENCY_11 (*)
- * @arg @ref LL_FLASH_LATENCY_12 (*)
- * @arg @ref LL_FLASH_LATENCY_13 (*)
- * @arg @ref LL_FLASH_LATENCY_14 (*)
- * @arg @ref LL_FLASH_LATENCY_15 (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) {
- return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
- * @brief Enable Prefetch
- * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) {
- SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
- * @brief Disable Prefetch
- * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) {
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
- * @brief Check if Prefetch buffer is enabled
- * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) {
- return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable Instruction cache
- * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableInstCache(void) {
- SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
- * @brief Disable Instruction cache
- * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableInstCache(void) {
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
- * @brief Enable Data cache
- * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableDataCache(void) {
- SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
-}
-
-/**
- * @brief Disable Data cache
- * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableDataCache(void) {
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
-}
-
-/**
- * @brief Enable Instruction cache reset
- * @note bit can be written only when the instruction cache is disabled
- * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) {
- SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
- * @brief Disable Instruction cache reset
- * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) {
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
- * @brief Enable Data cache reset
- * @note bit can be written only when the data cache is disabled
- * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) {
- SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
-}
-
-/**
- * @brief Disable Data cache reset
- * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) {
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
-}
-
-/**
- * @brief Enable Flash Power-down mode during run mode or Low-power run mode
- * @note Flash memory can be put in power-down mode only when the code is
- * executed from RAM
- * @note Flash must not be accessed when power down is enabled
- * @note Flash must not be put in power-down while a program or an erase
- * operation is on-going
- * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
- * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
- * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) {
- /* Following values must be written consecutively to unlock the RUN_PD bit in
- FLASH_ACR */
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
- SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
-}
-
-/**
- * @brief Disable Flash Power-down mode during run mode or Low-power run mode
- * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
- * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
- * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) {
- /* Following values must be written consecutively to unlock the RUN_PD bit in
- FLASH_ACR */
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
-}
-
-/**
- * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
- * @note Flash must not be put in power-down while a program or an erase
- * operation is on-going
- * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) {
- SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
-}
-
-/**
- * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
- * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) {
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined \
- (VREFBUF) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_SYSTEM_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_system.h
+ * @author MCD Application Team
+ * @brief Header file of SYSTEM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+ (+) Access to VREFBUF registers
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_SYSTEM_H
+#define __STM32G4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(FLASH) || defined(SYSCFG) || defined(DBGMCU) || defined(VREFBUF)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/* Defines used for position in the register */
+#define DBGMCU_REVID_POSITION (uint32_t) POSITION_VAL(DBGMCU_IDCODE_REV_ID)
+
+/**
+ * @brief Power-down in Run mode Flash key
+ */
+#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
+#define FLASH_PDKEY2 \
+ 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 \
+ to unlock the RUN_PD bit in FLASH_ACR */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+ * @{
+ */
+#define LL_SYSCFG_REMAP_FLASH \
+ 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH \
+ SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SRAM \
+ (SYSCFG_MEMRMP_MEM_MODE_1 | \
+ SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
+#if defined(FMC_Bank1_R)
+#define LL_SYSCFG_REMAP_FMC \
+ SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at \
+ 0x00000000 */
+#endif /* FMC_Bank1_R */
+#define LL_SYSCFG_REMAP_QUADSPI \
+ (SYSCFG_MEMRMP_MEM_MODE_2 | \
+ SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+ * @{
+ */
+#define LL_SYSCFG_BANKMODE_BANK1 \
+ 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) \
+ and Flash Bank2 mapped at 0x08040000 (and aliased at \
+ 0x00080000) */
+#define LL_SYSCFG_BANKMODE_BANK2 \
+ SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased \
+ @0x00000000) and Flash Bank1 mapped at 0x08040000 \
+ (and aliased at 0x00080000) */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @{
+ */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 \
+ SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 \
+ SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 \
+ SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 \
+ SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 \
+ SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(I2C2)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 \
+ SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#endif /* I2C2 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 \
+ SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(I2C4)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 \
+ SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
+#endif /* I2C4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ * @{
+ */
+#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
+#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
+#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
+#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
+#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
+#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
+#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ * @{
+ */
+#define LL_SYSCFG_EXTI_LINE0 \
+ (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1 \
+ (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2 \
+ (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3 \
+ (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4 \
+ (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5 \
+ (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6 \
+ (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7 \
+ (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8 \
+ (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9 \
+ (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10 \
+ (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11 \
+ (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12 \
+ (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13 \
+ (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14 \
+ (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15 \
+ (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @{
+ */
+#define LL_SYSCFG_TIMBREAK_ECC \
+ SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal \
+ with Break Input of TIM1/8/15/16/17 */
+#define LL_SYSCFG_TIMBREAK_PVD \
+ SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection \
+ with TIM1/8/15/16/17 Break Input \
+ and also the PVDE and PLS bits of the Power Control \
+ Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM_PARITY \
+ SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal \
+ with Break Input of TIM1/8/15/16/17 */
+#define LL_SYSCFG_TIMBREAK_LOCKUP \
+ SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 \
+ with Break Input of TIM1/15/16/17 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
+ * @{
+ */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE0 \
+ SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE1 \
+ SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE2 \
+ SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE3 \
+ SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE4 \
+ SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE5 \
+ SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE6 \
+ SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE7 \
+ SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE8 \
+ SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE9 \
+ SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
+#if defined(SYSCFG_SWPR_PAGE10)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE10 \
+ SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE11 \
+ SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE12 \
+ SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE13 \
+ SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE14 \
+ SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE15 \
+ SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE16 \
+ SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE17 \
+ SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE18 \
+ SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE19 \
+ SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
+#endif /* SYSCFG_SWPR_PAGE10 */
+#if defined(SYSCFG_SWPR_PAGE20)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE20 \
+ SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE21 \
+ SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE22 \
+ SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE23 \
+ SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE24 \
+ SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE25 \
+ SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE26 \
+ SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE27 \
+ SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE28 \
+ SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE29 \
+ SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE30 \
+ SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE31 \
+ SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
+#endif /* SYSCFG_SWPR_PAGE20 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE \
+ 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH \
+ DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 \
+ (DBGMCU_CR_TRACE_IOEN | \
+ DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with \
+ a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 \
+ (DBGMCU_CR_TRACE_IOEN | \
+ DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with \
+ a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 \
+ (DBGMCU_CR_TRACE_IOEN | \
+ DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a \
+ TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP \
+ DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when \
+ the core is halted*/
+#if defined(TIM3)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP \
+ DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when \
+ the core is halted*/
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP \
+ DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when \
+ the core is halted*/
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP \
+ DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when \
+ the core is halted*/
+#endif /* TIM5 */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP \
+ DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when \
+ the core is halted*/
+#if defined(TIM7)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP \
+ DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when \
+ the core is halted*/
+#endif /* TIM7 */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP \
+ DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped \
+ when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP \
+ DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is \
+ stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP \
+ DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is \
+ stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP \
+ DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
+#if defined(I2C2)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP \
+ DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
+#endif /* I2C2 */
+#if defined(I2C3)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP \
+ DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
+#endif /* I2C3 */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP \
+ DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped \
+ when the core is halted*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+ * @{
+ */
+#if defined(I2C4)
+#define LL_DBGMCU_APB1_GRP2_I2C4_STOP \
+ DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
+#endif /* I2C4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP \
+ DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when \
+ the core is halted*/
+#if defined(TIM8)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP \
+ DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when \
+ the core is halted*/
+#endif /* TIM8 */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP \
+ DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when \
+ the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP \
+ DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when \
+ the core is halted*/
+#if defined(TIM17)
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP \
+ DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when \
+ the core is halted*/
+#endif /* TIM17 */
+#if defined(TIM20)
+#define LL_DBGMCU_APB2_GRP1_TIM20_STOP \
+ DBGMCU_APB2FZ_DBG_TIM20_STOP /*!< The counter clock of TIM20 is stopped when \
+ the core is halted*/
+#endif /* TIM20 */
+#if defined(HRTIM1)
+#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP \
+ DBGMCU_APB2FZ_DBG_HRTIM1_STOP /*!< The counter clock of HRTIM1 is stopped \
+ when the core is halted*/
+#endif /* HRTIM1 */
+/**
+ * @}
+ */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
+ * @{
+ */
+#define LL_VREFBUF_VOLTAGE_SCALE0 \
+ ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) \
+ */
+#define LL_VREFBUF_VOLTAGE_SCALE1 \
+ VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
+#define LL_VREFBUF_VOLTAGE_SCALE2 \
+ VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3 \
+ FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states \
+ */
+#define LL_FLASH_LATENCY_4 \
+ FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states \
+ */
+#if defined(FLASH_ACR_LATENCY_5WS)
+#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7 \
+ FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states \
+ */
+#define LL_FLASH_LATENCY_8 \
+ FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states \
+ */
+#define LL_FLASH_LATENCY_9 \
+ FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states \
+ */
+#define LL_FLASH_LATENCY_10 \
+ FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states \
+ */
+#define LL_FLASH_LATENCY_11 \
+ FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12 \
+ FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13 \
+ FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14 \
+ FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15 \
+ FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
+#endif /* FLASH_ACR_LATENCY_5WS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @{
+ */
+
+/**
+ * @brief Set memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
+ * @param Memory This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) {
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+ * @brief Get memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) {
+ return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/**
+ * @brief Select Flash bank mode (Bank flashed at 0x08000000)
+ * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
+ * @param Bank This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) {
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
+}
+
+/**
+ * @brief Get Flash bank mode (Bank flashed at 0x08000000)
+ * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) {
+ return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+
+/**
+ * @brief Enable I/O analog switch voltage booster.
+ * @note When voltage booster is enabled, I/O analog switches are supplied
+ * by a dedicated voltage booster, from VDD power domain. This is
+ * the recommended configuration with low VDDA voltage operation.
+ * @note The I/O analog switch voltage booster is relevant for peripherals
+ * using I/O in analog input: ADC, COMP, OPAMP.
+ * However, COMP and OPAMP inputs have a high impedance and
+ * voltage booster do not impact performance significantly.
+ * Therefore, the voltage booster is mainly intended for
+ * usage with ADC.
+ * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable I/O analog switch voltage booster.
+ * @note When voltage booster is enabled, I/O analog switches are supplied
+ * by a dedicated voltage booster, from VDD power domain. This is
+ * the recommended configuration with low VDDA voltage operation.
+ * @note The I/O analog switch voltage booster is relevant for peripherals
+ * using I/O in analog input: ADC, COMP, OPAMP.
+ * However, COMP and OPAMP inputs have a high impedance and
+ * voltage booster do not impact performance significantly.
+ * Therefore, the voltage booster is mainly intended for
+ * usage with ADC.
+ * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the
+ * following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) {
+ SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the
+ * following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(
+ uint32_t ConfigFastModePlus) {
+ CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Enable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Enable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Enable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Enable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Enable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Enable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Disable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Disable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Disable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Disable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Disable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Disable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Check if Floating Point Unit Invalid operation Interrupt source is
+ * enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) {
+ return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) ==
+ (SYSCFG_CFGR1_FPU_IE_0))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is
+ * enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) {
+ return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) ==
+ (SYSCFG_CFGR1_FPU_IE_1))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or
+ * disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) {
+ return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) ==
+ (SYSCFG_CFGR1_FPU_IE_2))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or
+ * disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) {
+ return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) ==
+ (SYSCFG_CFGR1_FPU_IE_3))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Input denormal Interrupt source is
+ * enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) {
+ return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) ==
+ (SYSCFG_CFGR1_FPU_IE_4))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or
+ * disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) {
+ return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) ==
+ (SYSCFG_CFGR1_FPU_IE_5))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE
+ * @arg @ref LL_SYSCFG_EXTI_PORTF
+ * @arg @ref LL_SYSCFG_EXTI_PORTG
+ *
+ * (*) value not defined in all devices
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) {
+ MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U),
+ Port << (POSITION_VAL((Line >> 16U)) & 0x1FU));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE
+ * @arg @ref LL_SYSCFG_EXTI_PORTF
+ * @arg @ref LL_SYSCFG_EXTI_PORTG
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) {
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >>
+ (POSITION_VAL(Line >> 16U) & 0x1FU));
+}
+
+/**
+ * @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This
+ * bit is automatically cleared at the end of the CCMSRAM erase operation.)
+ * @note This bit is write-protected: setting this bit is possible only after
+ * the correct key sequence is written in the SYSCFG_SKR register as described
+ * in the Reference Manual.
+ * @rmtoll SYSCFG_SCSR CCMER LL_SYSCFG_EnableCCMSRAMErase
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void) {
+ /* Starts a hardware CCMSRAM erase operation*/
+ SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
+}
+
+/**
+ * @brief Check if CCMSRAM erase operation is on going
+ * @rmtoll SYSCFG_SCSR CCMBSY LL_SYSCFG_IsCCMSRAMEraseOngoing
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void) {
+ return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set connections to TIM1/8/15/16/17 Break inputs
+ * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
+ * @param Break This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) {
+ MODIFY_REG(SYSCFG->CFGR2,
+ SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL |
+ SYSCFG_CFGR2_ECCL,
+ Break);
+}
+
+/**
+ * @brief Get connections to TIM1/8/15/16/17 Break inputs
+ * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) {
+ return (uint32_t)(READ_BIT(
+ SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL |
+ SYSCFG_CFGR2_ECCL));
+}
+
+/**
+ * @brief Check if SRAM parity error detected
+ * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) {
+ return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Clear SRAM parity error flag
+ * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) {
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
+}
+
+/**
+ * @brief Enable CCMSRAM page write protection
+ * @note Write protection is cleared only by a system reset
+ * @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableCCMSRAMPageWRP
+ * @param CCMSRAMWRP This parameter can be a combination of the following
+ * values:
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP) {
+ SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
+}
+
+/**
+ * @brief CCMSRAM page write protection lock prior to erase
+ * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockCCMSRAMWRP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void) {
+ /* Writing a wrong key reactivates the write protection */
+ WRITE_REG(SYSCFG->SKR, 0x00);
+}
+
+/**
+ * @brief CCMSRAM page write protection unlock prior to erase
+ * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockCCMSRAMWRP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void) {
+ /* unlock the write protection of the CCMER bit */
+ WRITE_REG(SYSCFG->SKR, 0xCA);
+ WRITE_REG(SYSCFG->SKR, 0x53);
+}
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is
+ * 0x6415)
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) {
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) {
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >>
+ (DBGMCU_REVID_POSITION & 0x1FU));
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) {
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) {
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) {
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) {
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) {
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) {
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) {
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE,
+ PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) {
+ return (uint32_t)(READ_BIT(DBGMCU->CR,
+ DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) {
+ SET_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group2 peripherals)
+ * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) {
+ SET_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) {
+ CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group2 peripherals)
+ * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) {
+ CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) {
+ SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) {
+ CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @}
+ */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
+ * @{
+ */
+
+/**
+ * @brief Enable Internal voltage reference
+ * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_Enable(void) {
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Disable Internal voltage reference
+ * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_Disable(void) {
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Enable high impedance (VREF+pin is high impedance)
+ * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) {
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+ * @brief Disable high impedance (VREF+pin is internally connected to the
+ * voltage reference buffer output)
+ * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) {
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+ * @brief Set the Voltage reference scale
+ * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
+ * @param Scale This parameter can be one of the following values:
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) {
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
+}
+
+/**
+ * @brief Get the Voltage reference scale
+ * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) {
+ return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
+}
+
+/**
+ * @brief Check if Voltage reference buffer is ready
+ * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) {
+ return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get the trimming code for VREFBUF calibration
+ * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
+ * @retval Between 0 and 0x3F
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) {
+ return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
+}
+
+/**
+ * @brief Set the trimming code for VREFBUF calibration (Tune the internal
+ * reference buffer voltage)
+ * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
+ * @param Value Between 0 and 0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) {
+ WRITE_REG(VREFBUF->CCR, Value);
+}
+
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5 (*)
+ * @arg @ref LL_FLASH_LATENCY_6 (*)
+ * @arg @ref LL_FLASH_LATENCY_7 (*)
+ * @arg @ref LL_FLASH_LATENCY_8 (*)
+ * @arg @ref LL_FLASH_LATENCY_9 (*)
+ * @arg @ref LL_FLASH_LATENCY_10 (*)
+ * @arg @ref LL_FLASH_LATENCY_11 (*)
+ * @arg @ref LL_FLASH_LATENCY_12 (*)
+ * @arg @ref LL_FLASH_LATENCY_13 (*)
+ * @arg @ref LL_FLASH_LATENCY_14 (*)
+ * @arg @ref LL_FLASH_LATENCY_15 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) {
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5 (*)
+ * @arg @ref LL_FLASH_LATENCY_6 (*)
+ * @arg @ref LL_FLASH_LATENCY_7 (*)
+ * @arg @ref LL_FLASH_LATENCY_8 (*)
+ * @arg @ref LL_FLASH_LATENCY_9 (*)
+ * @arg @ref LL_FLASH_LATENCY_10 (*)
+ * @arg @ref LL_FLASH_LATENCY_11 (*)
+ * @arg @ref LL_FLASH_LATENCY_12 (*)
+ * @arg @ref LL_FLASH_LATENCY_13 (*)
+ * @arg @ref LL_FLASH_LATENCY_14 (*)
+ * @arg @ref LL_FLASH_LATENCY_15 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) {
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) {
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) {
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) {
+ return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable Instruction cache
+ * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void) {
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+ * @brief Disable Instruction cache
+ * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void) {
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+ * @brief Enable Data cache
+ * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void) {
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+ * @brief Disable Data cache
+ * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void) {
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+ * @brief Enable Instruction cache reset
+ * @note bit can be written only when the instruction cache is disabled
+ * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) {
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+ * @brief Disable Instruction cache reset
+ * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) {
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+ * @brief Enable Data cache reset
+ * @note bit can be written only when the data cache is disabled
+ * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) {
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+ * @brief Disable Data cache reset
+ * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) {
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+ * @brief Enable Flash Power-down mode during run mode or Low-power run mode
+ * @note Flash memory can be put in power-down mode only when the code is
+ * executed from RAM
+ * @note Flash must not be accessed when power down is enabled
+ * @note Flash must not be put in power-down while a program or an erase
+ * operation is on-going
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) {
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+ SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+ * @brief Disable Flash Power-down mode during run mode or Low-power run mode
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) {
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+ * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
+ * @note Flash must not be put in power-down while a program or an erase
+ * operation is on-going
+ * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) {
+ SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+ * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
+ * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) {
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined \
+ (VREFBUF) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_SYSTEM_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h
index 2dc490c..a80a614 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h
@@ -1,7660 +1,7680 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G4xx_LL_TIM_H
-#define __STM32G4xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(TIM1) || defined(TIM2) || defined(TIM3) || defined(TIM4) || \
- defined(TIM5) || defined(TIM6) || defined(TIM7) || defined(TIM8) || \
- defined(TIM15) || defined(TIM16) || defined(TIM17) || defined(TIM20)
-
-/** @defgroup TIM_LL TIM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
- * @{
- */
-static const uint8_t OFFSET_TAB_CCMRx[] = {
- 0x00U, /* 0: TIMx_CH1 */
- 0x00U, /* 1: TIMx_CH1N */
- 0x00U, /* 2: TIMx_CH2 */
- 0x00U, /* 3: TIMx_CH2N */
- 0x04U, /* 4: TIMx_CH3 */
- 0x04U, /* 5: TIMx_CH3N */
- 0x04U, /* 6: TIMx_CH4 */
- 0x04U, /* 7: TIMx_CH4N */
- 0x38U, /* 8: TIMx_CH5 */
- 0x38U /* 9: TIMx_CH6 */
-
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] = {
- 0U, /* 0: OC1M, OC1FE, OC1PE */
- 0U, /* 1: - NA */
- 8U, /* 2: OC2M, OC2FE, OC2PE */
- 0U, /* 3: - NA */
- 0U, /* 4: OC3M, OC3FE, OC3PE */
- 0U, /* 5: - NA */
- 8U, /* 6: OC4M, OC4FE, OC4PE */
- 0U, /* 7: - NA */
- 0U, /* 8: OC5M, OC5FE, OC5PE */
- 8U /* 9: OC6M, OC6FE, OC6PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] = {
- 0U, /* 0: CC1S, IC1PSC, IC1F */
- 0U, /* 1: - NA */
- 8U, /* 2: CC2S, IC2PSC, IC2F */
- 0U, /* 3: - NA */
- 0U, /* 4: CC3S, IC3PSC, IC3F */
- 0U, /* 5: - NA */
- 8U, /* 6: CC4S, IC4PSC, IC4F */
- 0U, /* 7: - NA */
- 0U, /* 8: - NA */
- 0U /* 9: - NA */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] = {
- 0U, /* 0: CC1P */
- 2U, /* 1: CC1NP */
- 4U, /* 2: CC2P */
- 6U, /* 3: CC2NP */
- 8U, /* 4: CC3P */
- 10U, /* 5: CC3NP */
- 12U, /* 6: CC4P */
- 14U, /* 7: CC4NP */
- 16U, /* 8: CC5P */
- 20U /* 9: CC6P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] = {
- 0U, /* 0: OIS1 */
- 1U, /* 1: OIS1N */
- 2U, /* 2: OIS2 */
- 3U, /* 3: OIS2N */
- 4U, /* 4: OIS3 */
- 5U, /* 5: OIS3N */
- 6U, /* 6: OIS4 */
- 7U, /* 7: OIS4N */
- 8U, /* 8: OIS5 */
- 10U /* 9: OIS6 */
-};
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
- * @{
- */
-
-/* Defines used for the bit position in the register and perform offsets */
-#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
-
-/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
-#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register
- */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-/** Legacy definitions for compatibility purpose
-@cond 0
- */
-/**
-@endcond
- */
-
-#define OCREF_CLEAR_SELECT_Pos (28U)
-#define OCREF_CLEAR_SELECT_Msk \
- (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
- * @{
- */
-/** @brief Convert channel id into channel index.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval none
- */
-#define TIM_GET_CHANNEL_INDEX(__CHANNEL__) \
- (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U \
- : ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U \
- : 9U)
-
-/** @brief Calculate the deadtime sampling period(in ps).
- * @param __TIMCLK__ timer input clock frequency (in Hz).
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval none
- */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) \
- ? ((uint64_t)1000000000000U / (__TIMCLK__)) \
- : ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) \
- ? ((uint64_t)1000000000000U / ((__TIMCLK__) >> 1U)) \
- : ((uint64_t)1000000000000U / ((__TIMCLK__) >> 2U)))
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
- * @{
- */
-
-/**
- * @brief TIM Time Base configuration structure definition.
- */
-typedef struct {
- uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM
- clock. This parameter can be a number between
- Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_SetPrescaler().*/
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref
- TIM_LL_EC_COUNTERMODE.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_SetCounterMode().*/
-
- uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into
- the active Auto-Reload Register at the next update
- event. This parameter must be a number between
- Min_Data=0x0000 and Max_Data=0xFFFF. Some timer
- instances may support 32 bits counters. In that case
- this parameter must be a number between 0x0000 and
- 0xFFFFFFFF.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_SetAutoReload().*/
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref
- TIM_LL_EC_CLOCKDIVISION.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_SetClockDivision().*/
-
- uint32_t
- RepetitionCounter; /*!< Specifies the repetition counter value. Each time
- the RCR downcounter reaches zero, an update event is
- generated and counting restarts from the RCR value
- (N). This means in PWM mode that (N+1) corresponds
- to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in
- center-aligned mode GP timers: this parameter must
- be a number between Min_Data = 0x00 and Max_Data =
- 0xFF. Advanced timers: this parameter must be a
- number between Min_Data = 0x0000 and Max_Data =
- 0xFFFF.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
- * @brief TIM Output Compare configuration structure definition.
- */
-typedef struct {
- uint32_t OCMode; /*!< Specifies the output mode.
- This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_OC_SetMode().*/
-
- uint32_t
- OCState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary
- functions
- @ref LL_TIM_CC_EnableChannel() or @ref
- LL_TIM_CC_DisableChannel().*/
-
- uint32_t
- OCNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary
- functions
- @ref LL_TIM_CC_EnableChannel() or @ref
- LL_TIM_CC_DisableChannel().*/
-
- uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the
- Capture Compare Register. This parameter can be a
- number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using
- unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref
- TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_OC_SetPolarity().*/
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref
- TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_OC_SetPolarity().*/
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during
- Idle state. This parameter can be a value of @ref
- TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_OC_SetIdleState().*/
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during
- Idle state. This parameter can be a value of @ref
- TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM Input Capture configuration structure definition.
- */
-
-typedef struct {
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref
- TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t ICActiveInput; /*!< Specifies the input.
- This parameter can be a value of @ref
- TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t
- ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t
- ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder interface configuration structure definition.
- */
-typedef struct {
- uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
- This parameter can be a value of @ref
- TIM_LL_EC_ENCODERMODE.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_SetEncoderMode().*/
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref
- TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
- This parameter can be a value of @ref
- TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t
- IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t
- IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
- This parameter can be a value of @ref
- TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
- This parameter can be a value of @ref
- TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t
- IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t
- IC2Filter; /*!< Specifies the TI2 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
- * @brief TIM Hall sensor interface configuration structure definition.
- */
-typedef struct {
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref
- TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- Prescaler must be set to get a maximum counter
- period longer than the time interval between 2
- consecutive changes on the Hall inputs. This
- parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of
- @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into
- the Capture Compare Register. A positive pulse
- (TRGO event) is generated with a programmable
- delay every time a change occurs on the Hall
- inputs. This parameter can be a number between
- Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
- * @brief BDTR (Break and Dead Time) structure definition
- */
-typedef struct {
- uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_LL_EC_OSSR
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as
- LOCK level 2 has been programmed. */
-
- uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OSSI
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as
- LOCK level 2 has been programmed. */
-
- uint32_t
- LockLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
- @note The LOCK bits can be written only once after the
- reset. Once the TIMx_BDTR register has been written, their
- content is frozen until the next reset.*/
-
- uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and
- the switching-on of the outputs. This parameter can be a
- number between Min_Data = 0x00 and Max_Data = 0xFF.
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_TIM_OC_SetDeadTime()
-
- @note This bit-field can not be modified as long as
- LOCK level 1, 2 or 3 has been programmed. */
-
- uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or
- not. This parameter can be a value of @ref
- TIM_LL_EC_BREAK_ENABLE
-
- This feature can be modified afterwards using
- unitary functions
- @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
- @note This bit-field can not be modified as long as
- LOCK level 1 has been programmed. */
-
- uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref
- TIM_LL_EC_BREAK_POLARITY
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long
- as LOCK level 1 has been programmed. */
-
- uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
- This parameter can be a value of @ref
- TIM_LL_EC_BREAK_FILTER
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long as
- LOCK level 1 has been programmed. */
-
- uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break
- input. This parameter can be a value of @ref
- TIM_LL_EC_BREAK_AFMODE
-
- This feature can be modified afterwards using
- unitary functions
- @ref LL_TIM_ConfigBRK()
-
- @note Bidirectional break input is only supported by
- advanced timers instances.
-
- @note This bit-field can not be modified as long as
- LOCK level 1 has been programmed. */
-
- uint32_t
- Break2State; /*!< Specifies whether the TIM Break2 input is enabled or
- not. This parameter can be a value of @ref
- TIM_LL_EC_BREAK2_ENABLE
-
- This feature can be modified afterwards using unitary
- functions
- @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
-
- @note This bit-field can not be modified as long as LOCK
- level 1 has been programmed. */
-
- uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
- This parameter can be a value of @ref
- TIM_LL_EC_BREAK2_POLARITY
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_ConfigBRK2()
-
- @note This bit-field can not be modified as long
- as LOCK level 1 has been programmed. */
-
- uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
- This parameter can be a value of @ref
- TIM_LL_EC_BREAK2_FILTER
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_TIM_ConfigBRK2()
-
- @note This bit-field can not be modified as long as
- LOCK level 1 has been programmed. */
-
- uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the
- break2 input. This parameter can be a value of @ref
- TIM_LL_EC_BREAK2_AFMODE
-
- This feature can be modified afterwards using
- unitary functions
- @ref LL_TIM_ConfigBRK2()
-
- @note Bidirectional break input is only supported
- by advanced timers instances.
-
- @note This bit-field can not be modified as long as
- LOCK level 1 has been programmed. */
-
- uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output
- feature is enabled or not. This parameter can be
- a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
- This feature can be modified afterwards using
- unitary functions
- @ref LL_TIM_EnableAutomaticOutput() or @ref
- LL_TIM_DisableAutomaticOutput()
-
- @note This bit-field can not be modified as
- long as LOCK level 1 has been programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_TIM_ReadReg function.
- * @{
- */
-#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
-#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
-#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
-#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
-#define LL_TIM_SR_CC1OF \
- TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag \
- */
-#define LL_TIM_SR_CC2OF \
- TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag \
- */
-#define LL_TIM_SR_CC3OF \
- TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag \
- */
-#define LL_TIM_SR_CC4OF \
- TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag \
- */
-#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
-#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
-#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
-#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
-#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
- * @{
- */
-#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
- * @{
- */
-#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
-#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
- * @{
- */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE \
- 0x00000000U /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE \
- TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next \
- update event */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_TIM_ReadReg and
- * LL_TIM_WriteReg functions.
- * @{
- */
-#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE \
- TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE \
- TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE \
- TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE \
- TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
-#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
-#define LL_TIM_DIER_DIRIE \
- TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
-#define LL_TIM_DIER_IERRIE \
- TIM_DIER_IERRIE /*!< Index Error interrupt enable \
- */
-#define LL_TIM_DIER_TERRIE \
- TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
- * @{
- */
-#define LL_TIM_UPDATESOURCE_REGULAR \
- 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update \
- generation through the slave mode controller generates an \
- update request */
-#define LL_TIM_UPDATESOURCE_COUNTER \
- TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
- * @{
- */
-#define LL_TIM_ONEPULSEMODE_SINGLE \
- TIM_CR1_OPM /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE \
- 0x00000000U /*!< Counter is not stopped at update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
- * @{
- */
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN \
- TIM_CR1_DIR /*!< Counter used as downcounter \
- */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN \
- TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output \
- compare interrupt flags of output channels are set only \
- when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP \
- TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output \
- compare interrupt flags of output channels are set only \
- when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN \
- TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output \
- compare interrupt flags of output channels are set only when \
- the counter is counting up or down. */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
- * @{
- */
-#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
- * @{
- */
-#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN \
- TIM_CR1_DIR /*!< Timer counter counts down */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
- * @{
- */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY \
- 0x00000000U /*!< Capture/compare control bits are updated by setting the \
- COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI \
- TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the \
- COMG bit or when a rising edge occurs on trigger input \
- (TRGI) */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
- * @{
- */
-#define LL_TIM_CCDMAREQUEST_CC \
- 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE \
- TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
- * @{
- */
-#define LL_TIM_LOCKLEVEL_OFF \
- 0x00000000U /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
- * @{
- */
-#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH1N \
- TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
-#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH2N \
- TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
-#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH3N \
- TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
-#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
-#define LL_TIM_CHANNEL_CH4N \
- TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
-#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
-#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
- * @{
- */
-#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE \
- TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
- * @{
- */
-#define LL_TIM_OCMODE_FROZEN \
- 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy \
- and the counter TIMx_CNT has no effect on the output channel \
- level */
-#define LL_TIM_OCMODE_ACTIVE \
- TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE \
- TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE \
- (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE \
- TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE \
- (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1 \
- (TIM_CCMR1_OC1M_2 | \
- TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as \
- TIMx_CNT<TIMx_CCRy else inactive. In downcounting, \
- channel y is inactive as long as TIMx_CNT>TIMx_CCRy \
- else active.*/
-#define LL_TIM_OCMODE_PWM2 \
- (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | \
- TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as \
- TIMx_CNT<TIMx_CCRy else active. In downcounting, \
- channel y is active as long as TIMx_CNT>TIMx_CCRy else \
- inactive*/
-#define LL_TIM_OCMODE_RETRIG_OPM1 \
- TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
-#define LL_TIM_OCMODE_RETRIG_OPM2 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
-#define LL_TIM_OCMODE_COMBINED_PWM1 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
-#define LL_TIM_OCMODE_COMBINED_PWM2 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | \
- TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | \
- TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 \
- (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
-#define LL_TIM_OCMODE_PULSE_ON_COMPARE \
- (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
-#define LL_TIM_OCMODE_DIRECTION_OUTPUT \
- (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | \
- TIM_CCMR2_OC3M_0) /*!<Direction output mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
- * @{
- */
-#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
- * @{
- */
-#define LL_TIM_OCIDLESTATE_LOW \
- 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
-#define LL_TIM_OCIDLESTATE_HIGH \
- TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
- * @{
- */
-#define LL_TIM_GROUPCH5_NONE \
- 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define LL_TIM_GROUPCH5_OC1REFC \
- TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC2REFC \
- TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC3REFC \
- TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
- * @{
- */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI \
- (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI \
- (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC \
- (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
- * @{
- */
-#define LL_TIM_ICPSC_DIV1 \
- 0x00000000U /*!< No prescaler, capture is done each time an edge is detected \
- on the capture input */
-#define LL_TIM_ICPSC_DIV2 \
- (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4 \
- (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8 \
- (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
- * @{
- */
-#define LL_TIM_IC_FILTER_FDIV1 \
- 0x00000000U /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2 \
- (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4 \
- (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8 \
- ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 \
- */
-#define LL_TIM_IC_FILTER_FDIV2_N6 \
- (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8 \
- ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6 \
- ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8 \
- ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) \
- << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6 \
- (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8 \
- ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5 \
- ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 \
- */
-#define LL_TIM_IC_FILTER_FDIV16_N6 \
- ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) \
- << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8 \
- ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 \
- */
-#define LL_TIM_IC_FILTER_FDIV32_N5 \
- ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) \
- << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6 \
- ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) \
- << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8 \
- (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
- * @{
- */
-#define LL_TIM_IC_POLARITY_RISING \
- 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is \
- not inverted */
-#define LL_TIM_IC_POLARITY_FALLING \
- TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 \
- is inverted */
-#define LL_TIM_IC_POLARITY_BOTHEDGE \
- (TIM_CCER_CC1P | \
- TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and \
- falling edges, TIxFP1 is not inverted */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
- * @{
- */
-#define LL_TIM_CLOCKSOURCE_INTERNAL \
- 0x00000000U /*!< The timer is clocked by the internal clock provided from \
- the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1 \
- (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a \
- selected input*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2 \
- TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the \
- external trigger input ETR */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
- * @{
- */
-#define LL_TIM_ENCODERMODE_X2_TI1 \
- TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts \
- up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X2_TI2 \
- TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts \
- up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X4_TI12 \
- (TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts \
- up/down on both TI1FP1 and TI2FP2 edges depending on the \
- level of the other input */
-#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 \
- (TIM_SMCR_SMS_3 | \
- TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
-#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 \
- edge sensitivity is set by CC2P */
-#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 \
- (TIM_SMCR_SMS_3 | \
- TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
-#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
- TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and \
- TI2FP2 edge sensitivity is set by CC1P and CC2P */
-#define LL_TIM_ENCODERMODE_X1_TI1 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
- TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 \
- edges only, edge sensitivity is set by CC1P */
-#define LL_TIM_ENCODERMODE_X1_TI2 \
- (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
- TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 \
- edges only, edge sensitivity is set by CC1P */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
- * @{
- */
-#define LL_TIM_TRGO_RESET \
- 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output \
- */
-#define LL_TIM_TRGO_ENABLE \
- TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output \
- */
-#define LL_TIM_TRGO_UPDATE \
- TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF \
- (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used \
- as trigger output */
-#define LL_TIM_TRGO_OC1REF \
- TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF \
- (TIM_CR2_MMS_2 | \
- TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF \
- (TIM_CR2_MMS_2 | \
- TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF \
- (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | \
- TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-#define LL_TIM_TRGO_ENCODERCLK \
- TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
- * @{
- */
-#define LL_TIM_TRGO2_RESET \
- 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output \
- 2 */
-#define LL_TIM_TRGO2_ENABLE \
- TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output \
- 2 */
-#define LL_TIM_TRGO2_UPDATE \
- TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
-#define LL_TIM_TRGO2_CC1F \
- (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is \
- used as trigger output 2 */
-#define LL_TIM_TRGO2_OC1 \
- TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC2 \
- (TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC3 \
- (TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4 \
- (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
- TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5 \
- TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6 \
- (TIM_CR2_MMS2_3 | \
- TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISINGFALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are \
- used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6_RISINGFALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | \
- TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger \
- output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are \
- used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as \
- trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
- TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger \
- output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING \
- (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
- TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as \
- trigger output 2 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
- * @{
- */
-#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET \
- TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input \
- (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED \
- (TIM_SMCR_SMS_2 | \
- TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the \
- trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER \
- (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at \
- a rising edge of the trigger TRGI */
-#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER \
- TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the \
- selected trigger input (TRGI) reinitializes the counter, \
- generates an update of the registers and starts the \
- counter */
-#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET \
- (TIM_SMCR_SMS_3 | \
- TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is \
- enabled when the trigger input (TRGI) is high. The \
- counter stops and is reset) as soon as the trigger \
- becomes low.Both startand stop of the counter are \
- controlled. */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
- * @{
- */
-#define LL_TIM_SMSPS_TIMUPDATE \
- 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update \
- event */
-#define LL_TIM_SMSPS_INDEX \
- TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
- * @{
- */
-#define LL_TIM_TS_ITR0 \
- 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1 \
- TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2 \
- TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3 \
- (TIM_SMCR_TS_0 | \
- TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED \
- TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 \
- (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used \
- as trigger input */
-#define LL_TIM_TS_TI2FP2 \
- (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used \
- as trigger input */
-#define LL_TIM_TS_ETRF \
- (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | \
- TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger \
- input */
-#define LL_TIM_TS_ITR4 \
- TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
-#define LL_TIM_TS_ITR5 \
- (TIM_SMCR_TS_3 | \
- TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
-#define LL_TIM_TS_ITR6 \
- (TIM_SMCR_TS_3 | \
- TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
-#define LL_TIM_TS_ITR7 \
- (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | \
- TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
-#define LL_TIM_TS_ITR8 \
- (TIM_SMCR_TS_3 | \
- TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
-#define LL_TIM_TS_ITR9 \
- (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | \
- TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
-#define LL_TIM_TS_ITR10 \
- (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | \
- TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
-#define LL_TIM_TS_ITR11 \
- (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | \
- TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
- * @{
- */
-#define LL_TIM_ETR_POLARITY_NONINVERTED \
- 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED \
- TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
- * @{
- */
-#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2 \
- TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4 \
- TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8 \
- TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
- * @{
- */
-#define LL_TIM_ETR_FILTER_FDIV1 \
- 0x00000000U /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2 \
- TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 \
- */
-#define LL_TIM_ETR_FILTER_FDIV1_N4 \
- TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 \
- */
-#define LL_TIM_ETR_FILTER_FDIV1_N8 \
- (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6 \
- TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 \
- */
-#define LL_TIM_ETR_FILTER_FDIV2_N8 \
- (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6 \
- (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8 \
- (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | \
- TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6 \
- TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 \
- */
-#define LL_TIM_ETR_FILTER_FDIV8_N8 \
- (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5 \
- (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6 \
- (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | \
- TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8 \
- (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5 \
- (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | \
- TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6 \
- (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | \
- TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8 \
- TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
- * @{
- */
-#define LL_TIM_TIM1_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM1_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM1_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM1_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM1_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM1_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM1_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM1_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 \
- TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
-#if defined(ADC4)
-#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
-#endif /* ADC4 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
- * @{
- */
-#define LL_TIM_TIM2_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM2_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM2_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM2_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM2_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM2_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM2_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM2_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR \
- TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
-#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
-#if defined(TIM5)
-#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
-#endif /* TIM5 */
-#define LL_TIM_TIM2_ETRSOURCE_LSE \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
- * @{
- */
-#define LL_TIM_TIM3_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM3_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM3_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM3_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM3_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM3_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM3_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM3_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR \
- TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
-#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
-#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
-#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
-#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
- * @{
- */
-#define LL_TIM_TIM4_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM4_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM4_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM4_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM4_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM4_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM4_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM4_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR \
- TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
-#if defined(TIM5)
-#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
-#endif /* TIM5 */
-/**
- * @}
- */
-
-#if defined(TIM5)
-/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
- * @{
- */
-#define LL_TIM_TIM5_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM5_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM5_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM5_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM5_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM5_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM5_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM5_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR \
- TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
-#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR \
- (TIM1_AF1_ETRSEL_3 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
-/**
- * @}
- */
-#endif /* TIM5 */
-
-/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
- * @{
- */
-#define LL_TIM_TIM8_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM8_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM8_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM8_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM8_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM8_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM8_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM8_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 \
- TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
-#if defined(ADC3)
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
-#endif /* ADC3 */
-/**
- * @}
- */
-
-#if defined(TIM20)
-/** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
- * @{
- */
-#define LL_TIM_TIM20_ETRSOURCE_GPIO \
- 0x00000000U /*!< ETR input is connected to GPIO */
-#define LL_TIM_TIM20_ETRSOURCE_COMP1 \
- TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_TIM20_ETRSOURCE_COMP2 \
- TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
-#define LL_TIM_TIM20_ETRSOURCE_COMP3 \
- (TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
-#define LL_TIM_TIM20_ETRSOURCE_COMP4 \
- TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM20_ETRSOURCE_COMP5 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM20_ETRSOURCE_COMP6 \
- (TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM20_ETRSOURCE_COMP7 \
- (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
-#endif /* COMP7 */
-#if defined(ADC3)
-#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 \
- TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */
-#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
-#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
-#endif /* ADC3 */
-#if defined(ADC5)
-#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
-#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
-#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 \
- (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
- TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
-#endif /* ADC5 */
-/**
- * @}
- */
-#endif /* TIM20 */
-
-/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
- * @{
- */
-#define LL_TIM_BREAK_POLARITY_LOW \
- 0x00000000U /*!< Break input BRK is active low */
-#define LL_TIM_BREAK_POLARITY_HIGH \
- TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
- * @{
- */
-#define LL_TIM_BREAK_FILTER_FDIV1 \
- 0x00000000U /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK_FILTER_FDIV1_N2 \
- 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV1_N4 \
- 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV1_N8 \
- 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N5 \
- 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV16_N6 \
- 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV16_N8 \
- 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV32_N5 \
- 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV32_N6 \
- 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 \
- */
-#define LL_TIM_BREAK_FILTER_FDIV32_N8 \
- 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
- * @{
- */
-#define LL_TIM_BREAK2_POLARITY_LOW \
- 0x00000000U /*!< Break input BRK2 is active low */
-#define LL_TIM_BREAK2_POLARITY_HIGH \
- TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
- * @{
- */
-#define LL_TIM_BREAK2_FILTER_FDIV1 \
- 0x00000000U /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N2 \
- 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N4 \
- 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N8 \
- 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N6 \
- 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N8 \
- 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N6 \
- 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N8 \
- 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N6 \
- 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N8 \
- 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 \
- */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N5 \
- 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N6 \
- 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N8 \
- 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N5 \
- 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N6 \
- 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N8 \
- 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OSSI OSSI
- * @{
- */
-#define LL_TIM_OSSI_DISABLE \
- 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSI_ENABLE \
- TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with \
- their inactive level then forced to their idle level after \
- the deadtime */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OSSR OSSR
- * @{
- */
-#define LL_TIM_OSSR_DISABLE \
- 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSR_ENABLE \
- TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their \
- inactive level as soon as CCxE=1 or CCxNE=1 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
- * @{
- */
-#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
-#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
- * @{
- */
-#define LL_TIM_BKIN_SOURCE_BKIN \
- TIM1_AF1_BKINE /*!< BKIN input from AF controller */
-#define LL_TIM_BKIN_SOURCE_BKCOMP1 \
- TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
-#define LL_TIM_BKIN_SOURCE_BKCOMP2 \
- TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
-#define LL_TIM_BKIN_SOURCE_BKCOMP3 \
- TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
-#define LL_TIM_BKIN_SOURCE_BKCOMP4 \
- TIM1_AF1_BKCMP4E /*!< internal signal: COMP4 output */
-#if defined(COMP5)
-#define LL_TIM_BKIN_SOURCE_BKCOMP5 \
- TIM1_AF1_BKCMP5E /*!< internal signal: COMP5 output */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_BKIN_SOURCE_BKCOMP6 \
- TIM1_AF1_BKCMP6E /*!< internal signal: COMP6 output */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_BKIN_SOURCE_BKCOMP7 \
- TIM1_AF1_BKCMP7E /*!< internal signal: COMP7 output */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
- * @{
- */
-#define LL_TIM_BKIN_POLARITY_LOW \
- TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
-#define LL_TIM_BKIN_POLARITY_HIGH \
- 0x00000000U /*!< BRK BKIN input is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
- * @{
- */
-#define LL_TIM_BREAK_AFMODE_INPUT \
- 0x00000000U /*!< Break input BRK in input mode */
-#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL \
- TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
- * @{
- */
-#define LL_TIM_BREAK2_AFMODE_INPUT \
- 0x00000000U /*!< Break2 input BRK2 in input mode */
-#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL \
- TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
- * @{
- */
-#define LL_TIM_DMABURST_BASEADDR_CR1 \
- 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2 \
- TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_SMCR \
- TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_DIER \
- (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR \
- TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR \
- (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1 \
- (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2 \
- (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | \
- TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER \
- TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_CNT \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | \
- TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_RCR \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1 \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | \
- TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2 \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | \
- TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3 \
- (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | \
- TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4 \
- TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_BDTR \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR5 \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR6 \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | \
- TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR3 \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DTR2 \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | \
- TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_ECR \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | \
- TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_TISEL \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | \
- TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA \
- burst */
-#define LL_TIM_DMABURST_BASEADDR_AF1 \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base \
- address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF2 \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | \
- TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst \
- */
-#define LL_TIM_DMABURST_BASEADDR_OR \
- (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | \
- TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst \
- */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
- * @{
- */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER \
- 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst \
- base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS \
- TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS \
- TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS \
- (TIM_DCR_DBL_1 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS \
- TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS \
- (TIM_DCR_DBL_2 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS \
- (TIM_DCR_DBL_2 | \
- TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS \
- (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS \
- TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS \
- (TIM_DCR_DBL_3 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS \
- (TIM_DCR_DBL_3 | \
- TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS \
- (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS \
- (TIM_DCR_DBL_3 | \
- TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS \
- (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS \
- (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | \
- TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS \
- (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS \
- TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS \
- (TIM_DCR_DBL_4 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_19TRANSFERS \
- (TIM_DCR_DBL_4 | \
- TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_20TRANSFERS \
- (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_21TRANSFERS \
- (TIM_DCR_DBL_4 | \
- TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_22TRANSFERS \
- (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_23TRANSFERS \
- (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | \
- TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_24TRANSFERS \
- (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_25TRANSFERS \
- (TIM_DCR_DBL_4 | \
- TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA \
- burst base address */
-#define LL_TIM_DMABURST_LENGTH_26TRANSFERS \
- (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | \
- TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA \
- burst base address */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM1_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
-#define LL_TIM_TIM1_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM1_TI1_RMP_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM1_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM1_TI1_RMP_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM2_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
-#define LL_TIM_TIM2_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM2_TI1_RMP_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM2_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM2_TI1_RMP_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM2_TI1_RMP_COMP5 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
- * @{
- */
-#define LL_TIM_TIM2_TI2_RMP_GPIO \
- 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
-#define LL_TIM_TIM2_TI2_RMP_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
-#define LL_TIM_TIM2_TI2_RMP_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
-#define LL_TIM_TIM2_TI2_RMP_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
-#define LL_TIM_TIM2_TI2_RMP_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
-#if defined(COMP6)
-#define LL_TIM_TIM2_TI2_RMP_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
- * @{
- */
-#define LL_TIM_TIM2_TI3_RMP_GPIO \
- 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
-#define LL_TIM_TIM2_TI3_RMP_COMP4 \
- TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
- * @{
- */
-#define LL_TIM_TIM2_TI4_RMP_GPIO \
- 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
-#define LL_TIM_TIM2_TI4_RMP_COMP1 \
- TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP2 \
- TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM3_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
-#define LL_TIM_TIM3_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM3_TI1_RMP_COMP5 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM3_TI1_RMP_COMP6 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM3_TI1_RMP_COMP7 \
- (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
- * @{
- */
-#define LL_TIM_TIM3_TI2_RMP_GPIO \
- 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
-#define LL_TIM_TIM3_TI2_RMP_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
-#define LL_TIM_TIM3_TI2_RMP_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
-#define LL_TIM_TIM3_TI2_RMP_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
-#define LL_TIM_TIM3_TI2_RMP_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM3_TI2_RMP_COMP5 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM3_TI2_RMP_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM3_TI2_RMP_COMP7 \
- (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
- * @{
- */
-#define LL_TIM_TIM3_TI3_RMP_GPIO \
- 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
-#define LL_TIM_TIM3_TI3_RMP_COMP3 \
- TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM4_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
-#define LL_TIM_TIM4_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM4_TI1_RMP_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM4_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM4_TI1_RMP_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM4_TI1_RMP_COMP5 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM4_TI1_RMP_COMP6 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM4_TI1_RMP_COMP7 \
- (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
- * @{
- */
-#define LL_TIM_TIM4_TI2_RMP_GPIO \
- 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
-#define LL_TIM_TIM4_TI2_RMP_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
-#define LL_TIM_TIM4_TI2_RMP_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
-#define LL_TIM_TIM4_TI2_RMP_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
-#define LL_TIM_TIM4_TI2_RMP_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM4_TI2_RMP_COMP5 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM4_TI2_RMP_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM4_TI2_RMP_COMP7 \
- (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
- * @{
- */
-#define LL_TIM_TIM4_TI3_RMP_GPIO \
- 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
-#if defined(COMP5)
-#define LL_TIM_TIM4_TI3_RMP_COMP5 \
- TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
-#endif /* COMP5 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM4_TI4_RMP TIM4 Timer Input Ch4 Remap
- * @{
- */
-#define LL_TIM_TIM4_TI4_RMP_GPIO \
- 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
-#if defined(COMP6)
-#define LL_TIM_TIM4_TI4_RMP_COMP6 \
- TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
-#endif /* COMP6 */
-/**
- * @}
- */
-
-#if defined(TIM5)
-/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM5_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
-#define LL_TIM_TIM5_TI1_RMP_LSI \
- TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
-#define LL_TIM_TIM5_TI1_RMP_LSE \
- TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
-#define LL_TIM_TIM5_TI1_RMP_RTC_WK \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
-#define LL_TIM_TIM5_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM5_TI1_RMP_COMP2 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM5_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM5_TI1_RMP_COMP4 \
- (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM5_TI1_RMP_COMP5 \
- TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM5_TI1_RMP_COMP6 \
- (TIM_TISEL_TI1SEL_3 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM5_TI1_RMP_COMP7 \
- (TIM_TISEL_TI1SEL_3 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 Timer Input Ch2 Remap
- * @{
- */
-#define LL_TIM_TIM5_TI2_RMP_GPIO \
- 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
-#define LL_TIM_TIM5_TI2_RMP_COMP1 \
- TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
-#define LL_TIM_TIM5_TI2_RMP_COMP2 \
- TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
-#define LL_TIM_TIM5_TI2_RMP_COMP3 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
-#define LL_TIM_TIM5_TI2_RMP_COMP4 \
- TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM5_TI2_RMP_COMP5 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_TIM5_TI2_RMP_COMP6 \
- (TIM_TISEL_TI2SEL_2 | \
- TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM5_TI2_RMP_COMP7 \
- (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-#endif /* TIM5 */
-
-/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM8_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
-#define LL_TIM_TIM8_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM8_TI1_RMP_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM8_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM8_TI1_RMP_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM15_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
-#define LL_TIM_TIM15_TI1_RMP_LSE \
- TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
-#define LL_TIM_TIM15_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM15_TI1_RMP_COMP2 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
-#if defined(COMP5)
-#define LL_TIM_TIM15_TI1_RMP_COMP5 \
- TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP7)
-#define LL_TIM_TIM15_TI1_RMP_COMP7 \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
- * @{
- */
-#define LL_TIM_TIM15_TI2_RMP_GPIO \
- 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
-#define LL_TIM_TIM15_TI2_RMP_COMP2 \
- TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
-#define LL_TIM_TIM15_TI2_RMP_COMP3 \
- TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
-#if defined(COMP6)
-#define LL_TIM_TIM15_TI2_RMP_COMP6 \
- (TIM_TISEL_TI2SEL_1 | \
- TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_TIM15_TI2_RMP_COMP7 \
- TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM16_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
-#if defined(COMP6)
-#define LL_TIM_TIM16_TI1_RMP_COMP6 \
- TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
-#endif /* COMP6 */
-#define LL_TIM_TIM16_TI1_RMP_MCO \
- TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
-#define LL_TIM_TIM16_TI1_RMP_HSE_32 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
-#define LL_TIM_TIM16_TI1_RMP_RTC_WK \
- TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
-#define LL_TIM_TIM16_TI1_RMP_LSE \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
-#define LL_TIM_TIM16_TI1_RMP_LSI \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM17_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
-#if defined(COMP5)
-#define LL_TIM_TIM17_TI1_RMP_COMP5 \
- TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
-#endif /* COMP5 */
-#define LL_TIM_TIM17_TI1_RMP_MCO \
- TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
-#define LL_TIM_TIM17_TI1_RMP_HSE_32 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
-#define LL_TIM_TIM17_TI1_RMP_RTC_WK \
- TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
-#define LL_TIM_TIM17_TI1_RMP_LSE \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
-#define LL_TIM_TIM17_TI1_RMP_LSI \
- (TIM_TISEL_TI1SEL_2 | \
- TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
-/**
- * @}
- */
-
-#if defined(TIM20)
-/** @defgroup TIM_LL_EC_TIM20_TI1_RMP TIM20 Timer Input Ch1 Remap
- * @{
- */
-#define LL_TIM_TIM20_TI1_RMP_GPIO \
- 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
-#define LL_TIM_TIM20_TI1_RMP_COMP1 \
- TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
-#define LL_TIM_TIM20_TI1_RMP_COMP2 \
- TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
-#define LL_TIM_TIM20_TI1_RMP_COMP3 \
- (TIM_TISEL_TI1SEL_1 | \
- TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
-#define LL_TIM_TIM20_TI1_RMP_COMP4 \
- TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
-/**
- * @}
- */
-#endif /* TIM20 */
-
-/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
- * @{
- */
-#define LL_TIM_OCREF_CLR_INT_ETR \
- OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
-#define LL_TIM_OCREF_CLR_INT_COMP1 \
- 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
-#define LL_TIM_OCREF_CLR_INT_COMP2 \
- TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
-#define LL_TIM_OCREF_CLR_INT_COMP3 \
- TIM1_AF2_OCRSEL_1 /*!< OCREF clear input is connected to COMP3_OUT */
-#define LL_TIM_OCREF_CLR_INT_COMP4 \
- (TIM1_AF2_OCRSEL_1 | \
- TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP4_OUT */
-#if defined(COMP5)
-#define LL_TIM_OCREF_CLR_INT_COMP5 \
- TIM1_AF2_OCRSEL_2 /*!< OCREF clear input is connected to COMP5_OUT */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define LL_TIM_OCREF_CLR_INT_COMP6 \
- (TIM1_AF2_OCRSEL_2 | \
- TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP6_OUT */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define LL_TIM_OCREF_CLR_INT_COMP7 \
- (TIM1_AF2_OCRSEL_2 | \
- TIM1_AF2_OCRSEL_1) /*!< OCREF clear input is connected to COMP7_OUT */
-#endif /* COMP7 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
- * @{
- */
-#define LL_TIM_INDEX_UP_DOWN \
- 0x00000000U /*!< Index resets the counter whatever the direction */
-#define LL_TIM_INDEX_UP \
- TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
-#define LL_TIM_INDEX_DOWN \
- TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
- * @{
- */
-#define LL_TIM_INDEX_POSITION_DOWN_DOWN \
- 0x00000000U /*!< Index resets the counter when AB = 00 */
-#define LL_TIM_INDEX_POSITION_DOWN_UP \
- TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
-#define LL_TIM_INDEX_POSITION_UP_DOWN \
- TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
-#define LL_TIM_INDEX_POSITION_UP_UP \
- (TIM_ECR_IPOS_1 | \
- TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
-#define LL_TIM_INDEX_POSITION_DOWN \
- 0x00000000U /*!< Index resets the counter when clock is 0 */
-#define LL_TIM_INDEX_POSITION_UP \
- TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
- * @{
- */
-#define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
-#define LL_TIM_INDEX_FIRST_ONLY \
- TIM_ECR_FIDX /*!< The first Index only resets the counter */
-/**
- * @}
- */
-/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
- * @{
- */
-#define LL_TIM_PWPRSC_X1 \
- 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
-#define LL_TIM_PWPRSC_X2 \
- TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
-#define LL_TIM_PWPRSC_X4 \
- TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
-#define LL_TIM_PWPRSC_X8 \
- (TIM_ECR_PWPRSC_1 | \
- TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
-#define LL_TIM_PWPRSC_X16 \
- TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
-#define LL_TIM_PWPRSC_X32 \
- (TIM_ECR_PWPRSC_2 | \
- TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
-#define LL_TIM_PWPRSC_X64 \
- (TIM_ECR_PWPRSC_2 | \
- TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
-#define LL_TIM_PWPRSC_X128 \
- (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | \
- TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
- * @{
- */
-#define LL_TIM_HSE_32_NOT_REQUEST \
- 0x00000000U /*!< Clock HSE/32 not requested \
- */
-#define LL_TIM_HSE_32_REQUEST \
- TIM_OR_HSE32EN /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
-/**
- * @}
- */
-
-/** Legacy definitions for compatibility purpose
-@cond 0
- */
-#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
-/**
-@endcond
- */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-/**
- * @brief Write a value in TIM register.
- * @param __INSTANCE__ TIM Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in TIM register.
- * @param __INSTANCE__ TIM Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
-/**
- * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
- * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
- * @note Relevant only if UIF flag remapping has been enabled (UIF status bit
- * is copied to TIMx_CNT register bit 31)
- * @param __CNT__ Counter value
- * @retval UIF status bit
- */
-#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
- (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
-
-/**
- * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to
- * achieve the requested dead time duration.
- * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision
- * (), 120);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @param __DT__ deadtime duration (in ns)
- * @retval DTG[0:7]
- */
-#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ((((uint64_t)((__DT__) * 1000U)) < \
- ((DT_DELAY_1 + 1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
- ? (uint8_t)(((uint64_t)((__DT__) * 1000U) / \
- TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & \
- DT_DELAY_1) \
- : (((uint64_t)((__DT__) * 1000U)) < \
- ((64U + (DT_DELAY_2 + 1U)) * 2U * \
- TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
- ? (uint8_t)(DT_RANGE_2 | \
- ((uint8_t)((uint8_t)((((uint64_t)((__DT__) * 1000U)) / \
- TIM_CALC_DTS((__TIMCLK__), \
- (__CKD__))) >> \
- 1U) - \
- (uint8_t)64) & \
- DT_DELAY_2)) \
- : (((uint64_t)((__DT__) * 1000U)) < \
- ((32U + (DT_DELAY_3 + 1U)) * 8U * \
- TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
- ? (uint8_t)(DT_RANGE_3 | \
- ((uint8_t)((uint8_t)(((((uint64_t)(__DT__) * 1000U)) / \
- TIM_CALC_DTS((__TIMCLK__), \
- (__CKD__))) >> \
- 3U) - \
- (uint8_t)32) & \
- DT_DELAY_3)) \
- : (((uint64_t)((__DT__) * 1000U)) < \
- ((32U + (DT_DELAY_4 + 1U)) * 16U * \
- TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
- ? (uint8_t)(DT_RANGE_4 | \
- ((uint8_t)((uint8_t)(((((uint64_t)(__DT__) * 1000U)) / \
- TIM_CALC_DTS((__TIMCLK__), \
- (__CKD__))) >> \
- 4U) - \
- (uint8_t)32) & \
- DT_DELAY_4)) \
- : 0U)
-
-/**
- * @brief HELPER macro calculating the prescaler value to achieve the required
- * counter clock frequency.
- * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CNTCLK__ counter clock frequency (in Hz)
- * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- (((__TIMCLK__) >= (__CNTCLK__)) \
- ? (uint32_t)(((__TIMCLK__) / (__CNTCLK__)) - 1U) \
- : 0U)
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the
- * required output signal frequency.
- * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (),
- * 10000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __FREQ__ output signal frequency (in Hz)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- ((((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
- ? (((__TIMCLK__) / ((__FREQ__) * ((__PSC__) + 1U))) - 1U) \
- : 0U)
-
-/**
- * @brief HELPER macro calculating the auto-reload value, with dithering
- * feature enabled, to achieve the required output signal frequency.
- * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler
- * (), 10000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __FREQ__ output signal frequency (in Hz)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
- ((((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
- ? (uint32_t)((((uint64_t)(__TIMCLK__) * 16U / \
- ((__FREQ__) * ((__PSC__) + 1U))) - \
- 16U)) \
- : 0U)
-
-/**
- * @brief HELPER macro calculating the compare value required to achieve the
- * required timer output compare active/inactive delay.
- * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (),
- * 10);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @retval Compare value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
- ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) / \
- ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
- * @brief HELPER macro calculating the compare value, with dithering feature
- * enabled, to achieve the required timer output compare active/inactive delay.
- * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler
- * (), 10);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @retval Compare value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
- ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) / \
- ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the
- * required pulse duration (when the timer operates in one pulse mode).
- * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10,
- * 20);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @param __PULSE__ pulse duration (in us)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) + \
- __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
- * @brief HELPER macro calculating the auto-reload value, with dithering
- * feature enabled, to achieve the required pulse duration (when the timer
- * operates in one pulse mode).
- * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler
- * (), 10, 20);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @param __PULSE__ pulse duration (in us)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), \
- (__PULSE__)) + \
- __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), \
- (__DELAY__))))
-
-/**
- * @brief HELPER macro retrieving the ratio of the input capture prescaler
- * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
- * @param __ICPSC__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- * @retval Input capture prescaler ratio (1, 2, 4 or 8)
- */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
- * @{
- */
-/**
- * @brief Enable timer counter.
- * @rmtoll CR1 CEN LL_TIM_EnableCounter
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
- * @brief Disable timer counter.
- * @rmtoll CR1 CEN LL_TIM_DisableCounter
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
- * @brief Indicates whether the timer counter is enabled.
- * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable update event generation.
- * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
- * @brief Disable update event generation.
- * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
- * @brief Indicates whether update event generation is enabled.
- * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
- * @param TIMx Timer instance
- * @retval Inverted state of bit (0 or 1).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set update event source
- * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the
- * following events generate an update interrupt or DMA request if enabled:
- * - Counter overflow/underflow
- * - Setting the UG bit
- * - Update generation through the slave mode controller
- * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
- * overflow/underflow generates an update interrupt or DMA request if
- * enabled.
- * @rmtoll CR1 URS LL_TIM_SetUpdateSource
- * @param TIMx Timer instance
- * @param UpdateSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx,
- uint32_t UpdateSource) {
- MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
- * @brief Get actual event update source
- * @rmtoll CR1 URS LL_TIM_GetUpdateSource
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
- * @brief Set one pulse mode (one shot v.s. repetitive).
- * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
- * @param TIMx Timer instance
- * @param OnePulseMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx,
- uint32_t OnePulseMode) {
- MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
- * @brief Get actual one pulse mode.
- * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
- * @brief Set the timer counter counting mode.
- * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- * check whether or not the counter mode selection feature is supported
- * by a timer instance.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode.
- * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
- * CR1 CMS LL_TIM_SetCounterMode
- * @param TIMx Timer instance
- * @param CounterMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_COUNTERMODE_UP
- * @arg @ref LL_TIM_COUNTERMODE_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx,
- uint32_t CounterMode) {
- MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
-}
-
-/**
- * @brief Get actual counter mode.
- * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- * check whether or not the counter mode selection feature is supported
- * by a timer instance.
- * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
- * CR1 CMS LL_TIM_GetCounterMode
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_COUNTERMODE_UP
- * @arg @ref LL_TIM_COUNTERMODE_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) {
- uint32_t counter_mode;
-
- counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
-
- if (counter_mode == 0U) {
- counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
- }
-
- return counter_mode;
-}
-
-/**
- * @brief Enable auto-reload (ARR) preload.
- * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
- * @brief Disable auto-reload (ARR) preload.
- * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
- * @brief Indicates whether auto-reload (ARR) preload is enabled.
- * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set the division ratio between the timer clock and the sampling
- * clock used by the dead-time generators (when supported) and the digital
- * filters.
- * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- * whether or not the clock division feature is supported by the timer
- * instance.
- * @rmtoll CR1 CKD LL_TIM_SetClockDivision
- * @param TIMx Timer instance
- * @param ClockDivision This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx,
- uint32_t ClockDivision) {
- MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
- * @brief Get the actual division ratio between the timer clock and the
- * sampling clock used by the dead-time generators (when supported) and the
- * digital filters.
- * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- * whether or not the clock division feature is supported by the timer
- * instance.
- * @rmtoll CR1 CKD LL_TIM_GetClockDivision
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
- * @brief Set the counter value.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note If dithering is activated, pay attention to the Counter value
- * interpretation
- * @rmtoll CNT CNT LL_TIM_SetCounter
- * @param TIMx Timer instance
- * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or
- * 0xFFFFFFFF)
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) {
- WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
- * @brief Get the counter value.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note If dithering is activated, pay attention to the Counter value
- * interpretation
- * @rmtoll CNT CNT LL_TIM_GetCounter
- * @param TIMx Timer instance
- * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
- */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
- * @brief Get the current direction of the counter
- * @rmtoll CR1 DIR LL_TIM_GetDirection
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_COUNTERDIRECTION_UP
- * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
- * @brief Set the prescaler value.
- * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] +
- * 1).
- * @note The prescaler can be changed on the fly as this control register is
- * buffered. The new prescaler ratio is taken into account at the next update
- * event.
- * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the
- * Prescaler parameter
- * @rmtoll PSC PSC LL_TIM_SetPrescaler
- * @param TIMx Timer instance
- * @param Prescaler between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx,
- uint32_t Prescaler) {
- WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
- * @brief Get the prescaler value.
- * @rmtoll PSC PSC LL_TIM_GetPrescaler
- * @param TIMx Timer instance
- * @retval Prescaler value between Min_Data=0 and Max_Data=65535
- */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
- * @brief Set the auto-reload value.
- * @note The counter is blocked while the auto-reload value is null.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the
- * AutoReload parameter In case dithering is activated,macro
- * __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
- * parameter.
- * @rmtoll ARR ARR LL_TIM_SetAutoReload
- * @param TIMx Timer instance
- * @param AutoReload between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx,
- uint32_t AutoReload) {
- WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
- * @brief Get the auto-reload value.
- * @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation
- * @param TIMx Timer instance
- * @retval Auto-reload value
- */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
- * @brief Set the repetition counter value.
- * @note For advanced timer instances RepetitionCounter can be up to 65535.
- * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a repetition counter.
- * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
- * @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for
- * advanced timer.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx,
- uint32_t RepetitionCounter) {
- WRITE_REG(TIMx->RCR, RepetitionCounter);
-}
-
-/**
- * @brief Get the repetition counter value.
- * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a repetition counter.
- * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
- * @param TIMx Timer instance
- * @retval Repetition counter value
- */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->RCR));
-}
-
-/**
- * @brief Force a continuous copy of the update interrupt flag (UIF) into the
- * timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition
- * signalled by the UIFCPY flag to be read in an atomic way.
- * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
- * @brief Disable update interrupt flag (UIF) remapping.
- * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
- * @brief Indicate whether update interrupt flag (UIF) copy is set.
- * @param Counter Counter value
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) {
- return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable dithering.
- * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance provides dithering.
- * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
-}
-
-/**
- * @brief Disable dithering.
- * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance provides dithering.
- * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
-}
-
-/**
- * @brief Indicates whether dithering is activated.
- * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance provides dithering.
- * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
- * @{
- */
-/**
- * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM)
- * preload.
- * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
- * they are updated only when a commutation event (COM) occurs.
- * @note Only on channels that have a complementary output.
- * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation
- * event.
- * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
- * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM)
- * preload.
- * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation
- * event.
- * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
- * @brief Set the updated source of the capture/compare control bits (CCxE,
- * CCxNE and OCxM).
- * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation
- * event.
- * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
- * @param TIMx Timer instance
- * @param CCUpdateSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
- * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx,
- uint32_t CCUpdateSource) {
- MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
-}
-
-/**
- * @brief Set the trigger of the capture/compare DMA request.
- * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
- * @param TIMx Timer instance
- * @param DMAReqTrigger This parameter can be one of the following values:
- * @arg @ref LL_TIM_CCDMAREQUEST_CC
- * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx,
- uint32_t DMAReqTrigger) {
- MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
- * @brief Get actual trigger of the capture/compare DMA request.
- * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_CCDMAREQUEST_CC
- * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
- * @brief Set the lock level to freeze the
- * configuration of several capture/compare parameters.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * the lock mechanism is supported by a timer instance.
- * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
- * @param TIMx Timer instance
- * @param LockLevel This parameter can be one of the following values:
- * @arg @ref LL_TIM_LOCKLEVEL_OFF
- * @arg @ref LL_TIM_LOCKLEVEL_1
- * @arg @ref LL_TIM_LOCKLEVEL_2
- * @arg @ref LL_TIM_LOCKLEVEL_3
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx,
- uint32_t LockLevel) {
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
-}
-
-/**
- * @brief Enable capture/compare channels.
- * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
- * CCER CC1NE LL_TIM_CC_EnableChannel\n
- * CCER CC2E LL_TIM_CC_EnableChannel\n
- * CCER CC2NE LL_TIM_CC_EnableChannel\n
- * CCER CC3E LL_TIM_CC_EnableChannel\n
- * CCER CC3NE LL_TIM_CC_EnableChannel\n
- * CCER CC4E LL_TIM_CC_EnableChannel\n
- * CCER CC4NE LL_TIM_CC_EnableChannel\n
- * CCER CC5E LL_TIM_CC_EnableChannel\n
- * CCER CC6E LL_TIM_CC_EnableChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx,
- uint32_t Channels) {
- SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
- * @brief Disable capture/compare channels.
- * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
- * CCER CC1NE LL_TIM_CC_DisableChannel\n
- * CCER CC2E LL_TIM_CC_DisableChannel\n
- * CCER CC2NE LL_TIM_CC_DisableChannel\n
- * CCER CC3E LL_TIM_CC_DisableChannel\n
- * CCER CC3NE LL_TIM_CC_DisableChannel\n
- * CCER CC4E LL_TIM_CC_DisableChannel\n
- * CCER CC4NE LL_TIM_CC_DisableChannel\n
- * CCER CC5E LL_TIM_CC_DisableChannel\n
- * CCER CC6E LL_TIM_CC_DisableChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx,
- uint32_t Channels) {
- CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
- * @brief Indicate whether channel(s) is(are) enabled.
- * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC6E LL_TIM_CC_IsEnabledChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx,
- uint32_t Channels) {
- return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
- * @{
- */
-/**
- * @brief Configure an output channel.
- * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
- * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
- * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
- * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
- * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
- * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
- * CCER CC1P LL_TIM_OC_ConfigOutput\n
- * CCER CC2P LL_TIM_OC_ConfigOutput\n
- * CCER CC3P LL_TIM_OC_ConfigOutput\n
- * CCER CC4P LL_TIM_OC_ConfigOutput\n
- * CCER CC5P LL_TIM_OC_ConfigOutput\n
- * CCER CC6P LL_TIM_OC_ConfigOutput\n
- * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS6 LL_TIM_OC_ConfigOutput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @param Configuration This parameter must be a combination of all the
- * following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t Configuration) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
- MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
- (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
- MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
- (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Define the behavior of the output reference signal OCxREF from which
- * OCx and OCxN (when relevant) are derived.
- * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
- * CCMR1 OC2M LL_TIM_OC_SetMode\n
- * CCMR2 OC3M LL_TIM_OC_SetMode\n
- * CCMR2 OC4M LL_TIM_OC_SetMode\n
- * CCMR3 OC5M LL_TIM_OC_SetMode\n
- * CCMR3 OC6M LL_TIM_OC_SetMode
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCMODE_FROZEN
- * @arg @ref LL_TIM_OCMODE_ACTIVE
- * @arg @ref LL_TIM_OCMODE_INACTIVE
- * @arg @ref LL_TIM_OCMODE_TOGGLE
- * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- * @arg @ref LL_TIM_OCMODE_PWM1
- * @arg @ref LL_TIM_OCMODE_PWM2
- * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
- * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
- * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
- * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
- * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel
- * 4 only)
- * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel
- * 4 only)
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t Mode) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg,
- ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),
- Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
- * @brief Get the output compare mode of an output channel.
- * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
- * CCMR1 OC2M LL_TIM_OC_GetMode\n
- * CCMR2 OC3M LL_TIM_OC_GetMode\n
- * CCMR2 OC4M LL_TIM_OC_GetMode\n
- * CCMR3 OC5M LL_TIM_OC_GetMode\n
- * CCMR3 OC6M LL_TIM_OC_GetMode
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCMODE_FROZEN
- * @arg @ref LL_TIM_OCMODE_ACTIVE
- * @arg @ref LL_TIM_OCMODE_INACTIVE
- * @arg @ref LL_TIM_OCMODE_TOGGLE
- * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- * @arg @ref LL_TIM_OCMODE_PWM1
- * @arg @ref LL_TIM_OCMODE_PWM2
- * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
- * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
- * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
- * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
- * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel
- * 4 only)
- * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel
- * 4 only)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)
- << SHIFT_TAB_OCxx[iChannel])) >>
- SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
- * @brief Set the polarity of an output channel.
- * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
- * CCER CC1NP LL_TIM_OC_SetPolarity\n
- * CCER CC2P LL_TIM_OC_SetPolarity\n
- * CCER CC2NP LL_TIM_OC_SetPolarity\n
- * CCER CC3P LL_TIM_OC_SetPolarity\n
- * CCER CC3NP LL_TIM_OC_SetPolarity\n
- * CCER CC4P LL_TIM_OC_SetPolarity\n
- * CCER CC4NP LL_TIM_OC_SetPolarity\n
- * CCER CC5P LL_TIM_OC_SetPolarity\n
- * CCER CC6P LL_TIM_OC_SetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH
- * @arg @ref LL_TIM_OCPOLARITY_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t Polarity) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
- Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Get the polarity of an output channel.
- * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
- * CCER CC1NP LL_TIM_OC_GetPolarity\n
- * CCER CC2P LL_TIM_OC_GetPolarity\n
- * CCER CC2NP LL_TIM_OC_GetPolarity\n
- * CCER CC3P LL_TIM_OC_GetPolarity\n
- * CCER CC3NP LL_TIM_OC_GetPolarity\n
- * CCER CC4P LL_TIM_OC_GetPolarity\n
- * CCER CC4NP LL_TIM_OC_GetPolarity\n
- * CCER CC5P LL_TIM_OC_GetPolarity\n
- * CCER CC6P LL_TIM_OC_GetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH
- * @arg @ref LL_TIM_OCPOLARITY_LOW
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >>
- SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Set the IDLE state of an output channel
- * @note This function is significant only for the timer instances
- * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
- * can be used to check whether or not a timer instance provides
- * a break input.
- * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
- * CR2 OIS2N LL_TIM_OC_SetIdleState\n
- * CR2 OIS2 LL_TIM_OC_SetIdleState\n
- * CR2 OIS2N LL_TIM_OC_SetIdleState\n
- * CR2 OIS3 LL_TIM_OC_SetIdleState\n
- * CR2 OIS3N LL_TIM_OC_SetIdleState\n
- * CR2 OIS4 LL_TIM_OC_SetIdleState\n
- * CR2 OIS4N LL_TIM_OC_SetIdleState\n
- * CR2 OIS5 LL_TIM_OC_SetIdleState\n
- * CR2 OIS6 LL_TIM_OC_SetIdleState
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @param IdleState This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCIDLESTATE_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t IdleState) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
- IdleState << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Get the IDLE state of an output channel
- * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
- * CR2 OIS2N LL_TIM_OC_GetIdleState\n
- * CR2 OIS2 LL_TIM_OC_GetIdleState\n
- * CR2 OIS2N LL_TIM_OC_GetIdleState\n
- * CR2 OIS3 LL_TIM_OC_GetIdleState\n
- * CR2 OIS3N LL_TIM_OC_GetIdleState\n
- * CR2 OIS4 LL_TIM_OC_GetIdleState\n
- * CR2 OIS4N LL_TIM_OC_GetIdleState\n
- * CR2 OIS5 LL_TIM_OC_GetIdleState\n
- * CR2 OIS6 LL_TIM_OC_GetIdleState
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH4N
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCIDLESTATE_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >>
- SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Enable fast mode for the output channel.
- * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
- * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
- * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
- * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
- * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
- * CCMR3 OC6FE LL_TIM_OC_EnableFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable fast mode for the output channel.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
- * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
- * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
- * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
- * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
- * CCMR3 OC6FE LL_TIM_OC_DisableFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates whether fast mode is enabled for the output channel.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
- * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
- * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
- * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
- * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
- * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
- * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
- * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
- * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
- * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
- * CCMR3 OC6PE LL_TIM_OC_EnablePreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
- * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
- * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
- * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
- * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
- * CCMR3 OC6PE LL_TIM_OC_DisablePreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for
- * the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable clearing the output channel on an external event.
- * @note This function can only be used in Output compare and PWM modes. It does
- * not work in Forced mode.
- * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external
- * event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
- * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
- * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
- * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
- * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
- * CCMR3 OC6CE LL_TIM_OC_EnableClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable clearing the output channel on an external event.
- * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external
- * event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
- * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
- * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
- * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
- * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
- * CCMR3 OC6CE LL_TIM_OC_DisableClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates clearing the output channel on an external event is enabled
- * for the output channel.
- * @note This function enables clearing the output channel on an external event.
- * @note This function can only be used in Output compare and PWM modes. It does
- * not work in Forced mode.
- * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external
- * event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
- * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
- * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
- * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
- * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
- * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of
- * the OCxREF signal and the rising edge of the Ocx and OCxN signals).
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * dead-time insertion feature is supported by a timer instance.
- * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the
- * DeadTime parameter
- * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
- * @param TIMx Timer instance
- * @param DeadTime between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx,
- uint32_t DeadTime) {
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
-}
-
-/**
- * @brief Set compare value for output channel 1 (TIMx_CCR1).
- * @note In 32-bit timer implementations compare value can be between 0x00000000
- * and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * output channel 1 is supported by a timer instance.
- * @note If dithering is activated, CompareValue can be calculated with macro
- * @ref __LL_TIM_CALC_DELAY_DITHER .
- * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx,
- uint32_t CompareValue) {
- WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 2 (TIMx_CCR2).
- * @note In 32-bit timer implementations compare value can be between 0x00000000
- * and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * output channel 2 is supported by a timer instance.
- * @note If dithering is activated, CompareValue can be calculated with macro
- * @ref __LL_TIM_CALC_DELAY_DITHER .
- * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx,
- uint32_t CompareValue) {
- WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 3 (TIMx_CCR3).
- * @note In 32-bit timer implementations compare value can be between 0x00000000
- * and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * output channel is supported by a timer instance.
- * @note If dithering is activated, CompareValue can be calculated with macro
- * @ref __LL_TIM_CALC_DELAY_DITHER .
- * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx,
- uint32_t CompareValue) {
- WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 4 (TIMx_CCR4).
- * @note In 32-bit timer implementations compare value can be between 0x00000000
- * and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * output channel 4 is supported by a timer instance.
- * @note If dithering is activated, CompareValue can be calculated with macro
- * @ref __LL_TIM_CALC_DELAY_DITHER .
- * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx,
- uint32_t CompareValue) {
- WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 5 (TIMx_CCR5).
- * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
- * output channel 5 is supported by a timer instance.
- * @note If dithering is activated, CompareValue can be calculated with macro
- * @ref __LL_TIM_CALC_DELAY_DITHER .
- * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx,
- uint32_t CompareValue) {
- MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 6 (TIMx_CCR6).
- * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
- * output channel 6 is supported by a timer instance.
- * @note If dithering is activated, CompareValue can be calculated with macro
- * @ref __LL_TIM_CALC_DELAY_DITHER .
- * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx,
- uint32_t CompareValue) {
- WRITE_REG(TIMx->CCR6, CompareValue);
-}
-
-/**
- * @brief Get compare value (TIMx_CCR1) set for output channel 1.
- * @note In 32-bit timer implementations returned compare value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * output channel 1 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR2) set for output channel 2.
- * @note In 32-bit timer implementations returned compare value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * output channel 2 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR3) set for output channel 3.
- * @note In 32-bit timer implementations returned compare value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * output channel 3 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR4) set for output channel 4.
- * @note In 32-bit timer implementations returned compare value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * output channel 4 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR5) set for output channel 5.
- * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
- * output channel 5 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR6) set for output channel 6.
- * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
- * output channel 6 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR6));
-}
-
-/**
- * @brief Select on which reference signal the OC5REF is combined to.
- * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the combined 3-phase PWM mode.
- * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
- * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
- * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
- * @param TIMx Timer instance
- * @param GroupCH5 This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_GROUPCH5_NONE
- * @arg @ref LL_TIM_GROUPCH5_OC1REFC
- * @arg @ref LL_TIM_GROUPCH5_OC2REFC
- * @arg @ref LL_TIM_GROUPCH5_OC3REFC
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx,
- uint32_t GroupCH5) {
- MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1),
- GroupCH5);
-}
-
-/**
- * @brief Set the pulse on compare pulse width prescaler.
- * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
- * whether or not the pulse on compare feature is supported by the timer
- * instance.
- * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
- * @param TIMx Timer instance
- * @param PulseWidthPrescaler This parameter can be one of the following
- * values:
- * @arg @ref LL_TIM_PWPRSC_X1
- * @arg @ref LL_TIM_PWPRSC_X2
- * @arg @ref LL_TIM_PWPRSC_X4
- * @arg @ref LL_TIM_PWPRSC_X8
- * @arg @ref LL_TIM_PWPRSC_X16
- * @arg @ref LL_TIM_PWPRSC_X32
- * @arg @ref LL_TIM_PWPRSC_X64
- * @arg @ref LL_TIM_PWPRSC_X128
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(
- TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler) {
- MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
-}
-
-/**
- * @brief Get the pulse on compare pulse width prescaler.
- * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
- * whether or not the pulse on compare feature is supported by the timer
- * instance.
- * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_PWPRSC_X1
- * @arg @ref LL_TIM_PWPRSC_X2
- * @arg @ref LL_TIM_PWPRSC_X4
- * @arg @ref LL_TIM_PWPRSC_X8
- * @arg @ref LL_TIM_PWPRSC_X16
- * @arg @ref LL_TIM_PWPRSC_X32
- * @arg @ref LL_TIM_PWPRSC_X64
- * @arg @ref LL_TIM_PWPRSC_X128
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
-}
-
-/**
- * @brief Set the pulse on compare pulse width duration.
- * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
- * whether or not the pulse on compare feature is supported by the timer
- * instance.
- * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
- * @param TIMx Timer instance
- * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx,
- uint32_t PulseWidth) {
- MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
-}
-
-/**
- * @brief Get the pulse on compare pulse width duration.
- * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
- * whether or not the pulse on compare feature is supported by the timer
- * instance.
- * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
- * @param TIMx Timer instance
- * @retval Returned value can be between Min_Data=0 and Max_Data=255:
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
- * @{
- */
-/**
- * @brief Configure input channel.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
- * CCMR1 IC1PSC LL_TIM_IC_Config\n
- * CCMR1 IC1F LL_TIM_IC_Config\n
- * CCMR1 CC2S LL_TIM_IC_Config\n
- * CCMR1 IC2PSC LL_TIM_IC_Config\n
- * CCMR1 IC2F LL_TIM_IC_Config\n
- * CCMR2 CC3S LL_TIM_IC_Config\n
- * CCMR2 IC3PSC LL_TIM_IC_Config\n
- * CCMR2 IC3F LL_TIM_IC_Config\n
- * CCMR2 CC4S LL_TIM_IC_Config\n
- * CCMR2 IC4PSC LL_TIM_IC_Config\n
- * CCMR2 IC4F LL_TIM_IC_Config\n
- * CCER CC1P LL_TIM_IC_Config\n
- * CCER CC1NP LL_TIM_IC_Config\n
- * CCER CC2P LL_TIM_IC_Config\n
- * CCER CC2NP LL_TIM_IC_Config\n
- * CCER CC3P LL_TIM_IC_Config\n
- * CCER CC3NP LL_TIM_IC_Config\n
- * CCER CC4P LL_TIM_IC_Config\n
- * CCER CC4NP LL_TIM_IC_Config
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Configuration This parameter must be a combination of all the
- * following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref
- * LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
- * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
- * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref
- * LL_TIM_IC_FILTER_FDIV32_N8
- * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref
- * LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t Configuration) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg,
- ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)
- << SHIFT_TAB_ICxx[iChannel]),
- ((Configuration >> 16U) &
- (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))
- << SHIFT_TAB_ICxx[iChannel]);
- MODIFY_REG(TIMx->CCER,
- ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P))
- << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Set the active input.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
- * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
- * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
- * CCMR2 CC4S LL_TIM_IC_SetActiveInput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICActiveInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx,
- uint32_t Channel,
- uint32_t ICActiveInput) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
- (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the current active input.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
- * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
- * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
- * CCMR2 CC4S LL_TIM_IC_GetActiveInput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >>
- SHIFT_TAB_ICxx[iChannel])
- << 16U);
-}
-
-/**
- * @brief Set the prescaler of input channel.
- * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
- * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
- * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
- * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICPrescaler This parameter can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ICPrescaler) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]),
- (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the current prescaler value acting on an input channel.
- * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
- * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
- * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
- * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >>
- SHIFT_TAB_ICxx[iChannel])
- << 16U);
-}
-
-/**
- * @brief Set the input filter duration.
- * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
- * CCMR1 IC2F LL_TIM_IC_SetFilter\n
- * CCMR2 IC3F LL_TIM_IC_SetFilter\n
- * CCMR2 IC4F LL_TIM_IC_SetFilter
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_IC_FILTER_FDIV1
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ICFilter) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]),
- (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the input filter duration.
- * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
- * CCMR1 IC2F LL_TIM_IC_GetFilter\n
- * CCMR2 IC3F LL_TIM_IC_GetFilter\n
- * CCMR2 IC4F LL_TIM_IC_GetFilter
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_IC_FILTER_FDIV1
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((
- uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >>
- SHIFT_TAB_ICxx[iChannel])
- << 16U);
-}
-
-/**
- * @brief Set the input channel polarity.
- * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
- * CCER CC1NP LL_TIM_IC_SetPolarity\n
- * CCER CC2P LL_TIM_IC_SetPolarity\n
- * CCER CC2NP LL_TIM_IC_SetPolarity\n
- * CCER CC3P LL_TIM_IC_SetPolarity\n
- * CCER CC3NP LL_TIM_IC_SetPolarity\n
- * CCER CC4P LL_TIM_IC_SetPolarity\n
- * CCER CC4NP LL_TIM_IC_SetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_IC_POLARITY_RISING
- * @arg @ref LL_TIM_IC_POLARITY_FALLING
- * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ICPolarity) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CCER,
- ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Get the current input channel polarity.
- * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
- * CCER CC1NP LL_TIM_IC_GetPolarity\n
- * CCER CC2P LL_TIM_IC_GetPolarity\n
- * CCER CC2NP LL_TIM_IC_GetPolarity\n
- * CCER CC3P LL_TIM_IC_GetPolarity\n
- * CCER CC3NP LL_TIM_IC_GetPolarity\n
- * CCER CC4P LL_TIM_IC_GetPolarity\n
- * CCER CC4NP LL_TIM_IC_GetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_IC_POLARITY_RISING
- * @arg @ref LL_TIM_IC_POLARITY_FALLING
- * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx,
- uint32_t Channel) {
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P)
- << SHIFT_TAB_CCxP[iChannel])) >>
- SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR
- * combination).
- * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
- * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
- * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to
- * the TI1 input.
- * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get captured value for input channel 1.
- * @note In 32-bit timer implementations returned captured value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * input channel 1 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
- * @brief Get captured value for input channel 2.
- * @note In 32-bit timer implementations returned captured value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * input channel 2 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
- * @brief Get captured value for input channel 3.
- * @note In 32-bit timer implementations returned captured value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * input channel 3 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
- * @brief Get captured value for input channel 4.
- * @note In 32-bit timer implementations returned captured value can be between
- * 0x00000000 and 0xFFFFFFFF.
- * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a 32 bits counter.
- * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * input channel 4 is supported by a timer instance.
- * @note If dithering is activated, pay attention to the returned value
- * interpretation.
- * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
- * @{
- */
-/**
- * @brief Enable external clock mode 2.
- * @note When external clock mode 2 is enabled the counter is clocked by any
- * active edge on the ETRF signal.
- * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
- * @brief Disable external clock mode 2.
- * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
- * @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set the clock source of the counter clock.
- * @note when selected clock source is external clock mode 1, the timer input
- * the external clock is applied is selected by calling the @ref
- * LL_TIM_SetTriggerInput() function. This timer input must be configured by
- * calling the @ref LL_TIM_IC_Config() function.
- * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode1.
- * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
- * SMCR ECE LL_TIM_SetClockSource
- * @param TIMx Timer instance
- * @param ClockSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
- * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
- * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx,
- uint32_t ClockSource) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
- * @brief Set the encoder interface mode.
- * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the encoder mode.
- * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
- * @param TIMx Timer instance
- * @param EncoderMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
- * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
- * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
- * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
- * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
- * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
- * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
- * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
- * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx,
- uint32_t EncoderMode) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation
- * configuration
- * @{
- */
-/**
- * @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance can operate as a master timer.
- * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
- * @param TIMx Timer instance
- * @param TimerSynchronization This parameter can be one of the following
- * values:
- * @arg @ref LL_TIM_TRGO_RESET
- * @arg @ref LL_TIM_TRGO_ENABLE
- * @arg @ref LL_TIM_TRGO_UPDATE
- * @arg @ref LL_TIM_TRGO_CC1IF
- * @arg @ref LL_TIM_TRGO_OC1REF
- * @arg @ref LL_TIM_TRGO_OC2REF
- * @arg @ref LL_TIM_TRGO_OC3REF
- * @arg @ref LL_TIM_TRGO_OC4REF
- * @arg @ref LL_TIM_TRGO_ENCODERCLK
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx,
- uint32_t TimerSynchronization) {
- MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
- * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
- * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance can be used for ADC synchronization.
- * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
- * @param TIMx Timer Instance
- * @param ADCSynchronization This parameter can be one of the following values:
- * @arg @ref LL_TIM_TRGO2_RESET
- * @arg @ref LL_TIM_TRGO2_ENABLE
- * @arg @ref LL_TIM_TRGO2_UPDATE
- * @arg @ref LL_TIM_TRGO2_CC1F
- * @arg @ref LL_TIM_TRGO2_OC1
- * @arg @ref LL_TIM_TRGO2_OC2
- * @arg @ref LL_TIM_TRGO2_OC3
- * @arg @ref LL_TIM_TRGO2_OC4
- * @arg @ref LL_TIM_TRGO2_OC5
- * @arg @ref LL_TIM_TRGO2_OC6
- * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
- * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
- * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
- * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
- * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
- * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx,
- uint32_t ADCSynchronization) {
- MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
-}
-
-/**
- * @brief Set the synchronization mode of a slave timer.
- * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
- * @param TIMx Timer instance
- * @param SlaveMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_SLAVEMODE_DISABLED
- * @arg @ref LL_TIM_SLAVEMODE_RESET
- * @arg @ref LL_TIM_SLAVEMODE_GATED
- * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
- * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
- * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx,
- uint32_t SlaveMode) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
- * @brief Set the selects the trigger input to be used to synchronize the
- * counter.
- * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR TS LL_TIM_SetTriggerInput
- * @param TIMx Timer instance
- * @param TriggerInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_TS_ITR0
- * @arg @ref LL_TIM_TS_ITR1
- * @arg @ref LL_TIM_TS_ITR2
- * @arg @ref LL_TIM_TS_ITR3
- * @arg @ref LL_TIM_TS_TI1F_ED
- * @arg @ref LL_TIM_TS_TI1FP1
- * @arg @ref LL_TIM_TS_TI2FP2
- * @arg @ref LL_TIM_TS_ETRF
- * @arg @ref LL_TIM_TS_ITR4
- * @arg @ref LL_TIM_TS_ITR5
- * @arg @ref LL_TIM_TS_ITR6
- * @arg @ref LL_TIM_TS_ITR7
- * @arg @ref LL_TIM_TS_ITR8
- * @arg @ref LL_TIM_TS_ITR9
- * @arg @ref LL_TIM_TS_ITR10
- * @arg @ref LL_TIM_TS_ITR11
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx,
- uint32_t TriggerInput) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
- * @brief Enable the Master/Slave mode.
- * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
- * @brief Disable the Master/Slave mode.
- * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
- * @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Configure the external trigger (ETR) input.
- * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an external trigger input.
- * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
- * SMCR ETPS LL_TIM_ConfigETR\n
- * SMCR ETF LL_TIM_ConfigETR
- * @param TIMx Timer instance
- * @param ETRPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
- * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
- * @param ETRPrescaler This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
- * @param ETRFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity,
- uint32_t ETRPrescaler,
- uint32_t ETRFilter) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF,
- ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
- * @brief Select the external trigger (ETR) input source.
- * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance supports ETR source selection.
- * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
- * @param TIMx Timer instance
- * @param ETRSource This parameter can be one of the following values:
- *
- * TIM1: any combination of ETR_RMP where
- *
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
- * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)
- *
- * TIM2: any combination of ETR_RMP where
- *
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
- * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
- *
- * TIM3: any combination of ETR_RMP where
- *
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
- * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
- *
- * TIM4: any combination of ETR_RMP where
- *
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
- * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)
- *
- * TIM5: any combination of ETR_RMP where (**)
- *
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
- * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)
- *
- * TIM8: any combination of ETR_RMP where
- *
- * . . ETR_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
- * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
- *
- * TIM20: any combination of ETR_RMP where (**)
- *
- * . . ETR_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
- * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)
- *
- * (*) Value not defined in all devices. \n
- * (**) Register not available in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx,
- uint32_t ETRSource) {
- MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
-}
-
-/**
- * @brief Enable SMS preload.
- * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the preload of SMS field in
- * SMCR register.
- * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
-}
-
-/**
- * @brief Disable SMS preload.
- * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the preload of SMS field in
- * SMCR register.
- * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
-}
-
-/**
- * @brief Indicate whether SMS preload is enabled.
- * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the preload of SMS field in
- * SMCR register.
- * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set the preload source of SMS.
- * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the preload of SMS field in
- * SMCR register.
- * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
- * @param TIMx Timer instance
- * @param PreloadSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_SMSPS_TIMUPDATE
- * @arg @ref LL_TIM_SMSPS_INDEX
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx,
- uint32_t PreloadSource) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
-}
-
-/**
- * @brief Get the preload source of SMS.
- * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the preload of SMS field in
- * SMCR register.
- * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_SMSPS_TIMUPDATE
- * @arg @ref LL_TIM_SMSPS_INDEX
- */
-__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Break_Function Break function configuration
- * @{
- */
-/**
- * @brief Enable the break function.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR BKE LL_TIM_EnableBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
- * @brief Disable the break function.
- * @rmtoll BDTR BKE LL_TIM_DisableBRK
- * @param TIMx Timer instance
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
- * @brief Configure the break input.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @note Bidirectional mode is only supported by advanced timer instances.
- * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance is an advanced-control timer.
- * @note In bidirectional mode (BKBID bit set), the Break input is configured
- * both in input mode and in open drain output mode. Any active Break event will
- * assert a low logic level on the Break input to indicate an internal
- * break event to external devices.
- * @note When bidirectional mode isn't supported, BreakAFMode must be set to
- * LL_TIM_BREAK_AFMODE_INPUT.
- * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
- * BDTR BKF LL_TIM_ConfigBRK\n
- * BDTR BKBID LL_TIM_ConfigBRK
- * @param TIMx Timer instance
- * @param BreakPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_POLARITY_LOW
- * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
- * @param BreakFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
- * @param BreakAFMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
- * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
- uint32_t BreakFilter,
- uint32_t BreakAFMode) {
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID,
- BreakPolarity | BreakFilter | BreakAFMode);
-}
-
-/**
- * @brief Disarm the break input (when it operates in bidirectional mode).
- * @note The break input can be disarmed only when it is configured in
- * bidirectional mode and when when MOE is reset.
- * @note Purpose is to be able to have the input voltage back to high-state,
- * whatever the time constant on the output .
- * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-/**
- * @brief Re-arm the break input (when it operates in bidirectional mode).
- * @note The Break input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-/**
- * @brief Enable the break 2 function.
- * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a second break input.
- * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-/**
- * @brief Disable the break 2 function.
- * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a second break input.
- * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-/**
- * @brief Configure the break 2 input.
- * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a second break input.
- * @note Bidirectional mode is only supported by advanced timer instances.
- * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance is an advanced-control timer.
- * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured
- * both in input mode and in open drain output mode. Any active Break event will
- * assert a low logic level on the Break 2 input to indicate an internal
- * break event to external devices.
- * @note When bidirectional mode isn't supported, Break2AFMode must be set to
- * LL_TIM_BREAK2_AFMODE_INPUT.
- * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
- * BDTR BK2F LL_TIM_ConfigBRK2\n
- * BDTR BK2BID LL_TIM_ConfigBRK2
- * @param TIMx Timer instance
- * @param Break2Polarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
- * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
- * @param Break2Filter This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
- * @param Break2AFMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
- * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx,
- uint32_t Break2Polarity,
- uint32_t Break2Filter,
- uint32_t Break2AFMode) {
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID,
- Break2Polarity | Break2Filter | Break2AFMode);
-}
-
-/**
- * @brief Disarm the break 2 input (when it operates in bidirectional mode).
- * @note The break 2 input can be disarmed only when it is configured in
- * bidirectional mode and when when MOE is reset.
- * @note Purpose is to be able to have the input voltage back to high-state,
- * whatever the time constant on the output.
- * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-/**
- * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
- * @note The Break 2 input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-/**
- * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run
- * modes.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
- * BDTR OSSR LL_TIM_SetOffStates
- * @param TIMx Timer instance
- * @param OffStateIdle This parameter can be one of the following values:
- * @arg @ref LL_TIM_OSSI_DISABLE
- * @arg @ref LL_TIM_OSSI_ENABLE
- * @param OffStateRun This parameter can be one of the following values:
- * @arg @ref LL_TIM_OSSR_DISABLE
- * @arg @ref LL_TIM_OSSR_ENABLE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx,
- uint32_t OffStateIdle,
- uint32_t OffStateRun) {
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR,
- OffStateIdle | OffStateRun);
-}
-
-/**
- * @brief Enable automatic output (MOE can be set by software or automatically
- * when a break input is active).
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
- * @brief Disable automatic output (MOE can be set only by software).
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
- * @brief Indicate whether automatic output is enabled.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
- * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs
- * by software and is reset in case of break or break2 event
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
- * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
- * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs
- * by software and is reset in case of break or break2 event.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
- * @brief Indicates whether outputs are enabled.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable the signals connected to the designated timer break input.
- * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance allows for break input selection.
- * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n
- * AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2NE LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n
- * AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
- * @param TIMx Timer instance
- * @param BreakInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_INPUT_BKIN
- * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
- *
- * (*) Value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx,
- uint32_t BreakInput,
- uint32_t Source) {
- __IO uint32_t *pReg =
- (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
- SET_BIT(*pReg, Source);
-}
-
-/**
- * @brief Disable the signals connected to the designated timer break input.
- * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance allows for break input selection.
- * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n
- * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n
- * AF2 BKINE LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP3E LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP4E LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP5E LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP6E LL_TIM_DisableBreakInputSource\n
- * AF2 BKCMP7E LL_TIM_DisableBreakInputSource
- * @param TIMx Timer instance
- * @param BreakInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_INPUT_BKIN
- * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
- *
- * (*) Value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx,
- uint32_t BreakInput,
- uint32_t Source) {
- __IO uint32_t *pReg =
- (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
- CLEAR_BIT(*pReg, Source);
-}
-
-/**
- * @brief Set the polarity of the break signal for the timer break input.
- * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance allows for break input selection.
- * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
- * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
- * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
- * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
- * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n
- * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
- * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
- * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
- * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n
- * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity
- * @param TIMx Timer instance
- * @param BreakInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_INPUT_BKIN
- * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
- * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_BKIN_POLARITY_LOW
- * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx,
- uint32_t BreakInput,
- uint32_t Source,
- uint32_t Polarity) {
- __IO uint32_t *pReg =
- (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
- MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE),
- (Polarity << TIM_POSITION_BRK_SOURCE));
-}
-/**
- * @brief Enable asymmetrical deadtime.
- * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance provides asymmetrical deadtime.
- * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
-}
-
-/**
- * @brief Disable asymmetrical dead-time.
- * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance provides asymmetrical deadtime.
- * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
-}
-
-/**
- * @brief Indicates whether asymmetrical deadtime is activated.
- * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance provides asymmetrical deadtime.
- * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set the falling edge dead-time delay (delay inserted between the
- * falling edge of the OCxREF signal and the rising edge of OCxN signals).
- * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
- * whether or not asymmetrical dead-time insertion feature is supported by a
- * timer instance.
- * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the
- * DeadTime parameter
- * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
- * been programmed (LOCK bits in TIMx_BDTR register).
- * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
- * @param TIMx Timer instance
- * @param DeadTime between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx,
- uint32_t DeadTime) {
- MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
-}
-
-/**
- * @brief Get the falling edge dead-time delay (delay inserted between the
- * falling edge of the OCxREF signal and the rising edge of OCxN signals).
- * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
- * whether or not asymmetrical dead-time insertion feature is supported by a
- * timer instance.
- * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
- * been programmed (LOCK bits in TIMx_BDTR register).
- * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
- * @param TIMx Timer instance
- * @retval Returned value can be between Min_Data=0 and Max_Data=255:
- */
-__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
-}
-
-/**
- * @brief Enable deadtime preload.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides deadtime preload.
- * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
-}
-
-/**
- * @brief Disable dead-time preload.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides deadtime preload.
- * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
-}
-
-/**
- * @brief Indicates whether deadtime preload is activated.
- * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides deadtime preload.
- * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
- * @{
- */
-/**
- * @brief Configures the timer DMA burst feature.
- * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance supports the DMA burst mode.
- * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
- * DCR DBA LL_TIM_ConfigDMABurst
- * @param TIMx Timer instance
- * @param DMABurstBaseAddress This parameter can be one of the following
- * values:
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
- * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
- * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
- * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
- * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
- * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
- * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
- * @param DMABurstLength This parameter can be one of the following values:
- * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
- * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx,
- uint32_t DMABurstBaseAddress,
- uint32_t DMABurstLength) {
- MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA),
- (DMABurstBaseAddress | DMABurstLength));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Encoder Encoder configuration
- * @{
- */
-
-/**
- * @brief Enable encoder index.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->ECR, TIM_ECR_IE);
-}
-
-/**
- * @brief Disable encoder index.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
-}
-
-/**
- * @brief Indicate whether encoder index is enabled.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
-}
-
-/**
- * @brief Set index direction
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
- * @param TIMx Timer instance
- * @param IndexDirection This parameter can be one of the following values:
- * @arg @ref LL_TIM_INDEX_UP_DOWN
- * @arg @ref LL_TIM_INDEX_UP
- * @arg @ref LL_TIM_INDEX_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx,
- uint32_t IndexDirection) {
- MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
-}
-
-/**
- * @brief Get actual index direction
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_INDEX_UP_DOWN
- * @arg @ref LL_TIM_INDEX_UP
- * @arg @ref LL_TIM_INDEX_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
-}
-
-/**
- * @brief Enable first index.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
-}
-
-/**
- * @brief Disable first index.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
-}
-
-/**
- * @brief Indicates whether first index is enabled.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set index positioning
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
- * @param TIMx Timer instance
- * @param IndexPositionning This parameter can be one of the following values:
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
- * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
- * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN
- * @arg @ref LL_TIM_INDEX_POSITION_UP
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx,
- uint32_t IndexPositionning) {
- MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
-}
-
-/**
- * @brief Get actual index positioning
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
- * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
- * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN
- * @arg @ref LL_TIM_INDEX_POSITION_UP
- */
-__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx) {
- return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
-}
-
-/**
- * @brief Configure encoder index.
- * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an index input.
- * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
- * ECR FIDX LL_TIM_ConfigIDX\n
- * ECR IPOS LL_TIM_ConfigIDX
- * @param TIMx Timer instance
- * @param Configuration This parameter must be a combination of all the
- * following values:
- * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref
- * LL_TIM_INDEX_UP_DOWN
- * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
- * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref
- * LL_TIM_INDEX_POSITION_UP
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx,
- uint32_t Configuration) {
- MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS,
- Configuration);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
- * @{
- */
-/**
- * @brief Remap TIM inputs (input channel, internal/external triggers).
- * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
- * a some timer inputs can be remapped.
- * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
- * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
- * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
- * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
- * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
- * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
- * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
- * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
- * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
- * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
- * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
- * TIM20_TISEL TI1SEL LL_TIM_SetRemap
- * @param TIMx Timer instance
- * @param Remap Remap param depends on the TIMx. Description available only
- * in CHM version of the User Manual (not in .pdf).
- * Otherwise see Reference Manual description of TISEL registers.
- *
- * Below description summarizes "Timer Instance" and "Remap" param
- * combinations:
- *
- * TIM1: one of the following values
- *
- * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
- * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
- * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
- * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
- *
- * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
- *
- * . . TI1_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
- * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
- * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
- * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
- * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
- *
- * . . TI2_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
- * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
- * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
- * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
- * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
- * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
- *
- * . . TI3_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
- * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
- *
- * . . TI4_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
- * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
- * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
- *
- * TIM3: any combination of TI1_RMP and TI2_RMP where
- *
- * . . TI1_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
- *
- * . . TI2_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
- *
- * . . TI3_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
- * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
- *
- * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
- *
- * . . TI1_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
- *
- * . . TI2_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
- *
- * . . TI3_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
- * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
- *
- * . . TI4_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
- * @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
- *
- * TIM5: any combination of TI1_RMP and TI2_RMP where (**)
- *
- * . . TI1_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*)
- *
- * . . TI2_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
- *
- * TIM8: one of the following values
- *
- * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
- * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
- * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
- * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
- *
- * TIM15: any combination of TI1_RMP and TI2_RMP where
- *
- * . . TI1_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
- * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
- * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
- * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
- *
- * . . TI2_RMP can be one of the following values
- * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
- * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
- * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
- * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
- *
- * TIM16: one of the following values
- *
- * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
- * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
- * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
- * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
- * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
- * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
- *
- * TIM17: one of the following values
- *
- * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
- * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
- * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
- * @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
- * @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
- * @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
- *
- * TIM20: one of the following values (**)
- *
- * @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*)
- * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
- * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
- * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
- * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
- *
- * (*) Value not defined in all devices. \n
- * (**) Register not available in all devices.
- *
- *
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) {
- MODIFY_REG(TIMx->TISEL,
- (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL |
- TIM_TISEL_TI4SEL),
- Remap);
-}
-
-/**
- * @brief Enable request for HSE/32 clock used for TISEL remap.
- * @note Only TIM16 and TIM17 support HSE/32 remap
- * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
-}
-
-/**
- * @brief Disable request for HSE/32 clock used for TISEL remap.
- * @note Only TIM16 and TIM17 support HSE/32 remap
- * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
-}
-
-/**
- * @brief Indicate whether request for HSE/32 clock is enabled.
- * @note Only TIM16 and TIM17 support HSE/32 remap
- * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
- * @{
- */
-/**
- * @brief Set the OCREF clear input source
- * @note The OCxREF signal of a given channel can be cleared when a high level
- * is applied on the OCREF_CLR_INPUT
- * @note This function can only be used in Output compare and PWM modes.
- * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can configure OCREF clear input source.
- * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
- * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
- * @param TIMx Timer instance
- * @param OCRefClearInputSource This parameter can be one of the following
- * values:
- * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
- * @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
- *
- * (*) Value not defined in all devices. \n
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(
- TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) {
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
- ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >>
- OCREF_CLEAR_SELECT_Pos)
- << TIM_SMCR_OCCS_Pos);
- MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
- * @{
- */
-/**
- * @brief Clear the update interrupt flag (UIF).
- * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
- * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt
- * is pending).
- * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
- * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set
- * (Capture/Compare 1 interrupt is pending).
- * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
- * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set
- * (Capture/Compare 2 interrupt is pending).
- * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
- * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set
- * (Capture/Compare 3 interrupt is pending).
- * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
- * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set
- * (Capture/Compare 4 interrupt is pending).
- * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
- * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set
- * (Capture/Compare 5 interrupt is pending).
- * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
- * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set
- * (Capture/Compare 6 interrupt is pending).
- * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the commutation interrupt flag (COMIF).
- * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
-}
-
-/**
- * @brief Indicate whether commutation interrupt flag (COMIF) is set
- * (commutation interrupt is pending).
- * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the trigger interrupt flag (TIF).
- * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
- * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger
- * interrupt is pending).
- * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the break interrupt flag (BIF).
- * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
-}
-
-/**
- * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt
- * is pending).
- * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the break 2 interrupt flag (B2IF).
- * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
-}
-
-/**
- * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2
- * interrupt is pending).
- * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
- * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag
- * (CC1OF) is set (Capture/Compare 1 interrupt is pending).
- * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
- * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag
- * (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
- * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
- * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag
- * (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
- * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
- * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag
- * (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
- * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the system break interrupt flag (SBIF).
- * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
-}
-
-/**
- * @brief Indicate whether system break interrupt flag (SBIF) is set (system
- * break interrupt is pending).
- * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the transition error interrupt flag (TERRF).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
-}
-
-/**
- * @brief Indicate whether transition error interrupt flag (TERRF) is set
- * (transition error interrupt is pending).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the index error interrupt flag (IERRF).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
-}
-
-/**
- * @brief Indicate whether index error interrupt flag (IERRF) is set (index
- * error interrupt is pending).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the direction change interrupt flag (DIRF).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
-}
-
-/**
- * @brief Indicate whether direction change interrupt flag (DIRF) is set
- * (direction change interrupt is pending).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear the index interrupt flag (IDXF).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) {
- WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
-}
-
-/**
- * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt
- * is pending).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
- * @{
- */
-/**
- * @brief Enable update interrupt (UIE).
- * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
- * @brief Disable update interrupt (UIE).
- * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
- * @brief Indicates whether the update interrupt (UIE) is enabled.
- * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 1 interrupt (CC1IE).
- * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
- * @brief Disable capture/compare 1 interrupt (CC1IE).
- * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
- * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 2 interrupt (CC2IE).
- * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
- * @brief Disable capture/compare 2 interrupt (CC2IE).
- * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
- * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 3 interrupt (CC3IE).
- * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
- * @brief Disable capture/compare 3 interrupt (CC3IE).
- * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
- * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 4 interrupt (CC4IE).
- * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
- * @brief Disable capture/compare 4 interrupt (CC4IE).
- * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
- * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable commutation interrupt (COMIE).
- * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
- * @brief Disable commutation interrupt (COMIE).
- * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
- * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
- * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable trigger interrupt (TIE).
- * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
- * @brief Disable trigger interrupt (TIE).
- * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
- * @brief Indicates whether the trigger interrupt (TIE) is enabled.
- * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable break interrupt (BIE).
- * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
- * @brief Disable break interrupt (BIE).
- * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
- * @brief Indicates whether the break interrupt (BIE) is enabled.
- * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable transition error interrupt (TERRIE).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
-}
-
-/**
- * @brief Disable transition error interrupt (TERRIE).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
-}
-
-/**
- * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable index error interrupt (IERRIE).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
-}
-
-/**
- * @brief Disable index error interrupt (IERRIE).
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
-}
-
-/**
- * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
- * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance provides encoder error management.
- * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable direction change interrupt (DIRIE).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
-}
-
-/**
- * @brief Disable direction change interrupt (DIRIE).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
-}
-
-/**
- * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable index interrupt (IDXIE).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
-}
-
-/**
- * @brief Disable index interrupt (IDXIE).
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
-}
-
-/**
- * @brief Indicates whether the index interrupt (IDXIE) is enabled.
- * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
- * to check whether or not a timer instance provides encoder interrupt
- * management.
- * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA Management
- * @{
- */
-/**
- * @brief Enable update DMA request (UDE).
- * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
- * @brief Disable update DMA request (UDE).
- * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
- * @brief Indicates whether the update DMA request (UDE) is enabled.
- * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 1 DMA request (CC1DE).
- * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
- * @brief Disable capture/compare 1 DMA request (CC1DE).
- * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is
- * enabled.
- * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 2 DMA request (CC2DE).
- * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
- * @brief Disable capture/compare 2 DMA request (CC2DE).
- * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is
- * enabled.
- * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 3 DMA request (CC3DE).
- * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
- * @brief Disable capture/compare 3 DMA request (CC3DE).
- * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is
- * enabled.
- * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable capture/compare 4 DMA request (CC4DE).
- * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
- * @brief Disable capture/compare 4 DMA request (CC4DE).
- * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is
- * enabled.
- * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable commutation DMA request (COMDE).
- * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
- * @brief Disable commutation DMA request (COMDE).
- * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
- * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
- * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable trigger interrupt (TDE).
- * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
- * @brief Disable trigger interrupt (TDE).
- * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) {
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
- * @brief Indicates whether the trigger interrupt (TDE) is enabled.
- * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) {
- return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
- * @{
- */
-/**
- * @brief Generate an update event.
- * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
- * @brief Generate Capture/Compare 1 event.
- * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
- * @brief Generate Capture/Compare 2 event.
- * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
- * @brief Generate Capture/Compare 3 event.
- * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
- * @brief Generate Capture/Compare 4 event.
- * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
- * @brief Generate commutation event.
- * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_COMG);
-}
-
-/**
- * @brief Generate trigger event.
- * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
- * @brief Generate break event.
- * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_BG);
-}
-
-/**
- * @brief Generate break 2 event.
- * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) {
- SET_BIT(TIMx->EGR, TIM_EGR_B2G);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
- * @{
- */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel,
- LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel,
- LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(
- LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(
- TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-void LL_TIM_HALLSENSOR_StructInit(
- LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(
- TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx,
- LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || \
- TIM15 || TIM16 || TIM17 || TIM20 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G4xx_LL_TIM_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_TIM_H
+#define __STM32G4xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(TIM1) || defined(TIM2) || defined(TIM3) || defined(TIM4) || \
+ defined(TIM5) || defined(TIM6) || defined(TIM7) || defined(TIM8) || \
+ defined(TIM15) || defined(TIM16) || defined(TIM17) || defined(TIM20)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] = {
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U, /* 6: TIMx_CH4 */
+ 0x04U, /* 7: TIMx_CH4N */
+ 0x38U, /* 8: TIMx_CH5 */
+ 0x38U /* 9: TIMx_CH6 */
+
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] = {
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U, /* 6: OC4M, OC4FE, OC4PE */
+ 0U, /* 7: - NA */
+ 0U, /* 8: OC5M, OC5FE, OC5PE */
+ 8U /* 9: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] = {
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U, /* 6: CC4S, IC4PSC, IC4F */
+ 0U, /* 7: - NA */
+ 0U, /* 8: - NA */
+ 0U /* 9: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] = {
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U, /* 6: CC4P */
+ 14U, /* 7: CC4NP */
+ 16U, /* 8: CC5P */
+ 20U /* 9: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] = {
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U, /* 6: OIS4 */
+ 7U, /* 7: OIS4N */
+ 8U, /* 8: OIS5 */
+ 10U /* 9: OIS6 */
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register
+ */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+/**
+@endcond
+ */
+
+#define OCREF_CLEAR_SELECT_Pos (28U)
+#define OCREF_CLEAR_SELECT_Msk \
+ (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval none
+ */
+#define TIM_GET_CHANNEL_INDEX(__CHANNEL__) \
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U \
+ : ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U \
+ : 9U)
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ ? ((uint64_t)1000000000000U / (__TIMCLK__)) \
+ : ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ ? ((uint64_t)1000000000000U / ((__TIMCLK__) >> 1U)) \
+ : ((uint64_t)1000000000000U / ((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct {
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM
+ clock. This parameter can be a number between
+ Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref
+ TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into
+ the active Auto-Reload Register at the next update
+ event. This parameter must be a number between
+ Min_Data=0x0000 and Max_Data=0xFFFF. Some timer
+ instances may support 32 bits counters. In that case
+ this parameter must be a number between 0x0000 and
+ 0xFFFFFFFF.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref
+ TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_SetClockDivision().*/
+
+ uint32_t
+ RepetitionCounter; /*!< Specifies the repetition counter value. Each time
+ the RCR downcounter reaches zero, an update event is
+ generated and counting restarts from the RCR value
+ (N). This means in PWM mode that (N+1) corresponds
+ to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in
+ center-aligned mode GP timers: this parameter must
+ be a number between Min_Data = 0x00 and Max_Data =
+ 0xFF. Advanced timers: this parameter must be a
+ number between Min_Data = 0x0000 and Max_Data =
+ 0xFFFF.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct {
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t
+ OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary
+ functions
+ @ref LL_TIM_CC_EnableChannel() or @ref
+ LL_TIM_CC_DisableChannel().*/
+
+ uint32_t
+ OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary
+ functions
+ @ref LL_TIM_CC_EnableChannel() or @ref
+ LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the
+ Capture Compare Register. This parameter can be a
+ number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using
+ unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref
+ TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref
+ TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during
+ Idle state. This parameter can be a value of @ref
+ TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during
+ Idle state. This parameter can be a value of @ref
+ TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct {
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref
+ TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref
+ TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t
+ ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t
+ ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct {
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref
+ TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref
+ TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref
+ TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t
+ IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t
+ IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref
+ TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref
+ TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t
+ IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t
+ IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct {
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref
+ TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter
+ period longer than the time interval between 2
+ consecutive changes on the Hall inputs. This
+ parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of
+ @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into
+ the Capture Compare Register. A positive pulse
+ (TRGO event) is generated with a programmable
+ delay every time a change occurs on the Hall
+ inputs. This parameter can be a number between
+ Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct {
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as
+ LOCK level 2 has been programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as
+ LOCK level 2 has been programmed. */
+
+ uint32_t
+ LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the
+ reset. Once the TIMx_BDTR register has been written, their
+ content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and
+ the switching-on of the outputs. This parameter can be a
+ number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as
+ LOCK level 1, 2 or 3 has been programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or
+ not. This parameter can be a value of @ref
+ TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using
+ unitary functions
+ @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as
+ LOCK level 1 has been programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref
+ TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long
+ as LOCK level 1 has been programmed. */
+
+ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
+ This parameter can be a value of @ref
+ TIM_LL_EC_BREAK_FILTER
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as
+ LOCK level 1 has been programmed. */
+
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break
+ input. This parameter can be a value of @ref
+ TIM_LL_EC_BREAK_AFMODE
+
+ This feature can be modified afterwards using
+ unitary functions
+ @ref LL_TIM_ConfigBRK()
+
+ @note Bidirectional break input is only supported by
+ advanced timers instances.
+
+ @note This bit-field can not be modified as long as
+ LOCK level 1 has been programmed. */
+
+ uint32_t
+ Break2State; /*!< Specifies whether the TIM Break2 input is enabled or
+ not. This parameter can be a value of @ref
+ TIM_LL_EC_BREAK2_ENABLE
+
+ This feature can be modified afterwards using unitary
+ functions
+ @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+ @note This bit-field can not be modified as long as LOCK
+ level 1 has been programmed. */
+
+ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
+ This parameter can be a value of @ref
+ TIM_LL_EC_BREAK2_POLARITY
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long
+ as LOCK level 1 has been programmed. */
+
+ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
+ This parameter can be a value of @ref
+ TIM_LL_EC_BREAK2_FILTER
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as
+ LOCK level 1 has been programmed. */
+
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the
+ break2 input. This parameter can be a value of @ref
+ TIM_LL_EC_BREAK2_AFMODE
+
+ This feature can be modified afterwards using
+ unitary functions
+ @ref LL_TIM_ConfigBRK2()
+
+ @note Bidirectional break input is only supported
+ by advanced timers instances.
+
+ @note This bit-field can not be modified as long as
+ LOCK level 1 has been programmed. */
+
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output
+ feature is enabled or not. This parameter can be
+ a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using
+ unitary functions
+ @ref LL_TIM_EnableAutomaticOutput() or @ref
+ LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as
+ long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF \
+ TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag \
+ */
+#define LL_TIM_SR_CC2OF \
+ TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag \
+ */
+#define LL_TIM_SR_CC3OF \
+ TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag \
+ */
+#define LL_TIM_SR_CC4OF \
+ TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag \
+ */
+#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
+#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
+#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
+#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
+#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ * @{
+ */
+#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE \
+ 0x00000000U /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE \
+ TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next \
+ update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and
+ * LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE \
+ TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE \
+ TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE \
+ TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE \
+ TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
+#define LL_TIM_DIER_DIRIE \
+ TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
+#define LL_TIM_DIER_IERRIE \
+ TIM_DIER_IERRIE /*!< Index Error interrupt enable \
+ */
+#define LL_TIM_DIER_TERRIE \
+ TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR \
+ 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update \
+ generation through the slave mode controller generates an \
+ update request */
+#define LL_TIM_UPDATESOURCE_COUNTER \
+ TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE \
+ TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE \
+ 0x00000000U /*!< Counter is not stopped at update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN \
+ TIM_CR1_DIR /*!< Counter used as downcounter \
+ */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN \
+ TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output \
+ compare interrupt flags of output channels are set only \
+ when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP \
+ TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output \
+ compare interrupt flags of output channels are set only \
+ when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN \
+ TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output \
+ compare interrupt flags of output channels are set only when \
+ the counter is counting up or down. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ * @{
+ */
+#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ * @{
+ */
+#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN \
+ TIM_CR1_DIR /*!< Timer counter counts down */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
+ * @{
+ */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY \
+ 0x00000000U /*!< Capture/compare control bits are updated by setting the \
+ COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI \
+ TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the \
+ COMG bit or when a rising edge occurs on trigger input \
+ (TRGI) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ * @{
+ */
+#define LL_TIM_CCDMAREQUEST_CC \
+ 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE \
+ TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ * @{
+ */
+#define LL_TIM_LOCKLEVEL_OFF \
+ 0x00000000U /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+ * @{
+ */
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N \
+ TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N \
+ TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N \
+ TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH4N \
+ TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
+#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ * @{
+ */
+#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE \
+ TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+ */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ * @{
+ */
+#define LL_TIM_OCMODE_FROZEN \
+ 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy \
+ and the counter TIMx_CNT has no effect on the output channel \
+ level */
+#define LL_TIM_OCMODE_ACTIVE \
+ TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE \
+ TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE \
+ (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE \
+ TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE \
+ (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1 \
+ (TIM_CCMR1_OC1M_2 | \
+ TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as \
+ TIMx_CNT<TIMx_CCRy else inactive. In downcounting, \
+ channel y is inactive as long as TIMx_CNT>TIMx_CCRy \
+ else active.*/
+#define LL_TIM_OCMODE_PWM2 \
+ (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | \
+ TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as \
+ TIMx_CNT<TIMx_CCRy else active. In downcounting, \
+ channel y is active as long as TIMx_CNT>TIMx_CCRy else \
+ inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1 \
+ TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | \
+ TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | \
+ TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 \
+ (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_PULSE_ON_COMPARE \
+ (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
+#define LL_TIM_OCMODE_DIRECTION_OUTPUT \
+ (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | \
+ TIM_CCMR2_OC3M_0) /*!<Direction output mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ * @{
+ */
+#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ * @{
+ */
+#define LL_TIM_OCIDLESTATE_LOW \
+ 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH \
+ TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+ * @{
+ */
+#define LL_TIM_GROUPCH5_NONE \
+ 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC \
+ TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC \
+ TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC \
+ TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+ * @{
+ */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI \
+ (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI \
+ (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC \
+ (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+ * @{
+ */
+#define LL_TIM_ICPSC_DIV1 \
+ 0x00000000U /*!< No prescaler, capture is done each time an edge is detected \
+ on the capture input */
+#define LL_TIM_ICPSC_DIV2 \
+ (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4 \
+ (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8 \
+ (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+ * @{
+ */
+#define LL_TIM_IC_FILTER_FDIV1 \
+ 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2 \
+ (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4 \
+ (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8 \
+ ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 \
+ */
+#define LL_TIM_IC_FILTER_FDIV2_N6 \
+ (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8 \
+ ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6 \
+ ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8 \
+ ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) \
+ << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6 \
+ (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8 \
+ ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5 \
+ ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 \
+ */
+#define LL_TIM_IC_FILTER_FDIV16_N6 \
+ ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) \
+ << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8 \
+ ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 \
+ */
+#define LL_TIM_IC_FILTER_FDIV32_N5 \
+ ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) \
+ << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6 \
+ ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) \
+ << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8 \
+ (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+ * @{
+ */
+#define LL_TIM_IC_POLARITY_RISING \
+ 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is \
+ not inverted */
+#define LL_TIM_IC_POLARITY_FALLING \
+ TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 \
+ is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE \
+ (TIM_CCER_CC1P | \
+ TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and \
+ falling edges, TIxFP1 is not inverted */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+ * @{
+ */
+#define LL_TIM_CLOCKSOURCE_INTERNAL \
+ 0x00000000U /*!< The timer is clocked by the internal clock provided from \
+ the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 \
+ (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a \
+ selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2 \
+ TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the \
+ external trigger input ETR */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+ * @{
+ */
+#define LL_TIM_ENCODERMODE_X2_TI1 \
+ TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts \
+ up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 \
+ TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts \
+ up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 \
+ (TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts \
+ up/down on both TI1FP1 and TI2FP2 edges depending on the \
+ level of the other input */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 \
+ (TIM_SMCR_SMS_3 | \
+ TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 \
+ edge sensitivity is set by CC2P */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 \
+ (TIM_SMCR_SMS_3 | \
+ TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
+ TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and \
+ TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define LL_TIM_ENCODERMODE_X1_TI1 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | \
+ TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 \
+ edges only, edge sensitivity is set by CC1P */
+#define LL_TIM_ENCODERMODE_X1_TI2 \
+ (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | \
+ TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 \
+ edges only, edge sensitivity is set by CC1P */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+ * @{
+ */
+#define LL_TIM_TRGO_RESET \
+ 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output \
+ */
+#define LL_TIM_TRGO_ENABLE \
+ TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output \
+ */
+#define LL_TIM_TRGO_UPDATE \
+ TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF \
+ (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used \
+ as trigger output */
+#define LL_TIM_TRGO_OC1REF \
+ TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF \
+ (TIM_CR2_MMS_2 | \
+ TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF \
+ (TIM_CR2_MMS_2 | \
+ TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF \
+ (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | \
+ TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+#define LL_TIM_TRGO_ENCODERCLK \
+ TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+ * @{
+ */
+#define LL_TIM_TRGO2_RESET \
+ 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output \
+ 2 */
+#define LL_TIM_TRGO2_ENABLE \
+ TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output \
+ 2 */
+#define LL_TIM_TRGO2_UPDATE \
+ TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F \
+ (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is \
+ used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1 \
+ TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2 \
+ (TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3 \
+ (TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4 \
+ (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
+ TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5 \
+ TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6 \
+ (TIM_CR2_MMS2_3 | \
+ TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are \
+ used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | \
+ TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger \
+ output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are \
+ used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as \
+ trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | \
+ TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger \
+ output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING \
+ (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | \
+ TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as \
+ trigger output 2 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+ * @{
+ */
+#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET \
+ TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input \
+ (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED \
+ (TIM_SMCR_SMS_2 | \
+ TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the \
+ trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER \
+ (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at \
+ a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER \
+ TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the \
+ selected trigger input (TRGI) reinitializes the counter, \
+ generates an update of the registers and starts the \
+ counter */
+#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET \
+ (TIM_SMCR_SMS_3 | \
+ TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is \
+ enabled when the trigger input (TRGI) is high. The \
+ counter stops and is reset) as soon as the trigger \
+ becomes low.Both startand stop of the counter are \
+ controlled. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
+ * @{
+ */
+#define LL_TIM_SMSPS_TIMUPDATE \
+ 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update \
+ event */
+#define LL_TIM_SMSPS_INDEX \
+ TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+ * @{
+ */
+#define LL_TIM_TS_ITR0 \
+ 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 \
+ TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 \
+ TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 \
+ (TIM_SMCR_TS_0 | \
+ TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_ITR4 \
+ TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
+#define LL_TIM_TS_ITR5 \
+ (TIM_SMCR_TS_3 | \
+ TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
+#define LL_TIM_TS_ITR6 \
+ (TIM_SMCR_TS_3 | \
+ TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
+#define LL_TIM_TS_ITR7 \
+ (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | \
+ TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
+#define LL_TIM_TS_ITR8 \
+ (TIM_SMCR_TS_3 | \
+ TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
+#define LL_TIM_TS_ITR9 \
+ (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | \
+ TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
+#define LL_TIM_TS_ITR10 \
+ (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | \
+ TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
+#define LL_TIM_TS_ITR11 \
+ (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | \
+ TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED \
+ TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 \
+ (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used \
+ as trigger input */
+#define LL_TIM_TS_TI2FP2 \
+ (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used \
+ as trigger input */
+#define LL_TIM_TS_ETRF \
+ (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | \
+ TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger \
+ input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+ * @{
+ */
+#define LL_TIM_ETR_POLARITY_NONINVERTED \
+ 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED \
+ TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+ * @{
+ */
+#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2 \
+ TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4 \
+ TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8 \
+ TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+ * @{
+ */
+#define LL_TIM_ETR_FILTER_FDIV1 \
+ 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2 \
+ TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 \
+ */
+#define LL_TIM_ETR_FILTER_FDIV1_N4 \
+ TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 \
+ */
+#define LL_TIM_ETR_FILTER_FDIV1_N8 \
+ (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6 \
+ TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 \
+ */
+#define LL_TIM_ETR_FILTER_FDIV2_N8 \
+ (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6 \
+ (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8 \
+ (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | \
+ TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 \
+ TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 \
+ */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 \
+ (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 \
+ (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 \
+ (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | \
+ TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 \
+ (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5 \
+ (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | \
+ TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6 \
+ (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | \
+ TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8 \
+ TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
+ * @{
+ */
+#define LL_TIM_TIM1_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM1_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM1_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM1_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM1_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 \
+ TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
+#if defined(ADC4)
+#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
+#endif /* ADC4 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
+ * @{
+ */
+#define LL_TIM_TIM2_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM2_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM2_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM2_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM2_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
+#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
+#if defined(TIM5)
+#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+#define LL_TIM_TIM2_ETRSOURCE_LSE \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
+ * @{
+ */
+#define LL_TIM_TIM3_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM3_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM3_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM3_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM3_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM3_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM3_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM3_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
+ * @{
+ */
+#define LL_TIM_TIM4_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM4_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM4_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM4_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM4_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
+#if defined(TIM5)
+#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+/**
+ * @}
+ */
+
+#if defined(TIM5)
+/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
+ * @{
+ */
+#define LL_TIM_TIM5_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM5_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM5_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM5_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM5_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR \
+ TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR \
+ (TIM1_AF1_ETRSEL_3 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
+/**
+ * @}
+ */
+#endif /* TIM5 */
+
+/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
+ * @{
+ */
+#define LL_TIM_TIM8_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM8_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM8_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM8_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM8_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 \
+ TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
+#if defined(ADC3)
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+/**
+ * @}
+ */
+
+#if defined(TIM20)
+/** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
+ * @{
+ */
+#define LL_TIM_TIM20_ETRSOURCE_GPIO \
+ 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM20_ETRSOURCE_COMP1 \
+ TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM20_ETRSOURCE_COMP2 \
+ TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM20_ETRSOURCE_COMP3 \
+ (TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM20_ETRSOURCE_COMP4 \
+ TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM20_ETRSOURCE_COMP5 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM20_ETRSOURCE_COMP6 \
+ (TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM20_ETRSOURCE_COMP7 \
+ (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#if defined(ADC3)
+#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 \
+ TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+#if defined(ADC5)
+#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 \
+ (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | \
+ TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
+#endif /* ADC5 */
+/**
+ * @}
+ */
+#endif /* TIM20 */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+ * @{
+ */
+#define LL_TIM_BREAK_POLARITY_LOW \
+ 0x00000000U /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH \
+ TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+ * @{
+ */
+#define LL_TIM_BREAK_FILTER_FDIV1 \
+ 0x00000000U /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2 \
+ 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4 \
+ 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8 \
+ 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5 \
+ 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6 \
+ 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8 \
+ 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5 \
+ 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6 \
+ 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 \
+ */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8 \
+ 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+ * @{
+ */
+#define LL_TIM_BREAK2_POLARITY_LOW \
+ 0x00000000U /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH \
+ TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+ * @{
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV1 \
+ 0x00000000U /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2 \
+ 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4 \
+ 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8 \
+ 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6 \
+ 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8 \
+ 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6 \
+ 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8 \
+ 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6 \
+ 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8 \
+ 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 \
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5 \
+ 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6 \
+ 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8 \
+ 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5 \
+ 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6 \
+ 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8 \
+ 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+ * @{
+ */
+#define LL_TIM_OSSI_DISABLE \
+ 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE \
+ TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with \
+ their inactive level then forced to their idle level after \
+ the deadtime */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+ * @{
+ */
+#define LL_TIM_OSSR_DISABLE \
+ 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE \
+ TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their \
+ inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+ * @{
+ */
+#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+ * @{
+ */
+#define LL_TIM_BKIN_SOURCE_BKIN \
+ TIM1_AF1_BKINE /*!< BKIN input from AF controller */
+#define LL_TIM_BKIN_SOURCE_BKCOMP1 \
+ TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP2 \
+ TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP3 \
+ TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP4 \
+ TIM1_AF1_BKCMP4E /*!< internal signal: COMP4 output */
+#if defined(COMP5)
+#define LL_TIM_BKIN_SOURCE_BKCOMP5 \
+ TIM1_AF1_BKCMP5E /*!< internal signal: COMP5 output */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_BKIN_SOURCE_BKCOMP6 \
+ TIM1_AF1_BKCMP6E /*!< internal signal: COMP6 output */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_BKIN_SOURCE_BKCOMP7 \
+ TIM1_AF1_BKCMP7E /*!< internal signal: COMP7 output */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+ * @{
+ */
+#define LL_TIM_BKIN_POLARITY_LOW \
+ TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH \
+ 0x00000000U /*!< BRK BKIN input is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+ * @{
+ */
+#define LL_TIM_BREAK_AFMODE_INPUT \
+ 0x00000000U /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL \
+ TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+ * @{
+ */
+#define LL_TIM_BREAK2_AFMODE_INPUT \
+ 0x00000000U /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL \
+ TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
+/**
+ * @}
+ */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_ReArmBRK(_PARAM_)
+#define LL_TIM_ReArmBRK2(_PARAM_)
+/**
+@endcond
+ */
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+ * @{
+ */
+#define LL_TIM_DMABURST_BASEADDR_CR1 \
+ 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2 \
+ TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_SMCR \
+ TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_DIER \
+ (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR \
+ TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR \
+ (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1 \
+ (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2 \
+ (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | \
+ TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER \
+ TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_CNT \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | \
+ TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_RCR \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1 \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | \
+ TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2 \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | \
+ TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3 \
+ (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | \
+ TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4 \
+ TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_BDTR \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5 \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6 \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | \
+ TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3 \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DTR2 \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | \
+ TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_ECR \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | \
+ TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_TISEL \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | \
+ TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA \
+ burst */
+#define LL_TIM_DMABURST_BASEADDR_AF1 \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base \
+ address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2 \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | \
+ TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst \
+ */
+#define LL_TIM_DMABURST_BASEADDR_OR \
+ (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | \
+ TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+ * @{
+ */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER \
+ 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst \
+ base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS \
+ TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS \
+ TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS \
+ (TIM_DCR_DBL_1 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS \
+ TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS \
+ (TIM_DCR_DBL_2 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS \
+ (TIM_DCR_DBL_2 | \
+ TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS \
+ (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS \
+ TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS \
+ (TIM_DCR_DBL_3 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS \
+ (TIM_DCR_DBL_3 | \
+ TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS \
+ (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS \
+ (TIM_DCR_DBL_3 | \
+ TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS \
+ (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS \
+ (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | \
+ TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS \
+ (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS \
+ TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS \
+ (TIM_DCR_DBL_4 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_19TRANSFERS \
+ (TIM_DCR_DBL_4 | \
+ TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_20TRANSFERS \
+ (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_21TRANSFERS \
+ (TIM_DCR_DBL_4 | \
+ TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_22TRANSFERS \
+ (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_23TRANSFERS \
+ (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | \
+ TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_24TRANSFERS \
+ (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_25TRANSFERS \
+ (TIM_DCR_DBL_4 | \
+ TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA \
+ burst base address */
+#define LL_TIM_DMABURST_LENGTH_26TRANSFERS \
+ (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | \
+ TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA \
+ burst base address */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM1_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
+#define LL_TIM_TIM1_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM1_TI1_RMP_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM1_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM1_TI1_RMP_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM2_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
+#define LL_TIM_TIM2_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI1_RMP_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM2_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM2_TI1_RMP_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM2_TI1_RMP_COMP5 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
+ * @{
+ */
+#define LL_TIM_TIM2_TI2_RMP_GPIO \
+ 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
+#define LL_TIM_TIM2_TI2_RMP_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI2_RMP_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM2_TI2_RMP_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM2_TI2_RMP_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
+#if defined(COMP6)
+#define LL_TIM_TIM2_TI2_RMP_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
+ * @{
+ */
+#define LL_TIM_TIM2_TI3_RMP_GPIO \
+ 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
+#define LL_TIM_TIM2_TI3_RMP_COMP4 \
+ TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
+ * @{
+ */
+#define LL_TIM_TIM2_TI4_RMP_GPIO \
+ 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP1 \
+ TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP2 \
+ TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM3_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM3_TI1_RMP_COMP5 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM3_TI1_RMP_COMP6 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM3_TI1_RMP_COMP7 \
+ (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
+ * @{
+ */
+#define LL_TIM_TIM3_TI2_RMP_GPIO \
+ 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
+#define LL_TIM_TIM3_TI2_RMP_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM3_TI2_RMP_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM3_TI2_RMP_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM3_TI2_RMP_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM3_TI2_RMP_COMP5 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM3_TI2_RMP_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM3_TI2_RMP_COMP7 \
+ (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
+ * @{
+ */
+#define LL_TIM_TIM3_TI3_RMP_GPIO \
+ 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
+#define LL_TIM_TIM3_TI3_RMP_COMP3 \
+ TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM4_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
+#define LL_TIM_TIM4_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM4_TI1_RMP_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM4_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM4_TI1_RMP_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM4_TI1_RMP_COMP5 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM4_TI1_RMP_COMP6 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM4_TI1_RMP_COMP7 \
+ (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
+ * @{
+ */
+#define LL_TIM_TIM4_TI2_RMP_GPIO \
+ 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
+#define LL_TIM_TIM4_TI2_RMP_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM4_TI2_RMP_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM4_TI2_RMP_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM4_TI2_RMP_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM4_TI2_RMP_COMP5 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM4_TI2_RMP_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM4_TI2_RMP_COMP7 \
+ (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
+ * @{
+ */
+#define LL_TIM_TIM4_TI3_RMP_GPIO \
+ 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
+#if defined(COMP5)
+#define LL_TIM_TIM4_TI3_RMP_COMP5 \
+ TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
+#endif /* COMP5 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM4_TI4_RMP TIM4 Timer Input Ch4 Remap
+ * @{
+ */
+#define LL_TIM_TIM4_TI4_RMP_GPIO \
+ 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
+#if defined(COMP6)
+#define LL_TIM_TIM4_TI4_RMP_COMP6 \
+ TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
+#endif /* COMP6 */
+/**
+ * @}
+ */
+
+#if defined(TIM5)
+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM5_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
+#define LL_TIM_TIM5_TI1_RMP_LSI \
+ TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
+#define LL_TIM_TIM5_TI1_RMP_LSE \
+ TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
+#define LL_TIM_TIM5_TI1_RMP_RTC_WK \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM5_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM5_TI1_RMP_COMP2 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM5_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM5_TI1_RMP_COMP4 \
+ (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM5_TI1_RMP_COMP5 \
+ TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM5_TI1_RMP_COMP6 \
+ (TIM_TISEL_TI1SEL_3 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM5_TI1_RMP_COMP7 \
+ (TIM_TISEL_TI1SEL_3 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 Timer Input Ch2 Remap
+ * @{
+ */
+#define LL_TIM_TIM5_TI2_RMP_GPIO \
+ 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
+#define LL_TIM_TIM5_TI2_RMP_COMP1 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM5_TI2_RMP_COMP2 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM5_TI2_RMP_COMP3 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM5_TI2_RMP_COMP4 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM5_TI2_RMP_COMP5 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM5_TI2_RMP_COMP6 \
+ (TIM_TISEL_TI2SEL_2 | \
+ TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM5_TI2_RMP_COMP7 \
+ (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+#endif /* TIM5 */
+
+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM8_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
+#define LL_TIM_TIM8_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM8_TI1_RMP_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM8_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM8_TI1_RMP_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM15_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_LSE \
+ TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
+#define LL_TIM_TIM15_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM15_TI1_RMP_COMP2 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM15_TI1_RMP_COMP5 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP7)
+#define LL_TIM_TIM15_TI1_RMP_COMP7 \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
+ * @{
+ */
+#define LL_TIM_TIM15_TI2_RMP_GPIO \
+ 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_COMP2 \
+ TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM15_TI2_RMP_COMP3 \
+ TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
+#if defined(COMP6)
+#define LL_TIM_TIM15_TI2_RMP_COMP6 \
+ (TIM_TISEL_TI2SEL_1 | \
+ TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM15_TI2_RMP_COMP7 \
+ TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM16_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
+#if defined(COMP6)
+#define LL_TIM_TIM16_TI1_RMP_COMP6 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#define LL_TIM_TIM16_TI1_RMP_MCO \
+ TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
+#define LL_TIM_TIM16_TI1_RMP_HSE_32 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
+#define LL_TIM_TIM16_TI1_RMP_RTC_WK \
+ TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM16_TI1_RMP_LSE \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
+#define LL_TIM_TIM16_TI1_RMP_LSI \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM17_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
+#if defined(COMP5)
+#define LL_TIM_TIM17_TI1_RMP_COMP5 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#define LL_TIM_TIM17_TI1_RMP_MCO \
+ TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
+#define LL_TIM_TIM17_TI1_RMP_HSE_32 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
+#define LL_TIM_TIM17_TI1_RMP_RTC_WK \
+ TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM17_TI1_RMP_LSE \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
+#define LL_TIM_TIM17_TI1_RMP_LSI \
+ (TIM_TISEL_TI1SEL_2 | \
+ TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
+/**
+ * @}
+ */
+
+#if defined(TIM20)
+/** @defgroup TIM_LL_EC_TIM20_TI1_RMP TIM20 Timer Input Ch1 Remap
+ * @{
+ */
+#define LL_TIM_TIM20_TI1_RMP_GPIO \
+ 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
+#define LL_TIM_TIM20_TI1_RMP_COMP1 \
+ TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM20_TI1_RMP_COMP2 \
+ TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM20_TI1_RMP_COMP3 \
+ (TIM_TISEL_TI1SEL_1 | \
+ TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM20_TI1_RMP_COMP4 \
+ TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
+/**
+ * @}
+ */
+#endif /* TIM20 */
+
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+ * @{
+ */
+#define LL_TIM_OCREF_CLR_INT_ETR \
+ OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
+#define LL_TIM_OCREF_CLR_INT_COMP1 \
+ 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP2 \
+ TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP3 \
+ TIM1_AF2_OCRSEL_1 /*!< OCREF clear input is connected to COMP3_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP4 \
+ (TIM1_AF2_OCRSEL_1 | \
+ TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_OCREF_CLR_INT_COMP5 \
+ TIM1_AF2_OCRSEL_2 /*!< OCREF clear input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_OCREF_CLR_INT_COMP6 \
+ (TIM1_AF2_OCRSEL_2 | \
+ TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_OCREF_CLR_INT_COMP7 \
+ (TIM1_AF2_OCRSEL_2 | \
+ TIM1_AF2_OCRSEL_1) /*!< OCREF clear input is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
+ * @{
+ */
+#define LL_TIM_INDEX_UP_DOWN \
+ 0x00000000U /*!< Index resets the counter whatever the direction */
+#define LL_TIM_INDEX_UP \
+ TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
+#define LL_TIM_INDEX_DOWN \
+ TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
+ * @{
+ */
+#define LL_TIM_INDEX_POSITION_DOWN_DOWN \
+ 0x00000000U /*!< Index resets the counter when AB = 00 */
+#define LL_TIM_INDEX_POSITION_DOWN_UP \
+ TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
+#define LL_TIM_INDEX_POSITION_UP_DOWN \
+ TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
+#define LL_TIM_INDEX_POSITION_UP_UP \
+ (TIM_ECR_IPOS_1 | \
+ TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
+#define LL_TIM_INDEX_POSITION_DOWN \
+ 0x00000000U /*!< Index resets the counter when clock is 0 */
+#define LL_TIM_INDEX_POSITION_UP \
+ TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
+ * @{
+ */
+#define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
+#define LL_TIM_INDEX_FIRST_ONLY \
+ TIM_ECR_FIDX /*!< The first Index only resets the counter */
+/**
+ * @}
+ */
+/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
+ * @{
+ */
+#define LL_TIM_PWPRSC_X1 \
+ 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
+#define LL_TIM_PWPRSC_X2 \
+ TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
+#define LL_TIM_PWPRSC_X4 \
+ TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
+#define LL_TIM_PWPRSC_X8 \
+ (TIM_ECR_PWPRSC_1 | \
+ TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
+#define LL_TIM_PWPRSC_X16 \
+ TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
+#define LL_TIM_PWPRSC_X32 \
+ (TIM_ECR_PWPRSC_2 | \
+ TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
+#define LL_TIM_PWPRSC_X64 \
+ (TIM_ECR_PWPRSC_2 | \
+ TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
+#define LL_TIM_PWPRSC_X128 \
+ (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | \
+ TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
+ * @{
+ */
+#define LL_TIM_HSE_32_NOT_REQUEST \
+ 0x00000000U /*!< Clock HSE/32 not requested \
+ */
+#define LL_TIM_HSE_32_REQUEST \
+ TIM_OR_HSE32EN /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
+/**
+ * @}
+ */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+/**
+ * @brief Write a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
+ * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+ * @note Relevant only if UIF flag remapping has been enabled (UIF status bit
+ * is copied to TIMx_CNT register bit 31)
+ * @param __CNT__ Counter value
+ * @retval UIF status bit
+ */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
+ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to
+ * achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision
+ * (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ((((uint64_t)((__DT__) * 1000U)) < \
+ ((DT_DELAY_1 + 1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
+ ? (uint8_t)(((uint64_t)((__DT__) * 1000U) / \
+ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & \
+ DT_DELAY_1) \
+ : (((uint64_t)((__DT__) * 1000U)) < \
+ ((64U + (DT_DELAY_2 + 1U)) * 2U * \
+ TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
+ ? (uint8_t)(DT_RANGE_2 | \
+ ((uint8_t)((uint8_t)((((uint64_t)((__DT__) * 1000U)) / \
+ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> \
+ 1U) - \
+ (uint8_t)64) & \
+ DT_DELAY_2)) \
+ : (((uint64_t)((__DT__) * 1000U)) < \
+ ((32U + (DT_DELAY_3 + 1U)) * 8U * \
+ TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
+ ? (uint8_t)(DT_RANGE_3 | \
+ ((uint8_t)((uint8_t)(((((uint64_t)(__DT__) * 1000U)) / \
+ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> \
+ 3U) - \
+ (uint8_t)32) & \
+ DT_DELAY_3)) \
+ : (((uint64_t)((__DT__) * 1000U)) < \
+ ((32U + (DT_DELAY_4 + 1U)) * 16U * \
+ TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) \
+ ? (uint8_t)(DT_RANGE_4 | \
+ ((uint8_t)((uint8_t)(((((uint64_t)(__DT__) * 1000U)) / \
+ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> \
+ 4U) - \
+ (uint8_t)32) & \
+ DT_DELAY_4)) \
+ : 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required
+ * counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ (((__TIMCLK__) >= (__CNTCLK__)) \
+ ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__) / 2U) / (__CNTCLK__)) - 1U) \
+ : 0U)
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the
+ * required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (),
+ * 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ ((((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
+ ? (((__TIMCLK__) / ((__FREQ__) * ((__PSC__) + 1U))) - 1U) \
+ : 0U)
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering
+ * feature enabled, to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler
+ * (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+ ((((__TIMCLK__) / ((__PSC__) + 1U)) >= (__FREQ__)) \
+ ? (uint32_t)((((uint64_t)(__TIMCLK__) * 16U / \
+ ((__FREQ__) * ((__PSC__) + 1U))) - \
+ 16U)) \
+ : 0U)
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the
+ * required timer output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (),
+ * 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) / \
+ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the compare value, with dithering feature
+ * enabled, to achieve the required timer output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler
+ * (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) / \
+ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the
+ * required pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10,
+ * 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) + \
+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value, with dithering
+ * feature enabled, to achieve the required pulse duration (when the timer
+ * operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler
+ * (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), \
+ (__PULSE__)) + \
+ __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), \
+ (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the
+ * following events generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if
+ * enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx,
+ uint32_t UpdateSource) {
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx,
+ uint32_t OnePulseMode) {
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx,
+ uint32_t CounterMode) {
+ MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) {
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U) {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling
+ * clock used by the dead-time generators (when supported) and the digital
+ * filters.
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx,
+ uint32_t ClockDivision) {
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the
+ * sampling clock used by the dead-time generators (when supported) and the
+ * digital filters.
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note If dithering is activated, pay attention to the Counter value
+ * interpretation
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or
+ * 0xFFFFFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) {
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note If dithering is activated, pay attention to the Counter value
+ * interpretation
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] +
+ * 1).
+ * @note The prescaler can be changed on the fly as this control register is
+ * buffered. The new prescaler ratio is taken into account at the next update
+ * event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the
+ * Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx,
+ uint32_t Prescaler) {
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the
+ * AutoReload parameter In case dithering is activated,macro
+ * __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
+ * parameter.
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx,
+ uint32_t AutoReload) {
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note For advanced timer instances RepetitionCounter can be up to 65535.
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for
+ * advanced timer.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx,
+ uint32_t RepetitionCounter) {
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the
+ * timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition
+ * signalled by the UIFCPY flag to be read in an atomic way.
+ * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) copy is set.
+ * @param Counter Counter value
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) {
+ return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable dithering.
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance provides dithering.
+ * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+ * @brief Disable dithering.
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance provides dithering.
+ * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+ * @brief Indicates whether dithering is activated.
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance provides dithering.
+ * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM)
+ * preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation
+ * event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM)
+ * preload.
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation
+ * event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and
+ * OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE,
+ * CCxNE and OCxM).
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation
+ * event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx,
+ uint32_t CCUpdateSource) {
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx,
+ uint32_t DMAReqTrigger) {
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx,
+ uint32_t LockLevel) {
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel\n
+ * CCER CC4NE LL_TIM_CC_EnableChannel\n
+ * CCER CC5E LL_TIM_CC_EnableChannel\n
+ * CCER CC6E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx,
+ uint32_t Channels) {
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel\n
+ * CCER CC4NE LL_TIM_CC_DisableChannel\n
+ * CCER CC5E LL_TIM_CC_DisableChannel\n
+ * CCER CC6E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx,
+ uint32_t Channels) {
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC6E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx,
+ uint32_t Channels) {
+ return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CCER CC5P LL_TIM_OC_ConfigOutput\n
+ * CCER CC6P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS6 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Configuration This parameter must be a combination of all the
+ * following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t Configuration) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode\n
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel
+ * 4 only)
+ * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel
+ * 4 only)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t Mode) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg,
+ ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),
+ Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode\n
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel
+ * 4 only)
+ * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel
+ * 4 only)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)
+ << SHIFT_TAB_OCxx[iChannel])) >>
+ SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity\n
+ * CCER CC4NP LL_TIM_OC_SetPolarity\n
+ * CCER CC5P LL_TIM_OC_SetPolarity\n
+ * CCER CC6P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t Polarity) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity\n
+ * CCER CC4NP LL_TIM_OC_GetPolarity\n
+ * CCER CC5P LL_TIM_OC_GetPolarity\n
+ * CCER CC6P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t IdleState) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH4N
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >>
+ SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for
+ * the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does
+ * not work in Forced mode.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external
+ * event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external
+ * event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled
+ * for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does
+ * not work in Forced mode.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external
+ * event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of
+ * the OCxREF signal and the rising edge of the Ocx and OCxN signals).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the
+ * DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx,
+ uint32_t DeadTime) {
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000
+ * and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro
+ * @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx,
+ uint32_t CompareValue) {
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000
+ * and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro
+ * @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx,
+ uint32_t CompareValue) {
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000
+ * and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro
+ * @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx,
+ uint32_t CompareValue) {
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000
+ * and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro
+ * @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx,
+ uint32_t CompareValue) {
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 5 (TIMx_CCR5).
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro
+ * @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx,
+ uint32_t CompareValue) {
+ MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 6 (TIMx_CCR6).
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @note If dithering is activated, CompareValue can be calculated with macro
+ * @ref __LL_TIM_CALC_DELAY_DITHER .
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx,
+ uint32_t CompareValue) {
+ WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note In 32-bit timer implementations returned compare value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note In 32-bit timer implementations returned compare value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note In 32-bit timer implementations returned compare value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note In 32-bit timer implementations returned compare value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR5) set for output channel 5.
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR6) set for output channel 6.
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+ * @brief Select on which reference signal the OC5REF is combined to.
+ * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the combined 3-phase PWM mode.
+ * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @param TIMx Timer instance
+ * @param GroupCH5 This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_GROUPCH5_NONE
+ * @arg @ref LL_TIM_GROUPCH5_OC1REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC2REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC3REFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx,
+ uint32_t GroupCH5) {
+ MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1),
+ GroupCH5);
+}
+
+/**
+ * @brief Set the pulse on compare pulse width prescaler.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
+ * @param TIMx Timer instance
+ * @param PulseWidthPrescaler This parameter can be one of the following
+ * values:
+ * @arg @ref LL_TIM_PWPRSC_X1
+ * @arg @ref LL_TIM_PWPRSC_X2
+ * @arg @ref LL_TIM_PWPRSC_X4
+ * @arg @ref LL_TIM_PWPRSC_X8
+ * @arg @ref LL_TIM_PWPRSC_X16
+ * @arg @ref LL_TIM_PWPRSC_X32
+ * @arg @ref LL_TIM_PWPRSC_X64
+ * @arg @ref LL_TIM_PWPRSC_X128
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(
+ TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler) {
+ MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
+}
+
+/**
+ * @brief Get the pulse on compare pulse width prescaler.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_PWPRSC_X1
+ * @arg @ref LL_TIM_PWPRSC_X2
+ * @arg @ref LL_TIM_PWPRSC_X4
+ * @arg @ref LL_TIM_PWPRSC_X8
+ * @arg @ref LL_TIM_PWPRSC_X16
+ * @arg @ref LL_TIM_PWPRSC_X32
+ * @arg @ref LL_TIM_PWPRSC_X64
+ * @arg @ref LL_TIM_PWPRSC_X128
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
+}
+
+/**
+ * @brief Set the pulse on compare pulse width duration.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
+ * @param TIMx Timer instance
+ * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx,
+ uint32_t PulseWidth) {
+ MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
+}
+
+/**
+ * @brief Get the pulse on compare pulse width duration.
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * whether or not the pulse on compare feature is supported by the timer
+ * instance.
+ * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
+ * @param TIMx Timer instance
+ * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * CCER CC4NP LL_TIM_IC_Config
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the
+ * following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref
+ * LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref
+ * LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref
+ * LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t Configuration) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg,
+ ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)
+ << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) &
+ (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))
+ << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER,
+ ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P))
+ << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx,
+ uint32_t Channel,
+ uint32_t ICActiveInput) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >>
+ SHIFT_TAB_ICxx[iChannel])
+ << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ICPrescaler) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]),
+ (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >>
+ SHIFT_TAB_ICxx[iChannel])
+ << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ICFilter) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]),
+ (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((
+ uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >>
+ SHIFT_TAB_ICxx[iChannel])
+ << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * CCER CC4NP LL_TIM_IC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ICPolarity) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER,
+ ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * CCER CC4NP LL_TIM_IC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx,
+ uint32_t Channel) {
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P)
+ << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR
+ * combination).
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to
+ * the TI1 input.
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note In 32-bit timer implementations returned captured value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note In 32-bit timer implementations returned captured value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note In 32-bit timer implementations returned captured value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note In 32-bit timer implementations returned captured value can be between
+ * 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @note If dithering is activated, pay attention to the returned value
+ * interpretation.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any
+ * active edge on the ETRF signal.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref
+ * LL_TIM_SetTriggerInput() function. This timer input must be configured by
+ * calling the @ref LL_TIM_IC_Config() function.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx,
+ uint32_t ClockSource) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+ * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
+ * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
+ * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
+ * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx,
+ uint32_t EncoderMode) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation
+ * configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following
+ * values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @arg @ref LL_TIM_TRGO_ENCODERCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx,
+ uint32_t TimerSynchronization) {
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+ * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
+ * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can be used for ADC synchronization.
+ * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
+ * @param TIMx Timer Instance
+ * @param ADCSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO2_RESET
+ * @arg @ref LL_TIM_TRGO2_ENABLE
+ * @arg @ref LL_TIM_TRGO2_UPDATE
+ * @arg @ref LL_TIM_TRGO2_CC1F
+ * @arg @ref LL_TIM_TRGO2_OC1
+ * @arg @ref LL_TIM_TRGO2_OC2
+ * @arg @ref LL_TIM_TRGO2_OC3
+ * @arg @ref LL_TIM_TRGO2_OC4
+ * @arg @ref LL_TIM_TRGO2_OC5
+ * @arg @ref LL_TIM_TRGO2_OC6
+ * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx,
+ uint32_t ADCSynchronization) {
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx,
+ uint32_t SlaveMode) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the
+ * counter.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_ITR4
+ * @arg @ref LL_TIM_TS_ITR5
+ * @arg @ref LL_TIM_TS_ITR6
+ * @arg @ref LL_TIM_TS_ITR7
+ * @arg @ref LL_TIM_TS_ITR8
+ * @arg @ref LL_TIM_TS_ITR9
+ * @arg @ref LL_TIM_TS_ITR10
+ * @arg @ref LL_TIM_TS_ITR11
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx,
+ uint32_t TriggerInput) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity,
+ uint32_t ETRPrescaler,
+ uint32_t ETRFilter) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF,
+ ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @brief Select the external trigger (ETR) input source.
+ * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports ETR source selection.
+ * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
+ * @param TIMx Timer instance
+ * @param ETRSource This parameter can be one of the following values:
+ *
+ * TIM1: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)
+ *
+ * TIM2: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
+ * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
+ *
+ * TIM3: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
+ * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
+ *
+ * TIM4: any combination of ETR_RMP where
+ *
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
+ * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)
+ *
+ * TIM5: any combination of ETR_RMP where (**)
+ *
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
+ * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)
+ *
+ * TIM8: any combination of ETR_RMP where
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
+ * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
+ *
+ * TIM20: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
+ * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx,
+ uint32_t ETRSource) {
+ MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+ * @brief Enable SMS preload.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in
+ * SMCR register.
+ * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+ * @brief Disable SMS preload.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in
+ * SMCR register.
+ * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+ * @brief Indicate whether SMS preload is enabled.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in
+ * SMCR register.
+ * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set the preload source of SMS.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in
+ * SMCR register.
+ * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
+ * @param TIMx Timer instance
+ * @param PreloadSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SMSPS_TIMUPDATE
+ * @arg @ref LL_TIM_SMSPS_INDEX
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx,
+ uint32_t PreloadSource) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
+}
+
+/**
+ * @brief Get the preload source of SMS.
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the preload of SMS field in
+ * SMCR register.
+ * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_SMSPS_TIMUPDATE
+ * @arg @ref LL_TIM_SMSPS_INDEX
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Configure the break input.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Bidirectional mode is only supported by advanced timer instances.
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance is an advanced-control timer.
+ * @note In bidirectional mode (BKBID bit set), the Break input is configured
+ * both in input mode and in open drain output mode. Any active Break event will
+ * assert a low logic level on the Break input to indicate an internal
+ * break event to external devices.
+ * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+ * LL_TIM_BREAK_AFMODE_INPUT.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
+ * BDTR BKF LL_TIM_ConfigBRK\n
+ * BDTR BKBID LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @param BreakFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+ * @param BreakAFMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+ * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+ uint32_t BreakFilter,
+ uint32_t BreakAFMode) {
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID,
+ BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+/**
+ * @brief Disarm the break input (when it operates in bidirectional mode).
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+ * @brief Enable the break 2 function.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Disable the break 2 function.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Configure the break 2 input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @note Bidirectional mode is only supported by advanced timer instances.
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance is an advanced-control timer.
+ * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured
+ * both in input mode and in open drain output mode. Any active Break event will
+ * assert a low logic level on the Break 2 input to indicate an internal
+ * break event to external devices.
+ * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+ * LL_TIM_BREAK2_AFMODE_INPUT.
+ * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
+ * BDTR BK2F LL_TIM_ConfigBRK2\n
+ * BDTR BK2BID LL_TIM_ConfigBRK2
+ * @param TIMx Timer instance
+ * @param Break2Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ * @param Break2Filter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+ * @param Break2AFMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+ * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx,
+ uint32_t Break2Polarity,
+ uint32_t Break2Filter,
+ uint32_t Break2AFMode) {
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID,
+ Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+/**
+ * @brief Disarm the break 2 input (when it operates in bidirectional mode).
+ * @note The break 2 input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output.
+ * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run
+ * modes.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx,
+ uint32_t OffStateIdle,
+ uint32_t OffStateRun) {
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR,
+ OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically
+ * when a break input is active).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs
+ * by software and is reset in case of break or break2 event
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs
+ * by software and is reset in case of break or break2 event.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the signals connected to the designated timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n
+ * AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2NE LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n
+ * AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
+ *
+ * (*) Value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx,
+ uint32_t BreakInput,
+ uint32_t Source) {
+ __IO uint32_t *pReg =
+ (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ SET_BIT(*pReg, Source);
+}
+
+/**
+ * @brief Disable the signals connected to the designated timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n
+ * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP4E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP5E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP6E LL_TIM_DisableBreakInputSource\n
+ * AF2 BK2CMP7E LL_TIM_DisableBreakInputSource
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
+ *
+ * (*) Value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx,
+ uint32_t BreakInput,
+ uint32_t Source) {
+ __IO uint32_t *pReg =
+ (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ CLEAR_BIT(*pReg, Source);
+}
+
+/**
+ * @brief Set the polarity of the break signal for the timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP5P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP6P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF1 BKCMP7P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP5P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP6P LL_TIM_SetBreakInputSourcePolarity\n
+ * AF2 BK2CMP7P LL_TIM_SetBreakInputSourcePolarity
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_POLARITY_LOW
+ * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+ *
+ * (*) Value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx,
+ uint32_t BreakInput,
+ uint32_t Source,
+ uint32_t Polarity) {
+ __IO uint32_t *pReg =
+ (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE),
+ (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+/**
+ * @brief Enable asymmetrical deadtime.
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance provides asymmetrical deadtime.
+ * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+ * @brief Disable asymmetrical dead-time.
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance provides asymmetrical deadtime.
+ * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+ * @brief Indicates whether asymmetrical deadtime is activated.
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance provides asymmetrical deadtime.
+ * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the falling edge dead-time delay (delay inserted between the
+ * falling edge of the OCxREF signal and the rising edge of OCxN signals).
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
+ * whether or not asymmetrical dead-time insertion feature is supported by a
+ * timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the
+ * DeadTime parameter
+ * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
+ * been programmed (LOCK bits in TIMx_BDTR register).
+ * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx,
+ uint32_t DeadTime) {
+ MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
+}
+
+/**
+ * @brief Get the falling edge dead-time delay (delay inserted between the
+ * falling edge of the OCxREF signal and the rising edge of OCxN signals).
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check
+ * whether or not asymmetrical dead-time insertion feature is supported by a
+ * timer instance.
+ * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
+ * been programmed (LOCK bits in TIMx_BDTR register).
+ * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
+ * @param TIMx Timer instance
+ * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
+}
+
+/**
+ * @brief Enable deadtime preload.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides deadtime preload.
+ * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+ * @brief Disable dead-time preload.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides deadtime preload.
+ * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+ * @brief Indicates whether deadtime preload is activated.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides deadtime preload.
+ * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following
+ * values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx,
+ uint32_t DMABurstBaseAddress,
+ uint32_t DMABurstLength) {
+ MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA),
+ (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Encoder Encoder configuration
+ * @{
+ */
+
+/**
+ * @brief Enable encoder index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+ * @brief Disable encoder index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+ * @brief Indicate whether encoder index is enabled.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
+}
+
+/**
+ * @brief Set index direction
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
+ * @param TIMx Timer instance
+ * @param IndexDirection This parameter can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_UP
+ * @arg @ref LL_TIM_INDEX_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx,
+ uint32_t IndexDirection) {
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
+}
+
+/**
+ * @brief Get actual index direction
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_UP
+ * @arg @ref LL_TIM_INDEX_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
+}
+
+/**
+ * @brief Enable first index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+ * @brief Disable first index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+ * @brief Indicates whether first index is enabled.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set index positioning
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
+ * @param TIMx Timer instance
+ * @param IndexPositionning This parameter can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx,
+ uint32_t IndexPositionning) {
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
+}
+
+/**
+ * @brief Get actual index positioning
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN
+ * @arg @ref LL_TIM_INDEX_POSITION_UP
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx) {
+ return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
+}
+
+/**
+ * @brief Configure encoder index.
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an index input.
+ * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
+ * ECR FIDX LL_TIM_ConfigIDX\n
+ * ECR IPOS LL_TIM_ConfigIDX
+ * @param TIMx Timer instance
+ * @param Configuration This parameter must be a combination of all the
+ * following values:
+ * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref
+ * LL_TIM_INDEX_UP_DOWN
+ * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
+ * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref
+ * LL_TIM_INDEX_POSITION_UP
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx,
+ uint32_t Configuration) {
+ MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS,
+ Configuration);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+ * @{
+ */
+/**
+ * @brief Remap TIM inputs (input channel, internal/external triggers).
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * a some timer inputs can be remapped.
+ * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
+ * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
+ * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
+ * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
+ * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
+ * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
+ * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
+ * TIM20_TISEL TI1SEL LL_TIM_SetRemap
+ * @param TIMx Timer instance
+ * @param Remap Remap param depends on the TIMx. Description available only
+ * in CHM version of the User Manual (not in .pdf).
+ * Otherwise see Reference Manual description of TISEL registers.
+ *
+ * Below description summarizes "Timer Instance" and "Remap" param
+ * combinations:
+ *
+ * TIM1: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
+ *
+ * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
+ * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
+ * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
+ *
+ * . . TI2_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
+ * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
+ * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
+ * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
+ * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
+ *
+ * . . TI3_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
+ *
+ * . . TI4_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+ *
+ * TIM3: any combination of TI1_RMP and TI2_RMP where
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
+ *
+ * . . TI2_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
+ *
+ * . . TI3_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
+ * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
+ *
+ * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
+ *
+ * . . TI2_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
+ *
+ * . . TI3_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
+ * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
+ *
+ * . . TI4_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
+ * @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
+ *
+ * TIM5: any combination of TI1_RMP and TI2_RMP where (**)
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*)
+ *
+ * . . TI2_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
+ *
+ * TIM8: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
+ *
+ * TIM15: any combination of TI1_RMP and TI2_RMP where
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
+ *
+ * . . TI2_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
+ * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
+ * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
+ * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
+ *
+ * TIM16: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+ *
+ * TIM17: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
+ *
+ * TIM20: one of the following values (**)
+ *
+ * @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
+ * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
+ * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
+ * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ *
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) {
+ MODIFY_REG(TIMx->TISEL,
+ (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL |
+ TIM_TISEL_TI4SEL),
+ Remap);
+}
+
+/**
+ * @brief Enable request for HSE/32 clock used for TISEL remap.
+ * @note Only TIM16 and TIM17 support HSE/32 remap
+ * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
+}
+
+/**
+ * @brief Disable request for HSE/32 clock used for TISEL remap.
+ * @note Only TIM16 and TIM17 support HSE/32 remap
+ * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
+}
+
+/**
+ * @brief Indicate whether request for HSE/32 clock is enabled.
+ * @note Only TIM16 and TIM17 support HSE/32 remap
+ * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+ * @{
+ */
+/**
+ * @brief Set the OCREF clear input source
+ * @note The OCxREF signal of a given channel can be cleared when a high level
+ * is applied on the OCREF_CLR_INPUT
+ * @note This function can only be used in Output compare and PWM modes.
+ * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can configure OCREF clear input source.
+ * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
+ * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
+ * @param TIMx Timer instance
+ * @param OCRefClearInputSource This parameter can be one of the following
+ * values:
+ * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
+ * @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(
+ TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) {
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
+ ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >>
+ OCREF_CLEAR_SELECT_Pos)
+ << TIM_SMCR_OCCS_Pos);
+ MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt
+ * is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set
+ * (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set
+ * (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set
+ * (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set
+ * (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
+ * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set
+ * (Capture/Compare 5 interrupt is pending).
+ * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
+ * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set
+ * (Capture/Compare 6 interrupt is pending).
+ * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set
+ * (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger
+ * interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt
+ * is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the break 2 interrupt flag (B2IF).
+ * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+ * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2
+ * interrupt is pending).
+ * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag
+ * (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag
+ * (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag
+ * (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag
+ * (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the system break interrupt flag (SBIF).
+ * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+ * @brief Indicate whether system break interrupt flag (SBIF) is set (system
+ * break interrupt is pending).
+ * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the transition error interrupt flag (TERRF).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
+}
+
+/**
+ * @brief Indicate whether transition error interrupt flag (TERRF) is set
+ * (transition error interrupt is pending).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the index error interrupt flag (IERRF).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
+}
+
+/**
+ * @brief Indicate whether index error interrupt flag (IERRF) is set (index
+ * error interrupt is pending).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the direction change interrupt flag (DIRF).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
+}
+
+/**
+ * @brief Indicate whether direction change interrupt flag (DIRF) is set
+ * (direction change interrupt is pending).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the index interrupt flag (IDXF).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) {
+ WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
+}
+
+/**
+ * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt
+ * is pending).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable transition error interrupt (TERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+ * @brief Disable transition error interrupt (TERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+ * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable index error interrupt (IERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+ * @brief Disable index error interrupt (IERRIE).
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+ * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance provides encoder error management.
+ * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable direction change interrupt (DIRIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+ * @brief Disable direction change interrupt (DIRIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+ * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable index interrupt (IDXIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+ * @brief Disable index interrupt (IDXIE).
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+ * @brief Indicates whether the index interrupt (IDXIE) is enabled.
+ * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used
+ * to check whether or not a timer instance provides encoder interrupt
+ * management.
+ * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is
+ * enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is
+ * enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is
+ * enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is
+ * enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) {
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) {
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+ * @brief Generate break 2 event.
+ * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) {
+ SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx,
+ const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel,
+ const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel,
+ const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(
+ LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(
+ TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(
+ LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(
+ TIM_TypeDef *TIMx,
+ const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx,
+ const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || \
+ TIM15 || TIM16 || TIM17 || TIM20 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_TIM_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
index e3bc9e3..281af75 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
@@ -1,4510 +1,4576 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_usart.h
- * @author MCD Application Team
- * @brief Header file of USART LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_USART_H
-#define STM32G4xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || \
- defined(UART5)
-
-/** @defgroup USART_LL USART
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Variables USART Private Variables
- * @{
- */
-/* Array used to get the USART prescaler division decimal values versus @ref
- * USART_LL_EC_PRESCALER values */
-static const uint32_t USART_PRESCALER_TAB[] = {
- 1UL, 2UL, 4UL, 6UL, 8UL, 10UL, 12UL, 16UL, 32UL, 64UL, 128UL, 256UL};
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
- * @{
- */
-
-/**
- * @brief LL USART Init Structure definition
- */
-typedef struct {
- uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the
- communication baud rate. This parameter can be a
- value of @ref USART_LL_EC_PRESCALER.
-
- This feature can be modified afterwards using
- unitary function @ref LL_USART_SetPrescaler().*/
-
- uint32_t
- BaudRate; /*!< This field defines expected Usart communication baud rate.
-
- This feature can be modified afterwards using unitary
- function @ref LL_USART_SetBaudRate().*/
-
- uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or
- received in a frame. This parameter can be a value of
- @ref USART_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary
- function @ref LL_USART_SetDataWidth().*/
-
- uint32_t
- StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
- This feature can be modified afterwards using unitary
- function @ref LL_USART_SetStopBitsLength().*/
-
- uint32_t
- Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_LL_EC_PARITY.
-
- This feature can be modified afterwards using unitary
- function @ref LL_USART_SetParity().*/
-
- uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit
- mode is enabled or disabled. This parameter can
- be a value of @ref USART_LL_EC_DIRECTION.
-
- This feature can be modified afterwards using
- unitary function @ref
- LL_USART_SetTransferDirection().*/
-
- uint32_t
- HardwareFlowControl; /*!< Specifies whether the hardware flow control mode
- is enabled or disabled. This parameter can be a
- value of @ref USART_LL_EC_HWCONTROL.
-
- This feature can be modified afterwards using
- unitary function @ref LL_USART_SetHWFlowCtrl().*/
-
- uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16
- or 8. This parameter can be a value of @ref
- USART_LL_EC_OVERSAMPLING.
-
- This feature can be modified afterwards using
- unitary function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
- * @brief LL USART Clock Init Structure definition
- */
-typedef struct {
- uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or
- disabled. This parameter can be a value of @ref
- USART_LL_EC_CLOCK.
-
- USART HW configuration can be modified afterwards
- using unitary functions
- @ref LL_USART_EnableSCLKOutput() or @ref
- LL_USART_DisableSCLKOutput(). For more details, refer
- to description of this function. */
-
- uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref
- USART_LL_EC_POLARITY.
-
- USART HW configuration can be modified afterwards
- using unitary functions @ref
- LL_USART_SetClockPolarity(). For more details,
- refer to description of this function. */
-
- uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit
- capture is made. This parameter can be a value of @ref
- USART_LL_EC_PHASE.
-
- USART HW configuration can be modified afterwards
- using unitary functions @ref LL_USART_SetClockPhase().
- For more details, refer to description of this
- function. */
-
- uint32_t
- LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to
- the last transmitted data bit (MSB) has to be output
- on the SCLK pin in synchronous mode. This parameter
- can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
- USART HW configuration can be modified afterwards
- using unitary functions @ref
- LL_USART_SetLastClkPulseOutput(). For more details,
- refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_USART_WriteReg function
- * @{
- */
-#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
-#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
-#define LL_USART_ICR_NECF \
- USART_ICR_NECF /*!< Noise error detected clear flag \
- */
-#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
-#define LL_USART_ICR_IDLECF \
- USART_ICR_IDLECF /*!< Idle line detected clear flag */
-#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
-#define LL_USART_ICR_TCCF \
- USART_ICR_TCCF /*!< Transmission complete clear flag */
-#define LL_USART_ICR_TCBGTCF \
- USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag \
- */
-#define LL_USART_ICR_LBDCF \
- USART_ICR_LBDCF /*!< LIN break detection clear flag */
-#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
-#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
-#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
-#define LL_USART_ICR_UDRCF \
- USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag \
- */
-#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
-#define LL_USART_ICR_WUCF \
- USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_USART_ReadReg function
- * @{
- */
-#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
-#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
-#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
-#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
-#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
-#define LL_USART_ISR_RXNE_RXFNE \
- USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
-#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
-#define LL_USART_ISR_TXE_TXFNF \
- USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full \
- flag*/
-#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
-#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
-#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
-#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
-#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
-#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */
-#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
-#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
-#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
-#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
-#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
-#define LL_USART_ISR_RWU \
- USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
-#define LL_USART_ISR_TEACK \
- USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
-#define LL_USART_ISR_REACK \
- USART_ISR_REACK /*!< Receive enable acknowledge flag */
-#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
-#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
-#define LL_USART_ISR_TCBGT \
- USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag \
- */
-#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
-#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_USART_ReadReg and
- * LL_USART_WriteReg functions
- * @{
- */
-#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE_RXFNEIE \
- USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty \
- interrupt enable */
-#define LL_USART_CR1_TCIE \
- USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE_TXFNFIE \
- USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not \
- full interrupt enable */
-#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_USART_CR1_CMIE \
- USART_CR1_CMIE /*!< Character match interrupt enable */
-#define LL_USART_CR1_RTOIE \
- USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
-#define LL_USART_CR1_EOBIE \
- USART_CR1_EOBIE /*!< End of Block interrupt enable \
- */
-#define LL_USART_CR1_TXFEIE \
- USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
-#define LL_USART_CR1_RXFFIE \
- USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
-#define LL_USART_CR2_LBDIE \
- USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#define LL_USART_CR3_WUFIE \
- USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
-#define LL_USART_CR3_TXFTIE \
- USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
-#define LL_USART_CR3_TCBGTIE \
- USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt \
- enable */
-#define LL_USART_CR3_RXFTIE \
- USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
- * @{
- */
-#define LL_USART_FIFOTHRESHOLD_1_8 \
- 0x00000000U /*!< FIFO reaches 1/8 of its depth */
-#define LL_USART_FIFOTHRESHOLD_1_4 \
- 0x00000001U /*!< FIFO reaches 1/4 of its depth */
-#define LL_USART_FIFOTHRESHOLD_1_2 \
- 0x00000002U /*!< FIFO reaches 1/2 of its depth */
-#define LL_USART_FIFOTHRESHOLD_3_4 \
- 0x00000003U /*!< FIFO reaches 3/4 of its depth */
-#define LL_USART_FIFOTHRESHOLD_7_8 \
- 0x00000004U /*!< FIFO reaches 7/8 of its depth */
-#define LL_USART_FIFOTHRESHOLD_8_8 \
- 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
- * @{
- */
-#define LL_USART_DIRECTION_NONE \
- 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX \
- USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX \
- USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX \
- (USART_CR1_TE | USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
- * @{
- */
-#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN \
- USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD \
- (USART_CR1_PCE | \
- USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
- * @{
- */
-#define LL_USART_WAKEUP_IDLELINE \
- 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK \
- USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_USART_DATAWIDTH_7B \
- USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits \
- */
-#define LL_USART_DATAWIDTH_8B \
- 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B \
- USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits \
- */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
- * @{
- */
-#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
- * @{
- */
-
-#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
- * @{
- */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT \
- 0x00000000U /*!< The clock pulse of the last data bit is not output to the \
- SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT \
- USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the \
- SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_USART_PHASE_1EDGE \
- 0x00000000U /*!< The first clock transition is the first data capture edge \
- */
-#define LL_USART_PHASE_2EDGE \
- USART_CR2_CPHA /*!< The second clock transition is the first data capture \
- edge */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_USART_POLARITY_LOW \
- 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH \
- USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission \
- window */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
- * @{
- */
-#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
-#define LL_USART_PRESCALER_DIV2 \
- (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
-#define LL_USART_PRESCALER_DIV4 \
- (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
-#define LL_USART_PRESCALER_DIV6 \
- (USART_PRESC_PRESCALER_1 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
-#define LL_USART_PRESCALER_DIV8 \
- (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
-#define LL_USART_PRESCALER_DIV10 \
- (USART_PRESC_PRESCALER_2 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
-#define LL_USART_PRESCALER_DIV12 \
- (USART_PRESC_PRESCALER_2 | \
- USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
-#define LL_USART_PRESCALER_DIV16 \
- (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
-#define LL_USART_PRESCALER_DIV32 \
- (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
-#define LL_USART_PRESCALER_DIV64 \
- (USART_PRESC_PRESCALER_3 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
-#define LL_USART_PRESCALER_DIV128 \
- (USART_PRESC_PRESCALER_3 | \
- USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
-#define LL_USART_PRESCALER_DIV256 \
- (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | \
- USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
- * @{
- */
-#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5 \
- (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
- * @{
- */
-#define LL_USART_TXRX_STANDARD \
- 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_USART_TXRX_SWAPPED \
- (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
- * @{
- */
-#define LL_USART_RXPIN_LEVEL_STANDARD \
- 0x00000000U /*!< RX pin signal works using the standard logic levels */
-#define LL_USART_RXPIN_LEVEL_INVERTED \
- (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
- * @{
- */
-#define LL_USART_TXPIN_LEVEL_STANDARD \
- 0x00000000U /*!< TX pin signal works using the standard logic levels */
-#define LL_USART_TXPIN_LEVEL_INVERTED \
- (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
- * @{
- */
-#define LL_USART_BINARY_LOGIC_POSITIVE \
- 0x00000000U /*!< Logical data from the data register are send/received in \
- positive/direct logic. (1=H, 0=L) */
-#define LL_USART_BINARY_LOGIC_NEGATIVE \
- USART_CR2_DATAINV /*!< Logical data from the data register are send/received \
- in negative/inverse logic. (1=L, 0=H). The parity bit \
- is also inverted. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_BITORDER Bit Order
- * @{
- */
-#define LL_USART_BITORDER_LSBFIRST \
- 0x00000000U /*!< data is transmitted/received with data bit 0 first, \
- following the start bit */
-#define LL_USART_BITORDER_MSBFIRST \
- USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, \
- following the start bit */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
- * @{
- */
-#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT \
- 0x00000000U /*!< Measurement of the start bit is used to detect the baud \
- rate */
-#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE \
- USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received \
- frame must start with a single bit = 1 -> Frame = \
- Start10xxxxxx */
-#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME \
- USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
-#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME \
- (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
- * @{
- */
-#define LL_USART_ADDRESS_DETECT_4B \
- 0x00000000U /*!< 4-bit address detection method selected */
-#define LL_USART_ADDRESS_DETECT_7B \
- USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method \
- selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
- * @{
- */
-#define LL_USART_HWCONTROL_NONE \
- 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS \
- USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is \
- space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS \
- USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS \
- input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS \
- (USART_CR3_RTSE | \
- USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
- * @{
- */
-#define LL_USART_WAKEUP_ON_ADDRESS \
- 0x00000000U /*!< Wake up active on address match */
-#define LL_USART_WAKEUP_ON_STARTBIT \
- USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
-#define LL_USART_WAKEUP_ON_RXNE \
- (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
- * @{
- */
-#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
- * @{
- */
-#define LL_USART_LINBREAK_DETECT_10B \
- 0x00000000U /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B \
- USART_CR2_LBDL /*!< 11-bit break detection method selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
- * @{
- */
-#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
-#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
- * @{
- */
-#define LL_USART_DMA_REG_DATA_TRANSMIT \
- 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_USART_DMA_REG_DATA_RECEIVE \
- 0x00000001U /*!< Get address of data register used for reception */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
- WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
- * @{
- */
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV
- * is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_USART_PRESCALER_DIV1
- * @arg @ref LL_USART_PRESCALER_DIV2
- * @arg @ref LL_USART_PRESCALER_DIV4
- * @arg @ref LL_USART_PRESCALER_DIV6
- * @arg @ref LL_USART_PRESCALER_DIV8
- * @arg @ref LL_USART_PRESCALER_DIV10
- * @arg @ref LL_USART_PRESCALER_DIV12
- * @arg @ref LL_USART_PRESCALER_DIV16
- * @arg @ref LL_USART_PRESCALER_DIV32
- * @arg @ref LL_USART_PRESCALER_DIV64
- * @arg @ref LL_USART_PRESCALER_DIV128
- * @arg @ref LL_USART_PRESCALER_DIV256
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_8
- * case
- */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
- (((((__PERIPHCLK__) / (USART_PRESCALER_TAB[(__PRESCALER__)])) * 2U) + \
- ((__BAUDRATE__) / 2U)) / \
- (__BAUDRATE__))
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 16 bits sampling mode (32 bits value of
- * USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_USART_PRESCALER_DIV1
- * @arg @ref LL_USART_PRESCALER_DIV2
- * @arg @ref LL_USART_PRESCALER_DIV4
- * @arg @ref LL_USART_PRESCALER_DIV6
- * @arg @ref LL_USART_PRESCALER_DIV8
- * @arg @ref LL_USART_PRESCALER_DIV10
- * @arg @ref LL_USART_PRESCALER_DIV12
- * @arg @ref LL_USART_PRESCALER_DIV16
- * @arg @ref LL_USART_PRESCALER_DIV32
- * @arg @ref LL_USART_PRESCALER_DIV64
- * @arg @ref LL_USART_PRESCALER_DIV128
- * @arg @ref LL_USART_PRESCALER_DIV256
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_16
- * case
- */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
- ((((__PERIPHCLK__) / (USART_PRESCALER_TAB[(__PRESCALER__)])) + \
- ((__BAUDRATE__) / 2U)) / \
- (__BAUDRATE__))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
- * @{
- */
-
-/**
- * @brief USART Enable
- * @rmtoll CR1 UE LL_USART_Enable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief USART Disable (all USART prescalers and outputs are disabled)
- * @note When USART is disabled, USART prescalers and outputs are stopped
- * immediately, and current operations are discarded. The configuration of the
- * USART is kept, but all the status flags, in the USARTx_ISR are set to their
- * default values.
- * @rmtoll CR1 UE LL_USART_Disable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief Indicate if USART is enabled
- * @rmtoll CR1 UE LL_USART_IsEnabled
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief FIFO Mode Enable
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
- * @brief FIFO Mode Disable
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
- * @brief Indicate if FIFO Mode is enabled
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configure TX FIFO Threshold
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
- * @param USARTx USART Instance
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx,
- uint32_t Threshold) {
- ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG,
- Threshold << USART_CR3_TXFTCFG_Pos);
-}
-
-/**
- * @brief Return TX FIFO Threshold Configuration
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
- */
-__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >>
- USART_CR3_TXFTCFG_Pos);
-}
-
-/**
- * @brief Configure RX FIFO Threshold
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
- * @param USARTx USART Instance
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx,
- uint32_t Threshold) {
- ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG,
- Threshold << USART_CR3_RXFTCFG_Pos);
-}
-
-/**
- * @brief Return RX FIFO Threshold Configuration
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
- */
-__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >>
- USART_CR3_RXFTCFG_Pos);
-}
-
-/**
- * @brief Configure TX and RX FIFOs Threshold
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
- * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
- * @param USARTx USART Instance
- * @param TXThreshold This parameter can be one of the following values:
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
- * @param RXThreshold This parameter can be one of the following values:
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
- * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
- * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
- * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx,
- uint32_t TXThreshold,
- uint32_t RXThreshold) {
- ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG,
- (TXThreshold << USART_CR3_TXFTCFG_Pos) |
- (RXThreshold << USART_CR3_RXFTCFG_Pos));
-}
-
-/**
- * @brief USART enabled in STOP Mode.
- * @note When this function is enabled, USART is able to wake up the MCU from
- * Stop mode, provided that USART clock selection is HSI or LSE in RCC.
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR1 UESM LL_USART_EnableInStopMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
- * @brief USART disabled in STOP Mode.
- * @note When this function is disabled, USART is not able to wake up the MCU
- * from Stop mode
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR1 UESM LL_USART_DisableInStopMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
- * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from
- * Stop mode or not)
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Receiver Enable (Receiver is enabled and begins searching for a start
- * bit)
- * @rmtoll CR1 RE LL_USART_EnableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Receiver Disable
- * @rmtoll CR1 RE LL_USART_DisableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Transmitter Enable
- * @rmtoll CR1 TE LL_USART_EnableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Transmitter Disable
- * @rmtoll CR1 TE LL_USART_DisableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Configure simultaneously enabled/disabled states
- * of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
- * CR1 TE LL_USART_SetTransferDirection
- * @param USARTx USART Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx,
- uint32_t TransferDirection) {
- ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE,
- TransferDirection);
-}
-
-/**
- * @brief Return enabled/disabled states of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
- * CR1 TE LL_USART_GetTransferDirection
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
- * @brief Configure Parity (enabled/disabled and parity mode if enabled).
- * @note This function selects if hardware parity control (generation and
- * detection) is enabled or disabled. When the parity control is enabled (Odd or
- * Even), computed parity bit is inserted at the MSB position (9th or 8th bit
- * depending on data width) and parity is checked on the received data.
- * @rmtoll CR1 PS LL_USART_SetParity\n
- * CR1 PCE LL_USART_SetParity
- * @param USARTx USART Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx,
- uint32_t Parity) {
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
- * @brief Return Parity configuration (enabled/disabled and parity mode if
- * enabled)
- * @rmtoll CR1 PS LL_USART_GetParity\n
- * CR1 PCE LL_USART_GetParity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
- * @brief Set Receiver Wake Up method from Mute mode.
- * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
- * @param USARTx USART Instance
- * @param Method This parameter can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx,
- uint32_t Method) {
- MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
- * @brief Return Receiver Wake Up method from Mute mode
- * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
- * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
- * CR1 M1 LL_USART_SetDataWidth
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_7B
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx,
- uint32_t DataWidth) {
- MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
- * @brief Return Word length (i.e. nb of data bits, excluding start and stop
- * bits)
- * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
- * CR1 M1 LL_USART_GetDataWidth
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_7B
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
- * @brief Allow switch between Mute Mode and Active mode
- * @rmtoll CR1 MME LL_USART_EnableMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
- * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
- * @rmtoll CR1 MME LL_USART_DisableMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
- * @brief Indicate if switch between Mute Mode and Active mode is allowed
- * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set Oversampling to 8-bit or 16-bit mode
- * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
- * @param USARTx USART Instance
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx,
- uint32_t OverSampling) {
- MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
- * @brief Return Oversampling mode
- * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
- * @brief Configure if Clock pulse of the last data bit is output to the SCLK
- * pin or not
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
- * @param USARTx USART Instance
- * @param LastBitClockPulse This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(
- USART_TypeDef *USARTx, uint32_t LastBitClockPulse) {
- MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
- * @brief Retrieve Clock pulse of the last data bit output configuration
- * (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
- * @brief Select the phase of the clock output on the SCLK pin in synchronous
- * mode
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_SetClockPhase
- * @param USARTx USART Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx,
- uint32_t ClockPhase) {
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
- * @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_GetClockPhase
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
- * @brief Select the polarity of the clock output on the SCLK pin in
- * synchronous mode
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
- * @param USARTx USART Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx,
- uint32_t ClockPolarity) {
- MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Return polarity of the clock output on the SCLK pin in synchronous
- * mode
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
- * @brief Configure Clock signal format (Phase Polarity and choice about output
- * of last bit clock pulse)
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clock Phase configuration using @ref LL_USART_SetClockPhase()
- * function
- * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity()
- * function
- * - Output of Last bit Clock pulse configuration using @ref
- * LL_USART_SetLastClkPulseOutput() function
- * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
- * CR2 CPOL LL_USART_ConfigClock\n
- * CR2 LBCL LL_USART_ConfigClock
- * @param USARTx USART Instance
- * @param Phase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @param LBCPOutput This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
- uint32_t Polarity,
- uint32_t LBCPOutput) {
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- Phase | Polarity | LBCPOutput);
-}
-
-/**
- * @brief Configure Clock source prescaler for baudrate generator and
- * oversampling
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue This parameter can be one of the following values:
- * @arg @ref LL_USART_PRESCALER_DIV1
- * @arg @ref LL_USART_PRESCALER_DIV2
- * @arg @ref LL_USART_PRESCALER_DIV4
- * @arg @ref LL_USART_PRESCALER_DIV6
- * @arg @ref LL_USART_PRESCALER_DIV8
- * @arg @ref LL_USART_PRESCALER_DIV10
- * @arg @ref LL_USART_PRESCALER_DIV12
- * @arg @ref LL_USART_PRESCALER_DIV16
- * @arg @ref LL_USART_PRESCALER_DIV32
- * @arg @ref LL_USART_PRESCALER_DIV64
- * @arg @ref LL_USART_PRESCALER_DIV128
- * @arg @ref LL_USART_PRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx,
- uint32_t PrescalerValue) {
- MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
-}
-
-/**
- * @brief Retrieve the Clock source prescaler for baudrate generator and
- * oversampling
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PRESCALER_DIV1
- * @arg @ref LL_USART_PRESCALER_DIV2
- * @arg @ref LL_USART_PRESCALER_DIV4
- * @arg @ref LL_USART_PRESCALER_DIV6
- * @arg @ref LL_USART_PRESCALER_DIV8
- * @arg @ref LL_USART_PRESCALER_DIV10
- * @arg @ref LL_USART_PRESCALER_DIV12
- * @arg @ref LL_USART_PRESCALER_DIV16
- * @arg @ref LL_USART_PRESCALER_DIV32
- * @arg @ref LL_USART_PRESCALER_DIV64
- * @arg @ref LL_USART_PRESCALER_DIV128
- * @arg @ref LL_USART_PRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
-}
-
-/**
- * @brief Enable Clock output on SCLK pin
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Disable Clock output on SCLK pin
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
- * @param USARTx USART Instance
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx,
- uint32_t StopBits) {
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Retrieve the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
- * @brief Configure Character frame format (Datawidth, Parity control, Stop
- * Bits)
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Data Width configuration using @ref LL_USART_SetDataWidth()
- * function
- * - Parity Control and mode configuration using @ref
- * LL_USART_SetParity() function
- * - Stop bits configuration using @ref LL_USART_SetStopBitsLength()
- * function
- * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
- * CR1 PCE LL_USART_ConfigCharacter\n
- * CR1 M0 LL_USART_ConfigCharacter\n
- * CR1 M1 LL_USART_ConfigCharacter\n
- * CR2 STOP LL_USART_ConfigCharacter
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_7B
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx,
- uint32_t DataWidth,
- uint32_t Parity,
- uint32_t StopBits) {
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M,
- Parity | DataWidth);
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Configure TX/RX pins swapping setting.
- * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
- * @param USARTx USART Instance
- * @param SwapConfig This parameter can be one of the following values:
- * @arg @ref LL_USART_TXRX_STANDARD
- * @arg @ref LL_USART_TXRX_SWAPPED
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx,
- uint32_t SwapConfig) {
- MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
- * @brief Retrieve TX/RX pins swapping configuration.
- * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_TXRX_STANDARD
- * @arg @ref LL_USART_TXRX_SWAPPED
- */
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
- * @brief Configure RX pin active level logic
- * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
- * @param USARTx USART Instance
- * @param PinInvMethod This parameter can be one of the following values:
- * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx,
- uint32_t PinInvMethod) {
- MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
- * @brief Retrieve RX pin active level logic configuration
- * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
- */
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
- * @brief Configure TX pin active level logic
- * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
- * @param USARTx USART Instance
- * @param PinInvMethod This parameter can be one of the following values:
- * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx,
- uint32_t PinInvMethod) {
- MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
- * @brief Retrieve TX pin active level logic configuration
- * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
- */
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
- * @brief Configure Binary data logic.
- * @note Allow to define how Logical data from the data register are
- * send/received : either in positive/direct logic (1=H, 0=L) or in
- * negative/inverse logic (1=L, 0=H)
- * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
- * @param USARTx USART Instance
- * @param DataLogic This parameter can be one of the following values:
- * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
- * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx,
- uint32_t DataLogic) {
- MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
- * @brief Retrieve Binary data configuration
- * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
- * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
- */
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
- * @brief Configure transfer bit order (either Less or Most Significant Bit
- * First)
- * @note MSB First means data is transmitted/received with the MSB first,
- * following the start bit. LSB First means data is transmitted/received with
- * data bit 0 first, following the start bit.
- * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
- * @param USARTx USART Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_USART_BITORDER_LSBFIRST
- * @arg @ref LL_USART_BITORDER_MSBFIRST
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx,
- uint32_t BitOrder) {
- MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
- * @brief Return transfer bit order (either Less or Most Significant Bit First)
- * @note MSB First means data is transmitted/received with the MSB first,
- * following the start bit. LSB First means data is transmitted/received with
- * data bit 0 first, following the start bit.
- * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_BITORDER_LSBFIRST
- * @arg @ref LL_USART_BITORDER_MSBFIRST
- */
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
- * @brief Enable Auto Baud-Rate Detection
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
- * @brief Disable Auto Baud-Rate Detection
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
- * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set Auto Baud-Rate mode bits
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
- * @param USARTx USART Instance
- * @param AutoBaudRateMode This parameter can be one of the following values:
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx,
- uint32_t AutoBaudRateMode) {
- MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
-}
-
-/**
- * @brief Return Auto Baud-Rate mode
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
- */
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
-}
-
-/**
- * @brief Enable Receiver Timeout
- * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
- * @brief Disable Receiver Timeout
- * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
- * @brief Indicate if Receiver Timeout feature is enabled
- * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set Address of the USART node.
- * @note This is used in multiprocessor communication during Mute mode or Stop
- * mode, for wake up with address mark detection.
- * @note 4bits address node is used when 4-bit Address Detection is selected
- * in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit
- * Address Detection is selected in ADDM7. (This is used in multiprocessor
- * communication during Mute mode or Stop mode, for wake up with 7-bit address
- * mark detection. The MSB of the character sent by the transmitter should be
- * equal to 1. It may also be used for character detection during normal
- * reception, Mute mode inactive (for example, end of block detection in ModBus
- * protocol). In this case, the whole received character (8-bit) is compared to
- * the ADD[7:0] value and CMF flag is set on match)
- * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
- * CR2 ADDM7 LL_USART_ConfigNodeAddress
- * @param USARTx USART Instance
- * @param AddressLen This parameter can be one of the following values:
- * @arg @ref LL_USART_ADDRESS_DETECT_4B
- * @arg @ref LL_USART_ADDRESS_DETECT_7B
- * @param NodeAddress 4 or 7 bit Address of the USART node.
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx,
- uint32_t AddressLen,
- uint32_t NodeAddress) {
- MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
- (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
- * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
- * @note If 4-bit Address Detection is selected in ADDM7,
- * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not
- * relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0)
- * of returned value are relevant (b31-b8 are not relevant)
- * @rmtoll CR2 ADD LL_USART_GetNodeAddress
- * @param USARTx USART Instance
- * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
- */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
- * @brief Return Length of Node Address used in Address Detection mode (7-bit
- * or 4-bit)
- * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_ADDRESS_DETECT_4B
- * @arg @ref LL_USART_ADDRESS_DETECT_7B
- */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
- * @brief Enable RTS HW Flow Control
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Disable RTS HW Flow Control
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Enable CTS HW Flow Control
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Disable CTS HW Flow Control
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
- * CR3 CTSE LL_USART_SetHWFlowCtrl
- * @param USARTx USART Instance
- * @param HardwareFlowControl This parameter can be one of the following
- * values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx,
- uint32_t HardwareFlowControl) {
- MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
- * @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
- * CR3 CTSE LL_USART_GetHWFlowCtrl
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
- * @brief Enable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Disable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Indicate if One bit sampling method is enabled
- * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable Overrun detection
- * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Disable Overrun detection
- * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Indicate if Overrun detection is enabled
- * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR3 WUS LL_USART_SetWKUPType
- * @param USARTx USART Instance
- * @param Type This parameter can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
- * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
- * @arg @ref LL_USART_WAKEUP_ON_RXNE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx,
- uint32_t Type) {
- MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
- * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR3 WUS LL_USART_GetWKUPType
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
- * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
- * @arg @ref LL_USART_WAKEUP_ON_RXNE
- */
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
-}
-
-/**
- * @brief Configure USART BRR register for achieving expected Baud Rate value.
- * @note Compute and set USARTDIV value in BRR Register (full BRR content)
- * according to used Peripheral Clock, Oversampling mode, and expected
- * Baud Rate values
- * @note Peripheral clock and Baud rate values provided as function parameters
- * should be valid (Baud rate value != 0)
- * @note In case of oversampling by 16 and 8, BRR content must be greater than
- * or equal to 16d.
- * @rmtoll BRR BRR LL_USART_SetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param PrescalerValue This parameter can be one of the following values:
- * @arg @ref LL_USART_PRESCALER_DIV1
- * @arg @ref LL_USART_PRESCALER_DIV2
- * @arg @ref LL_USART_PRESCALER_DIV4
- * @arg @ref LL_USART_PRESCALER_DIV6
- * @arg @ref LL_USART_PRESCALER_DIV8
- * @arg @ref LL_USART_PRESCALER_DIV10
- * @arg @ref LL_USART_PRESCALER_DIV12
- * @arg @ref LL_USART_PRESCALER_DIV16
- * @arg @ref LL_USART_PRESCALER_DIV32
- * @arg @ref LL_USART_PRESCALER_DIV64
- * @arg @ref LL_USART_PRESCALER_DIV128
- * @arg @ref LL_USART_PRESCALER_DIV256
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @param BaudRate Baud Rate
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx,
- uint32_t PeriphClk,
- uint32_t PrescalerValue,
- uint32_t OverSampling,
- uint32_t BaudRate) {
- uint32_t usartdiv;
- uint32_t brrtemp;
-
- if (PrescalerValue > LL_USART_PRESCALER_DIV256) {
- /* Do not overstep the size of USART_PRESCALER_TAB */
- } else if (BaudRate == 0U) {
- /* Can Not divide per 0 */
- } else if (OverSampling == LL_USART_OVERSAMPLING_8) {
- usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(
- PeriphClk, (uint8_t)PrescalerValue, BaudRate));
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- USARTx->BRR = brrtemp;
- } else {
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(
- PeriphClk, (uint8_t)PrescalerValue, BaudRate));
- }
-}
-
-/**
- * @brief Return current Baud Rate value, according to USARTDIV present in BRR
- * register (full BRR content), and to used Peripheral Clock and Oversampling
- * mode values
- * @note In case of non-initialized or invalid value stored in BRR register,
- * value 0 will be returned.
- * @note In case of oversampling by 16 and 8, BRR content must be greater than
- * or equal to 16d.
- * @rmtoll BRR BRR LL_USART_GetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param PrescalerValue This parameter can be one of the following values:
- * @arg @ref LL_USART_PRESCALER_DIV1
- * @arg @ref LL_USART_PRESCALER_DIV2
- * @arg @ref LL_USART_PRESCALER_DIV4
- * @arg @ref LL_USART_PRESCALER_DIV6
- * @arg @ref LL_USART_PRESCALER_DIV8
- * @arg @ref LL_USART_PRESCALER_DIV10
- * @arg @ref LL_USART_PRESCALER_DIV12
- * @arg @ref LL_USART_PRESCALER_DIV16
- * @arg @ref LL_USART_PRESCALER_DIV32
- * @arg @ref LL_USART_PRESCALER_DIV64
- * @arg @ref LL_USART_PRESCALER_DIV128
- * @arg @ref LL_USART_PRESCALER_DIV256
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval Baud Rate
- */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx,
- uint32_t PeriphClk,
- uint32_t PrescalerValue,
- uint32_t OverSampling) {
- uint32_t usartdiv;
- uint32_t brrresult = 0x0U;
- uint32_t periphclkpresc =
- (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
-
- usartdiv = USARTx->BRR;
-
- if (usartdiv == 0U) {
- /* Do not perform a division by 0 */
- } else if (OverSampling == LL_USART_OVERSAMPLING_8) {
- usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U));
- if (usartdiv != 0U) {
- brrresult = (periphclkpresc * 2U) / usartdiv;
- }
- } else {
- if ((usartdiv & 0xFFFFU) != 0U) {
- brrresult = periphclkpresc / usartdiv;
- }
- }
- return (brrresult);
-}
-
-/**
- * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
- * @rmtoll RTOR RTO LL_USART_SetRxTimeout
- * @param USARTx USART Instance
- * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx,
- uint32_t Timeout) {
- MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
-}
-
-/**
- * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
- * @rmtoll RTOR RTO LL_USART_GetRxTimeout
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
- */
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
-}
-
-/**
- * @brief Set Block Length value in reception
- * @rmtoll RTOR BLEN LL_USART_SetBlockLength
- * @param USARTx USART Instance
- * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx,
- uint32_t BlockLength) {
- MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
-}
-
-/**
- * @brief Get Block Length value in reception
- * @rmtoll RTOR BLEN LL_USART_GetBlockLength
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >>
- USART_RTOR_BLEN_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to
- * Irda feature
- * @{
- */
-
-/**
- * @brief Enable IrDA mode
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_EnableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Disable IrDA mode
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_DisableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Indicate if IrDA mode is enabled
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
- * @param USARTx USART Instance
- * @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_IRDA_POWER_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx,
- uint32_t PowerMode) {
- MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
- * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
- * @brief Set Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx,
- uint32_t PrescalerValue) {
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
- * @brief Return Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
- * @param USARTx USART Instance
- * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions
- * related to Smartcard feature
- * @{
- */
-
-/**
- * @brief Enable Smartcard NACK transmission
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Disable Smartcard NACK transmission
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable Smartcard mode
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Disable Smartcard mode
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Indicate if Smartcard mode is enabled
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @note This bit-field specifies the number of retries in transmit and
- * receive, in Smartcard mode. In transmission mode, it specifies the number of
- * automatic retransmission retries, before generating a transmission error (FE
- * bit set). In reception mode, it specifies the number or erroneous reception
- * trials, before generating a reception error (RXNE and PE bits set)
- * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
- * @param USARTx USART Instance
- * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(
- USART_TypeDef *USARTx, uint32_t AutoRetryCount) {
- MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT,
- AutoRetryCount << USART_CR3_SCARCNT_Pos);
-}
-
-/**
- * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
- * @param USARTx USART Instance
- * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and
- * Max_Data=7)
- */
-__STATIC_INLINE uint32_t
-LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >>
- USART_CR3_SCARCNT_Pos);
-}
-
-/**
- * @brief Set Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx,
- uint32_t PrescalerValue) {
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
- * @brief Return Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
- * @param USARTx USART Instance
- * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @brief Set Smartcard Guard time value, expressed in nb of baud clocks
- * periods (GT[7:0] bits : Guard time value)
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
- * @param USARTx USART Instance
- * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx,
- uint32_t GuardTime) {
- MODIFY_REG(USARTx->GTPR, USART_GTPR_GT,
- (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
-}
-
-/**
- * @brief Return Smartcard Guard time value, expressed in nb of baud clocks
- * periods (GT[7:0] bits : Guard time value)
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
- * @param USARTx USART Instance
- * @retval Smartcard Guard time value (Value between Min_Data=0x00 and
- * Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions
- * related to Half Duplex feature
- * @{
- */
-
-/**
- * @brief Enable Single Wire Half-Duplex mode
- * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
- * whether or not Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Disable Single Wire Half-Duplex mode
- * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
- * whether or not Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
- * whether or not Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions
- * related to SPI Slave feature
- * @{
- */
-/**
- * @brief Enable SPI Synchronous Slave mode
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
-}
-
-/**
- * @brief Disable SPI Synchronous Slave mode
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
-}
-
-/**
- * @brief Indicate if SPI Synchronous Slave mode is enabled
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable SPI Slave Selection using NSS input pin
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @note SPI Slave Selection depends on NSS input pin
- * (The slave is selected when NSS is low and deselected when NSS is
- * high).
- * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
-}
-
-/**
- * @brief Disable SPI Slave Selection using NSS input pin
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @note SPI Slave will be always selected and NSS input pin will be ignored.
- * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
-}
-
-/**
- * @brief Indicate if SPI Slave Selection depends on NSS input pin
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to
- * LIN feature
- * @{
- */
-
-/**
- * @brief Set LIN Break Detection Length
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @param LINBDLength This parameter can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx,
- uint32_t LINBDLength) {
- MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
- * @brief Return LIN Break Detection Length
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
- * @brief Enable LIN mode
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_EnableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Disable LIN mode
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_DisableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Indicate if LIN mode is enabled
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to
- * Driver Enable feature
- * @{
- */
-
-/**
- * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5
- * bits ([4:0] bits).
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
- * @param USARTx USART Instance
- * @param Time Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx,
- uint32_t Time) {
- MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
- * @brief Return DEDT (Driver Enable De-Assertion Time)
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
- * @param USARTx USART Instance
- * @retval Time value expressed on 5 bits ([4:0] bits) : Value between
- * Min_Data=0 and Max_Data=31
- */
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >>
- USART_CR1_DEDT_Pos);
-}
-
-/**
- * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5
- * bits ([4:0] bits).
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
- * @param USARTx USART Instance
- * @param Time Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx,
- uint32_t Time) {
- MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
- * @brief Return DEAT (Driver Enable Assertion Time)
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
- * @param USARTx USART Instance
- * @retval Time value expressed on 5 bits ([4:0] bits) : Value between
- * Min_Data=0 and Max_Data=31
- */
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >>
- USART_CR1_DEAT_Pos);
-}
-
-/**
- * @brief Enable Driver Enable (DE) Mode
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEM LL_USART_EnableDEMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
- * @brief Disable Driver Enable (DE) Mode
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEM LL_USART_DisableDEMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
- * @brief Indicate if Driver Enable (DE) Mode is enabled
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Select Driver Enable Polarity
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
- * @param USARTx USART Instance
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_USART_DE_POLARITY_HIGH
- * @arg @ref LL_USART_DE_POLARITY_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx,
- uint32_t Polarity) {
- MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
- * @brief Return Driver Enable Polarity
- * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
- * whether or not Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DE_POLARITY_HIGH
- * @arg @ref LL_USART_DE_POLARITY_LOW
- */
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) {
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
- * @{
- */
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Asynchronous
- * Mode (UART)
- * @note In UART mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Asynchronous Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
- * CR2 CLKEN LL_USART_ConfigAsyncMode\n
- * CR3 SCEN LL_USART_ConfigAsyncMode\n
- * CR3 IREN LL_USART_ConfigAsyncMode\n
- * CR3 HDSEL LL_USART_ConfigAsyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) {
- /* In Asynchronous mode, the following bits must be kept cleared:
- - LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Synchronous
- * Mode
- * @note In Synchronous mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the USART in Synchronous mode.
- * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * @note Other remaining configurations items related to Synchronous Mode
- * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be
- * set using dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
- * CR2 CLKEN LL_USART_ConfigSyncMode\n
- * CR3 SCEN LL_USART_ConfigSyncMode\n
- * CR3 IREN LL_USART_ConfigSyncMode\n
- * CR3 HDSEL LL_USART_ConfigSyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) {
- /* In Synchronous mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
- /* set the UART/USART in Synchronous mode */
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in LIN Mode
- * @note In LIN mode, the following bits must be kept cleared:
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also set the UART/USART in LIN mode.
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
- * @note Other remaining configurations items related to LIN Mode
- * (as Baud Rate, Word length, LIN Break Detection Length, ...) should
- * be set using dedicated functions
- * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
- * CR2 STOP LL_USART_ConfigLINMode\n
- * CR2 LINEN LL_USART_ConfigLINMode\n
- * CR3 IREN LL_USART_ConfigLINMode\n
- * CR3 SCEN LL_USART_ConfigLINMode\n
- * CR3 HDSEL LL_USART_ConfigLINMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) {
- /* In LIN mode, the following bits must be kept cleared:
- - STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
- /* Set the UART/USART in LIN mode */
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Half Duplex
- * Mode
- * @note In Half Duplex mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * This function also sets the UART/USART in Half Duplex mode.
- * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
- * whether or not Half-Duplex mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
- * @note Other remaining configurations items related to Half Duplex Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
- * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
- * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 IREN LL_USART_ConfigHalfDuplexMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) {
- /* In Half Duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
- /* set the UART/USART in Half Duplex mode */
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Smartcard
- * Mode
- * @note In Smartcard mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also configures Stop bits to 1.5 bits and
- * sets the USART in Smartcard mode (SCEN bit).
- * Clock Output is also enabled (CLKEN).
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength()
- * function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
- * @note Other remaining configurations items related to Smartcard Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
- * CR2 STOP LL_USART_ConfigSmartcardMode\n
- * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
- * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
- * CR3 SCEN LL_USART_ConfigSmartcardMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) {
- /* In Smartcard mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
- /* Configure Stop bits to 1.5 bits */
- /* Synchronous mode is activated by default */
- SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
- /* set the UART/USART in Smartcard mode */
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Irda Mode
- * @note In IRDA mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength()
- * function
- * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
- * @note Other remaining configurations items related to Irda Mode
- * (as Baud Rate, Word length, Power mode, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
- * CR2 CLKEN LL_USART_ConfigIrdaMode\n
- * CR2 STOP LL_USART_ConfigIrdaMode\n
- * CR3 SCEN LL_USART_ConfigIrdaMode\n
- * CR3 HDSEL LL_USART_ConfigIrdaMode\n
- * CR3 IREN LL_USART_ConfigIrdaMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) {
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
- /* set the UART/USART in IRDA mode */
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Multi
- * processor Mode (several USARTs connected in a network, one of the USARTs can
- * be the master, its TX output connected to the RX inputs of the other slaves
- * USARTs).
- * @note In MultiProcessor mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call
- * sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Multi processor Mode
- * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
- * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
- * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
- * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
- * CR3 IREN LL_USART_ConfigMultiProcessMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) {
- /* In Multi Processor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.
- */
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if the USART Parity Error Flag is set or not
- * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the USART Framing Error Flag is set or not
- * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the USART Noise error detected Flag is set or not
- * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if the USART OverRun Error Flag is set or not
- * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART IDLE line detected Flag is set or not
- * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL
- : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
-
-/**
- * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag
- * is set or not
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) {
- return (
- (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Transmission Complete Flag is set or not
- * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
-
-/**
- * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not
- * Full Flag is set or not
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART CTS interrupt Flag is set or not
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART CTS Flag is set or not
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Receiver Time Out Flag is set or not
- * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART End Of Block Flag is set or not
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the SPI Slave Underrun error flag is set or not
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Auto-Baud Rate Flag is set or not
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Busy Flag is set or not
- * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Character Match Flag is set or not
- * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Send Break Flag is set or not
- * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
- * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Wake Up from stop mode Flag is set or not
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
- * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
- * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART TX FIFO Empty Flag is set or not
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART RX FIFO Full Flag is set or not
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag
- * is set or not
- * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART TX FIFO Threshold Flag is set or not
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART RX FIFO Threshold Flag is set or not
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Clear Parity Error Flag
- * @rmtoll ICR PECF LL_USART_ClearFlag_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_PECF);
-}
-
-/**
- * @brief Clear Framing Error Flag
- * @rmtoll ICR FECF LL_USART_ClearFlag_FE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_FECF);
-}
-
-/**
- * @brief Clear Noise Error detected Flag
- * @rmtoll ICR NECF LL_USART_ClearFlag_NE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_NECF);
-}
-
-/**
- * @brief Clear OverRun Error Flag
- * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
- * @brief Clear IDLE line detected Flag
- * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
- * @brief Clear TX FIFO Empty Flag
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
-}
-
-/**
- * @brief Clear Transmission Complete Flag
- * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
-}
-
-/**
- * @brief Clear Smartcard Transmission Complete Before Guard Time Flag
- * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
-}
-
-/**
- * @brief Clear LIN Break Detection Flag
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
-}
-
-/**
- * @brief Clear CTS Interrupt Flag
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
- * @brief Clear Receiver Time Out Flag
- * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
-}
-
-/**
- * @brief Clear End Of Block Flag
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
-}
-
-/**
- * @brief Clear SPI Slave Underrun Flag
- * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
- * or not SPI Slave mode feature is supported by the USARTx instance.
- * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
-}
-
-/**
- * @brief Clear Character Match Flag
- * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
- * @brief Clear Wake Up from stop mode Flag
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) {
- WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
-
-/**
- * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
- * @brief Enable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
-
-/**
- * @brief Enable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
- * @brief Enable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Enable Character Match Interrupt
- * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
- * @brief Enable Receiver Timeout Interrupt
- * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
- * @brief Enable End Of Block Interrupt
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
- * @brief Enable TX FIFO Empty Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
- * @brief Enable RX FIFO Full Interrupt
- * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
- * @brief Enable LIN Break Detection Interrupt
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Enable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
- * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
- * NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt
- * is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
- * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Enable CTS Interrupt
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Enable Wake Up from Stop Mode Interrupt
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
- * @brief Enable TX FIFO Threshold Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
- * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-
-/**
- * @brief Enable RX FIFO Threshold Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
- * @brief Disable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
-
-/**
- * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
- * @brief Disable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
-
-/**
- * @brief Disable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
- * @brief Disable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Disable Character Match Interrupt
- * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
- * @brief Disable Receiver Timeout Interrupt
- * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
- * @brief Disable End Of Block Interrupt
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
- * @brief Disable TX FIFO Empty Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
- * @brief Disable RX FIFO Full Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
- * @brief Disable LIN Break Detection Interrupt
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Disable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
- * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
- * NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt
- * is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
- * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Disable CTS Interrupt
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Disable Wake Up from Stop Mode Interrupt
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
- * @brief Disable TX FIFO Threshold Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
- * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-
-/**
- * @brief Disable RX FIFO Threshold Interrupt
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
- * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
- * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE))
- ? 1UL
- : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
-
-/**
- * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt
- * is enabled or disabled.
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) ==
- (USART_CR1_RXNEIE_RXFNEIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Transmission Complete Interrupt is enabled or
- * disabled.
- * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL
- : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
-
-/**
- * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is
- * enabled or disabled
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) ==
- (USART_CR1_TXEIE_TXFNFIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
- * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Character Match Interrupt is enabled or disabled.
- * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
- * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Interrupt is enabled or
- * disabled.
- * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
- * not LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Error Interrupt is enabled or disabled.
- * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
- * not Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or
- * disabled.
- * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
- * whether or not Wake-up from Stop mode feature is supported by the USARTx
- * instance.
- * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if the Smartcard Transmission Complete Before Guard Time
- * Interrupt is enabled or disabled.
- * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
- * not Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE))
- ? 1UL
- : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
- * @{
- */
-
-/**
- * @brief Enable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Disable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for reception
- * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) {
- ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Disable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) {
- ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for transmission
- * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Enable DMA Disabling on Reception Error
- * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
- * @brief Disable DMA Disabling on Reception Error
- * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) {
- CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
- * @brief Indicate if DMA Disabling on Reception Error is disabled
- * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t
-LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) {
- return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL
- : 0UL);
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
- * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
- * @param USARTx USART Instance
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
- * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx,
- uint32_t Direction) {
- uint32_t data_reg_addr;
-
- if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) {
- /* return address of TDR register */
- data_reg_addr = (uint32_t) & (USARTx->TDR);
- } else {
- /* return address of RDR register */
- data_reg_addr = (uint32_t) & (USARTx->RDR);
- }
-
- return data_reg_addr;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 8 bits)
- * @rmtoll RDR RDR LL_USART_ReceiveData8
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) {
- return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 9 bits)
- * @rmtoll RDR RDR LL_USART_ReceiveData9
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
- */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) {
- return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
- * @rmtoll TDR TDR LL_USART_TransmitData8
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx,
- uint8_t Value) {
- USARTx->TDR = Value;
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
- * @rmtoll TDR TDR LL_USART_TransmitData9
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0x1FF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx,
- uint16_t Value) {
- USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Execution Execution
- * @{
- */
-
-/**
- * @brief Request an Automatic Baud Rate measurement on next received data
- * frame
- * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
- * check whether or not Auto Baud Rate detection feature is supported by the
- * USARTx instance.
- * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
-}
-
-/**
- * @brief Request Break sending
- * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
- * @brief Put USART in mute mode and set the RWU flag
- * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
- * @brief Request a Receive Data and FIFO flush
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @note Allows to discard the received data without reading them, and avoid
- * an overrun condition.
- * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
- * @brief Request a Transmit data and FIFO flush
- * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
- * not FIFO mode feature is supported by the USARTx instance.
- * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) {
- SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx,
- LL_USART_InitTypeDef *USART_InitStruct);
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(
- USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_USART_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_USART_H
+#define STM32G4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || \
+ defined(UART5)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+ * @{
+ */
+/* Array used to get the USART prescaler division decimal values versus @ref
+ * USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] = {
+ 1UL, 2UL, 4UL, 6UL, 8UL, 10UL, 12UL, 16UL, 32UL, 64UL, 128UL, 256UL};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct {
+ uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the
+ communication baud rate. This parameter can be a
+ value of @ref USART_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_USART_SetPrescaler().*/
+
+ uint32_t
+ BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or
+ received in a frame. This parameter can be a value of
+ @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t
+ StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t
+ Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit
+ mode is enabled or disabled. This parameter can
+ be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using
+ unitary function @ref
+ LL_USART_SetTransferDirection().*/
+
+ uint32_t
+ HardwareFlowControl; /*!< Specifies whether the hardware flow control mode
+ is enabled or disabled. This parameter can be a
+ value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16
+ or 8. This parameter can be a value of @ref
+ USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using
+ unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct {
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or
+ disabled. This parameter can be a value of @ref
+ USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards
+ using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref
+ LL_USART_DisableSCLKOutput(). For more details, refer
+ to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref
+ USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards
+ using unitary functions @ref
+ LL_USART_SetClockPolarity(). For more details,
+ refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit
+ capture is made. This parameter can be a value of @ref
+ USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards
+ using unitary functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this
+ function. */
+
+ uint32_t
+ LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to
+ the last transmitted data bit (MSB) has to be output
+ on the SCLK pin in synchronous mode. This parameter
+ can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards
+ using unitary functions @ref
+ LL_USART_SetLastClkPulseOutput(). For more details,
+ refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_USART_WriteReg function
+ * @{
+ */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF \
+ USART_ICR_NECF /*!< Noise error detected clear flag \
+ */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF \
+ USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF \
+ USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF \
+ USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag \
+ */
+#define LL_USART_ICR_LBDCF \
+ USART_ICR_LBDCF /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF \
+ USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag \
+ */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF \
+ USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE \
+ USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF \
+ USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full \
+ flag*/
+#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
+#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_USART_ISR_RWU \
+ USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK \
+ USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK \
+ USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT \
+ USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag \
+ */
+#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and
+ * LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE \
+ USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty \
+ interrupt enable */
+#define LL_USART_CR1_TCIE \
+ USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE \
+ USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not \
+ full interrupt enable */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR1_CMIE \
+ USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE \
+ USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE \
+ USART_CR1_EOBIE /*!< End of Block interrupt enable \
+ */
+#define LL_USART_CR1_TXFEIE \
+ USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE \
+ USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE \
+ USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE \
+ USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE \
+ USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE \
+ USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt \
+ enable */
+#define LL_USART_CR3_RXFTIE \
+ USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+ * @{
+ */
+#define LL_USART_FIFOTHRESHOLD_1_8 \
+ 0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4 \
+ 0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2 \
+ 0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4 \
+ 0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8 \
+ 0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8 \
+ 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE \
+ 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX \
+ USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX \
+ USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX \
+ (USART_CR1_TE | USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN \
+ USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD \
+ (USART_CR1_PCE | \
+ USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE \
+ 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK \
+ USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_USART_DATAWIDTH_7B \
+ USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits \
+ */
+#define LL_USART_DATAWIDTH_8B \
+ 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B \
+ USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits \
+ */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT \
+ 0x00000000U /*!< The clock pulse of the last data bit is not output to the \
+ SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT \
+ USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the \
+ SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE \
+ 0x00000000U /*!< The first clock transition is the first data capture edge \
+ */
+#define LL_USART_PHASE_2EDGE \
+ USART_CR2_CPHA /*!< The second clock transition is the first data capture \
+ edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW \
+ 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH \
+ USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission \
+ window */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+ * @{
+ */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 \
+ (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 \
+ (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 \
+ (USART_PRESC_PRESCALER_1 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 \
+ (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 \
+ (USART_PRESC_PRESCALER_2 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 \
+ (USART_PRESC_PRESCALER_2 | \
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 \
+ (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 \
+ (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 \
+ (USART_PRESC_PRESCALER_3 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 \
+ (USART_PRESC_PRESCALER_3 | \
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 \
+ (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | \
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 \
+ (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_USART_TXRX_STANDARD \
+ 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED \
+ (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_RXPIN_LEVEL_STANDARD \
+ 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED \
+ (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_TXPIN_LEVEL_STANDARD \
+ 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED \
+ (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_USART_BINARY_LOGIC_POSITIVE \
+ 0x00000000U /*!< Logical data from the data register are send/received in \
+ positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE \
+ USART_CR2_DATAINV /*!< Logical data from the data register are send/received \
+ in negative/inverse logic. (1=L, 0=H). The parity bit \
+ is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_USART_BITORDER_LSBFIRST \
+ 0x00000000U /*!< data is transmitted/received with data bit 0 first, \
+ following the start bit */
+#define LL_USART_BITORDER_MSBFIRST \
+ USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, \
+ following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ * @{
+ */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT \
+ 0x00000000U /*!< Measurement of the start bit is used to detect the baud \
+ rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE \
+ USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received \
+ frame must start with a single bit = 1 -> Frame = \
+ Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME \
+ USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME \
+ (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_USART_ADDRESS_DETECT_4B \
+ 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B \
+ USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method \
+ selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE \
+ 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS \
+ USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is \
+ space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS \
+ USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS \
+ input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS \
+ (USART_CR3_RTSE | \
+ USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ * @{
+ */
+#define LL_USART_WAKEUP_ON_ADDRESS \
+ 0x00000000U /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT \
+ USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE \
+ (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B \
+ 0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B \
+ USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_USART_DMA_REG_DATA_TRANSMIT \
+ 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE \
+ 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) \
+ WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV
+ * is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8
+ * case
+ */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__) / (USART_PRESCALER_TAB[(__PRESCALER__)])) * 2U) + \
+ ((__BAUDRATE__) / 2U)) / \
+ (__BAUDRATE__))
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of
+ * USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16
+ * case
+ */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__) / (USART_PRESCALER_TAB[(__PRESCALER__)])) + \
+ ((__BAUDRATE__) / 2U)) / \
+ (__BAUDRATE__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped
+ * immediately, and current operations are discarded. The configuration of the
+ * USART is kept, but all the status flags, in the USARTx_ISR are set to their
+ * default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief FIFO Mode Enable
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief FIFO Mode Disable
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief Indicate if FIFO Mode is enabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configure TX FIFO Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
+ * @param USARTx USART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx,
+ uint32_t Threshold) {
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG,
+ Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Return TX FIFO Threshold Configuration
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >>
+ USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure RX FIFO Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
+ * @param USARTx USART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx,
+ uint32_t Threshold) {
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG,
+ Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Return RX FIFO Threshold Configuration
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >>
+ USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure TX and RX FIFOs Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
+ * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
+ * @param USARTx USART Instance
+ * @param TXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @param RXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx,
+ uint32_t TXThreshold,
+ uint32_t RXThreshold) {
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG,
+ (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+ * @brief USART enabled in STOP Mode.
+ * @note When this function is enabled, USART is able to wake up the MCU from
+ * Stop mode, provided that USART clock selection is HSI or LSE in RCC.
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR1 UESM LL_USART_EnableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief USART disabled in STOP Mode.
+ * @note When this function is disabled, USART is not able to wake up the MCU
+ * from Stop mode
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR1 UESM LL_USART_DisableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from
+ * Stop mode or not)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start
+ * bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx,
+ uint32_t TransferDirection) {
+ ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE,
+ TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and
+ * detection) is enabled or disabled. When the parity control is enabled (Odd or
+ * Even), computed parity bit is inserted at the MSB position (9th or 8th bit
+ * depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx,
+ uint32_t Parity) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if
+ * enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx,
+ uint32_t Method) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
+ * CR1 M1 LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx,
+ uint32_t DataWidth) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop
+ * bits)
+ * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
+ * CR1 M1 LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_USART_EnableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_USART_DisableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx,
+ uint32_t OverSampling) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK
+ * pin or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(
+ USART_TypeDef *USARTx, uint32_t LastBitClockPulse) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous
+ * mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx,
+ uint32_t ClockPhase) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in
+ * synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx,
+ uint32_t ClockPolarity) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous
+ * mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output
+ * of last bit clock pulse)
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase()
+ * function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity()
+ * function
+ * - Output of Last bit Clock pulse configuration using @ref
+ * LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
+ uint32_t Polarity,
+ uint32_t LBCPOutput) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ Phase | Polarity | LBCPOutput);
+}
+
+/**
+ * @brief Configure Clock source prescaler for baudrate generator and
+ * oversampling
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx,
+ uint32_t PrescalerValue) {
+ MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Retrieve the Clock source prescaler for baudrate generator and
+ * oversampling
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx,
+ uint32_t StopBits) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop
+ * Bits)
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth()
+ * function
+ * - Parity Control and mode configuration using @ref
+ * LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength()
+ * function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M0 LL_USART_ConfigCharacter\n
+ * CR1 M1 LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx,
+ uint32_t DataWidth,
+ uint32_t Parity,
+ uint32_t StopBits) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M,
+ Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
+ * @param USARTx USART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx,
+ uint32_t SwapConfig) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx,
+ uint32_t PinInvMethod) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx,
+ uint32_t PinInvMethod) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ * @note Allow to define how Logical data from the data register are
+ * send/received : either in positive/direct logic (1=H, 0=L) or in
+ * negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx,
+ uint32_t DataLogic) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit
+ * First)
+ * @note MSB First means data is transmitted/received with the MSB first,
+ * following the start bit. LSB First means data is transmitted/received with
+ * data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
+ * @param USARTx USART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx,
+ uint32_t BitOrder) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first,
+ * following the start bit. LSB First means data is transmitted/received with
+ * data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Enable Auto Baud-Rate Detection
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Disable Auto Baud-Rate Detection
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set Auto Baud-Rate mode bits
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @param AutoBaudRateMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx,
+ uint32_t AutoBaudRateMode) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+ * @brief Return Auto Baud-Rate mode
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+ * @brief Enable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Disable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Indicate if Receiver Timeout feature is enabled
+ * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop
+ * mode, for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected
+ * in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit
+ * Address Detection is selected in ADDM7. (This is used in multiprocessor
+ * communication during Mute mode or Stop mode, for wake up with 7-bit address
+ * mark detection. The MSB of the character sent by the transmitter should be
+ * equal to 1. It may also be used for character detection during normal
+ * reception, Mute mode inactive (for example, end of block detection in ModBus
+ * protocol). In this case, the whole received character (8-bit) is compared to
+ * the ADD[7:0] value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_USART_ConfigNodeAddress
+ * @param USARTx USART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx,
+ uint32_t AddressLen,
+ uint32_t NodeAddress) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not
+ * relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0)
+ * of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit
+ * or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following
+ * values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx,
+ uint32_t HardwareFlowControl) {
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR3 WUS LL_USART_SetWKUPType
+ * @param USARTx USART Instance
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx,
+ uint32_t Type) {
+ MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+ * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR3 WUS LL_USART_GetWKUPType
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected
+ * Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters
+ * should be valid (Baud rate value != 0)
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than
+ * or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx,
+ uint32_t PeriphClk,
+ uint32_t PrescalerValue,
+ uint32_t OverSampling,
+ uint32_t BaudRate) {
+ uint32_t usartdiv;
+ uint32_t brrtemp;
+
+ if (PrescalerValue > LL_USART_PRESCALER_DIV256) {
+ /* Do not overstep the size of USART_PRESCALER_TAB */
+ } else if (BaudRate == 0U) {
+ /* Can Not divide per 0 */
+ } else if (OverSampling == LL_USART_OVERSAMPLING_8) {
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(
+ PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ USARTx->BRR = brrtemp;
+ } else {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(
+ PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR
+ * register (full BRR content), and to used Peripheral Clock and Oversampling
+ * mode values
+ * @note In case of non-initialized or invalid value stored in BRR register,
+ * value 0 will be returned.
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than
+ * or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx,
+ uint32_t PeriphClk,
+ uint32_t PrescalerValue,
+ uint32_t OverSampling) {
+ uint32_t usartdiv;
+ uint32_t brrresult = 0x0U;
+ uint32_t periphclkpresc =
+ (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+ usartdiv = USARTx->BRR;
+
+ if (usartdiv == 0U) {
+ /* Do not perform a division by 0 */
+ } else if (OverSampling == LL_USART_OVERSAMPLING_8) {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U));
+ if (usartdiv != 0U) {
+ brrresult = (periphclkpresc * 2U) / usartdiv;
+ }
+ } else {
+ if ((usartdiv & 0xFFFFU) != 0U) {
+ brrresult = periphclkpresc / usartdiv;
+ }
+ }
+ return (brrresult);
+}
+
+/**
+ * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_SetRxTimeout
+ * @param USARTx USART Instance
+ * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx,
+ uint32_t Timeout) {
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+ * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_GetRxTimeout
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+ * @brief Set Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_SetBlockLength
+ * @param USARTx USART Instance
+ * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx,
+ uint32_t BlockLength) {
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @brief Get Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_GetBlockLength
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >>
+ USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to
+ * Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx,
+ uint32_t PowerMode) {
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx,
+ uint32_t PrescalerValue) {
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions
+ * related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @note This bit-field specifies the number of retries in transmit and
+ * receive, in Smartcard mode. In transmission mode, it specifies the number of
+ * automatic retransmission retries, before generating a transmission error (FE
+ * bit set). In reception mode, it specifies the number or erroneous reception
+ * trials, before generating a reception error (RXNE and PE bits set)
+ * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(
+ USART_TypeDef *USARTx, uint32_t AutoRetryCount) {
+ MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT,
+ AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and
+ * Max_Data=7)
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >>
+ USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx,
+ uint32_t PrescalerValue) {
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks
+ * periods (GT[7:0] bits : Guard time value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx,
+ uint32_t GuardTime) {
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT,
+ (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks
+ * periods (GT[7:0] bits : Guard time value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and
+ * Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions
+ * related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
+ * whether or not Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
+ * whether or not Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
+ * whether or not Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions
+ * related to SPI Slave feature
+ * @{
+ */
+/**
+ * @brief Enable SPI Synchronous Slave mode
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+ * @brief Disable SPI Synchronous Slave mode
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+ * @brief Indicate if SPI Synchronous Slave mode is enabled
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable SPI Slave Selection using NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @note SPI Slave Selection depends on NSS input pin
+ * (The slave is selected when NSS is low and deselected when NSS is
+ * high).
+ * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+ * @brief Disable SPI Slave Selection using NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @note SPI Slave will be always selected and NSS input pin will be ignored.
+ * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+ * @brief Indicate if SPI Slave Selection depends on NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to
+ * LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx,
+ uint32_t LINBDLength) {
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to
+ * Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5
+ * bits ([4:0] bits).
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx,
+ uint32_t Time) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between
+ * Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >>
+ USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5
+ * bits ([4:0] bits).
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx,
+ uint32_t Time) {
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between
+ * Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >>
+ USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_EnableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_DisableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
+ * @param USARTx USART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx,
+ uint32_t Polarity) {
+ MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check
+ * whether or not Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t
+LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) {
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous
+ * Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) {
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous
+ * Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be
+ * set using dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) {
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should
+ * be set using dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) {
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex
+ * Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check
+ * whether or not Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) {
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard
+ * Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength()
+ * function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) {
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength()
+ * function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) {
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi
+ * processor Mode (several USARTs connected in a network, one of the USARTs can
+ * be the master, its TX output connected to the RX inputs of the other slaves
+ * USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call
+ * sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) {
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL
+ : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_RXNE \
+ LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag
+ * is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) {
+ return (
+ (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_TXE \
+ LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not
+ * Full Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS interrupt Flag is set or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receiver Time Out Flag is set or not
+ * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART End Of Block Flag is set or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the SPI Slave Underrun error flag is set or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Flag is set or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Wake Up from stop mode Flag is set or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART TX FIFO Empty Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Full Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag
+ * is set or not
+ * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART TX FIFO Threshold Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Threshold Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise Error detected Flag
+ * @rmtoll ICR NECF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+ * @brief Clear TX FIFO Empty Flag
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+ * @brief Clear Smartcard Transmission Complete Before Guard Time Flag
+ * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Receiver Time Out Flag
+ * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+ * @brief Clear End Of Block Flag
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+ * @brief Clear SPI Slave Underrun Flag
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether
+ * or not SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @brief Clear Wake Up from stop mode Flag
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) {
+ WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_EnableIT_RXNE \
+ LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_EnableIT_TXE \
+ LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Enable TX Empty and TX FIFO Not Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Enable End Of Block Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Enable TX FIFO Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Enable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
+ * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
+ * NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt
+ * is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable Wake Up from Stop Mode Interrupt
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+ * @brief Enable TX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+ * @brief Enable RX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_DisableIT_RXNE \
+ LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_DisableIT_TXE \
+ LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Disable TX Empty and TX FIFO Not Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Disable End Of Block Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Disable TX FIFO Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Disable RX FIFO Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation
+ * in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or
+ * NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt
+ * is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable Wake Up from Stop Mode Interrupt
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+ * @brief Disable TX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+ * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+ * @brief Disable RX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE))
+ ? 1UL
+ : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_RXNE \
+ LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt
+ * is enabled or disabled.
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) ==
+ (USART_CR1_RXNEIE_RXFNEIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or
+ * disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL
+ : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_TXE \
+ LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+ * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is
+ * enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) ==
+ (USART_CR1_TXEIE_TXFNFIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+ * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or
+ * disabled.
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or
+ * not LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or
+ * not Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or
+ * disabled.
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check
+ * whether or not Wake-up from Stop mode feature is supported by the USARTx
+ * instance.
+ * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if the Smartcard Transmission Complete Before Guard Time
+ * Interrupt is enabled or disabled.
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or
+ * not Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE))
+ ? 1UL
+ : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) {
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) {
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) {
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t
+LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) {
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL
+ : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
+ * @param USARTx USART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx,
+ uint32_t Direction) {
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) & (USARTx->TDR);
+ } else {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) & (USARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) {
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) {
+ return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx,
+ uint8_t Value) {
+ USARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx,
+ uint16_t Value) {
+ USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request an Automatic Baud Rate measurement on next received data
+ * frame
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to
+ * check whether or not Auto Baud Rate detection feature is supported by the
+ * USARTx instance.
+ * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put USART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+ * @brief Request a Receive Data and FIFO flush
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @note Allows to discard the received data without reading them, and avoid
+ * an overrun condition.
+ * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+ * @brief Request a Transmit data and FIFO flush
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or
+ * not FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) {
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx,
+ const LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(
+ USART_TypeDef *USARTx,
+ const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_USART_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h
index 12f2e06..f624a57 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h
@@ -1,242 +1,244 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_usb.h
- * @author MCD Application Team
- * @brief Header file of USB Low Layer HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_USB_H
-#define STM32G4xx_LL_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal_def.h"
-
-#if defined(USB)
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USB_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief USB Mode definition
- */
-
-typedef enum { USB_DEVICE_MODE = 0 } USB_ModeTypeDef;
-
-/**
- * @brief USB Initialization Structure definition
- */
-typedef struct {
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data
- = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref
- PCD_Speed/HCD_Speed (HCD_SPEED_xxx, HCD_SPEED_xxx) */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref
- PCD_PHY_Module/HCD_PHY_Module */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
-
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
-
- uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
-} USB_CfgTypeDef;
-
-typedef struct {
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and
- Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and
- Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0
- and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type */
-
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data
- = 0 and Max_Data = 1 */
-
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0
- and Max_addr = 1K */
-
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0
- and Max_addr = 1K */
-
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0
- and Max_addr = 1K */
-
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
-
- uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS
- peripheral, it is used only by USB OTG FS peripheral
- This parameter is added to ensure compatibility
- across USB peripherals */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0
- and Max_Data = 64KB */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet
- transfer */
-
- uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double
- buffer in */
-
- uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with
- bulk_in */
-
-} USB_EPTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
- * @{
- */
-#define EP_MPS_64 0U
-#define EP_MPS_32 1U
-#define EP_MPS_16 2U
-#define EP_MPS_8 3U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
- * @{
- */
-#define EP_TYPE_CTRL 0U
-#define EP_TYPE_ISOC 1U
-#define EP_TYPE_BULK 2U
-#define EP_TYPE_INTR 3U
-#define EP_TYPE_MSK 3U
-/**
- * @}
- */
-
-/** @defgroup USB_LL Device Speed
- * @{
- */
-#define USBD_FS_SPEED 2U
-/**
- * @}
- */
-
-#define BTABLE_ADDRESS 0x000U
-#define PMA_ACCESS 1U
-
-#define EP_ADDR_MSK 0x7U
-
-#ifndef USE_USB_DOUBLE_BUFFER
-#define USE_USB_DOUBLE_BUFFER 1U
-#endif /* USE_USB_DOUBLE_BUFFER */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
- * @{
- */
-
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
-
-#if defined(HAL_PCD_MODULE_ENABLED)
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-#endif /* defined (HAL_PCD_MODULE_ENABLED) */
-
-HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr,
- uint16_t wNBytes);
-
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr,
- uint16_t wNBytes);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* STM32G4xx_LL_USB_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_usb.h
+ * @author MCD Application Team
+ * @brief Header file of USB Low Layer HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_USB_H
+#define STM32G4xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined(USB)
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USB_LL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USB Mode definition
+ */
+
+typedef enum { USB_DEVICE_MODE = 0 } USB_ModeTypeDef;
+
+/**
+ * @brief USB Instance Initialization Structure definition
+ */
+typedef struct {
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data =
+ 1 and Max_Data = 15 */
+
+ uint8_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref
+ PCD_Speed/HCD_Speed (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+
+ uint8_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref
+ PCD_PHY_Module/HCD_PHY_Module */
+
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
+
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+} USB_CfgTypeDef;
+
+typedef struct {
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and
+ Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and
+ Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0
+ and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_LL_EP_Type */
+
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data
+ = 0 and Max_Data = 1 */
+
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0
+ and Max_addr = 1K */
+
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0
+ and Max_addr = 1K */
+
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0
+ and Max_addr = 1K */
+
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0
+ and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet
+ transfer */
+
+ uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double
+ buffer in */
+
+ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with
+ bulk_in */
+} USB_EPTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+ * @{
+ */
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+ * @{
+ */
+#define EP_TYPE_CTRL 0U
+#define EP_TYPE_ISOC 1U
+#define EP_TYPE_BULK 2U
+#define EP_TYPE_INTR 3U
+#define EP_TYPE_MSK 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL Device Speed
+ * @{
+ */
+#define USBD_FS_SPEED 2U
+/**
+ * @}
+ */
+
+#define BTABLE_ADDRESS 0x000U
+#define PMA_ACCESS 1U
+
+#ifndef USB_EP_RX_STRX
+#define USB_EP_RX_STRX (0x3U << 12)
+#endif /* USB_EP_RX_STRX */
+
+#define EP_ADDR_MSK 0x7U
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER 1U
+#endif /* USE_USB_DOUBLE_BUFFER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+ * @{
+ */
+
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
+
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
+
+#if defined(HAL_PCD_MODULE_ENABLED)
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
+
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
+uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
+
+void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes);
+
+void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32G4xx_LL_USB_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h
index 1b79ec6..343da40 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h
@@ -1,342 +1,364 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_utils.h
- * @author MCD Application Team
- * @brief Header file of UTILS LL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL UTILS driver contains a set of generic APIs that can be
- used by user:
- (+) Device electronic signature
- (+) Timing functions
- (+) PLL configuration functions
-
- @endverbatim
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G4xx_LL_UTILS_H
-#define STM32G4xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx.h"
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-/** @defgroup UTILS_LL UTILS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
- * @{
- */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY 0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
-
-/**
- * @brief Package data register base address
- */
-#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
- * @{
- */
-/**
- * @brief UTILS PLL structure definition
- */
-typedef struct {
- uint32_t
- PLLM; /*!< Division factor for PLL VCO input clock.
- This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
- uint32_t
- PLLN; /*!< Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 8 and
- Max_Data = 86
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
- uint32_t
- PLLR; /*!< Division for the main system clock.
- This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
- * @brief UTILS System, AHB and APB buses clock configuration structure
- * definition
- */
-typedef struct {
- uint32_t
- AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived
- from the system clock (SYSCLK). This parameter can be a
- value of @ref RCC_LL_EC_SYSCLK_DIV
-
- This feature can be modified afterwards using unitary
- function
- @ref LL_RCC_SetAHBPrescaler(). */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is
- derived from the AHB clock (HCLK). This parameter
- can be a value of @ref RCC_LL_EC_APB1_DIV
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_RCC_SetAPB1Prescaler(). */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is
- derived from the AHB clock (HCLK). This parameter
- can be a value of @ref RCC_LL_EC_APB2_DIV
-
- This feature can be modified afterwards using
- unitary function
- @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
- * @{
- */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
- * @{
- */
-#define LL_UTILS_HSEBYPASS_OFF \
- 0x00000000U /*!< HSE Bypass is not enabled */
-#define LL_UTILS_HSEBYPASS_ON \
- 0x00000001U /*!< HSE Bypass is enabled */
-/**
- * @}
- */
-
-/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
- * @{
- */
-#define LL_UTILS_PACKAGETYPE_LQFP64 \
- 0x00000000U /*!< LQFP64 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP100 \
- 0x00000002U /*!< LQFP100 package type */
-#define LL_UTILS_PACKAGETYPE_WLCSP81 \
- 0x00000005U /*!< WLCSP81 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP128 \
- 0x00000007U /*!< LQFP128 package type */
-#define LL_UTILS_PACKAGETYPE_UFQFPN32 \
- 0x00000008U /*!< UFQFPN32 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP32 \
- 0x00000009U /*!< LQFP32 package type */
-#define LL_UTILS_PACKAGETYPE_UFQFPN48 \
- 0x0000000AU /*!< UFQFPN48 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP48 \
- 0x0000000BU /*!< LQFP48 package type */
-#define LL_UTILS_PACKAGETYPE_WLCSP49 \
- 0x0000000CU /*!< WLCSP49 package type */
-#define LL_UTILS_PACKAGETYPE_UFBGA64 \
- 0x0000000DU /*!< UFBGA64 package type */
-#define LL_UTILS_PACKAGETYPE_UFBGA100 \
- 0x0000000EU /*!< UFBGA100 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE \
- 0x00000010U /*!< LQFP48 EBIKE package type */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
- * @{
- */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
- * @{
- */
-
-/**
- * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
- * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void) {
- return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
- * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
- * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void) {
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
- * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
- * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void) {
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
- * @brief Get Flash memory size
- * @note This bitfield indicates the size of the device Flash memory expressed
- * in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
- * @retval FLASH_SIZE[15:0]: Flash memory size
- */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void) {
- return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) &
- 0x0000FFFFUL);
-}
-
-/**
- * @brief Get Package type
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
- * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
- * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
- * @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
- * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
- * @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
- * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
- * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
- * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
- * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
- * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
- * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
- *
- */
-__STATIC_INLINE uint32_t LL_GetPackageType(void) {
- return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
-}
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source of the time
- * base.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC
- * helper macro)
- * @note When a RTOS is used, it is recommended to avoid changing the SysTick
- * configuration by calling this function, for a delay use rather
- * osDelay RTOS service.
- * @param Ticks Number of ticks
- * @retval None
- */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) {
- /* Configure the SysTick to have interrupt in 1ms time base */
- SysTick->LOAD =
- (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
-}
-
-void LL_Init1msTick(uint32_t HCLKFrequency);
-void LL_mDelay(uint32_t Delay);
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
- * @{
- */
-
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(
- uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G4xx_LL_UTILS_H */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_utils.h
+ * @author MCD Application Team
+ * @brief Header file of UTILS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_UTILS_H
+#define STM32G4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct {
+ uint32_t
+ PLLM; /*!< Division factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t
+ PLLN; /*!< Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 8 and
+ Max_Data = 86
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t
+ PLLR; /*!< Division for the main system clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure
+ * definition
+ */
+typedef struct {
+ uint32_t
+ AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived
+ from the system clock (SYSCLK). This parameter can be a
+ value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary
+ function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is
+ derived from the AHB clock (HCLK). This parameter
+ can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is
+ derived from the AHB clock (HCLK). This parameter
+ can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using
+ unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF \
+ 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON \
+ 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+ * @{
+ */
+#define LL_UTILS_PACKAGETYPE_LQFP64 \
+ 0x00000000U /*!< LQFP64 package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP64 \
+ 0x00000001U /*!< WLCSP64 package type */
+#if defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G431xx) || \
+ defined(STM32G414xx) || defined(STM32G441xx) || defined(STM32G471xx) || \
+ defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || \
+ defined(STM32G484xx)
+#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 \
+ 0x00000002U /*!< LQFP100 \ LQFP80 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100 \
+ LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 /*!< For backward compatibility */
+#else
+#define LL_UTILS_PACKAGETYPE_LQFP100 \
+ 0x00000002U /*!< LQFP100 package type */
+#endif /* STM32G411xB || STM32G411xC || STM32G431xx || STM32G414xx || \
+ STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx || \
+ STM32G474xx || STM32G484xx */
+#define LL_UTILS_PACKAGETYPE_WLCSP81 \
+ 0x00000005U /*!< WLCSP81 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 \
+ 0x00000007U /*!< LQFP128 \ UFBGA121 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP128 \
+ LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */
+#define LL_UTILS_PACKAGETYPE_UFQFPN32 \
+ 0x00000008U /*!< UFQFPN32 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP32 \
+ 0x00000009U /*!< LQFP32 package type */
+#define LL_UTILS_PACKAGETYPE_UFQFPN48 \
+ 0x0000000AU /*!< UFQFPN48 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP48 \
+ 0x0000000BU /*!< LQFP48 package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP49 \
+ 0x0000000CU /*!< WLCSP49 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA64 \
+ 0x0000000DU /*!< UFBGA64 package type */
+#define LL_UTILS_PACKAGETYPE_TFBGA100 \
+ 0x0000000EU /*!< TFBGA100 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA100 \
+ LL_UTILS_PACKAGETYPE_TFBGA100 /*!< For backward compatibility */
+#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE \
+ 0x00000010U /*!< LQFP48 EBIKE package type */
+#if defined(STM32G491xx) || defined(STM32G4A1xx)
+#define LL_UTILS_PACKAGETYPE_LQFP80 \
+ 0x00000011U /*!< LQFP80 package type */
+#endif /* STM32G491xx || STM32G4A1xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void) {
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void) {
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void) {
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed
+ * in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void) {
+ return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) &
+ 0x0000FFFFUL);
+}
+
+/**
+ * @brief Get Package type
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
+ *
+ */
+__STATIC_INLINE uint32_t LL_GetPackageType(void) {
+ return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time
+ * base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC
+ * helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather
+ * osDelay RTOS service.
+ * @param Ticks Frequency of Ticks (Hz)
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) {
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD =
+ (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(
+ uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_UTILS_H */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt
index b40364c..3edc4d1 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt
@@ -1,6 +1,6 @@
-This software component is provided to you as part of a software package and
-applicable license terms are in the Package_license file. If you received this
-software component outside of a package or without applicable license terms,
-the terms of the BSD-3-Clause license shall apply.
-You may obtain a copy of the BSD-3-Clause at:
-https://opensource.org/licenses/BSD-3-Clause
+This software component is provided to you as part of a software package and
+applicable license terms are in the Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply.
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
index b03ca54..a668dc1 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
@@ -1,721 +1,746 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal.c
- * @author MCD Application Team
- * @brief HAL module driver.
- * This is the common part of the HAL initialization
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The common HAL driver contains a set of generic and common APIs that can be
- used by the PPP peripheral drivers and the user to start using the HAL.
- [..]
- The HAL contains two APIs' categories:
- (+) Common HAL APIs
- (+) Services HAL APIs
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL HAL
- * @brief HAL module driver
- * @{
- */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/**
- * @brief STM32G4xx HAL Driver version number V1.2.2
- */
-#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
-#define __STM32G4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
-#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
-#define __STM32G4xx_HAL_VERSION \
- ((__STM32G4xx_HAL_VERSION_MAIN << 24U) | \
- (__STM32G4xx_HAL_VERSION_SUB1 << 16U) | \
- (__STM32G4xx_HAL_VERSION_SUB2 << 8U) | (__STM32G4xx_HAL_VERSION_RC))
-
-#if defined(VREFBUF)
-#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
-#endif /* VREFBUF */
-
-/* ------------ SYSCFG registers bit address in the alias region ------------ */
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-/* --- MEMRMP Register ---*/
-/* Alias word address of FB_MODE bit */
-#define MEMRMP_OFFSET SYSCFG_OFFSET
-#define FB_MODE_BitNumber ((uint8_t)0x8)
-#define FB_MODE_BB \
- (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
-
-/* --- GPC Register ---*/
-/* Alias word address of CCMER bit */
-#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
-#define CCMER_BitNumber ((uint8_t)0x0)
-#define SCSR_CCMER_BB \
- (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Exported variables
- * ---------------------------------------------------------*/
-/** @defgroup HAL_Exported_Variables HAL Exported Variables
- * @{
- */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
- * @{
- */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization
-Functions
- * @brief HAL Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the Flash interface the NVIC allocation and initial time
-base clock configuration.
- (+) De-Initialize common part of the HAL.
- (+) Configure the time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) SysTick timer is used by default as source of time base, but user
- can eventually implement his proper time base source (a general
-purpose timer for example or other time source), keeping in mind that Time base
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined
-and handled in milliseconds basis.
- (++) Time base configuration function (HAL_InitTick ()) is called
-automatically at the beginning of the program after reset by HAL_Init() or at
-any time when clock is configured, by HAL_RCC_ClockConfig().
- (++) Source of time base is configured to generate interrupts at
-regular time intervals. Care must be taken if HAL_Delay() is called from a
- peripheral ISR process, the Tick interrupt line must have higher
-priority (numerically lower) than the peripheral interrupt. Otherwise the caller
- ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __weak
- to make override possible in case of other implementations in
-user file.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is used to configure the Flash prefetch, the
- * Instruction and Data caches, the time base source, NVIC and any required
- * global low level hardware by calling the HAL_MspInit() callback function to
- * be optionally defined in user file stm32g4xx_hal_msp.c.
- *
- * @note HAL_Init() function is called at the beginning of program after reset
- * and before the clock configuration.
- *
- * @note In the default implementation the System Timer (Systick) is used as
- * source of time base. The Systick configuration is based on HSI clock, as HSI
- * is the clock used after a system Reset and the NVIC configuration is set to
- * Priority group 4. Once done, time base tick starts incrementing: the tick
- * variable counter is incremented each 1ms in the SysTick_Handler() interrupt
- * handler.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void) {
- HAL_StatusTypeDef status = HAL_OK;
- /* Configure Flash prefetch, Instruction cache, Data cache */
- /* Default configuration at reset is: */
- /* - Prefetch disabled */
- /* - Instruction cache enabled */
- /* - Data cache enabled */
-#if (INSTRUCTION_CACHE_ENABLE == 0U)
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-#endif /* INSTRUCTION_CACHE_ENABLE */
-
-#if (DATA_CACHE_ENABLE == 0U)
- __HAL_FLASH_DATA_CACHE_DISABLE();
-#endif /* DATA_CACHE_ENABLE */
-
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Use SysTick as time base source and configure 1ms tick (default clock after
- * Reset is HSI) */
- if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
- status = HAL_ERROR;
- } else {
- /* Init the low level hardware */
- HAL_MspInit();
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function de-initializes common part of the HAL and stops the
- * source of time base.
- * @note This function is optional.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DeInit(void) {
- /* Reset of all peripherals */
- __HAL_RCC_APB1_FORCE_RESET();
- __HAL_RCC_APB1_RELEASE_RESET();
-
- __HAL_RCC_APB2_FORCE_RESET();
- __HAL_RCC_APB2_RELEASE_RESET();
-
- __HAL_RCC_AHB1_FORCE_RESET();
- __HAL_RCC_AHB1_RELEASE_RESET();
-
- __HAL_RCC_AHB2_FORCE_RESET();
- __HAL_RCC_AHB2_RELEASE_RESET();
-
- __HAL_RCC_AHB3_FORCE_RESET();
- __HAL_RCC_AHB3_RELEASE_RESET();
-
- /* De-Init the low level hardware */
- HAL_MspDeInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the MSP.
- * @retval None
- */
-__weak void HAL_MspInit(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the MSP.
- * @retval None
- */
-__weak void HAL_MspDeInit(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function configures the source of the time base:
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program
- * after reset by HAL_Init() or at any time when clock is reconfigured by
- * HAL_RCC_ClockConfig().
- * @note In the default implementation, SysTick timer is the source of time
- * base. It is used to generate interrupts at regular time intervals. Care must
- * be taken if HAL_Delay() is called from a peripheral ISR process, The SysTick
- * interrupt must have higher priority (numerically lower) than the peripheral
- * interrupt. Otherwise the caller ISR process will be blocked. The function is
- * declared as __weak to be overwritten in case of other implementation in
- * user file.
- * @param TickPriority: Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (uwTickFreq != 0U) {
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) {
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- uwTickPrio = TickPriority;
- } else {
- status = HAL_ERROR;
- }
- } else {
- status = HAL_ERROR;
- }
- } else {
- status = HAL_ERROR;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Provide a tick value in millisecond
- (+) Provide a blocking delay in millisecond
- (+) Suspend the time base source interrupt
- (+) Resume the time base source interrupt
- (+) Get the HAL API driver version
- (+) Get the device identifier
- (+) Get the device revision identifier
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is called to increment a global variable "uwTick"
- * used as application time base.
- * @note In the default implementation, this variable is incremented each 1ms
- * in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void) { uwTick += uwTickFreq; }
-
-/**
- * @brief Provides a tick value in millisecond.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void) { return uwTick; }
-
-/**
- * @brief This function returns a tick priority.
- * @retval tick priority
- */
-uint32_t HAL_GetTickPrio(void) { return uwTickPrio; }
-
-/**
- * @brief Set new tick Freq.
- * @retval status
- */
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t prevTickFreq;
-
- assert_param(IS_TICKFREQ(Freq));
-
- if (uwTickFreq != Freq) {
- /* Back up uwTickFreq frequency */
- prevTickFreq = uwTickFreq;
-
- /* Update uwTickFreq global variable used by HAL_InitTick() */
- uwTickFreq = Freq;
-
- /* Apply the new tick Freq */
- status = HAL_InitTick(uwTickPrio);
-
- if (status != HAL_OK) {
- /* Restore previous tick frequency */
- uwTickFreq = prevTickFreq;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Returns tick frequency.
- * @retval tick period in Hz
- */
-uint32_t HAL_GetTickFreq(void) { return uwTickFreq; }
-
-/**
- * @brief This function provides minimum delay (in milliseconds) based
- * on variable incremented.
- * @note In the default implementation , SysTick timer is the source of time
- * base. It is used to generate interrupts at regular time intervals where
- * uwTick is incremented.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(uint32_t Delay) {
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a freq to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY) {
- wait += (uint32_t)(uwTickFreq);
- }
-
- while ((HAL_GetTick() - tickstart) < wait) {
- }
-}
-
-/**
- * @brief Suspends Tick increment.
- * @note In the default implementation , SysTick timer is the source of time
- * base. It is used to generate interrupts at regular time intervals. Once
- * HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so
- * Tick increment is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void) {
- /* Disable SysTick Interrupt */
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time
- * base. It is used to generate interrupts at regular time intervals. Once
- * HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick
- * increment is resumed.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void) {
- /* Enable SysTick Interrupt */
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Returns the HAL revision.
- * @retval version : 0xXYZR (8bits for each decimal, R for RC)
- */
-uint32_t HAL_GetHalVersion(void) { return __STM32G4xx_HAL_VERSION; }
-
-/**
- * @brief Returns the device revision identifier.
- * @retval Device revision identifier
- */
-uint32_t HAL_GetREVID(void) {
- return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U);
-}
-
-/**
- * @brief Returns the device identifier.
- * @retval Device identifier
- */
-uint32_t HAL_GetDEVID(void) { return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); }
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
- * @brief HAL Debug functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Debug functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Enable/Disable Debug module during SLEEP mode
- (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
- (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the Debug Module during SLEEP mode.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGSleepMode(void) {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGSleepMode(void) {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStopMode(void) {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStopMode(void) {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStandbyMode(void) {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStandbyMode(void) {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
- * @brief HAL SYSCFG configuration functions
- *
-@verbatim
- ===============================================================================
- ##### HAL SYSCFG configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start a hardware CCMSRAM erase operation
- (+) Enable/Disable the Internal FLASH Bank Swapping
- (+) Configure the Voltage reference buffer
- (+) Enable/Disable the Voltage reference buffer
- (+) Enable/Disable the I/O analog switch voltage booster
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start a hardware CCMSRAM erase operation.
- * @note As long as CCMSRAM is not erased the CCMER bit will be set.
- * This bit is automatically reset at the end of the CCMSRAM erase
- * operation.
- * @retval None
- */
-void HAL_SYSCFG_CCMSRAMErase(void) {
- /* unlock the write protection of the CCMER bit */
- SYSCFG->SKR = 0xCA;
- SYSCFG->SKR = 0x53;
- /* Starts a hardware CCMSRAM erase operation*/
- SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
-}
-
-/**
- * @brief Enable the Internal FLASH Bank Swapping.
- *
- * @note This function can be used only for STM32G4xx devices.
- *
- * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
- * and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
- *
- * @retval None
- */
-void HAL_SYSCFG_EnableMemorySwappingBank(void) {
- SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
-}
-
-/**
- * @brief Disable the Internal FLASH Bank Swapping.
- *
- * @note This function can be used only for STM32G4xx devices.
- *
- * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased
- * @0x0000 0000) and Flash Bank2 mapped at 0x08040000 (and aliased at
- * 0x00040000)
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableMemorySwappingBank(void) {
- CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
-}
-
-#if defined(VREFBUF)
-/**
- * @brief Configure the internal voltage reference buffer voltage scale.
- * @param VoltageScaling: specifies the output voltage to achieve
- * This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V.
- * This requires VDDA equal to or
- * higher than 2.4 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V.
- * This requires VDDA equal to or
- * higher than 2.8 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
- * This requires VDDA equal to or
- * higher than 3.15 V.
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) {
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
-
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
-}
-
-/**
- * @brief Configure the internal voltage reference buffer high impedance mode.
- * @param Mode: specifies the high impedance mode
- * This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is
- * internally connect to VREFINT output.
- * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high
- * impedance.
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) {
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
-
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
-}
-
-/**
- * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
- * @param TrimmingValue specifies trimming code for VREFBUF calibration
- * This parameter can be a number between Min_Data = 0x00 and Max_Data =
- * 0x3F
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) {
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
-
- MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
-}
-
-/**
- * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
- * @retval HAL_OK/HAL_TIMEOUT
- */
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) {
- uint32_t tickstart;
-
- SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait for VRR bit */
- while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) {
- if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableVREFBUF(void) {
- CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-#endif /* VREFBUF */
-
-/**
- * @brief Enable the I/O analog switch voltage booster
- *
- * @retval None
- */
-void HAL_SYSCFG_EnableIOSwitchBooster(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
- * @brief Disable the I/O analog switch voltage booster
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableIOSwitchBooster(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
- * @brief Enable the I/O analog switch voltage by VDD
- *
- * @retval None
- */
-void HAL_SYSCFG_EnableIOSwitchVDD(void) {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
-}
-
-/**
- * @brief Disable the I/O analog switch voltage by VDD
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableIOSwitchVDD(void) {
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
-}
-
-/** @brief CCMSRAM page write protection enable
- * @param Page: This parameter is a long 32bit value and can be a value of @ref
- * SYSCFG_CCMSRAMWRP
- * @note write protection can only be disabled by a system reset
- * @retval None
- */
-void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) {
- assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page));
-
- SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32G4xx HAL Driver version number V1.2.5
+ */
+#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32G4xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
+#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32G4xx_HAL_VERSION \
+ ((__STM32G4xx_HAL_VERSION_MAIN << 24U) | \
+ (__STM32G4xx_HAL_VERSION_SUB1 << 16U) | \
+ (__STM32G4xx_HAL_VERSION_SUB2 << 8U) | (__STM32G4xx_HAL_VERSION_RC))
+
+#if defined(VREFBUF)
+#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
+#endif /* VREFBUF */
+
+/* ------------ SYSCFG registers bit address in the alias region ------------ */
+#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
+/* --- MEMRMP Register ---*/
+/* Alias word address of FB_MODE bit */
+#define MEMRMP_OFFSET SYSCFG_OFFSET
+#define FB_MODE_BitNumber ((uint8_t)0x8)
+#define FB_MODE_BB \
+ (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
+
+/* --- GPC Register ---*/
+/* Alias word address of CCMER bit */
+#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
+#define CCMER_BitNumber ((uint8_t)0x0)
+#define SCSR_CCMER_BB \
+ (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))
+
+/* Private macro -------------------------------------------------------------*/
+/* Exported variables
+ * ---------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization
+Functions
+ * @brief HAL Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the Flash interface the NVIC allocation and initial time
+base clock configuration.
+ (+) De-Initialize common part of the HAL.
+ (+) Configure the time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general
+purpose timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined
+and handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called
+automatically at the beginning of the program after reset by HAL_Init() or at
+any time when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at
+regular time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher
+priority (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in
+user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is used to configure the Flash prefetch, the
+ * Instruction and Data caches, the time base source, NVIC and any required
+ * global low level hardware by calling the HAL_MspInit() callback function to
+ * be optionally defined in user file stm32g4xx_hal_msp.c.
+ *
+ * @note HAL_Init() function is called at the beginning of program after reset
+ * and before the clock configuration.
+ *
+ * @note In the default implementation the System Timer (Systick) is used as
+ * source of time base. The Systick configuration is based on HSI clock, as HSI
+ * is the clock used after a system Reset and the NVIC configuration is set to
+ * Priority group 4. Once done, time base tick starts incrementing: the tick
+ * variable counter is incremented each 1ms in the SysTick_Handler() interrupt
+ * handler.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void) {
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Configure Flash prefetch, Instruction cache, Data cache */
+ /* Default configuration at reset is: */
+ /* - Prefetch disabled */
+ /* - Instruction cache enabled */
+ /* - Data cache enabled */
+#if (INSTRUCTION_CACHE_ENABLE == 0U)
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE == 0U)
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Use SysTick as time base source and configure 1ms tick (default clock after
+ * Reset is HSI) */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
+ status = HAL_ERROR;
+ } else {
+ /* Init the low level hardware */
+ HAL_MspInit();
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function de-initializes common part of the HAL and stops the
+ * source of time base.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void) {
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB1_FORCE_RESET();
+ __HAL_RCC_AHB1_RELEASE_RESET();
+
+ __HAL_RCC_AHB2_FORCE_RESET();
+ __HAL_RCC_AHB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB3_FORCE_RESET();
+ __HAL_RCC_AHB3_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base:
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program
+ * after reset by HAL_Init() or at any time when clock is reconfigured by
+ * HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time
+ * base. It is used to generate interrupts at regular time intervals. Care must
+ * be taken if HAL_Delay() is called from a peripheral ISR process, The SysTick
+ * interrupt must have higher priority (numerically lower) than the peripheral
+ * interrupt. Otherwise the caller ISR process will be blocked. The function is
+ * declared as __weak to be overwritten in case of other implementation in
+ * user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (uwTickFreq != 0U) {
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) {
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ } else {
+ status = HAL_ERROR;
+ }
+ } else {
+ status = HAL_ERROR;
+ }
+ } else {
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void) { uwTick += uwTickFreq; }
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void) { return uwTick; }
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void) { return uwTickPrio; }
+
+/**
+ * @brief Set new tick Freq.
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t prevTickFreq;
+
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq) {
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+
+ if (status != HAL_OK) {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Returns tick frequency.
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
+ */
+uint32_t HAL_GetTickFreq(void) { return uwTickFreq; }
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time
+ * base. It is used to generate interrupts at regular time intervals where
+ * uwTick is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay) {
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY) {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait) {
+ }
+}
+
+/**
+ * @brief Suspends Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time
+ * base. It is used to generate interrupts at regular time intervals. Once
+ * HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so
+ * Tick increment is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void) {
+ /* Disable SysTick Interrupt */
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time
+ * base. It is used to generate interrupts at regular time intervals. Once
+ * HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick
+ * increment is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void) {
+ /* Enable SysTick Interrupt */
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Returns the HAL revision.
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void) { return __STM32G4xx_HAL_VERSION; }
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void) {
+ return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void) { return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); }
+
+/**
+ * @brief Return the first word of the unique device identifier (UID based on
+ * 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void) { return (READ_REG(*((uint32_t *)UID_BASE))); }
+
+/**
+ * @brief Return the second word of the unique device identifier (UID based on
+ * 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void) {
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Return the third word of the unique device identifier (UID based on
+ * 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void) {
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+ * @brief HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Debug functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable/Disable Debug module during SLEEP mode
+ (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void) {
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void) {
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void) {
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void) {
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void) {
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void) {
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+ * @brief HAL SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start a hardware CCMSRAM erase operation
+ (+) Enable/Disable the Internal FLASH Bank Swapping
+ (+) Configure the Voltage reference buffer
+ (+) Enable/Disable the Voltage reference buffer
+ (+) Enable/Disable the I/O analog switch voltage booster
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Start a hardware CCMSRAM erase operation.
+ * @note As long as CCMSRAM is not erased the CCMER bit will be set.
+ * This bit is automatically reset at the end of the CCMSRAM erase
+ * operation.
+ * @retval None
+ */
+void HAL_SYSCFG_CCMSRAMErase(void) {
+ /* unlock the write protection of the CCMER bit */
+ SYSCFG->SKR = 0xCA;
+ SYSCFG->SKR = 0x53;
+ /* Starts a hardware CCMSRAM erase operation*/
+ SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
+}
+
+/**
+ * @brief Enable the Internal FLASH Bank Swapping.
+ *
+ * @note This function can be used only for STM32G4xx devices.
+ *
+ * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+ * and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableMemorySwappingBank(void) {
+ SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
+}
+
+/**
+ * @brief Disable the Internal FLASH Bank Swapping.
+ *
+ * @note This function can be used only for STM32G4xx devices.
+ *
+ * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased
+ * @0x0000 0000) and Flash Bank2 mapped at 0x08040000 (and aliased at
+ * 0x00040000)
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableMemorySwappingBank(void) {
+ CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
+}
+
+#if defined(VREFBUF)
+/**
+ * @brief Configure the internal voltage reference buffer voltage scale.
+ * @param VoltageScaling: specifies the output voltage to achieve
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V.
+ * This requires VDDA equal to or
+ * higher than 2.4 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V.
+ * This requires VDDA equal to or
+ * higher than 2.8 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
+ * This requires VDDA equal to or
+ * higher than 3.15 V.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) {
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+ * @brief Configure the internal voltage reference buffer high impedance mode.
+ * @param Mode: specifies the high impedance mode
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is
+ * internally connect to VREFINT output.
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high
+ * impedance.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) {
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+ * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+ * @param TrimmingValue specifies trimming code for VREFBUF calibration
+ * This parameter can be a number between Min_Data = 0x00 and Max_Data =
+ * 0x3F
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) {
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+ MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+ * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
+ * @retval HAL_OK/HAL_TIMEOUT
+ */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) {
+ uint32_t tickstart;
+
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait for VRR bit */
+ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) {
+ if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVREFBUF(void) {
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+#endif /* VREFBUF */
+
+/**
+ * @brief Enable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOSwitchBooster(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOSwitchBooster(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Enable the I/O analog switch voltage by VDD
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOSwitchVDD(void) {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+}
+
+/**
+ * @brief Disable the I/O analog switch voltage by VDD
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOSwitchVDD(void) {
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+}
+
+/** @brief CCMSRAM page write protection enable
+ * @param Page: This parameter is a long 32bit value and can be a value of @ref
+ * SYSCFG_CCMSRAMWRP
+ * @note write protection can only be disabled by a system reset
+ * @retval None
+ */
+void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) {
+ assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page));
+
+ SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
index cf8afc0..0a51a0e 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
@@ -1,3571 +1,3591 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_adc.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Converter (ADC)
- * peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- * Other functions (extended functions) are available in file
- * "stm32g4xx_hal_adc_ex.c".
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### ADC peripheral features #####
- ==============================================================================
- [..]
- (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
-
- (+) Interrupt generation at the end of regular conversion and in case of
- analog watchdog or overrun events.
-
- (+) Single and continuous conversion modes.
-
- (+) Scan mode for conversion of several channels sequentially.
-
- (+) Data alignment with in-built data coherency.
-
- (+) Programmable sampling time (channel wise)
-
- (+) External trigger (timer or EXTI) with configurable polarity
-
- (+) DMA request generation for transfer of conversions data of regular group.
-
- (+) Configurable delay between conversions in Dual interleaved mode.
-
- (+) ADC channels selectable single/differential input.
-
- (+) ADC offset shared on 4 offset instances.
- (+) ADC gain compensation
-
- (+) ADC calibration
-
- (+) ADC conversion of regular group.
-
- (+) ADC supply requirements: 1.62 V to 3.6 V.
-
- (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
- Vdda or to an external voltage reference).
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- *** Configuration of top level parameters related to ADC ***
- ============================================================
- [..]
-
- (#) Enable the ADC interface
- (++) As prerequisite, ADC clock must be configured at RCC top level.
-
- (++) Two clock settings are mandatory:
- (+++) ADC clock (core clock, also possibly conversion clock).
-
- (+++) ADC clock (conversions clock).
- Two possible clock sources: synchronous clock derived from
- AHB clock or asynchronous clock derived from system clock or PLL (output
- divider P) running up to 75MHz.
-
- (+++) Example:
- Into HAL_ADC_MspInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
-
- RCC_ADCCLKSOURCE_PLL enable: (optional: if
- asynchronous clock selected)
- (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-
- (++) ADC clock source and clock prescaler are configured at ADC level
- with parameter "ClockPrescaler" using function HAL_ADC_Init().
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_ENABLE()
- (++) Configure these ADC pins in analog mode
- using function HAL_GPIO_Init()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Configure the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding ADC interruption vector
- ADCx_IRQHandler().
-
- (#) Optionally, in case of usage of DMA:
- (++) Configure the DMA (DMA channel, mode normal or circular, ...)
- using function HAL_DMA_Init().
- (++) Configure the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding DMA interruption vector
- DMAx_Channelx_IRQHandler().
-
- *** Configuration of ADC, group regular, channels parameters ***
- ================================================================
- [..]
-
- (#) Configure the ADC parameters (resolution, data alignment, ...)
- and regular group parameters (conversion trigger, sequencer, ...)
- using function HAL_ADC_Init().
-
- (#) Configure the channels for regular group parameters (channel number,
- channel rank into sequencer, ..., into regular group)
- using function HAL_ADC_ConfigChannel().
-
- (#) Optionally, configure the analog watchdog parameters (channels
- monitored, thresholds, ...)
- using function HAL_ADC_AnalogWDGConfig().
-
- *** Execution of ADC conversions ***
- ====================================
- [..]
-
- (#) Optionally, perform an automatic ADC calibration to improve the
- conversion accuracy
- using function HAL_ADCEx_Calibration_Start().
-
- (#) ADC driver can be used among three modes: polling, interruption,
- transfer by DMA.
-
- (++) ADC conversion by polling:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start()
- (+++) Wait for ADC conversion completion
- using function HAL_ADC_PollForConversion()
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop()
-
- (++) ADC conversion by interruption:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_IT()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback()
- (this function must be implemented in user program)
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_IT()
-
- (++) ADC conversion with transfer by DMA:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_DMA()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
- (these functions must be implemented in user program)
- (+++) Conversion results are automatically transferred by DMA into
- destination variable address.
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_DMA()
-
- [..]
-
- (@) Callback functions must be implemented in user program:
- (+@) HAL_ADC_ErrorCallback()
- (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
- (+@) HAL_ADC_ConvCpltCallback()
- (+@) HAL_ADC_ConvHalfCpltCallback
-
- *** Deinitialization of ADC ***
- ============================================================
- [..]
-
- (#) Disable the ADC interface
- (++) ADC clock can be hard reset and disabled at RCC top level.
- (++) Hard reset of ADC peripherals
- using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
- (++) ADC clock disable
- using the equivalent macro/functions as configuration step.
- (+++) Example:
- Into HAL_ADC_MspDeInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) RCC_OscInitStructure.OscillatorType =
- RCC_OSCILLATORTYPE_HSI14;
- (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not
- used for system clock)
- (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
- (#) ADC pins configuration
- (++) Disable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Disable the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-
- (#) Optionally, in case of usage of DMA:
- (++) Deinitialize the DMA
- using function HAL_DMA_Init().
- (++) Disable the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-
- [..]
-
- *** Callback registration ***
- =============================================
- [..]
-
- The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
- allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_ADC_RegisterCallback()
- to register an interrupt callback.
- [..]
-
- Function HAL_ADC_RegisterCallback() allows to register following callbacks:
- (+) ConvCpltCallback : ADC conversion complete callback
- (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer
- callback
- (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
- (+) ErrorCallback : ADC error callback
- (+) InjectedConvCpltCallback : ADC group injected conversion
- complete callback
- (+) InjectedQueueOverflowCallback : ADC group injected context queue
- overflow callback
- (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
- (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
- (+) EndOfSamplingCallback : ADC end of sampling callback
- (+) MspInitCallback : ADC Msp Init callback
- (+) MspDeInitCallback : ADC Msp DeInit callback
- This function takes as parameters the HAL peripheral handle, the Callback
- ID and a pointer to the user callback function.
- [..]
-
- Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
- weak function.
- [..]
-
- HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (+) ConvCpltCallback : ADC conversion complete callback
- (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer
- callback
- (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
- (+) ErrorCallback : ADC error callback
- (+) InjectedConvCpltCallback : ADC group injected conversion
- complete callback
- (+) InjectedQueueOverflowCallback : ADC group injected context queue
- overflow callback
- (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
- (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
- (+) EndOfSamplingCallback : ADC end of sampling callback
- (+) MspInitCallback : ADC Msp Init callback
- (+) MspDeInitCallback : ADC Msp DeInit callback
- [..]
-
- By default, after the HAL_ADC_Init() and when the state is
- HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions:
- examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit()
- only when these callbacks are null (not registered beforehand).
- [..]
-
- If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
- whatever the state.
- [..]
-
- Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
- Exception done MspInit/MspDeInit functions that can be
- registered/unregistered in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the
- Init/DeInit.
- [..]
-
- Then, the user first registers the MspInit/MspDeInit user callbacks
- using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
- or HAL_ADC_Init() function.
- [..]
-
- When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all
- callbacks are set to the corresponding weak functions.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADC ADC
- * @brief ADC HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-
-#define ADC_CFGR_FIELDS_1 \
- ((ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | \
- ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_EXTEN | \
- ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated \
- when no regular conversion is on-going */
-
-/* Timeout values for ADC operations (enable settling time, */
-/* disable settling time, ...). */
-/* Values defined to be higher than worst cases: low clock frequency, */
-/* maximum prescalers. */
-#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
-#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
-
-/* Timeout to wait for current conversion on going to be completed. */
-/* Timeout fixed to longest ADC conversion possible, for 1 channel: */
-/* - maximum sampling time (640.5 adc_clk) */
-/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
-/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
-/* - ADC oversampling ratio 256 */
-/* Calculation: 653 * 4096 * 256 CPU clock cycles max */
-/* Unit: cycles of CPU clock. */
-#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES \
- (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization
-functions
- * @brief ADC Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC.
- (+) De-initialize the ADC.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the ADC peripheral and regular group according to
- * parameters specified in structure "ADC_InitTypeDef".
- * @note As prerequisite, ADC clock must be configured at RCC top level
- * (refer to description of RCC configuration for ADC
- * in header of this file).
- * @note Possibility to update parameters on the fly:
- * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
- * coming from ADC state reset. Following calls to this function can
- * be used to reconfigure some parameters of ADC_InitTypeDef
- * structure on the fly, without modifying MSP configuration. If ADC
- * MSP has to be modified again, HAL_ADC_DeInit() must be called
- * before HAL_ADC_Init().
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InitTypeDef".
- * @note This function configures the ADC within 2 scopes: scope of entire
- * ADC and scope of regular group. For parameters details, see comments
- * of structure "ADC_InitTypeDef".
- * @note Parameters related to common ADC registers (ADC clock mode) are set
- * only if all ADCs are disabled.
- * If this is not the case, these common parameters setting are
- * bypassed without error reporting: it can be the intended behaviour in
- * case of update of a parameter of ADC_InitTypeDef on the fly,
- * without disabling the other ADCs.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmpCFGR;
- uint32_t tmp_adc_reg_is_conversion_on_going;
- __IO uint32_t wait_loop_index = 0UL;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check ADC handle */
- if (hadc == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
- assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
- assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
- assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
- assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
- assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
- assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
- assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
-
- if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-
- if (hadc->Init.DiscontinuousConvMode == ENABLE) {
- assert_param(
- IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
- }
- }
-
- /* DISCEN and CONT bits cannot be set at the same time */
- assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) &&
- (hadc->Init.ContinuousConvMode == ENABLE)));
-
- /* Actions performed only if ADC is coming from state reset: */
- /* - Initialization of ADC MSP */
- if (hadc->State == HAL_ADC_STATE_RESET) {
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- /* Init the ADC Callback settings */
- hadc->ConvCpltCallback =
- HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
- hadc->ConvHalfCpltCallback =
- HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
- hadc->LevelOutOfWindowCallback =
- HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
- hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
- hadc->InjectedConvCpltCallback =
- HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
- hadc->InjectedQueueOverflowCallback =
- HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
- hadc->LevelOutOfWindow2Callback =
- HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
- hadc->LevelOutOfWindow3Callback =
- HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
- hadc->EndOfSamplingCallback =
- HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
-
- if (hadc->MspInitCallback == NULL) {
- hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
- }
-
- /* Init the low level hardware */
- hadc->MspInitCallback(hadc);
-#else
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Initialize Lock */
- hadc->Lock = HAL_UNLOCKED;
- }
-
- /* - Exit from deep-power-down mode and ADC voltage regulator enable */
- if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) {
- /* Disable ADC deep power down mode */
- LL_ADC_DisableDeepPowerDown(hadc->Instance);
-
- /* System was in deep power down mode, calibration must
- be relaunched or a previously saved calibration factor
- re-applied once the ADC voltage regulator is enabled */
- }
-
- if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) {
- /* Enable ADC internal voltage regulator */
- LL_ADC_EnableInternalRegulator(hadc->Instance);
-
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles, scaling in us split to not */
- /* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) *
- ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
- while (wait_loop_index != 0UL) {
- wait_loop_index--;
- }
- }
-
- /* Verification that ADC voltage regulator is correctly enabled, whether */
- /* or not ADC is coming from state reset (if any potential problem of */
- /* clocking, voltage regulator would not be enabled). */
- if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed and if there is no conversion on going on regular */
- /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
- /* called to update a parameter on the fly). */
- tmp_adc_reg_is_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
-
- if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) &&
- (tmp_adc_reg_is_conversion_on_going == 0UL)) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Configuration of common ADC parameters */
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - clock configuration */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
- /* Reset configuration of ADC common register CCR: */
- /* */
- /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set
- */
- /* according to adc->Init.ClockPrescaler. It selects the clock */
- /* source and sets the clock division factor. */
- /* */
- /* Some parameters of this register are not reset, since they are set */
- /* by other functions and must be kept in case of usage of this */
- /* function on the fly (update of a parameter of ADC_InitTypeDef */
- /* without needing to reconfigure all other ADC groups/channels */
- /* parameters): */
- /* - when multimode feature is available, multimode-related */
- /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
- /* HAL_ADCEx_MultiModeConfigChannel() ) */
- /* - internal measurement paths: Vbat, temperature sensor, Vref */
- /* (set into HAL_ADC_ConfigChannel() or */
- /* HAL_ADCEx_InjectedConfigChannel() ) */
- LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
- hadc->Init.ClockPrescaler);
- }
- }
-
- /* Configuration of ADC: */
- /* - resolution Init.Resolution */
- /* - data alignment Init.DataAlign */
- /* - external trigger to start conversion Init.ExternalTrigConv */
- /* - external trigger polarity Init.ExternalTrigConvEdge */
- /* - continuous conversion mode Init.ContinuousConvMode */
- /* - overrun Init.Overrun */
- /* - discontinuous mode Init.DiscontinuousConvMode */
- /* - discontinuous mode channel count Init.NbrOfDiscConversion */
- tmpCFGR =
- (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
- hadc->Init.Overrun | hadc->Init.DataAlign | hadc->Init.Resolution |
- ADC_CFGR_REG_DISCONTINUOUS(
- (uint32_t)hadc->Init.DiscontinuousConvMode));
-
- if (hadc->Init.DiscontinuousConvMode == ENABLE) {
- tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
- }
-
- /* Enable external trigger if trigger selection is different of software */
- /* start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) {
- tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) |
- hadc->Init.ExternalTrigConvEdge);
- }
-
- /* Update Configuration Register CFGR */
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
-
- /* Configuration of sampling mode */
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG,
- hadc->Init.SamplingMode);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Gain Compensation Init.GainCompensation */
- /* - DMA continuous request Init.DMAContinuousRequests */
- /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
- /* - Oversampling parameters Init.Oversampling */
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
- if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- tmpCFGR =
- (ADC_CFGR_DFSDM(hadc) |
- ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
- ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
-
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
-
- if (hadc->Init.GainCompensation != 0UL) {
- SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
- MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF,
- hadc->Init.GainCompensation);
- } else {
- CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
- MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
- }
-
- if (hadc->Init.OversamplingMode == ENABLE) {
- assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
- assert_param(
- IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
- assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(
- hadc->Init.Oversampling.TriggeredMode));
- assert_param(IS_ADC_REGOVERSAMPLING_MODE(
- hadc->Init.Oversampling.OversamplingStopReset));
-
- /* Configuration of Oversampler: */
- /* - Oversampling Ratio */
- /* - Right bit shift */
- /* - Triggered mode */
- /* - Oversampling mode (continued/resumed) */
- MODIFY_REG(
- hadc->Instance->CFGR2,
- ADC_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS | ADC_CFGR2_ROVSM,
- ADC_CFGR2_ROVSE | hadc->Init.Oversampling.Ratio |
- hadc->Init.Oversampling.RightBitShift |
- hadc->Init.Oversampling.TriggeredMode |
- hadc->Init.Oversampling.OversamplingStopReset);
- } else {
- /* Disable ADC oversampling scope on ADC group regular */
- CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
- }
- }
-
- /* Configuration of regular group sequencer: */
- /* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
- /* Parameter "NbrOfConversion" is discarded. */
- /* Note: Scan mode is not present by hardware on this device, but */
- /* emulated by software for alignment over all STM32 devices. */
- /* - if scan mode is enabled, regular channels sequence length is set to */
- /* parameter "NbrOfConversion". */
-
- if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) {
- /* Set number of ranks in regular group sequencer */
- MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L,
- (hadc->Init.NbrOfConversion - (uint8_t)1));
- } else {
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
- }
-
- /* Initialize the ADC state */
- /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- } else {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Deinitialize the ADC peripheral registers to their default reset
- * values, with deinitialization of the ADC MSP.
- * @note For devices with several ADCs: reset of ADC common registers is done
- * only if all ADCs sharing the same common group are disabled.
- * (function "HAL_ADC_MspDeInit()" is also called under the same
- * conditions: all ADC instances use the same core clock at RCC level, disabling
- * the core clock reset all ADC instances).
- * If this is not the case, reset of these common parameters reset is
- * bypassed without error reporting: it can be the intended behavior in
- * case of reset of a single ADC while the other ADCs sharing the same
- * common group is still running.
- * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
- * this saves more power by reducing leakage currents
- * and is particularly interesting before entering MCU low-power modes.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check ADC handle */
- if (hadc == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Stop potential conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- /* Flush register JSQR: reset the queue sequencer when injected */
- /* queue sequencer is enabled and ADC disabled. */
- /* The software and hardware triggers of the injected sequence are both */
- /* internally disabled just after the completion of the last valid */
- /* injected sequence. */
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK) {
- /* Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
- }
- }
-
- /* Note: HAL ADC deInit is done independently of ADC conversion stop */
- /* and disable return status. In case of status fail, attempt to */
- /* perform deinitialization anyway and it is up user code in */
- /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
- /* system RCC hard reset. */
-
- /* ========== Reset ADC registers ========== */
- /* Reset register IER */
- __HAL_ADC_DISABLE_IT(
- hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF |
- ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC |
- ADC_IT_EOSMP | ADC_IT_RDY));
-
- /* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(
- hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF |
- ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS |
- ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
-
- /* Reset register CR */
- /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
- ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
- no direct reset applicable.
- Update CR register to reset value where doable by software */
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
- SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
-
- /* Reset register CFGR */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-
- /* Reset register CFGR2 */
- CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS |
- ADC_CFGR2_OVSS | ADC_CFGR2_OVSR |
- ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
-
- /* Reset register SMPR1 */
- CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
-
- /* Reset register SMPR2 */
- CLEAR_BIT(hadc->Instance->SMPR2,
- ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
- ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
- ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
-
- /* Reset register TR1 */
- CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
-
- /* Reset register TR2 */
- CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
-
- /* Reset register TR3 */
- CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
- ADC_SQR1_SQ1 | ADC_SQR1_L);
-
- /* Reset register SQR2 */
- CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
- ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
-
- /* Reset register SQR3 */
- CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 |
- ADC_SQR3_SQ12 | ADC_SQR3_SQ11 |
- ADC_SQR3_SQ10);
-
- /* Reset register SQR4 */
- CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
-
- /* Register JSQR was reset when the ADC was disabled */
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset register OFR1 */
- CLEAR_BIT(hadc->Instance->OFR1,
- ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
- /* Reset register OFR2 */
- CLEAR_BIT(hadc->Instance->OFR2,
- ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
- /* Reset register OFR3 */
- CLEAR_BIT(hadc->Instance->OFR3,
- ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
- /* Reset register OFR4 */
- CLEAR_BIT(hadc->Instance->OFR4,
- ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset register AWD2CR */
- CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
-
- /* Reset register AWD3CR */
- CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
-
- /* Reset register DIFSEL */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
-
- /* Reset register CALFACT */
- CLEAR_BIT(hadc->Instance->CALFACT,
- ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-
- /* ========== Reset common ADC registers ========== */
-
- /* Software is allowed to change common parameters only when all the other
- ADCs are disabled. */
- if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
- /* Reset configuration of ADC common register CCR:
- - clock mode: CKMODE, PRESCEN
- - multimode related parameters (when this feature is available): MDMA,
- DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
- - internal measurement paths: Vbat, temperature sensor, Vref (set into
- HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
- */
- ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
-
- /* ========== Hard reset ADC peripheral ========== */
- /* Performs a global reset of the entire ADC peripherals instances */
- /* sharing the same common ADC instance: ADC state is forced to */
- /* a similar state as after device power-on. */
- /* Note: A possible implementation is to add RCC bus reset of ADC */
- /* (for example, using macro */
- /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
- /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- if (hadc->MspDeInitCallback == NULL) {
- hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware */
- hadc->MspDeInitCallback(hadc);
-#else
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
- }
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Reset injected channel configuration parameters */
- hadc->InjectionConfig.ContextQueue = 0;
- hadc->InjectionConfig.ChannelCount = 0;
-
- /* Set ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Initialize the ADC MSP.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspInit must be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitialize the ADC MSP.
- * @param hadc ADC handle
- * @note All ADC instances use the same core clock at RCC level, disabling
- * the core clock reset all ADC instances).
- * @retval None
- */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspDeInit must be implemented in the user file.
- */
-}
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User ADC Callback
- * To be used instead of the weak predefined callback
- * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion
- * complete callback ID
- * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA
- * half-transfer callback ID
- * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog
- * 1 callback ID
- * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback
- * ID
- * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected
- * conversion complete callback ID
- * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected
- * context queue overflow callback ID
- * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog
- * 2 callback ID
- * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog
- * 3 callback ID
- * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling
- * callback ID
- * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init
- * callback ID
- * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit
- * callback ID
- * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc,
- HAL_ADC_CallbackIDTypeDef CallbackID,
- pADC_CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) {
- switch (CallbackID) {
- case HAL_ADC_CONVERSION_COMPLETE_CB_ID:
- hadc->ConvCpltCallback = pCallback;
- break;
-
- case HAL_ADC_CONVERSION_HALF_CB_ID:
- hadc->ConvHalfCpltCallback = pCallback;
- break;
-
- case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID:
- hadc->LevelOutOfWindowCallback = pCallback;
- break;
-
- case HAL_ADC_ERROR_CB_ID:
- hadc->ErrorCallback = pCallback;
- break;
-
- case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID:
- hadc->InjectedConvCpltCallback = pCallback;
- break;
-
- case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID:
- hadc->InjectedQueueOverflowCallback = pCallback;
- break;
-
- case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID:
- hadc->LevelOutOfWindow2Callback = pCallback;
- break;
-
- case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID:
- hadc->LevelOutOfWindow3Callback = pCallback;
- break;
-
- case HAL_ADC_END_OF_SAMPLING_CB_ID:
- hadc->EndOfSamplingCallback = pCallback;
- break;
-
- case HAL_ADC_MSPINIT_CB_ID:
- hadc->MspInitCallback = pCallback;
- break;
-
- case HAL_ADC_MSPDEINIT_CB_ID:
- hadc->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (HAL_ADC_STATE_RESET == hadc->State) {
- switch (CallbackID) {
- case HAL_ADC_MSPINIT_CB_ID:
- hadc->MspInitCallback = pCallback;
- break;
-
- case HAL_ADC_MSPDEINIT_CB_ID:
- hadc->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Unregister a ADC Callback
- * ADC callback is redirected to the weak predefined callback
- * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion
- * complete callback ID
- * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA
- * half-transfer callback ID
- * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog
- * 1 callback ID
- * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback
- * ID
- * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected
- * conversion complete callback ID
- * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected
- * context queue overflow callback ID
- * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog
- * 2 callback ID
- * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog
- * 3 callback ID
- * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling
- * callback ID
- * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init
- * callback ID
- * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit
- * callback ID
- * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(
- ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) {
- switch (CallbackID) {
- case HAL_ADC_CONVERSION_COMPLETE_CB_ID:
- hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
- break;
-
- case HAL_ADC_CONVERSION_HALF_CB_ID:
- hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
- break;
-
- case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID:
- hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
- break;
-
- case HAL_ADC_ERROR_CB_ID:
- hadc->ErrorCallback = HAL_ADC_ErrorCallback;
- break;
-
- case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID:
- hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
- break;
-
- case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID:
- hadc->InjectedQueueOverflowCallback =
- HAL_ADCEx_InjectedQueueOverflowCallback;
- break;
-
- case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID:
- hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
- break;
-
- case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID:
- hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
- break;
-
- case HAL_ADC_END_OF_SAMPLING_CB_ID:
- hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
- break;
-
- case HAL_ADC_MSPINIT_CB_ID:
- hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_ADC_MSPDEINIT_CB_ID:
- hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default:
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (HAL_ADC_STATE_RESET == hadc->State) {
- switch (CallbackID) {
- case HAL_ADC_MSPINIT_CB_ID:
- hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_ADC_MSPDEINIT_CB_ID:
- hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default:
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation
-functions
- * @brief ADC IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of regular group.
- (+) Stop conversion of regular group.
- (+) Poll for conversion complete on regular group.
- (+) Poll for conversion event.
- (+) Get result of regular channel conversion.
- (+) Start conversion of regular group and enable interruptions.
- (+) Stop conversion of regular group and disable interruptions.
- (+) Handle ADC interrupt request
- (+) Start conversion of regular group and enable DMA transfer.
- (+) Stop conversion of regular group and disable ADC DMA transfer.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable ADC, start conversion of regular group.
- * @note Interruptions enabled in this function: None.
- * @note Case of multimode enabled (when multimode feature is available):
- * if ADC is Slave, ADC is enabled but conversion is not started,
- * if ADC is master, ADC is enabled and multimode conversion is
- * started.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-#if defined(ADC_MULTIMODE_SUPPORT)
- const ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
- HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - if ADC instance is master or if multimode feature is not available
- - if multimode setting is disabled (ADC instance slave in independent
- mode) */
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#endif
-
- /* Set ADC error code */
- /* Check if a conversion is on going on ADC group injected */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
- /* Reset ADC error code fields related to regular conversions only */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- } else {
- /* Reset all ADC error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Clear ADC group regular conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations)
- */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (when multimode feature is available): */
- /* - if ADC is slave and dual regular conversions are enabled, ADC is */
- /* enabled only (conversion is not started), */
- /* - if ADC is master, ADC is enabled and conversion is started. */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
- /* ADC instance is not a multimode slave instance with multimode regular
- * conversions enabled */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* Start ADC group regular conversion */
- LL_ADC_REG_StartConversion(hadc->Instance);
- } else {
- /* ADC instance is a multimode slave instance with multimode regular
- * conversions enabled */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- /* if Master ADC JAUTO bit is set, update Slave State in setting
- HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit
- */
- tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
- if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
- }
- }
-#else
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* Start ADC group regular conversion */
- LL_ADC_REG_StartConversion(hadc->Instance);
-#endif
- } else {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- } else {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop
- * function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on ADC groups regular and injected
- */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK) {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Wait for regular group conversion to be completed.
- * @note ADC conversion flags EOS (end of sequence) and EOC (end of
- * conversion) are cleared by this function, with an exception:
- * if low power feature "LowPowerAutoWait" is enabled, flags are
- * not cleared to not interfere with this feature until data register
- * is read using function HAL_ADC_GetValue().
- * @note This function cannot be used in a particular setup: ADC configured
- * in DMA mode and polling for end of each conversion (ADC init
- * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
- * In this case, DMA resets the flag EOC and polling cannot be
- * performed on each conversion. Nevertheless, polling can still
- * be performed on the complete sequence (ADC init
- * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc,
- uint32_t Timeout) {
- uint32_t tickstart;
- uint32_t tmp_Flag_End;
- uint32_t tmp_cfgr;
-#if defined(ADC_MULTIMODE_SUPPORT)
- const ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* If end of conversion selected to end of sequence conversions */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) {
- tmp_Flag_End = ADC_FLAG_EOS;
- }
- /* If end of conversion selected to end of unitary conversion */
- else /* ADC_EOC_SINGLE_CONV */
- {
- /* Verification that ADC configuration is compliant with polling for */
- /* each conversion: */
- /* Particular case is ADC configured in DMA mode and ADC sequencer with */
- /* several ranks and polling for end of each conversion. */
- /* For code simplicity sake, this particular case is generalized to */
- /* ADC configured in DMA mode and and polling for end of each conversion. */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
- /* Check ADC DMA mode in independent mode on ADC group regular */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- } else {
- tmp_Flag_End = (ADC_FLAG_EOC);
- }
- } else {
- /* Check ADC DMA mode in multimode on ADC group regular */
- if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(
- hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- } else {
- tmp_Flag_End = (ADC_FLAG_EOC);
- }
- }
-#else
- /* Check ADC DMA mode */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- } else {
- tmp_Flag_End = (ADC_FLAG_EOC);
- }
-#endif
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait until End of unitary conversion or sequence conversions flag is raised
- */
- while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) {
- /* Check if timeout is disabled (set to infinite wait) */
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) {
- /* New check to avoid false timeout detection in case of preemption */
- if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) &&
- (hadc->Init.ContinuousConvMode == DISABLE)) {
- /* Check whether end of sequence is reached */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
-
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
- /* Retrieve handle ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- } else {
- /* Retrieve Master ADC CFGR register */
- tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-#else
- /* Retrieve handle ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
-#endif
-
- /* Clear polled flag */
- if (tmp_Flag_End == ADC_FLAG_EOS) {
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
- } else {
- /* Clear end of conversion EOC flag of regular group if low power feature */
- /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
- /* until data register is read using function HAL_ADC_GetValue(). */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) {
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Poll for ADC event.
- * @param hadc ADC handle
- * @param EventType the ADC event type.
- * This parameter can be one of the following values:
- * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
- * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main
- * analog watchdog, present on all STM32 devices)
- * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional
- * analog watchdog, not present on all STM32 families)
- * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional
- * analog watchdog, not present on all STM32 families)
- * @arg @ref ADC_OVR_EVENT ADC Overrun event
- * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow
- * event
- * @param Timeout Timeout value in millisecond.
- * @note The relevant flag is cleared if found to be set, except for
- * ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is
- * set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially
- * overwritten by a new converted data as soon as OVR is cleared. To reset OVR
- * flag once the preserved data is retrieved, the user can resort to macro
- * __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc,
- uint32_t EventType, uint32_t Timeout) {
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EVENT_TYPE(EventType));
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Check selected event flag */
- while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) {
- /* Check if timeout is disabled (set to infinite wait) */
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) {
- /* New check to avoid false timeout detection in case of preemption */
- if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- switch (EventType) {
- /* End Of Sampling event */
- case ADC_EOSMP_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
-
- /* Clear the End Of Sampling flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
-
- break;
-
- /* Analog watchdog (level out of window) event */
- /* Note: In case of several analog watchdog enabled, if needed to know */
- /* which one triggered and on which ADCx, test ADC state of analog watchdog
- */
- /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
- /* For example: */
- /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
- /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
- /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
-
- /* Check analog watchdog 1 flag */
- case ADC_AWD_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
-
- break;
-
- /* Check analog watchdog 2 flag */
- case ADC_AWD2_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
-
- break;
-
- /* Check analog watchdog 3 flag */
- case ADC_AWD3_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
-
- break;
-
- /* Injected context queue overflow event */
- case ADC_JQOVF_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- /* Set ADC error code to Injected context queue overflow */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-
- /* Clear ADC Injected context queue overflow flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-
- break;
-
- /* Overrun event */
- default: /* Case ADC_OVR_EVENT */
- /* If overrun is set to overwrite previous data, overrun event is not */
- /* considered as an error. */
- /* (cf ref manual "Managing conversions without using the DMA and without
- */
- /* overrun ") */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-
- /* Set ADC error code to overrun */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- } else {
- /* Clear ADC Overrun flag only if Overrun is set to
- ADC_OVR_DATA_OVERWRITTEN otherwise, data register is potentially
- overwritten by new converted data as soon as OVR is cleared. */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- }
- break;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable ADC, start conversion of regular group with interruption.
- * @note Interruptions enabled in this function according to initialization
- * setting : EOC (end of conversion), EOS (end of sequence),
- * OVR overrun.
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled (when multimode feature is available):
- * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
- * ADC Master.
- * For ADC Slave, ADC is enabled only (conversion is not started).
- * For ADC Master, ADC is enabled and multimode conversion is started.
- * @note To guarantee a proper reset of all interruptions once all the needed
- * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
- * a correct stop of the IT-based conversions.
- * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
- * interruption. If required (e.g. in case of oversampling with trigger
- * mode), the user must:
- * 1. first clear the EOSMP flag if set with macro
- * __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
- * 2. then enable the EOSMP interrupt with macro
- * __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-#if defined(ADC_MULTIMODE_SUPPORT)
- const ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
- HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - if ADC instance is master or if multimode feature is not available
- - if multimode setting is disabled (ADC instance slave in independent
- mode) */
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#endif
-
- /* Set ADC error code */
- /* Check if a conversion is on going on ADC group injected */
- if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) {
- /* Reset ADC error code fields related to regular conversions only */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- } else {
- /* Reset all ADC error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Clear ADC group regular conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations)
- */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Disable all interruptions before enabling the desired ones */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* Enable ADC end of conversion interrupt */
- switch (hadc->Init.EOCSelection) {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
- break;
- }
-
- /* Enable ADC overrun interrupt */
- /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
- ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
- behavior and no CPU time is lost for a non-processed interruption */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) {
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
- }
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (when multimode feature is available): */
- /* - if ADC is slave and dual regular conversions are enabled, ADC is */
- /* enabled only (conversion is not started), */
- /* - if ADC is master, ADC is enabled and conversion is started. */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
- /* ADC instance is not a multimode slave instance with multimode regular
- * conversions enabled */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Enable as well injected interruptions in case
- HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
- allows to start regular and injected conversions when JAUTO is
- set with a single call to HAL_ADC_Start_IT() */
- switch (hadc->Init.EOCSelection) {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
- }
-
- /* Start ADC group regular conversion */
- LL_ADC_REG_StartConversion(hadc->Instance);
- } else {
- /* ADC instance is a multimode slave instance with multimode regular
- * conversions enabled */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- /* if Master ADC JAUTO bit is set, Slave injected interruptions
- are enabled nevertheless (for same reason as above) */
- tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
- if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) {
- /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
- and in resetting HAL_ADC_STATE_INJ_EOC bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
- /* Next, set Slave injected interruptions */
- switch (hadc->Init.EOCSelection) {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
- }
- }
-#else
- /* ADC instance is not a multimode slave instance with multimode regular
- * conversions enabled */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Enable as well injected interruptions in case
- HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
- allows to start regular and injected conversions when JAUTO is
- set with a single call to HAL_ADC_Start_IT() */
- switch (hadc->Init.EOCSelection) {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
- }
-
- /* Start ADC group regular conversion */
- LL_ADC_REG_StartConversion(hadc->Instance);
-#endif
- } else {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- } else {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable interrution of
- * end-of-conversion, disable ADC peripheral.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on ADC groups regular and injected
- */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK) {
- /* Disable ADC end of conversion interrupt for regular group */
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Enable ADC, start conversion of regular group and transfer result
- * through DMA.
- * @note Interruptions enabled in this function:
- * overrun (if applicable), DMA half transfer, DMA transfer complete.
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled (when multimode feature is available):
- * HAL_ADC_Start_DMA() is designed for single-ADC mode only. For multimode, the
- * dedicated HAL_ADCEx_MultiModeStart_DMA() function must be used.
- * @param hadc ADC handle
- * @param pData Destination Buffer address.
- * @param Length Number of data to be transferred from ADC peripheral to memory
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData,
- uint32_t Length) {
- HAL_StatusTypeDef tmp_hal_status;
-#if defined(ADC_MULTIMODE_SUPPORT)
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* Process locked */
- __HAL_LOCK(hadc);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Ensure that multimode regular conversions are not enabled. */
- /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
- if ((ADC_IS_INDEPENDENT(hadc) != RESET) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN))
-#endif /* ADC_MULTIMODE_SUPPORT */
- {
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
- HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - if ADC instance is master or if multimode feature is not available
- - if multimode setting is disabled (ADC instance slave in independent
- mode) */
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) ==
- hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#endif
-
- /* Check if a conversion is on going on ADC group injected */
- if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) {
- /* Reset ADC error code fields related to regular conversions only */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- } else {
- /* Reset all ADC error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
- /* ADC start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc,
- (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* With DMA, overrun event is always considered as an error even if
- hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
- ADC_IT_OVR is enabled. */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Enable ADC DMA mode */
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-
- /* Start the DMA channel */
- tmp_hal_status =
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR,
- (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately.
- */
- /* If external trigger has been selected, conversion will start at next
- */
- /* trigger event. */
- /* Start ADC group regular conversion */
- LL_ADC_REG_StartConversion(hadc->Instance);
- } else {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- }
-#if defined(ADC_MULTIMODE_SUPPORT)
- else {
- tmp_hal_status = HAL_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-#endif
- } else {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on ADC group injected. If ADC group injected is under use,
- * it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note Case of multimode enabled (when multimode feature is available):
- * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
- * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must
- * be used.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential ADC group regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK) {
- /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop */
- /* while DMA transfer is on going) */
- if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) {
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripheral */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, */
- /* to keep in memory a potential failing status. */
- if (tmp_hal_status == HAL_OK) {
- tmp_hal_status = ADC_Disable(hadc);
- } else {
- (void)ADC_Disable(hadc);
- }
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Get ADC regular group conversion result.
- * @note Reading register DR automatically clears ADC flag EOC
- * (ADC group regular end of unitary conversion).
- * @note This function does not clear ADC flag EOS
- * (ADC group regular end of sequence conversion).
- * Occurrence of flag EOS rising:
- * - If sequencer is composed of 1 rank, flag EOS is equivalent
- * to flag EOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag EOC only is raised, at the end of the scan sequence
- * both flags EOC and EOS are raised.
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADC_PollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc ADC handle
- * @retval ADC group regular conversion data
- */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) {
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Note: EOC flag is not cleared here by software because automatically */
- /* cleared by hardware when reading register DR. */
-
- /* Return ADC converted value */
- return hadc->Instance->DR;
-}
-
-/**
- * @brief Start ADC conversion sampling phase of regular group
- * @note: This function should only be called to start sampling when
- * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
- * mode has been selected
- * - @ref ADC_SOFTWARE_START has been selected as trigger source
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc) {
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Start sampling */
- SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop ADC conversion sampling phase of regular group and start
- * conversion
- * @note: This function should only be called to stop sampling when
- * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
- * mode has been selected
- * - @ref ADC_SOFTWARE_START has been selected as trigger source
- * - after sampling has been started using @ref HAL_ADC_StartSampling.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc) {
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Start sampling */
- CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handle ADC interrupt request.
- * @param hadc ADC handle
- * @retval None
- */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) {
- uint32_t overrun_error =
- 0UL; /* flag set if overrun occurrence has to be considered as an error */
- uint32_t tmp_isr = hadc->Instance->ISR;
- uint32_t tmp_ier = hadc->Instance->IER;
- uint32_t tmp_adc_inj_is_trigger_source_sw_start;
- uint32_t tmp_adc_reg_is_trigger_source_sw_start;
- uint32_t tmp_cfgr;
-#if defined(ADC_MULTIMODE_SUPPORT)
- const ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-
- /* ========== Check End of Sampling flag for ADC group regular ========== */
- if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) &&
- ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) {
- /* Update state machine on end of sampling status if not in error state */
- if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
- }
-
- /* End Of Sampling callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->EndOfSamplingCallback(hadc);
-#else
- HAL_ADCEx_EndOfSamplingCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
- }
-
- /* ====== Check ADC group regular end of unitary conversion sequence
- * conversions ===== */
- if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) &&
- ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
- (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) &&
- ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) {
- /* Update state machine on conversion status if not in error state */
- if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- }
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going */
- /* to disable interruption. */
- if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) {
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
- /* check CONT bit directly in handle ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- } else {
- /* else need to check Master ADC CONT bit */
- tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-#else
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
-#endif
-
- /* Carry on if continuous mode is disabled */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) {
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) {
- /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
- /* ADSTART==0 (no conversion on going) */
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* Disable ADC end of sequence conversion interrupt */
- /* Note: Overrun interrupt was enabled with EOC interrupt in */
- /* HAL_Start_IT(), but is not disabled here because can be used */
- /* by overrun IRQ process below. */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- } else {
- /* Change ADC state to error state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- }
- }
-
- /* Conversion complete callback */
- /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
- /* to determine if conversion has been triggered from EOC or EOS, */
- /* possibility to use: */
- /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->ConvCpltCallback(hadc);
-#else
- HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Clear regular group conversion flag */
- /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
- /* conversion flags clear induces the release of the preserved data.*/
- /* Therefore, if the preserved data value is needed, it must be */
- /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
- }
-
- /* ====== Check ADC group injected end of unitary conversion sequence
- * conversions ===== */
- if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) &&
- ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
- (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) &&
- ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) {
- /* Update state machine on conversion status if not in error state */
- if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
- }
-
- /* Retrieve ADC configuration */
- tmp_adc_inj_is_trigger_source_sw_start =
- LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
- tmp_adc_reg_is_trigger_source_sw_start =
- LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- } else {
- tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-#else
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
-#endif
-
- /* Disable interruption if no further conversion upcoming by injected */
- /* external trigger or by automatic injected conversion with regular */
- /* group having no further conversion upcoming (same conditions as */
- /* regular group interruption disabling above), */
- /* and if injected scan sequence is completed. */
- if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) {
- if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) {
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) {
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come
- */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) {
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- } else {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- }
- }
- }
-
- /* Injected Conversion complete callback */
- /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
- if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
- if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
- interruption has been triggered by end of conversion or end of
- sequence. */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->InjectedConvCpltCallback(hadc);
-#else
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Clear injected group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
- }
-
- /* ========== Check Analog watchdog 1 flag ========== */
- if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) &&
- ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Level out of window 1 callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->LevelOutOfWindowCallback(hadc);
-#else
- HAL_ADC_LevelOutOfWindowCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
- }
-
- /* ========== Check analog watchdog 2 flag ========== */
- if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) &&
- ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Level out of window 2 callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->LevelOutOfWindow2Callback(hadc);
-#else
- HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
- }
-
- /* ========== Check analog watchdog 3 flag ========== */
- if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) &&
- ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Level out of window 3 callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->LevelOutOfWindow3Callback(hadc);
-#else
- HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
- }
-
- /* ========== Check Overrun flag ========== */
- if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) &&
- ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) {
- /* If overrun is set to overwrite previous data (default setting), */
- /* overrun event is not considered as an error. */
- /* (cf ref manual "Managing conversions without using the DMA and without */
- /* overrun ") */
- /* Exception for usage with DMA overrun event always considered as an */
- /* error. */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) {
- overrun_error = 1UL;
- } else {
- /* Check DMA configuration */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) {
- /* Multimode (when feature is available) is enabled,
- Common Control Register MDMA bits must be checked. */
- if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(
- hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) {
- overrun_error = 1UL;
- }
- } else
-#endif
- {
- /* Multimode not set or feature not available or ADC independent */
- if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) {
- overrun_error = 1UL;
- }
- }
- }
-
- if (overrun_error == 1UL) {
- /* Change ADC state to error state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-
- /* Set ADC error code to overrun */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-
- /* Error callback */
- /* Note: In case of overrun, ADC conversion data is preserved until */
- /* flag OVR is reset. */
- /* Therefore, old ADC conversion data can be retrieved in */
- /* function "HAL_ADC_ErrorCallback()". */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->ErrorCallback(hadc);
-#else
- HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
- }
-
- /* Clear ADC overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- }
-
- /* ========== Check Injected context queue overflow flag ========== */
- if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) &&
- ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) {
- /* Change ADC state to overrun state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- /* Set ADC error code to Injected context queue overflow */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-
- /* Clear the Injected context queue overflow flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-
- /* Injected context queue overflow callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->InjectedQueueOverflowCallback(hadc);
-#else
- HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief Conversion complete callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvCpltCallback must be implemented in the user
- file.
- */
-}
-
-/**
- * @brief Conversion DMA half-transfer callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvHalfCpltCallback must be implemented in the
- user file.
- */
-}
-
-/**
- * @brief Analog watchdog 1 callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_LevelOutOfWindowCallback must be implemented in the
- user file.
- */
-}
-
-/**
- * @brief ADC error callback in non-blocking mode
- * (ADC conversion with interruption or transfer by DMA).
- * @note In case of error due to overrun when using ADC with DMA transfer
- * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
- * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
- * - If needed, restart a new ADC conversion using function
- * "HAL_ADC_Start_DMA()"
- * (this function is also clearing overrun flag)
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ErrorCallback must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on regular group
- (+) Configure the analog watchdog
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure a channel to be assigned to ADC group regular.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be disabled using function
- * HAL_ADC_DeInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes channel into ADC group regular,
- * following calls to this function can be used to reconfigure
- * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
- * without resetting the ADC.
- * The setting of these parameters is conditioned to ADC state:
- * Refer to comments of structure "ADC_ChannelConfTypeDef".
- * @param hadc ADC handle
- * @param sConfig Structure of ADC channel assigned to ADC group regular.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc,
- ADC_ChannelConfTypeDef *sConfig) {
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmpOffsetShifted;
- uint32_t tmp_config_internal_channel;
- __IO uint32_t wait_loop_index = 0UL;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
- assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
-
- /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
- ignored (considered as reset) */
- assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) &&
- (hadc->Init.OversamplingMode == ENABLE)));
-
- /* Verification of channel number */
- if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) {
- assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
- } else {
- assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Channel number */
- /* - Channel rank */
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* Set ADC group regular sequence: channel on the selected scan sequence
- * rank */
- LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank,
- sConfig->Channel);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Channel sampling time */
- /* - Channel offset */
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
- if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
- if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) {
- /* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel,
- LL_ADC_SAMPLINGTIME_2CYCLES_5);
-
- /* Set ADC sampling time common configuration */
- LL_ADC_SetSamplingTimeCommonConfig(
- hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
- } else {
- /* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel,
- sConfig->SamplingTime);
-
- /* Set ADC sampling time common configuration */
- LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance,
- LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
- }
-
- /* Configure the offset: offset enable/disable, channel, offset value */
-
- /* Shift the offset with respect to the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set
- * to 0 */
- tmpOffsetShifted =
- ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
-
- if (sConfig->OffsetNumber != ADC_OFFSET_NONE) {
- /* Set ADC selected offset number */
- LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber,
- sConfig->Channel, tmpOffsetShifted);
-
- assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign));
- assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
- /* Set ADC selected offset sign & saturation */
- LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber,
- sConfig->OffsetSign);
- LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber,
- (sConfig->OffsetSaturation == ENABLE)
- ? LL_ADC_OFFSET_SATURATION_ENABLE
- : LL_ADC_OFFSET_SATURATION_DISABLE);
- } else {
- /* Scan each offset register to check if the selected channel is
- * targeted. */
- /* If this is the case, the corresponding offset number is disabled. */
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1,
- LL_ADC_OFFSET_DISABLE);
- }
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2,
- LL_ADC_OFFSET_DISABLE);
- }
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3,
- LL_ADC_OFFSET_DISABLE);
- }
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4,
- LL_ADC_OFFSET_DISABLE);
- }
- }
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Single or differential mode */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- /* Set mode single-ended or differential input of the selected ADC channel
- */
- LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel,
- sConfig->SingleDiff);
-
- /* Configuration of differential mode */
- if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) {
- /* Set sampling time of the selected ADC channel */
- /* Note: ADC channel number masked with value "0x1F" to ensure shift
- * value within 32 bits range */
- LL_ADC_SetChannelSamplingTime(
- hadc->Instance,
- (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
- (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) +
- 1UL) &
- 0x1FUL)),
- sConfig->SamplingTime);
- }
- }
-
- /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
- /* If internal channel selected, enable dedicated internal buffers and */
- /* paths. */
- /* Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_DeInit(). */
-
- if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) {
- tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance));
-
- /* If the requested internal measurement path has already been enabled, */
- /* bypass the configuration processing. */
- if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) ||
- (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) &&
- ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) ==
- 0UL)) {
- if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) {
- LL_ADC_SetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance),
- LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
-
- /* Delay for temperature sensor stabilization time */
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles, scaling in us split to not */
- /* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) *
- ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
- while (wait_loop_index != 0UL) {
- wait_loop_index--;
- }
- }
- } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) &&
- ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) ==
- 0UL)) {
- if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) {
- LL_ADC_SetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance),
- LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
- }
- } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
- ((tmp_config_internal_channel &
- LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) {
- if (ADC_VREFINT_INSTANCE(hadc)) {
- LL_ADC_SetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance),
- LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
- }
- } else {
- /* nothing to do */
- }
- }
- }
-
- /* If a conversion is on going on regular group, no update on regular */
- /* channel could be done on neither of the channel configuration structure */
- /* parameters. */
- else {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Configure the analog watchdog.
- * @note Possibility to update parameters on the fly:
- * This function initializes the selected analog watchdog, successive
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_AnalogWDGConfTypeDef".
- * @note On this STM32 series, analog watchdog thresholds can be modified
- * while ADC conversion is on going.
- * In this case, some constraints must be taken into account:
- * the programmed threshold values are effective from the next
- * ADC EOC (end of unitary conversion).
- * Considering that registers write delay may happen due to
- * bus activity, this might cause an uncertainty on the
- * effective timing of the new programmed threshold values.
- * @param hadc ADC handle
- * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(
- ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) {
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmpAWDHighThresholdShifted;
- uint32_t tmpAWDLowThresholdShifted;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
- assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
- assert_param(
- IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig));
- assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-
- if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) {
- assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
- }
-
- /* Verify thresholds range */
- if (hadc->Init.OversamplingMode == ENABLE) {
- /* Case of oversampling enabled: depending on ratio and shift configuration,
- analog watchdog thresholds can be higher than ADC resolution.
- Verify if thresholds are within maximum thresholds range. */
- assert_param(
- IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
- assert_param(
- IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
- } else {
- /* Verify if thresholds are within the selected ADC resolution */
- assert_param(
- IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
- assert_param(
- IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on ADC groups regular and injected: */
- /* - Analog watchdog channels */
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
- if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- /* Analog watchdog configuration */
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) {
- /* Configuration of analog watchdog: */
- /* - Set the analog watchdog enable mode: one or overall group of */
- /* channels, on groups regular and-or injected. */
- switch (AnalogWDGConfig->WatchdogMode) {
- case ADC_ANALOGWATCHDOG_SINGLE_REG:
- LL_ADC_SetAnalogWDMonitChannels(
- hadc->Instance, LL_ADC_AWD1,
- __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
- LL_ADC_GROUP_REGULAR));
- break;
-
- case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
- LL_ADC_SetAnalogWDMonitChannels(
- hadc->Instance, LL_ADC_AWD1,
- __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
- LL_ADC_GROUP_INJECTED));
- break;
-
- case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
- LL_ADC_SetAnalogWDMonitChannels(
- hadc->Instance, LL_ADC_AWD1,
- __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
- LL_ADC_GROUP_REGULAR_INJECTED));
- break;
-
- case ADC_ANALOGWATCHDOG_ALL_REG:
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
- LL_ADC_AWD_ALL_CHANNELS_REG);
- break;
-
- case ADC_ANALOGWATCHDOG_ALL_INJEC:
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
- LL_ADC_AWD_ALL_CHANNELS_INJ);
- break;
-
- case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
- LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
- break;
-
- default: /* ADC_ANALOGWATCHDOG_NONE */
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
- LL_ADC_AWD_DISABLE);
- break;
- }
-
- /* Set the filtering configuration */
- MODIFY_REG(hadc->Instance->TR1, ADC_TR1_AWDFILT,
- AnalogWDGConfig->FilteringConfig);
-
- /* Update state, clear previous result related to AWD1 */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Clear flag ADC analog watchdog */
- /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
- /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
- /* (in case left enabled by previous ADC operations). */
- LL_ADC_ClearFlag_AWD1(hadc->Instance);
-
- /* Configure ADC analog watchdog interrupt */
- if (AnalogWDGConfig->ITMode == ENABLE) {
- LL_ADC_EnableIT_AWD1(hadc->Instance);
- } else {
- LL_ADC_DisableIT_AWD1(hadc->Instance);
- }
- }
- /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
- else {
- switch (AnalogWDGConfig->WatchdogMode) {
- case ADC_ANALOGWATCHDOG_SINGLE_REG:
- case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
- case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
- /* Update AWD by bitfield to keep the possibility to monitor */
- /* several channels by successive calls of this function. */
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) {
- SET_BIT(hadc->Instance->AWD2CR,
- (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- AnalogWDGConfig->Channel) &
- 0x1FUL)));
- } else {
- SET_BIT(hadc->Instance->AWD3CR,
- (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- AnalogWDGConfig->Channel) &
- 0x1FUL)));
- }
- break;
-
- case ADC_ANALOGWATCHDOG_ALL_REG:
- case ADC_ANALOGWATCHDOG_ALL_INJEC:
- case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
- AnalogWDGConfig->WatchdogNumber,
- LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
- break;
-
- default: /* ADC_ANALOGWATCHDOG_NONE */
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
- AnalogWDGConfig->WatchdogNumber,
- LL_ADC_AWD_DISABLE);
- break;
- }
-
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) {
- /* Update state, clear previous result related to AWD2 */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Clear flag ADC analog watchdog */
- /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
- /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
- /* (in case left enabled by previous ADC operations). */
- LL_ADC_ClearFlag_AWD2(hadc->Instance);
-
- /* Configure ADC analog watchdog interrupt */
- if (AnalogWDGConfig->ITMode == ENABLE) {
- LL_ADC_EnableIT_AWD2(hadc->Instance);
- } else {
- LL_ADC_DisableIT_AWD2(hadc->Instance);
- }
- }
- /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
- else {
- /* Update state, clear previous result related to AWD3 */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Clear flag ADC analog watchdog */
- /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
- /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
- /* (in case left enabled by previous ADC operations). */
- LL_ADC_ClearFlag_AWD3(hadc->Instance);
-
- /* Configure ADC analog watchdog interrupt */
- if (AnalogWDGConfig->ITMode == ENABLE) {
- LL_ADC_EnableIT_AWD3(hadc->Instance);
- } else {
- LL_ADC_DisableIT_AWD3(hadc->Instance);
- }
- }
- }
- }
-
- /* Analog watchdog thresholds configuration */
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) {
- /* Shift the offset with respect to the selected ADC resolution: */
- /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
- /* are set to 0. */
- tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(
- hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted =
- ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
- }
- /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
- else {
- /* Shift the offset with respect to the selected ADC resolution: */
- /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */
- /* are set to 0. */
- tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(
- hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(
- hadc, AnalogWDGConfig->LowThreshold);
- }
-
- /* Set ADC analog watchdog thresholds value of both thresholds high and low */
- LL_ADC_ConfigAnalogWDThresholds(
- hadc->Instance, AnalogWDGConfig->WatchdogNumber,
- tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- * @brief ADC Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral state and errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions to get in run-time the status of the
- peripheral.
- (+) Check the ADC state
- (+) Check the ADC error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the ADC handle state.
- * @note ADC state machine is managed by bitfields, ADC status must be
- * compared with states bits.
- * For example:
- * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
- * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
- * @param hadc ADC handle
- * @retval ADC handle state (bitfield on 32 bits)
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) {
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Return ADC handle state */
- return hadc->State;
-}
-
-/**
- * @brief Return the ADC error code.
- * @param hadc ADC handle
- * @retval ADC error code (bitfield on 32 bits)
- */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) {
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- return hadc->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-
-/**
- * @brief Stop ADC conversion.
- * @param hadc ADC handle
- * @param ConversionGroup ADC group regular and/or injected.
- * This parameter can be one of the following values:
- * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
- * @arg @ref ADC_INJECTED_GROUP ADC injected conversion
- * type.
- * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected
- * conversion type.
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc,
- uint32_t ConversionGroup) {
- uint32_t tickstart;
- uint32_t Conversion_Timeout_CPU_cycles = 0UL;
- uint32_t conversion_group_reassigned = ConversionGroup;
- uint32_t tmp_ADC_CR_ADSTART_JADSTART;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
-
- /* Verification if ADC is not already stopped (on regular and injected */
- /* groups) to bypass this function if not needed. */
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
- if ((tmp_adc_is_conversion_on_going_regular != 0UL) ||
- (tmp_adc_is_conversion_on_going_injected != 0UL)) {
- /* Particular case of continuous auto-injection mode combined with */
- /* auto-delay mode. */
- /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
- /* injected group stop ADC_CR_JADSTP). */
- /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
- /* (see reference manual). */
- if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) &&
- (hadc->Init.ContinuousConvMode == ENABLE) &&
- (hadc->Init.LowPowerAutoWait == ENABLE)) {
- /* Use stop of regular group */
- conversion_group_reassigned = ADC_REGULAR_GROUP;
-
- /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
- while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) {
- if (Conversion_Timeout_CPU_cycles >=
- (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- Conversion_Timeout_CPU_cycles++;
- }
-
- /* Clear JEOS */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
- }
-
- /* Stop potential conversion on going on ADC group regular */
- if (conversion_group_reassigned != ADC_INJECTED_GROUP) {
- /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) {
- if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) {
- /* Stop ADC group regular conversion */
- LL_ADC_REG_StopConversion(hadc->Instance);
- }
- }
- }
-
- /* Stop potential conversion on going on ADC group injected */
- if (conversion_group_reassigned != ADC_REGULAR_GROUP) {
- /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) {
- if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) {
- /* Stop ADC group injected conversion */
- LL_ADC_INJ_StopConversion(hadc->Instance);
- }
- }
- }
-
- /* Selection of start and stop bits with respect to the regular or injected
- * group */
- switch (conversion_group_reassigned) {
- case ADC_REGULAR_INJECTED_GROUP:
- tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
- break;
- case ADC_INJECTED_GROUP:
- tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
- break;
- /* Case ADC_REGULAR_GROUP only*/
- default:
- tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
- break;
- }
-
- /* Wait for conversion effectively stopped */
- tickstart = HAL_GetTick();
-
- while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) {
- if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption */
- if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable the selected ADC.
- * @note Prerequisite condition to use this function: ADC must be disabled
- * and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) {
- uint32_t tickstart;
-
- /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
- /* enabling phase not yet completed: flag ADC ready not yet set). */
- /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
- /* causes: ADC clock not running, ...). */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- /* Check if conditions to enable the ADC are fulfilled */
- if ((hadc->Instance->CR &
- (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |
- ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- /* Enable the ADC peripheral */
- LL_ADC_Enable(hadc->Instance);
-
- /* Wait for ADC effectively enabled */
- tickstart = HAL_GetTick();
-
- while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) {
- /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
- has been cleared (after a calibration), ADEN bit is reset by the
- calibration logic.
- The workaround is to continue setting ADEN until ADRDY is becomes 1.
- Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
- 4 ADC clock cycle duration */
- /* Note: Test of ADC enabled required due to hardware constraint to */
- /* not enable ADC if already enabled. */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- LL_ADC_Enable(hadc->Instance);
- }
-
- if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Disable the selected ADC.
- * @note Prerequisite condition to use this function: ADC conversions must be
- * stopped.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) {
- uint32_t tickstart;
- const uint32_t tmp_adc_is_disable_on_going =
- LL_ADC_IsDisableOngoing(hadc->Instance);
-
- /* Verification if ADC is not already disabled: */
- /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
- /* disabled. */
- if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) &&
- (tmp_adc_is_disable_on_going == 0UL)) {
- /* Check if conditions to disable the ADC are fulfilled */
- if ((hadc->Instance->CR &
- (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) {
- /* Disable the ADC peripheral */
- LL_ADC_Disable(hadc->Instance);
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
- } else {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- /* Wait for ADC effectively disabled */
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) {
- if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption */
- if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief DMA transfer complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) {
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef *hadc =
- (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Update state machine on conversion status if not in error state */
- if ((hadc->State &
- (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going */
- /* to disable interruption. */
- /* Is it the end of the regular sequence ? */
- if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) {
- /* Are conversions software-triggered ? */
- if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) {
- /* Is CONT bit set ? */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) {
- /* CONT bit is not set, no more conversions expected */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
- } else {
- /* DMA End of Transfer interrupt was triggered but conversions sequence
- is not over. If DMACFG is set to 0, conversions are stopped. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) {
- /* DMACFG bit is not set, conversions are stopped. */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
-
- /* Conversion complete callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->ConvCpltCallback(hadc);
-#else
- HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
- } else /* DMA and-or internal error occurred */
- {
- if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) {
- /* Call HAL ADC Error Callback function */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->ErrorCallback(hadc);
-#else
- HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
- } else {
- /* Call ADC DMA error callback */
- hadc->DMA_Handle->XferErrorCallback(hdma);
- }
- }
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) {
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef *hadc =
- (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Half conversion callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->ConvHalfCpltCallback(hadc);
-#else
- HAL_ADC_ConvHalfCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA error callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAError(DMA_HandleTypeDef *hdma) {
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef *hadc =
- (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
- /* Set ADC error code to DMA error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-
- /* Error callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- hadc->ErrorCallback(hadc);
-#else
- HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ * Other functions (extended functions) are available in file
+ * "stm32g4xx_hal_adc_ex.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+ (+) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (channel wise)
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Configurable delay between conversions in Dual interleaved mode.
+
+ (+) ADC channels selectable single/differential input.
+
+ (+) ADC offset shared on 4 offset instances.
+ (+) ADC gain compensation
+
+ (+) ADC calibration
+
+ (+) ADC conversion of regular group.
+
+ (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
+
+ (+++) ADC clock (conversions clock).
+ Two possible clock sources: synchronous clock derived from
+ AHB clock or asynchronous clock derived from system clock or PLL (output
+ divider P) running up to 75MHz.
+
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
+
+ RCC_ADCCLKSOURCE_PLL enable: (optional: if
+ asynchronous clock selected)
+ (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (++) ADC clock source and clock prescaler are configured at ADC level
+ with parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) RCC_OscInitStructure.OscillatorType =
+ RCC_OSCILLATORTYPE_HSI14;
+ (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not
+ used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following
+ callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer
+ callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion
+ complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue
+ overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback
+ ID and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the
+ default weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral
+ handle, and the Callback ID. This function allows to reset following
+ callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer
+ callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion
+ complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue
+ overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref
+ HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref
+ HAL_ADC_DeInit() only when these callbacks are null (not registered
+ beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref
+ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered
+ beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state
+ only. Exception done MspInit/MspDeInit functions that can be
+ registered/unregistered in @ref HAL_ADC_STATE_READY or @ref
+ HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can
+ be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all
+ callbacks are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+#define ADC_CFGR_FIELDS_1 \
+ (ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | \
+ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_EXTEN | \
+ ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can \
+be updated when no regular conversion is on-going */
+
+/* Timeout values for ADC operations (enable settling time, */
+/* disable settling time, ...). */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
+#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed. */
+/* Timeout fixed to longest ADC conversion possible, for 1 channel: */
+/* - maximum sampling time (640.5 adc_clk) */
+/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
+/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
+/* - ADC oversampling ratio 256 */
+/* Calculation: 653 * 4096 * 256 CPU clock cycles max */
+/* Unit: cycles of CPU clock. */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES \
+ (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization
+functions
+ * @brief ADC Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (refer to description of RCC configuration for ADC
+ * in header of this file).
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note Parameters related to common ADC registers (ADC clock mode) are set
+ * only if all ADCs are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_cfgr;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check ADC handle */
+ if (hadc == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
+ assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE) {
+ assert_param(
+ IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* DISCEN and CONT bits cannot be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) &&
+ (hadc->Init.ContinuousConvMode == ENABLE)));
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET) {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback =
+ HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback =
+ HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback =
+ HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ hadc->InjectedConvCpltCallback =
+ HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
+ hadc->InjectedQueueOverflowCallback =
+ HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow2Callback =
+ HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow3Callback =
+ HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
+ hadc->EndOfSamplingCallback =
+ HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
+
+ if (hadc->MspInitCallback == NULL) {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize Lock */
+ hadc->Lock = HAL_UNLOCKED;
+ }
+
+ /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) {
+ /* Disable ADC deep power down mode */
+ LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+ /* System was in deep power down mode, calibration must
+ be relaunched or a previously saved calibration factor
+ re-applied once the ADC voltage regulator is enabled */
+ }
+
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) {
+ /* Enable ADC internal voltage regulator */
+ LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) *
+ ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL) {
+ wait_loop_index--;
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+ if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) &&
+ (tmp_adc_is_conversion_on_going_regular == 0UL)) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - clock configuration */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
+ /* Reset configuration of ADC common register CCR: */
+ /* */
+ /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set
+ */
+ /* according to adc->Init.ClockPrescaler. It selects the clock */
+ /* source and sets the clock division factor. */
+ /* */
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - when multimode feature is available, multimode-related */
+ /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
+ /* HAL_ADCEx_MultiModeConfigChannel() ) */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() or */
+ /* HAL_ADCEx_InjectedConfigChannel() ) */
+ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ hadc->Init.ClockPrescaler);
+ }
+ }
+
+ /* Configuration of ADC: */
+ /* - resolution Init.Resolution */
+ /* - data alignment Init.DataAlign */
+ /* - external trigger to start conversion Init.ExternalTrigConv */
+ /* - external trigger polarity Init.ExternalTrigConvEdge */
+ /* - continuous conversion mode Init.ContinuousConvMode */
+ /* - overrun Init.Overrun */
+ /* - discontinuous mode Init.DiscontinuousConvMode */
+ /* - discontinuous mode channel count Init.NbrOfDiscConversion */
+ tmp_cfgr =
+ (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun | hadc->Init.DataAlign | hadc->Init.Resolution |
+ ADC_CFGR_REG_DISCONTINUOUS(
+ (uint32_t)hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE) {
+ tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) {
+ tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) |
+ hadc->Init.ExternalTrigConvEdge);
+ }
+
+ /* Update Configuration Register CFGR */
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
+
+ /* Configuration of sampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG,
+ hadc->Init.SamplingMode);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Gain Compensation Init.GainCompensation */
+ /* - DMA continuous request Init.DMAContinuousRequests */
+ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
+ /* - Oversampling parameters Init.Oversampling */
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ tmp_cfgr =
+ (ADC_CFGR_DFSDM(hadc) |
+ ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
+
+ if (hadc->Init.GainCompensation != 0UL) {
+ SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+ MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF,
+ hadc->Init.GainCompensation);
+ } else {
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+ MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
+ }
+
+ if (hadc->Init.OversamplingMode == ENABLE) {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+ assert_param(
+ IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+ assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(
+ hadc->Init.Oversampling.TriggeredMode));
+ assert_param(IS_ADC_REGOVERSAMPLING_MODE(
+ hadc->Init.Oversampling.OversamplingStopReset));
+
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ MODIFY_REG(
+ hadc->Instance->CFGR2,
+ ADC_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS | ADC_CFGR2_ROVSM,
+ ADC_CFGR2_ROVSE | hadc->Init.Oversampling.Ratio |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset);
+ } else {
+ /* Disable ADC oversampling scope on ADC group regular */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+ }
+ }
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) {
+ /* Set number of ranks in regular group sequencer */
+ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L,
+ (hadc->Init.NbrOfConversion - (uint8_t)1));
+ } else {
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ }
+
+ /* Initialize the ADC state */
+ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ } else {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * (function "HAL_ADC_MspDeInit()" is also called under the same
+ * conditions: all ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behavior in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+ * this saves more power by reducing leakage currents
+ * and is particularly interesting before entering MCU low-power modes.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check ADC handle */
+ if (hadc == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ /* Flush register JSQR: reset the queue sequencer when injected */
+ /* queue sequencer is enabled and ADC disabled. */
+ /* The software and hardware triggers of the injected sequence are both */
+ /* internally disabled just after the completion of the last valid */
+ /* injected sequence. */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK) {
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+ /* Note: HAL ADC deInit is done independently of ADC conversion stop */
+ /* and disable return status. In case of status fail, attempt to */
+ /* perform deinitialization anyway and it is up user code in */
+ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
+ /* system RCC hard reset. */
+
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(
+ hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF |
+ ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(
+ hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF |
+ ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS |
+ ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+ /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+ ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+ no direct reset applicable.
+ Update CR register to reset value where doable by software */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+ SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS |
+ ADC_CFGR2_OVSS | ADC_CFGR2_OVSR |
+ ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2,
+ ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+ /* Reset register TR1 */
+ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register TR2 */
+ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+
+ /* Reset register TR3 */
+ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 |
+ ADC_SQR3_SQ12 | ADC_SQR3_SQ11 |
+ ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Register JSQR was reset when the ADC was disabled */
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(hadc->Instance->OFR1,
+ ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(hadc->Instance->OFR2,
+ ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(hadc->Instance->OFR3,
+ ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(hadc->Instance->OFR4,
+ ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT,
+ ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+ /* ========== Reset common ADC registers ========== */
+
+ /* Software is allowed to change common parameters only when all the other
+ ADCs are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
+ /* Reset configuration of ADC common register CCR:
+ - clock mode: CKMODE, PRESCEN
+ - multimode related parameters (when this feature is available): MDMA,
+ DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+ - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ */
+ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripherals instances */
+ /* sharing the same common ADC instance: ADC state is forced to */
+ /* a similar state as after device power-on. */
+ /* Note: A possible implementation is to add RCC bus reset of ADC */
+ /* (for example, using macro */
+ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL) {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Reset injected channel configuration parameters */
+ hadc->InjectionConfig.ContextQueue = 0;
+ hadc->InjectionConfig.ChannelCount = 0;
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initialize the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the ADC MSP.
+ * @param hadc ADC handle
+ * @note All ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion
+ * complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA
+ * half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog
+ * 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback
+ * ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected
+ * conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected
+ * context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog
+ * 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog
+ * 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling
+ * callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init
+ * callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit
+ * callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc,
+ HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) {
+ switch (CallbackID) {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID:
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID:
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID:
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID:
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID:
+ hadc->InjectedConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID:
+ hadc->InjectedQueueOverflowCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID:
+ hadc->LevelOutOfWindow2Callback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID:
+ hadc->LevelOutOfWindow3Callback = pCallback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID:
+ hadc->EndOfSamplingCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID:
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID:
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (HAL_ADC_STATE_RESET == hadc->State) {
+ switch (CallbackID) {
+ case HAL_ADC_MSPINIT_CB_ID:
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID:
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion
+ * complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA
+ * half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog
+ * 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback
+ * ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected
+ * conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected
+ * context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog
+ * 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog
+ * 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling
+ * callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init
+ * callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit
+ * callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(
+ ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) {
+ switch (CallbackID) {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID:
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID:
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID:
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID:
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID:
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID:
+ hadc->InjectedQueueOverflowCallback =
+ HAL_ADCEx_InjectedQueueOverflowCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID:
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID:
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID:
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID:
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID:
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default:
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (HAL_ADC_STATE_RESET == hadc->State) {
+ switch (CallbackID) {
+ case HAL_ADC_MSPINIT_CB_ID:
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID:
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default:
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation
+functions
+ * @brief ADC IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable ADC, start conversion of regular group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * if ADC is Slave, ADC is enabled but conversion is not started,
+ * if ADC is master, ADC is enabled and multimode conversion is
+ * started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
+ HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent
+ mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ } else {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations)
+ */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
+ /* ADC instance is not a multimode slave instance with multimode regular
+ * conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ } else {
+ /* ADC instance is a multimode slave instance with multimode regular
+ * conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ /* if Master ADC JAUTO bit is set, update Slave State in setting
+ HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit
+ */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+#else
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+ } else {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ } else {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop
+ * function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected
+ */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK) {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc,
+ uint32_t Timeout) {
+ uint32_t tickstart;
+ uint32_t tmp_Flag_End;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence conversions */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) {
+ tmp_Flag_End = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of unitary conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
+ /* Check ADC DMA mode in independent mode on ADC group regular */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ } else {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ } else {
+ /* Check ADC DMA mode in multimode on ADC group regular */
+ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(
+ hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ } else {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ }
+#else
+ /* Check ADC DMA mode */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ } else {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of unitary conversion or sequence conversions flag is raised
+ */
+ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) &&
+ (hadc->Init.ContinuousConvMode == DISABLE)) {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
+ /* Retrieve handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ } else {
+ /* Retrieve Master ADC CFGR register */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ /* Retrieve handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear polled flag */
+ if (tmp_Flag_End == ADC_FLAG_EOS) {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+ } else {
+ /* Clear end of conversion EOC flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for ADC event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main
+ * analog watchdog, present on all STM32 series)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional
+ * analog watchdog, not present on all STM32 series)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional
+ * analog watchdog, not present on all STM32 series)
+ * @arg @ref ADC_OVR_EVENT ADC Overrun event
+ * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow
+ * event
+ * @param Timeout Timeout value in millisecond.
+ * @note The relevant flag is cleared if found to be set, except for
+ * ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is
+ * set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially
+ * overwritten by a new converted data as soon as OVR is cleared. To reset OVR
+ * flag once the preserved data is retrieved, the user can resort to macro
+ * __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc,
+ uint32_t EventType, uint32_t Timeout) {
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ switch (EventType) {
+ /* End Of Sampling event */
+ case ADC_EOSMP_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+ /* Clear the End Of Sampling flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+ break;
+
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog
+ */
+ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
+
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+ break;
+
+ /* Injected context queue overflow event */
+ case ADC_JQOVF_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear ADC Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without
+ */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ } else {
+ /* Clear ADC Overrun flag only if Overrun is set to
+ ADC_OVR_DATA_OVERWRITTEN otherwise, data register is potentially
+ overwritten by new converted data as soon as OVR is cleared. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+ break;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : EOC (end of conversion), EOS (end of sequence),
+ * OVR overrun.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+ * ADC Master.
+ * For ADC Slave, ADC is enabled only (conversion is not started).
+ * For ADC Master, ADC is enabled and multimode conversion is started.
+ * @note To guarantee a proper reset of all interruptions once all the needed
+ * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+ * a correct stop of the IT-based conversions.
+ * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+ * interruption. If required (e.g. in case of oversampling with trigger
+ * mode), the user must:
+ * 1. first clear the EOSMP flag if set with macro
+ * __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+ * 2. then enable the EOSMP interrupt with macro
+ * __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
+ HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent
+ mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ } else {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations)
+ */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Disable all interruptions before enabling the desired ones */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection) {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ break;
+ }
+
+ /* Enable ADC overrun interrupt */
+ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+ ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+ behavior and no CPU time is lost for a non-processed interruption */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
+ /* ADC instance is not a multimode slave instance with multimode regular
+ * conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection) {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ } else {
+ /* ADC instance is a multimode slave instance with multimode regular
+ * conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ /* if Master ADC JAUTO bit is set, Slave injected interruptions
+ are enabled nevertheless (for same reason as above) */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) {
+ /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+ and in resetting HAL_ADC_STATE_INJ_EOC bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+ /* Next, set Slave injected interruptions */
+ switch (hadc->Init.EOCSelection) {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+ }
+#else
+ /* ADC instance is not a multimode slave instance with multimode regular
+ * conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection) {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+ } else {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ } else {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected
+ */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK) {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group and transfer result
+ * through DMA.
+ * @note Interruptions enabled in this function:
+ * overrun (if applicable), DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Start_DMA() is designed for single-ADC mode only. For multimode, the
+ * dedicated HAL_ADCEx_MultiModeStart_DMA() function must be used.
+ * @param hadc ADC handle
+ * @param pData Destination Buffer address.
+ * @param Length Number of data to be transferred from ADC peripheral to memory
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData,
+ uint32_t Length) {
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Ensure that multimode regular conversions are not enabled. */
+ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
+ if ((ADC_IS_INDEPENDENT(hadc) != RESET) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN))
+#endif /* ADC_MULTIMODE_SUPPORT */
+ {
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
+ HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent
+ mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) ==
+ hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ } else {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
+ /* ADC start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc,
+ (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* With DMA, overrun event is always considered as an error even if
+ hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+ ADC_IT_OVR is enabled. */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Start the DMA channel */
+ tmp_hal_status =
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR,
+ (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately.
+ */
+ /* If external trigger has been selected, conversion will start at next
+ */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ } else {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ }
+#if defined(ADC_MULTIMODE_SUPPORT)
+ else {
+ tmp_hal_status = HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+ } else {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on ADC group injected. If ADC group injected is under use,
+ * it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must
+ * be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential ADC group regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK) {
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) {
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK) {
+ tmp_hal_status = ADC_Disable(hadc);
+ } else {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) {
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Start ADC conversion sampling phase of regular group
+ * @note: This function should only be called to start sampling when
+ * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+ * mode has been selected
+ * - @ref ADC_SOFTWARE_START has been selected as trigger source
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc) {
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Start sampling */
+ SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop ADC conversion sampling phase of regular group and start
+ * conversion
+ * @note: This function should only be called to stop sampling when
+ * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+ * mode has been selected
+ * - @ref ADC_SOFTWARE_START has been selected as trigger source
+ * - after sampling has been started using @ref HAL_ADC_StartSampling.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc) {
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Start sampling */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) {
+ uint32_t overrun_error =
+ 0UL; /* flag set if overrun occurrence has to be considered as an error */
+ uint32_t tmp_isr = hadc->Instance->ISR;
+ uint32_t tmp_ier = hadc->Instance->IER;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Sampling flag for ADC group regular ========== */
+ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) &&
+ ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) {
+ /* Update state machine on end of sampling status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+ }
+
+ /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->EndOfSamplingCallback(hadc);
+#else
+ HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+ }
+
+ /* ====== Check ADC group regular end of unitary conversion sequence
+ * conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) &&
+ ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+ (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) &&
+ ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) {
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)) {
+ /* check CONT bit directly in handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ } else {
+ /* else need to check Master ADC CONT bit */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Carry on if continuous mode is disabled */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ } else {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
+ /* to determine if conversion has been triggered from EOC or EOS, */
+ /* possibility to use: */
+ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ /* ====== Check ADC group injected end of unitary conversion sequence
+ * conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) &&
+ ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+ (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) &&
+ ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start =
+ LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start =
+ LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ } else {
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Disable interruption if no further conversion upcoming by injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above), */
+ /* and if injected scan sequence is completed. */
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) {
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) {
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come
+ */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) {
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ } else {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+ }
+
+ /* Injected Conversion complete callback */
+ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ interruption has been triggered by end of conversion or end of
+ sequence. */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedConvCpltCallback(hadc);
+#else
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* ========== Check Analog watchdog 1 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) &&
+ ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) &&
+ ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow2Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) &&
+ ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow3Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+
+ /* ========== Check Overrun flag ========== */
+ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) &&
+ ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) {
+ overrun_error = 1UL;
+ } else {
+ /* Check DMA configuration */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) {
+ /* Multimode (when feature is available) is enabled,
+ Common Control Register MDMA bits must be checked. */
+ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(
+ hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) {
+ overrun_error = 1UL;
+ }
+ } else
+#endif /* ADC_MULTIMODE_SUPPORT */
+ {
+ /* Multimode not set or feature not available or ADC independent */
+ if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) {
+ overrun_error = 1UL;
+ }
+ }
+ }
+
+ if (overrun_error == 1UL) {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ /* Note: In case of overrun, ADC conversion data is preserved until */
+ /* flag OVR is reset. */
+ /* Therefore, old ADC conversion data can be retrieved in */
+ /* function "HAL_ADC_ErrorCallback()". */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+ /* ========== Check Injected context queue overflow flag ========== */
+ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) &&
+ ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) {
+ /* Change ADC state to overrun state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear the Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ /* Injected context queue overflow callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedQueueOverflowCallback(hadc);
+#else
+ HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user
+ file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the
+ user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 1 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOutOfWindowCallback must be implemented in the
+ user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non-blocking mode
+ * (ADC conversion with interruption or transfer by DMA).
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group regular.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into ADC group regular,
+ * following calls to this function can be used to reconfigure
+ * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+ * without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param pConfig Structure of ADC channel assigned to ADC group regular.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc,
+ const ADC_ChannelConfTypeDef *pConfig) {
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpOffsetShifted;
+ uint32_t tmp_config_internal_channel;
+ __IO uint32_t wait_loop_index = 0UL;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
+ assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
+
+ /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+ ignored (considered as reset) */
+ assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) &&
+ (hadc->Init.OversamplingMode == ENABLE)));
+
+ /* Verification of channel number */
+ if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) {
+ assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
+ } else {
+ assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel rank */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* Set ADC group regular sequence: channel on the selected scan sequence
+ * rank */
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank,
+ pConfig->Channel);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+ if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel,
+ LL_ADC_SAMPLINGTIME_2CYCLES_5);
+
+ /* Set ADC sampling time common configuration */
+ LL_ADC_SetSamplingTimeCommonConfig(
+ hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+ } else {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel,
+ pConfig->SamplingTime);
+
+ /* Set ADC sampling time common configuration */
+ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance,
+ LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+ }
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set
+ * to 0 */
+ tmpOffsetShifted =
+ ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
+
+ if (pConfig->OffsetNumber != ADC_OFFSET_NONE) {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber,
+ pConfig->Channel, tmpOffsetShifted);
+
+ assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
+ /* Set ADC selected offset sign & saturation */
+ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber,
+ pConfig->OffsetSign);
+ LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
+ (pConfig->OffsetSaturation == ENABLE)
+ ? LL_ADC_OFFSET_SATURATION_ENABLE
+ : LL_ADC_OFFSET_SATURATION_DISABLE);
+ } else {
+ /* Scan each offset register to check if the selected channel is
+ * targeted. */
+ /* If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ /* Set mode single-ended or differential input of the selected ADC channel
+ */
+ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel,
+ pConfig->SingleDiff);
+
+ /* Configuration of differential mode */
+ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) {
+ /* Set sampling time of the selected ADC channel */
+ /* Note: ADC channel number masked with value "0x1F" to ensure shift
+ * value within 32 bits range */
+ LL_ADC_SetChannelSamplingTime(
+ hadc->Instance,
+ (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
+ (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) +
+ 1UL) &
+ 0x1FUL)),
+ pConfig->SamplingTime);
+ }
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) ||
+ (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) ==
+ 0UL)) {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) {
+ LL_ADC_SetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) *
+ ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL) {
+ wait_loop_index--;
+ }
+ }
+ } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) ==
+ 0UL)) {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) {
+ LL_ADC_SetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
+ ((tmp_config_internal_channel &
+ LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) {
+ if (ADC_VREFINT_INSTANCE(hadc)) {
+ LL_ADC_SetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ } else {
+ /* nothing to do */
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Configure the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, successive
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @note On this STM32 series, analog watchdog thresholds can be modified
+ * while ADC conversion is on going.
+ * In this case, some constraints must be taken into account:
+ * the programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
+ * @param hadc ADC handle
+ * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(
+ ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) {
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_awd_high_threshold_shifted;
+ uint32_t tmp_awd_low_threshold_shifted;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
+ assert_param(
+ IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
+ assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
+
+ if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) {
+ assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
+ }
+
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE) {
+ /* Case of oversampling enabled: depending on ratio and shift configuration,
+ analog watchdog thresholds can be higher than ADC resolution.
+ Verify if thresholds are within maximum thresholds range. */
+ assert_param(
+ IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
+ assert_param(
+ IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
+ } else {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+ pAnalogWDGConfig->HighThreshold));
+ assert_param(
+ IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on ADC groups regular and injected: */
+ /* - Analog watchdog channels */
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ /* Analog watchdog configuration */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: one or overall group of */
+ /* channels, on groups regular and-or injected. */
+ switch (pAnalogWDGConfig->WatchdogMode) {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ LL_ADC_SetAnalogWDMonitChannels(
+ hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(
+ hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(
+ hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ LL_ADC_AWD_ALL_CHANNELS_REG);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ LL_ADC_AWD_ALL_CHANNELS_INJ);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ /* Set the filtering configuration */
+ MODIFY_REG(hadc->Instance->TR1, ADC_TR1_AWDFILT,
+ pAnalogWDGConfig->FilteringConfig);
+
+ /* Update state, clear previous result related to AWD1 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE) {
+ LL_ADC_EnableIT_AWD1(hadc->Instance);
+ } else {
+ LL_ADC_DisableIT_AWD1(hadc->Instance);
+ }
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+ else {
+ switch (pAnalogWDGConfig->WatchdogMode) {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) {
+ SET_BIT(hadc->Instance->AWD2CR,
+ (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ pAnalogWDGConfig->Channel) &
+ 0x1FUL)));
+ } else {
+ SET_BIT(hadc->Instance->AWD3CR,
+ (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ pAnalogWDGConfig->Channel) &
+ 0x1FUL)));
+ }
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
+ pAnalogWDGConfig->WatchdogNumber,
+ LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
+ pAnalogWDGConfig->WatchdogNumber,
+ LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) {
+ /* Update state, clear previous result related to AWD2 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE) {
+ LL_ADC_EnableIT_AWD2(hadc->Instance);
+ } else {
+ LL_ADC_DisableIT_AWD2(hadc->Instance);
+ }
+ }
+ /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else {
+ /* Update state, clear previous result related to AWD3 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE) {
+ LL_ADC_EnableIT_AWD3(hadc->Instance);
+ } else {
+ LL_ADC_DisableIT_AWD3(hadc->Instance);
+ }
+ }
+ }
+ }
+
+ /* Analog watchdog thresholds configuration */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) {
+ /* Shift the offset with respect to the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* are set to 0. */
+ tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(
+ hadc, pAnalogWDGConfig->HighThreshold);
+ tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(
+ hadc, pAnalogWDGConfig->LowThreshold);
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+ else {
+ /* Shift the offset with respect to the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */
+ /* are set to 0. */
+ tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(
+ hadc, pAnalogWDGConfig->HighThreshold);
+ tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(
+ hadc, pAnalogWDGConfig->LowThreshold);
+ }
+
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ LL_ADC_ConfigAnalogWDThresholds(
+ hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
+ tmp_awd_high_threshold_shifted, tmp_awd_low_threshold_shifted);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ADC handle state.
+ * @note ADC state machine is managed by bitfields, ADC status must be
+ * compared with states bits.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ * @param hadc ADC handle
+ * @retval ADC handle state (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) {
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC handle state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code.
+ * @param hadc ADC handle
+ * @retval ADC error code (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) {
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Stop ADC conversion.
+ * @param hadc ADC handle
+ * @param ConversionGroup ADC group regular and/or injected.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
+ * @arg @ref ADC_INJECTED_GROUP ADC injected conversion
+ * type.
+ * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected
+ * conversion type.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc,
+ uint32_t ConversionGroup) {
+ uint32_t tickstart;
+ uint32_t Conversion_Timeout_CPU_cycles = 0UL;
+ uint32_t conversion_group_reassigned = ConversionGroup;
+ uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+ /* Verification if ADC is not already stopped (on regular and injected */
+ /* groups) to bypass this function if not needed. */
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular != 0UL) ||
+ (tmp_adc_is_conversion_on_going_injected != 0UL)) {
+ /* Particular case of continuous auto-injection mode combined with */
+ /* auto-delay mode. */
+ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
+ /* injected group stop ADC_CR_JADSTP). */
+ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
+ /* (see reference manual). */
+ if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) &&
+ (hadc->Init.ContinuousConvMode == ENABLE) &&
+ (hadc->Init.LowPowerAutoWait == ENABLE)) {
+ /* Use stop of regular group */
+ conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+ /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) {
+ if (Conversion_Timeout_CPU_cycles >=
+ (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ Conversion_Timeout_CPU_cycles++;
+ }
+
+ /* Clear JEOS */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+ }
+
+ /* Stop potential conversion on going on ADC group regular */
+ if (conversion_group_reassigned != ADC_INJECTED_GROUP) {
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Stop potential conversion on going on ADC group injected */
+ if (conversion_group_reassigned != ADC_REGULAR_GROUP) {
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) {
+ /* Stop ADC group injected conversion */
+ LL_ADC_INJ_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Selection of start and stop bits with respect to the regular or injected
+ * group */
+ switch (conversion_group_reassigned) {
+ case ADC_REGULAR_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+ break;
+ case ADC_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+ break;
+ /* Case ADC_REGULAR_GROUP only*/
+ default:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+ break;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) {
+ uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if ((hadc->Instance->CR &
+ (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |
+ ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ LL_ADC_Enable(hadc->Instance);
+
+ if ((LL_ADC_GetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance)) &
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) {
+ /* Delay for temperature sensor buffer stabilization time */
+ /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */
+ /* LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed */
+ /* in case of ADC enable after a system wake up */
+ /* from low power mode. */
+
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) *
+ ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL) {
+ wait_loop_index--;
+ }
+ }
+
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) {
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ LL_ADC_Enable(hadc->Instance);
+ }
+
+ if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) {
+ uint32_t tickstart;
+ const uint32_t tmp_adc_is_disable_on_going =
+ LL_ADC_IsDisableOngoing(hadc->Instance);
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) &&
+ (tmp_adc_is_disable_on_going == 0UL)) {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if ((hadc->Instance->CR &
+ (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) {
+ /* Disable the ADC peripheral */
+ LL_ADC_Disable(hadc->Instance);
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ } else {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) {
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc =
+ (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State &
+ (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ /* Is it the end of the regular sequence ? */
+ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) {
+ /* Are conversions software-triggered ? */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) {
+ /* Is CONT bit set ? */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) {
+ /* CONT bit is not set, no more conversions expected */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ } else {
+ /* DMA End of Transfer interrupt was triggered but conversions sequence
+ is not over. If DMACFG is set to 0, conversions are stopped. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) {
+ /* DMACFG bit is not set, conversions are stopped. */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ } else /* DMA and-or internal error occurred */
+ {
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ } else {
+ /* Call ADC DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) {
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc =
+ (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAError(DMA_HandleTypeDef *hdma) {
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc =
+ (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
index 46c6ee4..0695d0a 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
@@ -1,2265 +1,2264 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_adc_ex.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Converter (ADC)
- * peripheral:
- * + Peripheral Control functions
- * Other functions (generic functions) are available in file
- * "stm32g4xx_hal_adc.c".
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- [..]
- (@) Sections "ADC peripheral features" and "How to use this driver" are
- available in file of generic functions "stm32g4xx_hal_adc.c".
- [..]
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADCEx ADCEx
- * @brief ADC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
- * @{
- */
-
-#define ADC_JSQR_FIELDS \
- ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ1 | \
- ADC_JSQR_JSQ2 | ADC_JSQR_JSQ3 | \
- ADC_JSQR_JSQ4)) /*!< ADC_JSQR fields of parameters that can be updated \
- anytime once the ADC is enabled */
-
-/* Fixed timeout value for ADC calibration. */
-/* Values defined to be higher than worst cases: low clock frequency, */
-/* maximum prescalers. */
-/* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value */
-/* considering both possible ADC clocking scheme: */
-/* - ADC clock from synchronous clock with AHB prescaler 512, */
-/* ADC prescaler 4. */
-/* Ratio max = 512 *4 = 2048 */
-/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
-/* Highest CPU clock PLL (PLLR). */
-/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
-/* = 3968 ) */
-/* Calibration_time MAX = 81 / f_ADC */
-/* = 81 / (f_CPU/3938) = 318978 CPU cycles */
-#define ADC_CALIBRATION_TIMEOUT \
- (318978UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
- * @{
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output
-operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
- (+) Perform the ADC self-calibration for single or differential ending.
- (+) Get calibration factors for single or differential ending.
- (+) Set calibration factors for single or differential ending.
-
- (+) Start conversion of ADC group injected.
- (+) Stop conversion of ADC group injected.
- (+) Poll for conversion complete on ADC group injected.
- (+) Get result of ADC group injected channel conversion.
- (+) Start conversion of ADC group injected and enable interruptions.
- (+) Stop conversion of ADC group injected and disable interruptions.
-
- (+) When multimode feature is available, start multimode and enable DMA
-transfer.
- (+) Stop multimode and disable ADC DMA transfer.
- (+) Get result of multimode conversion.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform an ADC automatic self-calibration
- * Calibration prerequisite: ADC must be disabled (execute this
- * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
- * @param hadc ADC handle
- * @param SingleDiff Selection of single-ended or differential input
- * This parameter can be one of the following values:
- * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential
- * ended
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc,
- uint32_t SingleDiff) {
- HAL_StatusTypeDef tmp_hal_status;
- __IO uint32_t wait_loop_index = 0UL;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Calibration prerequisite: ADC must be disabled. */
-
- /* Disable the ADC (if not already disabled) */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Start ADC calibration in mode single-ended or differential */
- LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
-
- /* Wait for calibration completion */
- while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) {
- wait_loop_index++;
- if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- } else {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Note: No need to update variable "tmp_hal_status" here: already set */
- /* to state "HAL_ERROR" by function disabling the ADC. */
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Get the calibration factor.
- * @param hadc ADC handle.
- * @param SingleDiff This parameter can be only:
- * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential
- * ended
- * @retval Calibration value.
- */
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc,
- uint32_t SingleDiff) {
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
- /* Return the selected ADC calibration value */
- return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
-}
-
-/**
- * @brief Set the calibration factor to overwrite automatic conversion result.
- * ADC must be enabled and no conversion is ongoing.
- * @param hadc ADC handle
- * @param SingleDiff This parameter can be only:
- * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential
- * ended
- * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc,
- uint32_t SingleDiff,
- uint32_t CalibrationFactor) {
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
- assert_param(IS_ADC_CALFACT(CalibrationFactor));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Verification of hardware constraints before modifying the calibration */
- /* factors register: ADC must be enabled, no conversion on going. */
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
-
- if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) &&
- (tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- /* Set the selected ADC calibration value */
- LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
- } else {
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- /* Update ADC error code */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- /* Update ADC state machine to error */
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Enable ADC, start conversion of injected group.
- * @note Interruptions enabled in this function: None.
- * @note Case of multimode enabled when multimode feature is available:
- * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
- * then for ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
- uint32_t tmp_config_injected_queue;
-#if defined(ADC_MULTIMODE_SUPPORT)
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) {
- return HAL_BUSY;
- } else {
- /* In case of software trigger detection enabled, JQDIS must be set
- (which can be done only if ADSTART and JADSTART are both cleared).
- If JQDIS is not set at that point, returns an error
- - since software trigger detection is disabled. User needs to
- resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
- - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
- the queue is empty */
- tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-
- if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) &&
- (tmp_config_injected_queue == 0UL)) {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK) {
- /* Check if a regular conversion is ongoing */
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) {
- /* Reset ADC error code field related to injected conversions only */
- CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
- } else {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - if ADC instance is master or if multimode feature is not available
- - if multimode setting is disabled (ADC instance slave in independent
- mode) */
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#endif
-
- /* Clear ADC group injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations)
- */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Enable conversion of injected group, if automatic injected conversion
- */
- /* is disabled. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (when multimode feature is available): */
- /* if ADC is slave, */
- /* - ADC is enabled only (conversion is not started), */
- /* - if multimode only concerns regular conversion, ADC is enabled */
- /* and conversion is started. */
- /* If ADC is master or independent, */
- /* - ADC is enabled and conversion is started. */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
- /* ADC instance is not a multimode slave instance with multimode
- * injected conversions enabled */
- if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
- LL_ADC_INJ_TRIG_INDEPENDENT) {
- LL_ADC_INJ_StartConversion(hadc->Instance);
- }
- } else {
- /* ADC instance is not a multimode slave instance with multimode
- * injected conversions enabled */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#else
- if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
- LL_ADC_INJ_TRIG_INDEPENDENT) {
- /* Start ADC group injected conversion */
- LL_ADC_INJ_StartConversion(hadc->Instance);
- }
-#endif
-
- } else {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
- }
-}
-
-/**
- * @brief Stop conversion of injected channels. Disable ADC peripheral if
- * no regular conversion is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note In case of multimode enabled (when multimode feature is available),
- * HAL_ADCEx_InjectedStop() must be called for ADC master first, then
- * for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For
- * ADC slave, ADC is disabled only (conversion stop of ADC master has already
- * stopped conversion of ADC slave).
- * @param hadc ADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going on injected group only. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-
- /* Disable ADC peripheral if injected conversions are effectively stopped */
- /* and if no conversion on regular group is on-going */
- if (tmp_hal_status == HAL_OK) {
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on injected group is stopped, but ADC not disabled since */
- /* conversion on regular group is still running. */
- else {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Wait for injected group conversion to be completed.
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
- * checked and cleared depending on AUTDLY bit status.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc,
- uint32_t Timeout) {
- uint32_t tickstart;
- uint32_t tmp_Flag_End;
- uint32_t tmp_adc_inj_is_trigger_source_sw_start;
- uint32_t tmp_adc_reg_is_trigger_source_sw_start;
- uint32_t tmp_cfgr;
-#if defined(ADC_MULTIMODE_SUPPORT)
- const ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* If end of sequence selected */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) {
- tmp_Flag_End = ADC_FLAG_JEOS;
- } else /* end of conversion selected */
- {
- tmp_Flag_End = ADC_FLAG_JEOC;
- }
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait until End of Conversion or Sequence flag is raised */
- while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) {
- /* Check if timeout is disabled (set to infinite wait) */
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) {
- /* New check to avoid false timeout detection in case of preemption */
- if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Retrieve ADC configuration */
- tmp_adc_inj_is_trigger_source_sw_start =
- LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
- tmp_adc_reg_is_trigger_source_sw_start =
- LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- } else {
- tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-#else
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
-#endif
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-
- /* Determine whether any further conversion upcoming on group injected */
- /* by external trigger or by automatic injected conversion */
- /* from group regular. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) {
- /* Check whether end of sequence is reached */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) {
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
- }
-
- /* Clear polled flag */
- if (tmp_Flag_End == ADC_FLAG_JEOS) {
- /* Clear end of sequence JEOS flag of injected group if low power feature */
- /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
- /* For injected groups, no new conversion will start before JEOS is */
- /* cleared. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) {
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
- }
- } else {
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
- }
-
- /* Return API HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable ADC, start conversion of injected group with interruption.
- * @note Interruptions enabled in this function according to initialization
- * setting : JEOC (end of conversion) or JEOS (end of sequence)
- * @note Case of multimode enabled (when multimode feature is enabled):
- * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
- * then for ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
- uint32_t tmp_config_injected_queue;
-#if defined(ADC_MULTIMODE_SUPPORT)
- uint32_t tmp_multimode_config =
- LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
-#endif
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) {
- return HAL_BUSY;
- } else {
- /* In case of software trigger detection enabled, JQDIS must be set
- (which can be done only if ADSTART and JADSTART are both cleared).
- If JQDIS is not set at that point, returns an error
- - since software trigger detection is disabled. User needs to
- resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
- - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
- the queue is empty */
- tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-
- if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) &&
- (tmp_config_injected_queue == 0UL)) {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK) {
- /* Check if a regular conversion is ongoing */
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) {
- /* Reset ADC error code field related to injected conversions only */
- CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
- } else {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - if ADC instance is master or if multimode feature is not available
- - if multimode setting is disabled (ADC instance slave in independent
- mode) */
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#endif
-
- /* Clear ADC group injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations)
- */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Enable ADC Injected context queue overflow interrupt if this feature */
- /* is enabled. */
- if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) {
- __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
- }
-
- /* Enable ADC end of conversion interrupt */
- switch (hadc->Init.EOCSelection) {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
-
- /* Enable conversion of injected group, if automatic injected conversion
- */
- /* is disabled. */
- /* If software start has been selected, conversion starts immediately.
- */
- /* If external trigger has been selected, conversion will start at next
- */
- /* trigger event. */
- /* Case of multimode enabled (when multimode feature is available): */
- /* if ADC is slave, */
- /* - ADC is enabled only (conversion is not started), */
- /* - if multimode only concerns regular conversion, ADC is enabled */
- /* and conversion is started. */
- /* If ADC is master or independent, */
- /* - ADC is enabled and conversion is started. */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
- (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
- (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
- /* ADC instance is not a multimode slave instance with multimode
- * injected conversions enabled */
- if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
- LL_ADC_INJ_TRIG_INDEPENDENT) {
- LL_ADC_INJ_StartConversion(hadc->Instance);
- }
- } else {
- /* ADC instance is not a multimode slave instance with multimode
- * injected conversions enabled */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-#else
- if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
- LL_ADC_INJ_TRIG_INDEPENDENT) {
- /* Start ADC group injected conversion */
- LL_ADC_INJ_StartConversion(hadc->Instance);
- }
-#endif
-
- } else {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
- }
-}
-
-/**
- * @brief Stop conversion of injected channels, disable interruption of
- * end-of-conversion. Disable ADC peripheral if no regular conversion
- * is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note Case of multimode enabled (when multimode feature is available):
- * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
- * then for ADC slave.
- * For ADC master, conversion is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going on injected group only. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-
- /* Disable ADC peripheral if injected conversions are effectively stopped */
- /* and if no conversion on the other group (regular group) is intended to */
- /* continue. */
- if (tmp_hal_status == HAL_OK) {
- /* Disable ADC end of conversion interrupt for injected channels */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
-
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on injected group is stopped, but ADC not disabled since */
- /* conversion on regular group is still running. */
- else {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Enable ADC, start MultiMode conversion and transfer regular results
- * through DMA.
- * @note Multimode must have been previously configured using
- * HAL_ADCEx_MultiModeConfigChannel() function.
- * Interruptions enabled in this function:
- * overrun, DMA half transfer, DMA transfer complete.
- * Each of these interruptions has its dedicated callback function.
- * @note State field of Slave ADC handle is not updated in this configuration:
- * user should not rely on it for information related to Slave regular
- * conversions.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @param pData Destination Buffer address.
- * @param Length Length of data to be transferred from ADC peripheral to memory
- * (in bytes).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc,
- uint32_t *pData,
- uint32_t Length) {
- HAL_StatusTypeDef tmp_hal_status;
- ADC_HandleTypeDef tmphadcSlave;
- ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-
- if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) {
- return HAL_BUSY;
- } else {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Temporary handle minimum initialization */
- __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
- ADC_CLEAR_ERRORCODE(&tmphadcSlave);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL) {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Enable the ADC peripherals: master and slave (in case if not already */
- /* enabled previously) */
- tmp_hal_status = ADC_Enable(hadc);
- if (tmp_hal_status == HAL_OK) {
- tmp_hal_status = ADC_Enable(&tmphadcSlave);
- }
-
- /* Start multimode conversion of ADCs pair */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
- HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
- /* Pointer to the common control register */
- tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations)
- */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Start the DMA channel */
- tmp_hal_status =
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR,
- (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Start ADC group regular conversion */
- LL_ADC_REG_StartConversion(hadc->Instance);
- } else {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
- }
-}
-
-/**
- * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC
- * peripheral.
- * @note Multimode is kept enabled after this function. MultiMode DMA bits
- * (MDMA and DMACFG bits of common CCR register) are maintained. To
- * disable Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user
- * can resort to HAL_ADCEx_DisableMultiMode() API.
- * @note In case of DMA configured in circular mode, function
- * HAL_ADC_Stop_DMA() must be called after this function with handle of
- * ADC slave, to properly disable the DMA channel.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
- uint32_t tickstart;
- ADC_HandleTypeDef tmphadcSlave;
- uint32_t tmphadcSlave_conversion_on_going;
- HAL_StatusTypeDef tmphadcSlave_disable_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential multimode conversion on going, on regular and injected
- * groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK) {
- /* Temporary handle minimum initialization */
- __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
- ADC_CLEAR_ERRORCODE(&tmphadcSlave);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped (ADC master and ADC slave), then disable ADC */
-
- /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
- tickstart = HAL_GetTick();
-
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
- (tmphadcSlave_conversion_on_going == 1UL)) {
- if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption */
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
- (tmphadcSlave_conversion_on_going == 1UL)) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- }
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop */
- /* while DMA transfer is on going) */
- /* Note: DMA channel of ADC slave should be stopped after this function */
- /* with HAL_ADC_Stop_DMA() API. */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status == HAL_ERROR) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripherals: master and slave */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in
- */
- /* memory a potential failing status. */
- if (tmp_hal_status == HAL_OK) {
- tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
- if ((ADC_Disable(hadc) == HAL_OK) &&
- (tmphadcSlave_disable_status == HAL_OK)) {
- tmp_hal_status = HAL_OK;
- }
- } else {
- /* In case of error, attempt to disable ADC master and slave without
- * status assert */
- (void)ADC_Disable(hadc);
- (void)ADC_Disable(&tmphadcSlave);
- }
-
- /* Set ADC state (ADC master) */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Return the last ADC Master and Slave regular conversions results when
- * in multimode configuration.
- * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
- * @retval The converted data values.
- */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) {
- const ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Prevent unused argument(s) compilation warning if no assert_param check */
- /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
- UNUSED(hadc);
-
- /* Pointer to the common control register */
- tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
-
- /* Return the multi mode conversion value */
- return tmpADC_Common->CDR;
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @brief Get ADC injected group conversion result.
- * @note Reading register JDRx automatically clears ADC flag JEOC
- * (ADC group injected end of unitary conversion).
- * @note This function does not clear ADC flag JEOS
- * (ADC group injected end of sequence conversion)
- * Occurrence of flag JEOS rising:
- * - If sequencer is composed of 1 rank, flag JEOS is equivalent
- * to flag JEOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag JEOC only is raised, at the end of the scan sequence
- * both flags JEOC and EOS are raised.
- * Flag JEOS must not be cleared by this function because
- * it would not be compliant with low power features
- * (feature low power auto-wait, not available on all STM32 families).
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc ADC handle
- * @param InjectedRank the converted ADC injected rank.
- * This parameter can be one of the following values:
- * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
- * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
- * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
- * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
- * @retval ADC group injected conversion data
- */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc,
- uint32_t InjectedRank) {
- uint32_t tmp_jdr;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-
- /* Get ADC converted value */
- switch (InjectedRank) {
- case ADC_INJECTED_RANK_4:
- tmp_jdr = hadc->Instance->JDR4;
- break;
- case ADC_INJECTED_RANK_3:
- tmp_jdr = hadc->Instance->JDR3;
- break;
- case ADC_INJECTED_RANK_2:
- tmp_jdr = hadc->Instance->JDR2;
- break;
- case ADC_INJECTED_RANK_1:
- default:
- tmp_jdr = hadc->Instance->JDR1;
- break;
- }
-
- /* Return ADC converted value */
- return tmp_jdr;
-}
-
-/**
- * @brief Injected conversion complete callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_InjectedConvCpltCallback must be implemented in
- the user file.
- */
-}
-
-/**
- * @brief Injected context queue overflow callback.
- * @note This callback is called if injected context queue is enabled
- (parameter "QueueInjectedContext" in injected channel configuration)
- and if a new injected context is set when queue is full (maximum 2
- contexts).
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
- in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 2 callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in
- the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 3 callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in
- the user file.
- */
-}
-
-/**
- * @brief End Of Sampling callback in non-blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_EndOfSamplingCallback must be implemented in the
- user file.
- */
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC peripheral if no
- * conversion is on going on injected group.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if regular conversions are effectively stopped
- and if no injected conversions are on-going */
- if (tmp_hal_status == HAL_OK) {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on injected group is stopped, but ADC not disabled since */
- /* conversion on regular group is still running. */
- else {
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of ADC groups regular and injected,
- * disable interrution of end-of-conversion,
- * disable ADC peripheral if no conversion is on going
- * on injected group.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped
- and if no injected conversion is on-going */
- if (tmp_hal_status == HAL_OK) {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- /* Disable all regular-related interrupts */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* 2. Disable ADC peripheral if no injected conversions are on-going */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
- tmp_hal_status = ADC_Disable(hadc);
- /* if no issue reported */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- } else {
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral if no conversion is on going
- * on injected group.
- * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode
- * only. For multimode (when multimode feature is available),
- * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped
- and if no injected conversion is on-going */
- if (tmp_hal_status == HAL_OK) {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripheral */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, */
- /* to keep in memory a potential failing status. */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
- if (tmp_hal_status == HAL_OK) {
- tmp_hal_status = ADC_Disable(hadc);
- } else {
- (void)ADC_Disable(hadc);
- }
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK) {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- } else {
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer,
- * disable ADC peripheral if no injected conversion is on-going.
- * @note Multimode is kept enabled after this function. Multimode DMA bits
- * (MDMA and DMACFG bits of common CCR register) are maintained. To
- * disable multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user
- * can resort to HAL_ADCEx_DisableMultiMode() API.
- * @note In case of DMA configured in circular mode, function
- * HAL_ADCEx_RegularStop_DMA() must be called after this function with
- * handle of ADC slave, to properly disable the DMA channel.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
- uint32_t tickstart;
- ADC_HandleTypeDef tmphadcSlave;
- uint32_t tmphadcSlave_conversion_on_going;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential multimode conversion on going, on regular groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK) {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- /* Temporary handle minimum initialization */
- __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
- ADC_CLEAR_ERRORCODE(&tmphadcSlave);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped (ADC master and ADC slave), then disable ADC */
-
- /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
- tickstart = HAL_GetTick();
-
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
- (tmphadcSlave_conversion_on_going == 1UL)) {
- if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption */
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
- (tmphadcSlave_conversion_on_going == 1UL)) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- }
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop */
- /* while DMA transfer is on going) */
- /* Note: DMA channel of ADC slave should be stopped after this function */
- /* with HAL_ADCEx_RegularStop_DMA() API. */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripherals: master and slave if no injected */
- /* conversion is on-going. */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in
- */
- /* memory a potential failing status. */
- if (tmp_hal_status == HAL_OK) {
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
- tmp_hal_status = ADC_Disable(hadc);
- if (tmp_hal_status == HAL_OK) {
- if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) ==
- 0UL) {
- tmp_hal_status = ADC_Disable(&tmphadcSlave);
- }
- }
- }
-
- if (tmp_hal_status == HAL_OK) {
- /* Both Master and Slave ADC's could be disabled. Update Master State */
- /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- } else {
- /* injected (Master or Slave) conversions are still on-going,
- no Master State change */
- }
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control
-functions
- * @brief ADC Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on injected group
- (+) Configure multimode when multimode feature is available
- (+) Enable or Disable Injected Queue
- (+) Disable ADC voltage regulator
- (+) Enter ADC deep-power-down mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure a channel to be assigned to ADC group injected.
- * @note Possibility to update parameters on the fly:
- * This function initializes injected group, following calls to this
- * function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
- * The setting of these parameters is conditioned to ADC state:
- * Refer to comments of structure "ADC_InjectionConfTypeDef".
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be disabled using function
- * HAL_ADC_DeInit().
- * @note Caution: For Injected Context Queue use, a context must be fully
- * defined before start of injected conversion. All channels are
- * configured consecutively for the same ADC instance. Therefore, the number of
- * calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of
- * parameter InjectedNbrOfConversion for each context.
- * - Example 1: If 1 context is intended to be used (or if there is no use of
- * the Injected Queue Context feature) and if the context contains 3 injected
- * ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must
- * be called once for each channel (i.e. 3 times) before starting a conversion.
- * This function must not be called to configure a 4th injected channel:
- * it would start a new context into context queue.
- * - Example 2: If 2 contexts are intended to be used and each of them contains
- * 3 injected ranks (InjectedNbrOfConversion = 3),
- * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
- * for each context (3 channels x 2 contexts = 6 calls). Conversion can
- * start once the 1st context is set, that is after the first three
- * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the
- * fly.
- * @param hadc ADC handle
- * @param sConfigInjected Structure of ADC injected group and ADC channel for
- * injected group.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(
- ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) {
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmpOffsetShifted;
- uint32_t tmp_config_internal_channel;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
- __IO uint32_t wait_loop_index = 0;
-
- uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
- assert_param(
- IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
- assert_param(
- IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
- assert_param(
- IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
- assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
-
- if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
- assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
- assert_param(
- IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
- assert_param(
- IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
- }
-
- /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
- ignored (considered as reset) */
- assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) &&
- (sConfigInjected->InjecOversamplingMode == ENABLE)));
-
- /* JDISCEN and JAUTO bits can't be set at the same time */
- assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) &&
- (sConfigInjected->AutoInjectedConv == ENABLE)));
-
- /* DISCEN and JAUTO bits can't be set at the same time */
- assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) &&
- (sConfigInjected->AutoInjectedConv == ENABLE)));
-
- /* Verification of channel number */
- if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) {
- assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
- } else {
- assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Configuration of injected group sequencer: */
- /* Hardware constraint: Must fully define injected context register JSQR */
- /* before make it entering into injected sequencer queue. */
- /* */
- /* - if scan mode is disabled: */
- /* * Injected channels sequence length is set to 0x00: 1 channel */
- /* converted (channel on injected rank 1) */
- /* Parameter "InjectedNbrOfConversion" is discarded. */
- /* * Injected context register JSQR setting is simple: register is fully */
- /* defined on one call of this function (for injected rank 1) and can */
- /* be entered into queue directly. */
- /* - if scan mode is enabled: */
- /* * Injected channels sequence length is set to parameter */
- /* "InjectedNbrOfConversion". */
- /* * Injected context register JSQR setting more complex: register is */
- /* fully defined over successive calls of this function, for each */
- /* injected channel rank. It is entered into queue only when all */
- /* injected ranks have been set. */
- /* Note: Scan mode is not present by hardware on this device, but used */
- /* by software for alignment over all STM32 devices. */
-
- if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
- (sConfigInjected->InjectedNbrOfConversion == 1U)) {
- /* Configuration of context register JSQR: */
- /* - number of ranks in injected group sequencer: fixed to 1st rank */
- /* (scan mode disabled, only rank 1 used) */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
- /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
-
- if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) {
- /* Enable external trigger if trigger selection is different of */
- /* software start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if (sConfigInjected->ExternalTrigInjecConv !=
- ADC_INJECTED_SOFTWARE_START) {
- tmp_JSQR_ContextQueueBeingBuilt =
- (ADC_JSQR_RK(sConfigInjected->InjectedChannel,
- ADC_INJECTED_RANK_1) |
- (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) |
- sConfigInjected->ExternalTrigInjecConvEdge);
- } else {
- tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(
- sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
- }
-
- MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS,
- tmp_JSQR_ContextQueueBeingBuilt);
- /* For debug and informative reasons, hadc handle saves JSQR setting */
- hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
- }
- } else {
- /* Case of scan mode enabled, several channels to set into injected group */
- /* sequencer. */
- /* */
- /* Procedure to define injected context register JSQR over successive */
- /* calls of this function, for each injected channel rank: */
- /* 1. Start new context and set parameters related to all injected */
- /* channels: injected sequence length and trigger. */
-
- /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
- /* call of the context under setting */
- if (hadc->InjectionConfig.ChannelCount == 0U) {
- /* Initialize number of channels that will be configured on the context */
- /* being built */
- hadc->InjectionConfig.ChannelCount =
- sConfigInjected->InjectedNbrOfConversion;
- /* Handle hadc saves the context under build up over each
- HAL_ADCEx_InjectedConfigChannel() call, this context will be written in
- JSQR register at the last call. At this point, the context is merely
- reset */
- hadc->InjectionConfig.ContextQueue = 0x00000000U;
-
- /* Configuration of context register JSQR: */
- /* - number of ranks in injected group sequencer */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
-
- /* Enable external trigger if trigger selection is different of */
- /* software start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if (sConfigInjected->ExternalTrigInjecConv !=
- ADC_INJECTED_SOFTWARE_START) {
- tmp_JSQR_ContextQueueBeingBuilt =
- ((sConfigInjected->InjectedNbrOfConversion - 1U) |
- (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) |
- sConfigInjected->ExternalTrigInjecConvEdge);
- } else {
- tmp_JSQR_ContextQueueBeingBuilt =
- ((sConfigInjected->InjectedNbrOfConversion - 1U));
- }
- }
-
- /* 2. Continue setting of context under definition with parameter */
- /* related to each channel: channel rank sequence */
- /* Clear the old JSQx bits for the selected rank */
- tmp_JSQR_ContextQueueBeingBuilt &=
- ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
-
- /* Set the JSQx bits for the selected rank */
- tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(
- sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
-
- /* Decrease channel count */
- hadc->InjectionConfig.ChannelCount--;
-
- /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this
- HAL_ADCEx_InjectedConfigChannel() call, aggregate the setting to those
- already built during the previous HAL_ADCEx_InjectedConfigChannel() calls
- (for the same context of course) */
- hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
-
- /* 4. End of context setting: if this is the last channel set, then write
- context into register JSQR and make it enter into queue */
- if (hadc->InjectionConfig.ChannelCount == 0U) {
- MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS,
- hadc->InjectionConfig.ContextQueue);
- }
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on injected group: */
- /* - Injected context queue: Queue disable (active context is kept) or */
- /* enable (context decremented, up to 2 contexts queued) */
- /* - Injected discontinuous mode: can be enabled only if auto-injected */
- /* mode is disabled. */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
- /* If auto-injected mode is disabled: no constraint */
- if (sConfigInjected->AutoInjectedConv == DISABLE) {
- MODIFY_REG(
- hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
- ADC_CFGR_INJECT_CONTEXT_QUEUE(
- (uint32_t)sConfigInjected->QueueInjectedContext) |
- ADC_CFGR_INJECT_DISCCONTINUOUS(
- (uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
- }
- /* If auto-injected mode is enabled: Injected discontinuous setting is */
- /* discarded. */
- else {
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
- ADC_CFGR_INJECT_CONTEXT_QUEUE(
- (uint32_t)sConfigInjected->QueueInjectedContext));
- }
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Automatic injected conversion: can be enabled if injected group */
- /* external triggers are disabled. */
- /* - Channel sampling time */
- /* - Channel offset */
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
-
- if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- /* If injected group external triggers are disabled (set to injected */
- /* software start): no constraint */
- if ((sConfigInjected->ExternalTrigInjecConv ==
- ADC_INJECTED_SOFTWARE_START) ||
- (sConfigInjected->ExternalTrigInjecConvEdge ==
- ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) {
- if (sConfigInjected->AutoInjectedConv == ENABLE) {
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
- } else {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
- }
- }
- /* If Automatic injected conversion was intended to be set and could not */
- /* due to injected group external triggers enabled, error is reported. */
- else {
- if (sConfigInjected->AutoInjectedConv == ENABLE) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- } else {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
- }
- }
-
- if (sConfigInjected->InjecOversamplingMode == ENABLE) {
- assert_param(
- IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
- assert_param(IS_ADC_RIGHT_BIT_SHIFT(
- sConfigInjected->InjecOversampling.RightBitShift));
-
- /* JOVSE must be reset in case of triggered regular mode */
- assert_param(!(
- READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
- (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
-
- /* Configuration of Injected Oversampler: */
- /* - Oversampling Ratio */
- /* - Right bit shift */
-
- /* Enable OverSampling mode */
- MODIFY_REG(hadc->Instance->CFGR2,
- ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS,
- ADC_CFGR2_JOVSE | sConfigInjected->InjecOversampling.Ratio |
- sConfigInjected->InjecOversampling.RightBitShift);
- } else {
- /* Disable Regular OverSampling */
- CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
- }
-
- /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
- if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) {
- /* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance,
- sConfigInjected->InjectedChannel,
- LL_ADC_SAMPLINGTIME_2CYCLES_5);
-
- /* Set ADC sampling time common configuration */
- LL_ADC_SetSamplingTimeCommonConfig(
- hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
- } else {
- /* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance,
- sConfigInjected->InjectedChannel,
- sConfigInjected->InjectedSamplingTime);
-
- /* Set ADC sampling time common configuration */
- LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance,
- LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
- }
-
- /* Configure the offset: offset enable/disable, channel, offset value */
-
- /* Shift the offset with respect to the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to
- * 0 */
- tmpOffsetShifted =
- ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
-
- if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) {
- /* Set ADC selected offset number */
- LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber,
- sConfigInjected->InjectedChannel, tmpOffsetShifted);
-
- /* Set ADC selected offset sign & saturation */
- LL_ADC_SetOffsetSign(hadc->Instance,
- sConfigInjected->InjectedOffsetNumber,
- sConfigInjected->InjectedOffsetSign);
- LL_ADC_SetOffsetSaturation(
- hadc->Instance, sConfigInjected->InjectedOffsetNumber,
- (sConfigInjected->InjectedOffsetSaturation == ENABLE)
- ? LL_ADC_OFFSET_SATURATION_ENABLE
- : LL_ADC_OFFSET_SATURATION_DISABLE);
- } else {
- /* Scan each offset register to check if the selected channel is targeted.
- */
- /* If this is the case, the corresponding offset number is disabled. */
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1,
- LL_ADC_OFFSET_DISABLE);
- }
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2,
- LL_ADC_OFFSET_DISABLE);
- }
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3,
- LL_ADC_OFFSET_DISABLE);
- }
- if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
- __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) {
- LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4,
- LL_ADC_OFFSET_DISABLE);
- }
- }
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Single or differential mode */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- /* Set mode single-ended or differential input of the selected ADC channel
- */
- LL_ADC_SetChannelSingleDiff(hadc->Instance,
- sConfigInjected->InjectedChannel,
- sConfigInjected->InjectedSingleDiff);
-
- /* Configuration of differential mode */
- /* Note: ADC channel number masked with value "0x1F" to ensure shift value
- * within 32 bits range */
- if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) {
- /* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(
- hadc->Instance,
- (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
- (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
- (uint32_t)sConfigInjected->InjectedChannel) +
- 1UL) &
- 0x1FUL)),
- sConfigInjected->InjectedSamplingTime);
- }
- }
-
- /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
- /* internal measurement paths enable: If internal channel selected, */
- /* enable dedicated internal buffers and path. */
- /* Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_DeInit(). */
-
- if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) {
- tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance));
-
- /* If the requested internal measurement path has already been enabled, */
- /* bypass the configuration processing. */
- if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) ||
- (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) &&
- ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) ==
- 0UL)) {
- if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) {
- LL_ADC_SetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance),
- LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
-
- /* Delay for temperature sensor stabilization time */
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles, scaling in us split to not */
- /* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index =
- ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) *
- (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
- while (wait_loop_index != 0UL) {
- wait_loop_index--;
- }
- }
- } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
- ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) ==
- 0UL)) {
- if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) {
- LL_ADC_SetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance),
- LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
- }
- } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
- ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) ==
- 0UL)) {
- if (ADC_VREFINT_INSTANCE(hadc)) {
- LL_ADC_SetCommonPathInternalCh(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance),
- LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
- }
- } else {
- /* nothing to do */
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Enable ADC multimode and configure multimode parameters
- * @note Possibility to update parameters on the fly:
- * This function initializes multimode parameters, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
- * the ADCs.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_MultiModeTypeDef".
- * @note To move back configuration from multimode to single mode, ADC must
- * be reset (using function HAL_ADC_Init() ).
- * @param hadc Master ADC handle
- * @param multimode Structure of ADC multimode configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(
- ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) {
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSlave;
- uint32_t tmphadcSlave_conversion_on_going;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_MULTIMODE(multimode->Mode));
- if (multimode->Mode != ADC_MODE_INDEPENDENT) {
- assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
- assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Temporary handle minimum initialization */
- __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
- ADC_CLEAR_ERRORCODE(&tmphadcSlave);
-
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL) {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Multimode DMA configuration */
- /* - Multimode DMA mode */
- tmphadcSlave_conversion_on_going =
- LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) &&
- (tmphadcSlave_conversion_on_going == 0UL)) {
- /* Pointer to the common control register */
- tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
-
- /* If multimode is selected, configure all multimode parameters. */
- /* Otherwise, reset multimode parameters (can be used in case of */
- /* transition from multimode to independent mode). */
- if (multimode->Mode != ADC_MODE_INDEPENDENT) {
- MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
- multimode->DMAAccessMode |
- ADC_CCR_MULTI_DMACONTREQ(
- (uint32_t)hadc->Init.DMAContinuousRequests));
-
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* - Multimode delay */
- /* Note: Delay range depends on selected resolution: */
- /* from 1 to 12 clock cycles for 12 bits */
- /* from 1 to 10 clock cycles for 10 bits, */
- /* from 1 to 8 clock cycles for 8 bits */
- /* from 1 to 6 clock cycles for 6 bits */
- /* If a higher delay is selected, it will be clipped to maximum delay
- */
- /* range */
- if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
- MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
- multimode->Mode | multimode->TwoSamplingDelay);
- }
- } else /* ADC_MODE_INDEPENDENT */
- {
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
-
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* - Multimode delay */
- if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
- __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
- }
- }
- }
- /* If one of the ADC sharing the same common group is enabled, no update */
- /* could be done on neither of the multimode structure parameters. */
- else {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @brief Enable Injected Queue
- * @note This function resets CFGR register JQDIS bit in order to enable the
- * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
- * are both equal to 0 to ensure that no regular nor injected
- * conversion is ongoing.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
-
- /* Parameter can be set only if no conversion is on-going */
- if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-
- /* Update state, clear previous result related to injected queue overflow */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- tmp_hal_status = HAL_OK;
- } else {
- tmp_hal_status = HAL_ERROR;
- }
-
- return tmp_hal_status;
-}
-
-/**
- * @brief Disable Injected Queue
- * @note This function sets CFGR register JQDIS bit in order to disable the
- * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
- * are both equal to 0 to ensure that no regular nor injected
- * conversion is ongoing.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
- uint32_t tmp_adc_is_conversion_on_going_regular;
- uint32_t tmp_adc_is_conversion_on_going_injected;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- tmp_adc_is_conversion_on_going_regular =
- LL_ADC_REG_IsConversionOngoing(hadc->Instance);
- tmp_adc_is_conversion_on_going_injected =
- LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
-
- /* Parameter can be set only if no conversion is on-going */
- if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
- (tmp_adc_is_conversion_on_going_injected == 0UL)) {
- LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
- tmp_hal_status = HAL_OK;
- } else {
- tmp_hal_status = HAL_ERROR;
- }
-
- return tmp_hal_status;
-}
-
-/**
- * @brief Disable ADC voltage regulator.
- * @note Disabling voltage regulator allows to save power. This operation can
- * be carried out only when ADC is disabled.
- * @note To enable again the voltage regulator, the user is expected to
- * resort to HAL_ADC_Init() API.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Setting of this feature is conditioned to ADC state: ADC must be ADC
- * disabled */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- LL_ADC_DisableInternalRegulator(hadc->Instance);
- tmp_hal_status = HAL_OK;
- } else {
- tmp_hal_status = HAL_ERROR;
- }
-
- return tmp_hal_status;
-}
-
-/**
- * @brief Enter ADC deep-power-down mode
- * @note This mode is achieved in setting DEEPPWD bit and allows to save power
- * in reducing leakage currents. It is particularly interesting before
- * entering stop modes.
- * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
- * ADC voltage regulator. This means that this API encompasses
- * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
- * calibration is lost.
- * @note To exit the ADC deep-power-down mode, the user is expected to
- * resort to HAL_ADC_Init() API as well as to relaunch a calibration
- * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
- * saved calibration factor.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) {
- HAL_StatusTypeDef tmp_hal_status;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Setting of this feature is conditioned to ADC state: ADC must be ADC
- * disabled */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
- LL_ADC_EnableDeepPowerDown(hadc->Instance);
- tmp_hal_status = HAL_OK;
- } else {
- tmp_hal_status = HAL_ERROR;
- }
-
- return tmp_hal_status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Peripheral Control functions
+ * Other functions (generic functions) are available in file
+ * "stm32g4xx_hal_adc.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32g4xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+ * @{
+ */
+
+#define ADC_JSQR_FIELDS \
+ ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ1 | \
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4)) /*!< ADC_JSQR fields of \
+ parameters that can be updated anytime once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+/* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value */
+/* considering both possible ADC clocking scheme: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* ADC prescaler 4. */
+/* Ratio max = 512 *4 = 2048 */
+/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
+/* Highest CPU clock PLL (PLLR). */
+/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
+/* = 3968 ) */
+/* Calibration_time MAX = 81 / f_ADC */
+/* = 81 / (f_CPU/3938) = 318978 CPU cycles */
+#define ADC_CALIBRATION_TIMEOUT \
+ (318978UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output
+operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Perform the ADC self-calibration for single or differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+ (+) Start conversion of ADC group injected.
+ (+) Stop conversion of ADC group injected.
+ (+) Poll for conversion complete on ADC group injected.
+ (+) Get result of ADC group injected channel conversion.
+ (+) Start conversion of ADC group injected and enable interruptions.
+ (+) Stop conversion of ADC group injected and disable interruptions.
+
+ (+) When multimode feature is available, start multimode and enable DMA
+transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential
+ * ended
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc,
+ uint32_t SingleDiff) {
+ HAL_StatusTypeDef tmp_hal_status;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Start ADC calibration in mode single-ended or differential */
+ LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+
+ /* Wait for calibration completion */
+ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) {
+ wait_loop_index++;
+ if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ } else {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Note: No need to update variable "tmp_hal_status" here: already set */
+ /* to state "HAL_ERROR" by function disabling the ADC. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get the calibration factor.
+ * @param hadc ADC handle.
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential
+ * ended
+ * @retval Calibration value.
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc,
+ uint32_t SingleDiff) {
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Return the selected ADC calibration value */
+ return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+}
+
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result.
+ * ADC must be enabled and no conversion is ongoing.
+ * @param hadc ADC handle
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential
+ * ended
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc,
+ uint32_t SingleDiff,
+ uint32_t CalibrationFactor) {
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) &&
+ (tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ /* Set the selected ADC calibration value */
+ LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+ } else {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ /* Update ADC error code */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Update ADC state machine to error */
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled when multimode feature is available:
+ * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) {
+ return HAL_BUSY;
+ } else {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) &&
+ (tmp_config_injected_queue == 0UL)) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) {
+ /* Reset ADC error code field related to injected conversions only */
+ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ } else {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent
+ mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations)
+ */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of injected group, if automatic injected conversion
+ */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
+ /* ADC instance is not a multimode slave instance with multimode
+ * injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
+ LL_ADC_INJ_TRIG_INDEPENDENT) {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ } else {
+ /* ADC instance is not a multimode slave instance with multimode
+ * injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
+ LL_ADC_INJ_TRIG_INDEPENDENT) {
+ /* Start ADC group injected conversion */
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ } else {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of multimode enabled (when multimode feature is available),
+ * HAL_ADCEx_InjectedStop() must be called for ADC master first, then
+ * for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For
+ * ADC slave, ADC is disabled only (conversion stop of ADC master has already
+ * stopped conversion of ADC slave).
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on regular group is on-going */
+ if (tmp_hal_status == HAL_OK) {
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+ * checked and cleared depending on AUTDLY bit status.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc,
+ uint32_t Timeout) {
+ uint32_t tickstart;
+ uint32_t tmp_flag_end;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of sequence selected */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) {
+ tmp_flag_end = ADC_FLAG_JEOS;
+ } else /* end of conversion selected */
+ {
+ tmp_flag_end = ADC_FLAG_JEOC;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion or Sequence flag is raised */
+ while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start =
+ LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start =
+ LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ } else {
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
+ ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) {
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+
+ /* Clear polled flag */
+ if (tmp_flag_end == ADC_FLAG_JEOS) {
+ /* Clear end of sequence JEOS flag of injected group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
+ /* For injected groups, no new conversion will start before JEOS is */
+ /* cleared. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ }
+ } else {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ }
+
+ /* Return API HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : JEOC (end of conversion) or JEOS (end of sequence)
+ * @note Case of multimode enabled (when multimode feature is enabled):
+ * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config =
+ LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) {
+ return HAL_BUSY;
+ } else {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) &&
+ (tmp_config_injected_queue == 0UL)) {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) {
+ /* Reset ADC error code field related to injected conversions only */
+ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ } else {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent
+ mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)) {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations)
+ */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC Injected context queue overflow interrupt if this feature */
+ /* is enabled. */
+ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+ }
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection) {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+
+ /* Enable conversion of injected group, if automatic injected conversion
+ */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately.
+ */
+ /* If external trigger has been selected, conversion will start at next
+ */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) ||
+ (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) ||
+ (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)) {
+ /* ADC instance is not a multimode slave instance with multimode
+ * injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
+ LL_ADC_INJ_TRIG_INDEPENDENT) {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ } else {
+ /* ADC instance is not a multimode slave instance with multimode
+ * injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) ==
+ LL_ADC_INJ_TRIG_INDEPENDENT) {
+ /* Start ADC group injected conversion */
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ } else {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+ * then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on the other group (regular group) is intended to */
+ /* continue. */
+ if (tmp_hal_status == HAL_OK) {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC, start MultiMode conversion and transfer regular results
+ * through DMA.
+ * @note Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * overrun, DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note State field of Slave ADC handle is not updated in this configuration:
+ * user should not rely on it for information related to Slave regular
+ * conversions.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData Destination Buffer address.
+ * @param Length Length of data to be transferred from ADC peripheral to memory
+ * (in bytes).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc,
+ uint32_t *pData,
+ uint32_t Length) {
+ HAL_StatusTypeDef tmp_hal_status;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) {
+ return HAL_BUSY;
+ } else {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL) {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status == HAL_OK) {
+ tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
+ }
+
+ /* Start multimode conversion of ADCs pair */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC |
+ HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations)
+ */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ tmp_hal_status =
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR,
+ (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ } else {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC
+ * peripheral.
+ * @note Multimode is kept enabled after this function. MultiMode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To
+ * disable Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user
+ * can resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ uint32_t tmp_hadc_slave_conversion_on_going;
+ HAL_StatusTypeDef tmp_hadc_slave_disable_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential multimode conversion on going, on regular and injected
+ * groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK) {
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
+ (tmp_hadc_slave_conversion_on_going == 1UL)) {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption */
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
+ (tmp_hadc_slave_conversion_on_going == 1UL)) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADC_Stop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status == HAL_ERROR) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in
+ */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK) {
+ tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
+ if ((ADC_Disable(hadc) == HAL_OK) &&
+ (tmp_hadc_slave_disable_status == HAL_OK)) {
+ tmp_hal_status = HAL_OK;
+ }
+ } else {
+ /* In case of error, attempt to disable ADC master and slave without
+ * status assert */
+ (void)ADC_Disable(hadc);
+ (void)ADC_Disable(&tmp_hadc_slave);
+ }
+
+ /* Set ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Return the last ADC Master and Slave regular conversions results when
+ * in multimode configuration.
+ * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+ * @retval The converted data values.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) {
+ const ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
+ UNUSED(hadc);
+
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Return the multi mode conversion value */
+ return tmpADC_Common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 series).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+ * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+ * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+ * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc,
+ uint32_t InjectedRank) {
+ uint32_t tmp_jdr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch (InjectedRank) {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+
+/**
+ * @brief Injected conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedConvCpltCallback must be implemented in
+ the user file.
+ */
+}
+
+/**
+ * @brief Injected context queue overflow callback.
+ * @note This callback is called if injected context queue is enabled
+ (parameter "QueueInjectedContext" in injected channel configuration)
+ and if a new injected context is set when queue is full (maximum 2
+ contexts).
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
+ in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in
+ the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in
+ the user file.
+ */
+}
+
+/**
+ * @brief End Of Sampling callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_EndOfSamplingCallback must be implemented in the
+ user file.
+ */
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral if no
+ * conversion is on going on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if regular conversions are effectively stopped
+ and if no injected conversions are on-going */
+ if (tmp_hal_status == HAL_OK) {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of ADC groups regular and injected,
+ * disable interrution of end-of-conversion,
+ * disable ADC peripheral if no conversion is on going
+ * on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK) {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable all regular-related interrupts */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable ADC peripheral if no injected conversions are on-going */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
+ tmp_hal_status = ADC_Disable(hadc);
+ /* if no issue reported */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ } else {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral if no conversion is on going
+ * on injected group.
+ * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode
+ * only. For multimode (when multimode feature is available),
+ * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK) {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
+ if (tmp_hal_status == HAL_OK) {
+ tmp_hal_status = ADC_Disable(hadc);
+ } else {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK) {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ } else {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer,
+ * disable ADC peripheral if no injected conversion is on-going.
+ * @note Multimode is kept enabled after this function. Multimode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To
+ * disable multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user
+ * can resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADCEx_RegularStop_DMA() must be called after this function with
+ * handle of ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ uint32_t tmp_hadc_slave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential multimode conversion on going, on regular groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK) {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
+ (tmp_hadc_slave_conversion_on_going == 1UL)) {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption */
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) ||
+ (tmp_hadc_slave_conversion_on_going == 1UL)) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADCEx_RegularStop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave if no injected */
+ /* conversion is on-going. */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in
+ */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK) {
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
+ tmp_hal_status = ADC_Disable(hadc);
+ if (tmp_hal_status == HAL_OK) {
+ if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) ==
+ 0UL) {
+ tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
+ }
+ }
+ }
+
+ if (tmp_hal_status == HAL_OK) {
+ /* Both Master and Slave ADC's could be disabled. Update Master State */
+ /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ } else {
+ /* injected (Master or Slave) conversions are still on-going,
+ no Master State change */
+ }
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control
+functions
+ * @brief ADC Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on injected group
+ (+) Configure multimode when multimode feature is available
+ (+) Enable or Disable Injected Queue
+ (+) Disable ADC voltage regulator
+ (+) Enter ADC deep-power-down mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group injected.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_InjectionConfTypeDef".
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Caution: For Injected Context Queue use, a context must be fully
+ * defined before start of injected conversion. All channels are
+ * configured consecutively for the same ADC instance. Therefore, the number of
+ * calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of
+ * parameter InjectedNbrOfConversion for each context.
+ * - Example 1: If 1 context is intended to be used (or if there is no use of
+ * the Injected Queue Context feature) and if the context contains 3 injected
+ * ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must
+ * be called once for each channel (i.e. 3 times) before starting a conversion.
+ * This function must not be called to configure a 4th injected channel:
+ * it would start a new context into context queue.
+ * - Example 2: If 2 contexts are intended to be used and each of them contains
+ * 3 injected ranks (InjectedNbrOfConversion = 3),
+ * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+ * for each context (3 channels x 2 contexts = 6 calls). Conversion can
+ * start once the 1st context is set, that is after the first three
+ * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the
+ * fly.
+ * @param hadc ADC handle
+ * @param pConfigInjected Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(
+ ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected) {
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_offset_shifted;
+ uint32_t tmp_config_internal_channel;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+ __IO uint32_t wait_loop_index = 0;
+
+ uint32_t tmp_jsqr_context_queue_being_built = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
+ assert_param(
+ IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
+ assert_param(
+ IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
+ assert_param(
+ IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+ assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
+ assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
+ assert_param(
+ IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
+ assert_param(
+ IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+ ignored (considered as reset) */
+ assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) &&
+ (pConfigInjected->InjecOversamplingMode == ENABLE)));
+
+ /* JDISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) &&
+ (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* DISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) &&
+ (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* Verification of channel number */
+ if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) {
+ assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+ } else {
+ assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* Hardware constraint: Must fully define injected context register JSQR */
+ /* before make it entering into injected sequencer queue. */
+ /* */
+ /* - if scan mode is disabled: */
+ /* * Injected channels sequence length is set to 0x00: 1 channel */
+ /* converted (channel on injected rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* * Injected context register JSQR setting is simple: register is fully */
+ /* defined on one call of this function (for injected rank 1) and can */
+ /* be entered into queue directly. */
+ /* - if scan mode is enabled: */
+ /* * Injected channels sequence length is set to parameter */
+ /* "InjectedNbrOfConversion". */
+ /* * Injected context register JSQR setting more complex: register is */
+ /* fully defined over successive calls of this function, for each */
+ /* injected channel rank. It is entered into queue only when all */
+ /* injected ranks have been set. */
+ /* Note: Scan mode is not present by hardware on this device, but used */
+ /* by software for alignment over all STM32 devices. */
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
+ (pConfigInjected->InjectedNbrOfConversion == 1U)) {
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer: fixed to 1st rank */
+ /* (scan mode disabled, only rank 1 used) */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+ if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) {
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (pConfigInjected->ExternalTrigInjecConv !=
+ ADC_INJECTED_SOFTWARE_START) {
+ tmp_jsqr_context_queue_being_built =
+ (ADC_JSQR_RK(pConfigInjected->InjectedChannel,
+ ADC_INJECTED_RANK_1) |
+ (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) |
+ pConfigInjected->ExternalTrigInjecConvEdge);
+ } else {
+ tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(
+ pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+ }
+
+ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS,
+ tmp_jsqr_context_queue_being_built);
+ /* For debug and informative reasons, hadc handle saves JSQR setting */
+ hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
+ }
+ } else {
+ /* Case of scan mode enabled, several channels to set into injected group */
+ /* sequencer. */
+ /* */
+ /* Procedure to define injected context register JSQR over successive */
+ /* calls of this function, for each injected channel rank: */
+ /* 1. Start new context and set parameters related to all injected */
+ /* channels: injected sequence length and trigger. */
+
+ /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+ /* call of the context under setting */
+ if (hadc->InjectionConfig.ChannelCount == 0U) {
+ /* Initialize number of channels that will be configured on the context */
+ /* being built */
+ hadc->InjectionConfig.ChannelCount =
+ pConfigInjected->InjectedNbrOfConversion;
+ /* Handle hadc saves the context under build up over each
+ HAL_ADCEx_InjectedConfigChannel() call, this context will be written in
+ JSQR register at the last call. At this point, the context is merely
+ reset */
+ hadc->InjectionConfig.ContextQueue = 0x00000000U;
+
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (pConfigInjected->ExternalTrigInjecConv !=
+ ADC_INJECTED_SOFTWARE_START) {
+ tmp_jsqr_context_queue_being_built =
+ ((pConfigInjected->InjectedNbrOfConversion - 1U) |
+ (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) |
+ pConfigInjected->ExternalTrigInjecConvEdge);
+ } else {
+ tmp_jsqr_context_queue_being_built =
+ ((pConfigInjected->InjectedNbrOfConversion - 1U));
+ }
+ }
+
+ /* 2. Continue setting of context under definition with parameter */
+ /* related to each channel: channel rank sequence */
+ /* Clear the old JSQx bits for the selected rank */
+ tmp_jsqr_context_queue_being_built &=
+ ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
+
+ /* Set the JSQx bits for the selected rank */
+ tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(
+ pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
+
+ /* Decrease channel count */
+ hadc->InjectionConfig.ChannelCount--;
+
+ /* 3. tmp_jsqr_context_queue_being_built is fully built for this
+ HAL_ADCEx_InjectedConfigChannel() call, aggregate the setting to those
+ already built during the previous HAL_ADCEx_InjectedConfigChannel() calls
+ (for the same context of course) */
+ hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
+
+ /* 4. End of context setting: if this is the last channel set, then write
+ context into register JSQR and make it enter into queue */
+ if (hadc->InjectionConfig.ChannelCount == 0U) {
+ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS,
+ hadc->InjectionConfig.ContextQueue);
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on injected group: */
+ /* - Injected context queue: Queue disable (active context is kept) or */
+ /* enable (context decremented, up to 2 contexts queued) */
+ /* - Injected discontinuous mode: can be enabled only if auto-injected */
+ /* mode is disabled. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) {
+ /* If auto-injected mode is disabled: no constraint */
+ if (pConfigInjected->AutoInjectedConv == DISABLE) {
+ MODIFY_REG(
+ hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE(
+ (uint32_t)pConfigInjected->QueueInjectedContext) |
+ ADC_CFGR_INJECT_DISCCONTINUOUS(
+ (uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+ /* If auto-injected mode is enabled: Injected discontinuous setting is */
+ /* discarded. */
+ else {
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE(
+ (uint32_t)pConfigInjected->QueueInjectedContext));
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Automatic injected conversion: can be enabled if injected group */
+ /* external triggers are disabled. */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ /* If injected group external triggers are disabled (set to injected */
+ /* software start): no constraint */
+ if ((pConfigInjected->ExternalTrigInjecConv ==
+ ADC_INJECTED_SOFTWARE_START) ||
+ (pConfigInjected->ExternalTrigInjecConvEdge ==
+ ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) {
+ if (pConfigInjected->AutoInjectedConv == ENABLE) {
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ } else {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ }
+ }
+ /* If Automatic injected conversion was intended to be set and could not */
+ /* due to injected group external triggers enabled, error is reported. */
+ else {
+ if (pConfigInjected->AutoInjectedConv == ENABLE) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ } else {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ }
+ }
+
+ if (pConfigInjected->InjecOversamplingMode == ENABLE) {
+ assert_param(
+ IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(
+ pConfigInjected->InjecOversampling.RightBitShift));
+
+ /* JOVSE must be reset in case of triggered regular mode */
+ assert_param(!(
+ READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
+ (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+ /* Configuration of Injected Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+
+ /* Enable OverSampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE | pConfigInjected->InjecOversampling.Ratio |
+ pConfigInjected->InjecOversampling.RightBitShift);
+ } else {
+ /* Disable Regular OverSampling */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+ }
+
+ /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+ if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ pConfigInjected->InjectedChannel,
+ LL_ADC_SAMPLINGTIME_2CYCLES_5);
+
+ /* Set ADC sampling time common configuration */
+ LL_ADC_SetSamplingTimeCommonConfig(
+ hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+ } else {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ pConfigInjected->InjectedChannel,
+ pConfigInjected->InjectedSamplingTime);
+
+ /* Set ADC sampling time common configuration */
+ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance,
+ LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+ }
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to
+ * 0 */
+ tmp_offset_shifted =
+ ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
+
+ if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
+ pConfigInjected->InjectedChannel, tmp_offset_shifted);
+
+ /* Set ADC selected offset sign & saturation */
+ LL_ADC_SetOffsetSign(hadc->Instance,
+ pConfigInjected->InjectedOffsetNumber,
+ pConfigInjected->InjectedOffsetSign);
+ LL_ADC_SetOffsetSaturation(
+ hadc->Instance, pConfigInjected->InjectedOffsetNumber,
+ (pConfigInjected->InjectedOffsetSaturation == ENABLE)
+ ? LL_ADC_OFFSET_SATURATION_ENABLE
+ : LL_ADC_OFFSET_SATURATION_DISABLE);
+ } else {
+ /* Scan each offset register to check if the selected channel is targeted.
+ */
+ /* If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4,
+ LL_ADC_OFFSET_DISABLE);
+ }
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ /* Set mode single-ended or differential input of the selected ADC channel
+ */
+ LL_ADC_SetChannelSingleDiff(hadc->Instance,
+ pConfigInjected->InjectedChannel,
+ pConfigInjected->InjectedSingleDiff);
+
+ /* Configuration of differential mode */
+ /* Note: ADC channel number masked with value "0x1F" to ensure shift value
+ * within 32 bits range */
+ if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(
+ hadc->Instance,
+ (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
+ (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+ (uint32_t)pConfigInjected->InjectedChannel) +
+ 1UL) &
+ 0x1FUL)),
+ pConfigInjected->InjectedSamplingTime);
+ }
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel)) {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) ||
+ (pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) ==
+ 0UL)) {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) {
+ LL_ADC_SetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index =
+ ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) *
+ (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
+ while (wait_loop_index != 0UL) {
+ wait_loop_index--;
+ }
+ }
+ } else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) ==
+ 0UL)) {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) {
+ LL_ADC_SetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ } else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) ==
+ 0UL)) {
+ if (ADC_VREFINT_INSTANCE(hadc)) {
+ LL_ADC_SetCommonPathInternalCh(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ } else {
+ /* nothing to do */
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+ * the ADCs.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To move back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc Master ADC handle
+ * @param pMultimode Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(
+ ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) {
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmp_hadc_slave;
+ uint32_t tmp_hadc_slave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
+ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) {
+ assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
+ assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+ ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+ if (tmp_hadc_slave.Instance == NULL) {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Multimode DMA configuration */
+ /* - Multimode DMA mode */
+ tmp_hadc_slave_conversion_on_going =
+ LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) &&
+ (tmp_hadc_slave_conversion_on_going == 0UL)) {
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* If multimode is selected, configure all multimode parameters. */
+ /* Otherwise, reset multimode parameters (can be used in case of */
+ /* transition from multimode to independent mode). */
+ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) {
+ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
+ pMultimode->DMAAccessMode |
+ ADC_CCR_MULTI_DMACONTREQ(
+ (uint32_t)hadc->Init.DMAContinuousRequests));
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ /* Note: Delay range depends on selected resolution: */
+ /* from 1 to 12 clock cycles for 12 bits */
+ /* from 1 to 10 clock cycles for 10 bits, */
+ /* from 1 to 8 clock cycles for 8 bits */
+ /* from 1 to 6 clock cycles for 6 bits */
+ /* If a higher delay is selected, it will be clipped to maximum delay
+ */
+ /* range */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
+ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
+ pMultimode->Mode | pMultimode->TwoSamplingDelay);
+ }
+ } else /* ADC_MODE_INDEPENDENT */
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(
+ __LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+ }
+ }
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Enable Injected Queue
+ * @note This function resets CFGR register JQDIS bit in order to enable the
+ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+ * are both equal to 0 to ensure that no regular nor injected
+ * conversion is ongoing.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ /* Parameter can be set only if no conversion is on-going */
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ /* Update state, clear previous result related to injected queue overflow */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ tmp_hal_status = HAL_OK;
+ } else {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Disable Injected Queue
+ * @note This function sets CFGR register JQDIS bit in order to disable the
+ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+ * are both equal to 0 to ensure that no regular nor injected
+ * conversion is ongoing.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ tmp_adc_is_conversion_on_going_regular =
+ LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected =
+ LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ /* Parameter can be set only if no conversion is on-going */
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL) &&
+ (tmp_adc_is_conversion_on_going_injected == 0UL)) {
+ LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
+ tmp_hal_status = HAL_OK;
+ } else {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Disable ADC voltage regulator.
+ * @note Disabling voltage regulator allows to save power. This operation can
+ * be carried out only when ADC is disabled.
+ * @note To enable again the voltage regulator, the user is expected to
+ * resort to HAL_ADC_Init() API.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC
+ * disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ } else {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enter ADC deep-power-down mode
+ * @note This mode is achieved in setting DEEPPWD bit and allows to save power
+ * in reducing leakage currents. It is particularly interesting before
+ * entering stop modes.
+ * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+ * ADC voltage regulator. This means that this API encompasses
+ * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+ * calibration is lost.
+ * @note To exit the ADC deep-power-down mode, the user is expected to
+ * resort to HAL_ADC_Init() API as well as to relaunch a calibration
+ * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+ * saved calibration factor.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) {
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC
+ * disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) {
+ LL_ADC_EnableDeepPowerDown(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ } else {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c
index de4d3ff..e685d3f 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c
@@ -1,520 +1,545 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_cortex.c
- * @author MCD Application Team
- * @brief CORTEX HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CORTEX:
- * + Initialization and Configuration functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- *** How to configure Interrupts using CORTEX HAL driver ***
- ===========================================================
- [..]
- This section provides functions allowing to configure the NVIC interrupts
- (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
-
- (#) Configure the NVIC Priority Grouping using
- HAL_NVIC_SetPriorityGrouping() function.
- (#) Configure the priority of the selected IRQ Channels using
- HAL_NVIC_SetPriority().
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more
- possible. The pending IRQ priority will be managed only by the sub priority.
-
- -@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest pre-emption priority
- (+@) Lowest sub priority
- (+@) Lowest hardware priority (IRQ number)
-
- [..]
- *** How to configure SysTick using CORTEX HAL driver ***
- ========================================================
- [..]
- Setup SysTick Timer for time base.
-
- (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function
- which is a CMSIS function that:
- (++) Configures the SysTick Reload register with value passed as
- function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
- (++) Resets the SysTick Counter register.
- (++) Configures the SysTick Counter clock source to be Core Clock Source
- (HCLK).
- (++) Enables the SysTick Interrupt.
- (++) Starts the SysTick Counter.
-
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the
- macro
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after
- the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG()
- macro is defined inside the stm32g4xx_hal_cortex.h file.
-
- (+) You can change the SysTick IRQ priority by calling the
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the
- HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the
- NVIC_SetPriority() function which is a CMSIS function.
-
- (+) To adjust the SysTick time base, use the following formula:
-
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config()
- function
- (++) Reload Value should not exceed 0xFFFFFF
-
- @endverbatim
- ******************************************************************************
-
- The table below gives the allowed values of the pre-emption priority and
- subpriority according to the Priority Grouping configuration performed by
- HAL_NVIC_SetPriorityGrouping() function.
-
- ==========================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority |
- NVIC_IRQChannelSubPriority | Description
- ==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0-15
- | 0 bit for pre-emption priority | | | 4
- bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7
- | 1 bit for pre-emption priority | | | 3
- bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3
- | 2 bits for pre-emption priority | | | 2
- bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1
- | 3 bits for pre-emption priority | | | 1
- bit for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0-15 | 0 |
- 4 bits for pre-emption priority | | | 0 bit
- for subpriority
- ==========================================================================================================================
-
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This section provides the CORTEX HAL driver functions allowing to
-configure Interrupts SysTick functionalities
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the priority grouping field (pre-emption priority and
- * subpriority) using the required unlock sequence.
- * @param PriorityGroup: The priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
- * 1 bit for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
- * 0 bit for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more
- * possible. The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value
- */
- NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
- * @brief Set the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority
- * @param SubPriority: the subpriority level for the IRQ channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority,
- uint32_t SubPriority) {
- uint32_t prioritygroup;
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
-
- NVIC_SetPriority(
- IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
- * @brief Enable a device specific interrupt in the NVIC interrupt controller.
- * @note To configure interrupts priority correctly, the
- * NVIC_PriorityGroupConfig() function should be called before.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) {
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
-}
-
-/**
- * @brief Disable a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) {
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Disable interrupt */
- NVIC_DisableIRQ(IRQn);
-}
-
-/**
- * @brief Initiate a system reset request to reset the MCU.
- * @retval None
- */
-void HAL_NVIC_SystemReset(void) {
- /* System Reset */
- NVIC_SystemReset();
-}
-
-/**
- * @brief Initialize the System Timer with interrupt enabled and start the
- * System Tick Timer (SysTick): Counter is in free running mode to generate
- * periodic interrupts.
- * @param TicksNumb: Specifies the ticks Number of ticks between two
- * interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) {
- return SysTick_Config(TicksNumb);
-}
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @brief Cortex control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the priority grouping field from the NVIC Interrupt Controller.
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
- */
-uint32_t HAL_NVIC_GetPriorityGrouping(void) {
- /* Get the PRIGROUP[10:8] field value */
- return NVIC_GetPriorityGrouping();
-}
-
-/**
- * @brief Get the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @param PriorityGroup: the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
- * 1 bit for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
- * 0 bit for subpriority
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting
- * from 0).
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
- * @retval None
- */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup,
- uint32_t *pPreemptPriority, uint32_t *pSubPriority) {
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority,
- pSubPriority);
-}
-
-/**
- * @brief Set Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Set interrupt pending */
- NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Get Pending Interrupt (read the pending register in the NVIC
- * and return the pending bit for the specified interrupt).
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if pending else 0 */
- return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Clear the pending bit of an external interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Clear pending interrupt */
- NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
- * @brief Get active interrupt (read the active register in NVIC and return the
- * active bit).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to
- * the appropriate CMSIS device file (stm32g4xxxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
- /* Return 1 if active else 0 */
- return NVIC_GetActive(IRQn);
-}
-
-/**
- * @brief Configure the SysTick clock source.
- * @param CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected
- * as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock
- * source.
- * @retval None
- */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) {
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- } else {
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
- }
-}
-
-/**
- * @brief Handle SYSTICK interrupt request.
- * @retval None
- */
-void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); }
-
-/**
- * @brief SYSTICK callback.
- * @retval None
- */
-__weak void HAL_SYSTICK_Callback(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SYSTICK_Callback could be implemented in the user file
- */
-}
-
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Enable the MPU.
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged accessto the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-void HAL_MPU_Enable(uint32_t MPU_Control) {
- /* Enable the MPU */
- MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
-
- /* Ensure MPU setting take effects */
- __DSB();
- __ISB();
-}
-
-/**
- * @brief Disable the MPU.
- * @retval None
- */
-void HAL_MPU_Disable(void) {
- /* Make sure outstanding transfers are done */
- __DMB();
-
- /* Disable the MPU and clear the control register*/
- MPU->CTRL = 0;
-}
-
-/**
- * @brief Initialize and configure the Region and the memory to be protected.
- * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
- * @retval None
- */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) {
- /* Check the parameters */
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
- /* Set the Region number */
- MPU->RNR = MPU_Init->Number;
-
- if ((MPU_Init->Enable) != 0U) {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(
- IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- } else {
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
- }
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and Configuration functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts
+ (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using
+ HAL_NVIC_SetPriorityGrouping() function.
+ (#) Configure the priority of the selected IRQ Channels using
+ HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more
+ possible. The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest pre-emption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure SysTick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base.
+
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function
+ which is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as
+ function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source
+ (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the
+ macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after
+ the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG()
+ macro is defined inside the stm32g4xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the
+ HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the
+ NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config()
+ function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+
+ The table below gives the allowed values of the pre-emption priority and
+ subpriority according to the Priority Grouping configuration performed by
+ HAL_NVIC_SetPriorityGrouping() function.
+
+ ==========================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority |
+ NVIC_IRQChannelSubPriority | Description
+ ==========================================================================================================================
+ NVIC_PRIORITYGROUP_0 | 0 | 0-15
+ | 0 bit for pre-emption priority | | | 4
+ bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_1 | 0-1 | 0-7
+ | 1 bit for pre-emption priority | | | 3
+ bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_2 | 0-3 | 0-3
+ | 2 bits for pre-emption priority | | | 2
+ bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_3 | 0-7 | 0-1
+ | 3 bits for pre-emption priority | | | 1
+ bit for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_4 | 0-15 | 0 |
+ 4 bits for pre-emption priority | | | 0 bit
+ for subpriority
+ ==========================================================================================================================
+
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to
+configure Interrupts SysTick functionalities
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the priority grouping field (pre-emption priority and
+ * subpriority) using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * 1 bit for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+ * 0 bit for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more
+ * possible. The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value
+ */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Set the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority,
+ uint32_t SubPriority) {
+ uint32_t prioritygroup;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(
+ IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enable a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the
+ * NVIC_PriorityGroupConfig() function should be called before.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disable a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiate a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void) {
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initialize the System Timer with interrupt enabled and start the
+ * System Tick Timer (SysTick): Counter is in free running mode to generate
+ * periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two
+ * interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) {
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void) {
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Get the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * 1 bit for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+ * 0 bit for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting
+ * from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup,
+ uint32_t *pPreemptPriority, uint32_t *pSubPriority) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority,
+ pSubPriority);
+}
+
+/**
+ * @brief Set Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Get Pending Interrupt (read the pending register in the NVIC
+ * and return the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clear the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Get active interrupt (read the active register in NVIC and return the
+ * active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to
+ * the appropriate CMSIS device file (stm32g4xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configure the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected
+ * as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock
+ * source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) {
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ } else {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief Handle SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); }
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged accessto the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control) {
+ /* Enable the MPU */
+ MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+
+ /* Ensure MPU setting take effects */
+ __DSB();
+ __ISB();
+}
+
+/**
+ * @brief Disable the MPU.
+ * @retval None
+ */
+void HAL_MPU_Disable(void) {
+ /* Make sure outstanding transfers are done */
+ __DMB();
+
+ /* Disable the MPU and clear the control register*/
+ MPU->CTRL = 0;
+}
+
+/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber) {
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber) {
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Initialize and configure the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) {
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
index 7e4c831..ac3c8f9d 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
@@ -1,1077 +1,1078 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_dma.c
- * @author MCD Application Team
- * @brief DMA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access (DMA) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and errors functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the DMA Channel
- (except for internal SRAM / FLASH memories: no initialization is
- necessary). Please refer to the Reference manual for connection between
- peripherals and DMA requests.
-
- (#) For a given Channel, program the required configuration through the
- following parameters: Channel request, Transfer Direction, Source and
- Destination data formats, Circular or Normal mode, Channel Priority level,
- Source and Destination Increment mode using HAL_DMA_Init() function.
-
- Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA
- & DMAMUX thanks to:
- (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or
- __HAL_RCC_DMA2_CLK_ENABLE() ;
- (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
-
- (#) Use HAL_DMA_GetState() function to return the DMA state and
- HAL_DMA_GetError() in case of error detection.
-
- (#) Use HAL_DMA_Abort() function to abort the current transfer
-
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration
- of Source address and destination address and the Length of data to be
- transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current
- transfer, in this case a fixed Timeout can be configured by User depending
- from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the
- configuration of Source address and destination address and the Length of data
- to be transferred. In this case the DMA interrupt is configured
- (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt
- subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is
- executed and user can add his own function to register callbacks with
- HAL_DMA_RegisterCallback().
-
- *** DMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of macros in DMA HAL driver.
-
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
- (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel
- interrupt has occurred or not.
-
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros
-
- @endverbatim
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA DMA
- * @brief DMA HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @{
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t DataLength);
-
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/* Exported functions
- * ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization
-functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize the DMA Channel
-source and destination addresses, incrementation and data sizes, transfer
-direction, circular/normal mode selection, memory-to-memory mode selection and
-Channel priority value.
- [..]
- The HAL_DMA_Init() function follows the DMA configuration procedures as
-described in reference manual.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA according to the specified
- * parameters in the DMA_InitTypeDef and initialize the associated
- * handle.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
- uint32_t tmp;
-
- /* Check the DMA handle allocation */
- if (hdma == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
- assert_param(IS_DMA_MODE(hdma->Init.Mode));
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
- assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
-
- /* Compute the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) /
- ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1))
- << 2;
- hdma->DmaBaseAddress = DMA1;
- } else {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) /
- ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1))
- << 2;
- hdma->DmaBaseAddress = DMA2;
- }
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Get the CR register value */
- tmp = hdma->Instance->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
- tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
- DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
- DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-
- /* Prepare the DMA Channel configuration */
- tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc |
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
- hdma->Init.Mode | hdma->Init.Priority;
-
- /* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
- /* Initialize parameters for DMAMUX channel :
- DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
- */
- DMA_CalcDMAMUXChannelBaseAndMask(hdma);
-
- if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) {
- /* if memory to memory force the request to 0*/
- hdma->Init.Request = DMA_REQUEST_MEM2MEM;
- }
-
- /* Set peripheral request to DMAMUX channel */
- hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if (((hdma->Init.Request > 0U) &&
- (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) {
- /* Initialize parameters for DMAMUX request generator :
- DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
- */
- DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
-
- /* Reset the DMAMUX request generator register*/
- hdma->DMAmuxRequestGen->RGCR = 0U;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- } else {
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
- hdma->DMAmuxRequestGenStatusMask = 0U;
- }
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the DMA peripheral.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) {
- /* Check the DMA handle allocation */
- if (NULL == hdma) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* Disable the selected DMA Channelx */
- __HAL_DMA_DISABLE(hdma);
-
- /* Compute the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) /
- ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1))
- << 2;
- hdma->DmaBaseAddress = DMA1;
- } else {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) /
- ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1))
- << 2;
- hdma->DmaBaseAddress = DMA2;
- }
-
- /* Reset DMA Channel control register */
- hdma->Instance->CCR = 0;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Initialize parameters for DMAMUX channel :
- DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
-
- DMA_CalcDMAMUXChannelBaseAndMask(hdma);
-
- /* Reset the DMAMUX channel that corresponds to the DMA channel */
- hdma->DMAmuxChannel->CCR = 0;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Reset Request generator parameters if any */
- if (((hdma->Init.Request > 0U) &&
- (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) {
- /* Initialize parameters for DMAMUX request generator :
- DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
- */
- DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
-
- /* Reset the DMAMUX request generator register*/
- hdma->DMAmuxRequestGen->RGCR = 0U;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
- hdma->DMAmuxRequestGenStatusMask = 0U;
-
- /* Clean callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state */
- hdma->State = HAL_DMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start
-DMA transfer
- (+) Configure the source, destination address and data length and
- Start DMA transfer with interrupt
- (+) Abort DMA transfer
- (+) Poll for transfer complete
- (+) Handle DMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the DMA Transfer.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to
- * destination (up to 256Kbytes-1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t DataLength) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if (HAL_DMA_STATE_READY == hdma->State) {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear
- * flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- } else {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to
- * destination (up to 256Kbytes-1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t DataLength) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if (HAL_DMA_STATE_READY == hdma->State) {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear
- * flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete interrupt */
- /* Enable the transfer Error interrupt */
- if (NULL != hdma->XferHalfCpltCallback) {
- /* Enable the Half transfer complete interrupt as well */
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- } else {
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
- }
-
- /* Check if DMAMUX Synchronization is enabled*/
- if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) {
- /* Enable DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
- }
-
- if (hdma->DMAmuxRequestGen != 0U) {
- /* if using DMAMUX request generator, enable the DMAMUX request generator
- * overrun IT*/
- /* enable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
- }
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- } else {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Abort the DMA Transfer.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hdma->State != HAL_DMA_STATE_BUSY) {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- status = HAL_ERROR;
- } else {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* disable the DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if (hdma->DMAmuxRequestGen != 0U) {
- /* if using DMAMUX request generator, disable the DMAMUX request generator
- * overrun IT*/
- /* disable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
- }
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (HAL_DMA_STATE_BUSY != hdma->State) {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- status = HAL_ERROR;
- } else {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* disable the DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if (hdma->DMAmuxRequestGen != 0U) {
- /* if using DMAMUX request generator, disable the DMAMUX request generator
- * overrun IT*/
- /* disable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
- if (hdma->XferAbortCallback != NULL) {
- hdma->XferAbortCallback(hdma);
- }
- }
- return status;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CompleteLevel Specifies the DMA level complete.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(
- DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
- uint32_t Timeout) {
- uint32_t temp;
- uint32_t tickstart;
-
- if (HAL_DMA_STATE_BUSY != hdma->State) {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- __HAL_UNLOCK(hdma);
- return HAL_ERROR;
- }
-
- /* Polling mode not supported in circular mode */
- if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if (HAL_DMA_FULL_TRANSFER == CompleteLevel) {
- /* Transfer Complete flag */
-
- temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU);
- } else {
- /* Half Transfer Complete flag */
- temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU);
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while (0U == (hdma->DmaBaseAddress->ISR & temp)) {
- if ((0U != (hdma->DmaBaseAddress->ISR &
- ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))) {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR =
- ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- }
- }
-
- /*Check for DMAMUX Request generator (if used) overrun status */
- if (hdma->DMAmuxRequestGen != 0U) {
- /* if using DMAMUX request generator Check for DMAMUX request generator
- * overrun */
- if ((hdma->DMAmuxRequestGenStatus->RGSR &
- hdma->DMAmuxRequestGenStatusMask) != 0U) {
- /* Disable the request gen overrun interrupt */
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
- }
- }
-
- /* Check for DMAMUX Synchronization overrun */
- if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) {
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
- }
-
- if (HAL_DMA_FULL_TRANSFER == CompleteLevel) {
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR =
- ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU));
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- hdma->State = HAL_DMA_STATE_READY;
- } else {
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR =
- ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU));
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle DMA interrupt request.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) {
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
- uint32_t source_it = hdma->Instance->CCR;
-
- /* Half Transfer Complete Interrupt management ******************************/
- if ((0U !=
- (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) &&
- (0U != (source_it & DMA_IT_HT))) {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
- /* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- }
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR =
- ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* but in Transfer Complete case */
-
- if (hdma->XferHalfCpltCallback != NULL) {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
- /* Transfer Complete Interrupt management ***********************************/
- else if ((0U != (flag_it &
- ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)))) &&
- (0U != (source_it & DMA_IT_TC))) {
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
- /* Disable the transfer complete and error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR =
- ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferCpltCallback != NULL) {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
- /* Transfer Error Interrupt management **************************************/
- else if ((0U != (flag_it &
- ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))) &&
- (0U != (source_it & DMA_IT_TE))) {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Disable ALL DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR =
- ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferErrorCallback != NULL) {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- } else {
- /* Nothing To Do */
- }
- return;
-}
-
-/**
- * @brief Register callbacks
- * @param hdma pointer to a DMA_HandleTypeDef structure that
- * contains the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifier
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback pointer to private callbacsk function which has
- * pointer to a DMA_HandleTypeDef structure as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(
- DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID,
- void (*pCallback)(DMA_HandleTypeDef *_hdma)) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if (HAL_DMA_STATE_READY == hdma->State) {
- switch (CallbackID) {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- } else {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hdma pointer to a DMA_HandleTypeDef structure that
- * contains the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifier
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(
- DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if (HAL_DMA_STATE_READY == hdma->State) {
- switch (CallbackID) {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- } else {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors
-functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the DMA hande state.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL state
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) {
- /* Return DMA handle state */
- return hdma->State;
-}
-
-/**
- * @brief Return the DMA error code.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval DMA Error Code
- */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; }
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Sets the DMA Transfer parameter.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to
- * destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t DataLength) {
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if (hdma->DMAmuxRequestGen != 0U) {
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
-
- /* Configure DMA Channel data length */
- hdma->Instance->CNDTR = DataLength;
-
- /* Memory to Peripheral */
- if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
- /* Configure DMA Channel destination address */
- hdma->Instance->CPAR = DstAddress;
-
- /* Configure DMA Channel source address */
- hdma->Instance->CMAR = SrcAddress;
- }
- /* Peripheral to Memory */
- else {
- /* Configure DMA Channel source address */
- hdma->Instance->CPAR = SrcAddress;
-
- /* Configure DMA Channel destination address */
- hdma->Instance->CMAR = DstAddress;
- }
-}
-
-/**
- * @brief Updates the DMA handle with the DMAMUX channel and status mask
- * depending on stream number
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * Stream.
- * @retval None
- */
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) {
- uint32_t dmamux_base_addr;
- uint32_t channel_number;
- DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
-
- /* check if instance is not outside the DMA channel range */
- if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) {
- /* DMA1 */
- DMAMUX1_ChannelBase = DMAMUX1_Channel0;
- } else {
- /* DMA2 */
-#if defined(STM32G471xx) || defined(STM32G473xx) || defined(STM32G474xx) || \
- defined(STM32G483xx) || defined(STM32G484xx) || defined(STM32G491xx) || \
- defined(STM32G4A1xx)
- DMAMUX1_ChannelBase = DMAMUX1_Channel8;
-#elif defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32GBK1CB)
- DMAMUX1_ChannelBase = DMAMUX1_Channel6;
-#else
- DMAMUX1_ChannelBase = DMAMUX1_Channel7;
-#endif /* STM32G4x1xx) */
- }
- dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
- channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
- hdma->DMAmuxChannel =
- (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr +
- ((hdma->ChannelIndex >> 2U) *
- ((uint32_t)DMAMUX1_Channel1 -
- (uint32_t)DMAMUX1_Channel0)));
- hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
- hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
-}
-
-/**
- * @brief Updates the DMA handle with the DMAMUX request generator params
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * Channel.
- * @retval None
- */
-
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) {
- uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
-
- /* DMA Channels are connected to DMAMUX1 request generator blocks*/
- hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((
- uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
-
- hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
-
- hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_dma.c
+ * @author MCD Application Team
+ * @brief DMA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary). Please refer to the Reference manual for connection between
+ peripherals and DMA requests.
+
+ (#) For a given Channel, program the required configuration through the
+ following parameters: Channel request, Transfer Direction, Source and
+ Destination data formats, Circular or Normal mode, Channel Priority level,
+ Source and Destination Increment mode using HAL_DMA_Init() function.
+
+ Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA
+ & DMAMUX thanks to:
+ (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or
+ __HAL_RCC_DMA2_CLK_ENABLE() ;
+ (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and
+ HAL_DMA_GetError() in case of error detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration
+ of Source address and destination address and the Length of data to be
+ transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current
+ transfer, in this case a fixed Timeout can be configured by User depending
+ from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the
+ configuration of Source address and destination address and the Length of data
+ to be transferred. In this case the DMA interrupt is configured
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt
+ subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is
+ executed and user can add his own function to register callbacks with
+ HAL_DMA_RegisterCallback().
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel
+ interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t DataLength);
+
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/* Exported functions
+ * ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization
+functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel
+source and destination addresses, incrementation and data sizes, transfer
+direction, circular/normal mode selection, memory-to-memory mode selection and
+Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as
+described in reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and initialize the associated
+ * handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
+ uint32_t tmp;
+
+ /* Check the DMA handle allocation */
+ if (hdma == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
+
+ /* Compute the channel index */
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) /
+ ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1))
+ << 2;
+ hdma->DmaBaseAddress = DMA1;
+ } else {
+ /* DMA2 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) /
+ ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1))
+ << 2;
+ hdma->DmaBaseAddress = DMA2;
+ }
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
+ tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Initialize parameters for DMAMUX channel :
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+ */
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) {
+ /* if memory to memory force the request to 0*/
+ hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ }
+
+ /* Set peripheral request to DMAMUX channel */
+ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (((hdma->Init.Request > 0U) &&
+ (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) {
+ /* Initialize parameters for DMAMUX request generator :
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ */
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+ /* Reset the DMAMUX request generator register*/
+ hdma->DMAmuxRequestGen->RGCR = 0U;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ } else {
+ hdma->DMAmuxRequestGen = 0U;
+ hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGenStatusMask = 0U;
+ }
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the DMA peripheral.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) {
+ /* Check the DMA handle allocation */
+ if (NULL == hdma) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Compute the channel index */
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) /
+ ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1))
+ << 2;
+ hdma->DmaBaseAddress = DMA1;
+ } else {
+ /* DMA2 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) /
+ ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1))
+ << 2;
+ hdma->DmaBaseAddress = DMA2;
+ }
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0;
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Initialize parameters for DMAMUX channel :
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+ /* Reset the DMAMUX channel that corresponds to the DMA channel */
+ hdma->DMAmuxChannel->CCR = 0;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Reset Request generator parameters if any */
+ if (((hdma->Init.Request > 0U) &&
+ (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) {
+ /* Initialize parameters for DMAMUX request generator :
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ */
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+ /* Reset the DMAMUX request generator register*/
+ hdma->DMAmuxRequestGen->RGCR = 0U;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ hdma->DMAmuxRequestGen = 0U;
+ hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGenStatusMask = 0U;
+
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start
+DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA Transfer.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to
+ * destination (up to 256Kbytes-1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t DataLength) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State) {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length & clear
+ * flags*/
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ } else {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+ status = HAL_BUSY;
+ }
+ return status;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to
+ * destination (up to 256Kbytes-1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t DataLength) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State) {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length & clear
+ * flags*/
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ /* Enable the transfer Error interrupt */
+ if (NULL != hdma->XferHalfCpltCallback) {
+ /* Enable the Half transfer complete interrupt as well */
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ } else {
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ }
+
+ /* Check if DMAMUX Synchronization is enabled*/
+ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) {
+ /* Enable DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ }
+
+ if (hdma->DMAmuxRequestGen != 0U) {
+ /* if using DMAMUX request generator, enable the DMAMUX request generator
+ * overrun IT*/
+ /* enable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ } else {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+ return status;
+}
+
+/**
+ * @brief Abort the DMA Transfer.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hdma->State != HAL_DMA_STATE_BUSY) {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ status = HAL_ERROR;
+ } else {
+ /* Disable DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* disable the DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (hdma->DMAmuxRequestGen != 0U) {
+ /* if using DMAMUX request generator, disable the DMAMUX request generator
+ * overrun IT*/
+ /* disable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+ }
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_DMA_STATE_BUSY != hdma->State) {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ status = HAL_ERROR;
+ } else {
+ /* Disable DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* disable the DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (hdma->DMAmuxRequestGen != 0U) {
+ /* if using DMAMUX request generator, disable the DMAMUX request generator
+ * overrun IT*/
+ /* disable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Call User Abort callback */
+ if (hdma->XferAbortCallback != NULL) {
+ hdma->XferAbortCallback(hdma);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel Specifies the DMA level complete.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(
+ DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+ uint32_t Timeout) {
+ uint32_t temp;
+ uint32_t tickstart;
+
+ if (HAL_DMA_STATE_BUSY != hdma->State) {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode */
+ if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) {
+ /* Transfer Complete flag */
+
+ temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU);
+ } else {
+ /* Half Transfer Complete flag */
+ temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (0U == (hdma->DmaBaseAddress->ISR & temp)) {
+ if ((0U != (hdma->DmaBaseAddress->ISR &
+ ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))) {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR =
+ ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /*Check for DMAMUX Request generator (if used) overrun status */
+ if (hdma->DMAmuxRequestGen != 0U) {
+ /* if using DMAMUX request generator Check for DMAMUX request generator
+ * overrun */
+ if ((hdma->DMAmuxRequestGenStatus->RGSR &
+ hdma->DMAmuxRequestGenStatusMask) != 0U) {
+ /* Disable the request gen overrun interrupt */
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+ }
+ }
+
+ /* Check for DMAMUX Synchronization overrun */
+ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) {
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+ }
+
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) {
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR =
+ ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+ } else {
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR =
+ ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU));
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle DMA interrupt request.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) {
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ uint32_t source_it = hdma->Instance->CCR;
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if ((0U !=
+ (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) &&
+ (0U != (source_it & DMA_IT_HT))) {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR =
+ ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* but in Transfer Complete case */
+
+ if (hdma->XferHalfCpltCallback != NULL) {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ /* Transfer Complete Interrupt management ***********************************/
+ else if ((0U != (flag_it &
+ ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)))) &&
+ (0U != (source_it & DMA_IT_TC))) {
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
+ /* Disable the transfer complete and error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR =
+ ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferCpltCallback != NULL) {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ /* Transfer Error Interrupt management **************************************/
+ else if ((0U != (flag_it &
+ ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))) &&
+ (0U != (source_it & DMA_IT_TE))) {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Disable ALL DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR =
+ ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL) {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ } else {
+ /* Nothing To Do */
+ }
+ return;
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that
+ * contains the configuration information for the specified DMA Channel.
+ * @param CallbackID User Callback identifier
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @param pCallback pointer to private callbacsk function which has
+ * pointer to a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(
+ DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID,
+ void (*pCallback)(DMA_HandleTypeDef *_hdma)) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State) {
+ switch (CallbackID) {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that
+ * contains the configuration information for the specified DMA Channel.
+ * @param CallbackID User Callback identifier
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(
+ DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State) {
+ switch (CallbackID) {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors
+functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DMA hande state.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) {
+ /* Return DMA handle state */
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to
+ * destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t DataLength) {
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (hdma->DMAmuxRequestGen != 0U) {
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Memory to Peripheral */
+ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Peripheral to Memory */
+ else {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @brief Updates the DMA handle with the DMAMUX channel and status mask
+ * depending on stream number
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * Stream.
+ * @retval None
+ */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) {
+ uint32_t dmamux_base_addr;
+ uint32_t channel_number;
+ DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
+
+ /* check if instance is not outside the DMA channel range */
+ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) {
+ /* DMA1 */
+ DMAMUX1_ChannelBase = DMAMUX1_Channel0;
+ } else {
+ /* DMA2 */
+#if defined(STM32G471xx) || defined(STM32G473xx) || defined(STM32G474xx) || \
+ defined(STM32G414xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
+ defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+ DMAMUX1_ChannelBase = DMAMUX1_Channel8;
+#elif defined(STM32G411xB) || defined(STM32G431xx) || defined(STM32G441xx) || \
+ defined(STM32GBK1CB)
+ DMAMUX1_ChannelBase = DMAMUX1_Channel6;
+#else
+ DMAMUX1_ChannelBase = DMAMUX1_Channel7;
+#endif /* STM32G4x1xx) */
+ }
+ dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
+ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
+ hdma->DMAmuxChannel =
+ (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr +
+ ((hdma->ChannelIndex >> 2U) *
+ ((uint32_t)DMAMUX1_Channel1 -
+ (uint32_t)DMAMUX1_Channel0)));
+ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+ hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
+}
+
+/**
+ * @brief Updates the DMA handle with the DMAMUX request generator params
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * Channel.
+ * @retval None
+ */
+
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) {
+ uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+ /* DMA Channels are connected to DMAMUX1 request generator blocks*/
+ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((
+ uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+
+ hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+
+ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
index e6aa7ca..44a1ac0 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
@@ -1,300 +1,300 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_dma_ex.c
- * @author MCD Application Team
- * @brief DMA Extension HAL module driver
- * This file provides firmware functions to manage the following
- * functionalities of the DMA Extension peripheral:
- * + Extended features functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The DMA Extension HAL driver can be used as follows:
-
- (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync
- function.
- (+) Configure the DMA_MUX Request Generator Block using
- HAL_DMAEx_ConfigMuxRequestGenerator function. Functions
- HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator
- can then be used to respectively enable/disable the request generator.
-
- (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler
- should be called from the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. As
- only one interrupt line is available for all DMAMUX channels and request
- generators , HAL_DMAEx_MUX_IRQHandler should be called with, as parameter, the
- appropriate DMA handle as many as used DMAs in the user project (exception
- done if a given DMA is not using the DMAMUX SYNC block neither a request
- generator)
-
- @endverbatim
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMAEx DMAEx
- * @brief DMA Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private Constants ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
- * @{
- */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
- (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync
-function.
- (+) Configure the DMAMUX Request Generator Block using
-HAL_DMAEx_ConfigMuxRequestGenerator function. Functions
-HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can
-then be used to respectively enable/disable the request generator.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the DMAMUX synchronization parameters for a given DMA
- * channel (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * channel.
- * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the
- * DMAMUX synchronization parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(
- DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) {
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
-
- assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
- assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
- assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
- assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
-
- /*Check if the DMA state is ready */
- if (hdma->State == HAL_DMA_STATE_READY) {
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- /* Set the new synchronization parameters (and keep the request ID filled
- * during the Init)*/
- MODIFY_REG(
- hdma->DMAmuxChannel->CCR, (~DMAMUX_CxCR_DMAREQ_ID),
- ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) |
- ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) |
- pSyncConfig->SyncPolarity |
- ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) |
- ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
-
- /* Process UnLocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
- } else {
- /*DMA State not Ready*/
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMAMUX request generator block used by the given DMA
- * channel (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * channel.
- * @param pRequestGeneratorConfig : pointer to
- * HAL_DMA_MuxRequestGeneratorConfigTypeDef : contains the request generator
- * parameters.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(
- DMA_HandleTypeDef *hdma,
- HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) {
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- assert_param(
- IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
-
- assert_param(
- IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
- assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(
- pRequestGeneratorConfig->RequestNumber));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) {
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- /* Set the request generator new parameters */
- hdma->DMAmuxRequestGen->RGCR =
- pRequestGeneratorConfig->SignalID |
- ((pRequestGeneratorConfig->RequestNumber - 1U)
- << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) |
- pRequestGeneratorConfig->Polarity;
- /* Process UnLocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the DMAMUX request generator block used by the given DMA
- * channel (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) {
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) {
- /* Enable the request generator*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
-
- return HAL_OK;
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the DMAMUX request generator block used by the given DMA
- * channel (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA
- * channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(
- DMA_HandleTypeDef *hdma) {
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) {
- /* Disable the request generator*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
-
- return HAL_OK;
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handles DMAMUX interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA channel.
- * @retval None
- */
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) {
- /* Check for DMAMUX Synchronization overrun */
- if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) {
- /* Disable the synchro overrun interrupt */
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
-
- if (hdma->XferErrorCallback != NULL) {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
-
- if (hdma->DMAmuxRequestGen != 0) {
- /* if using a DMAMUX request generator block Check for DMAMUX request
- * generator overrun */
- if ((hdma->DMAmuxRequestGenStatus->RGSR &
- hdma->DMAmuxRequestGenStatusMask) != 0U) {
- /* Disable the request gen overrun interrupt */
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
-
- if (hdma->XferErrorCallback != NULL) {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_dma_ex.c
+ * @author MCD Application Team
+ * @brief DMA Extension HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the DMA Extension peripheral:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The DMA Extension HAL driver can be used as follows:
+
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync
+ function.
+ (+) Configure the DMA_MUX Request Generator Block using
+ HAL_DMAEx_ConfigMuxRequestGenerator function. Functions
+ HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator
+ can then be used to respectively enable/disable the request generator.
+
+ (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler
+ should be called from the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. As
+ only one interrupt line is available for all DMAMUX channels and request
+ generators , HAL_DMAEx_MUX_IRQHandler should be called with, as parameter, the
+ appropriate DMA handle as many as used DMAs in the user project (exception
+ done if a given DMA is not using the DMAMUX SYNC block neither a request
+ generator)
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @brief DMA Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync
+function.
+ (+) Configure the DMAMUX Request Generator Block using
+HAL_DMAEx_ConfigMuxRequestGenerator function. Functions
+HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can
+then be used to respectively enable/disable the request generator.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DMAMUX synchronization parameters for a given DMA
+ * channel (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * channel.
+ * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the
+ * DMAMUX synchronization parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(
+ DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) {
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+
+ assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
+ assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+ assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+ assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+ /*Check if the DMA state is ready */
+ if (hdma->State == HAL_DMA_STATE_READY) {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ /* Set the new synchronization parameters (and keep the request ID filled
+ * during the Init)*/
+ MODIFY_REG(
+ hdma->DMAmuxChannel->CCR, (~DMAMUX_CxCR_DMAREQ_ID),
+ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) |
+ ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) |
+ pSyncConfig->SyncPolarity |
+ ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) |
+ ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+
+ /* Process UnLocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+ } else {
+ /*DMA State not Ready*/
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMAMUX request generator block used by the given DMA
+ * channel (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * channel.
+ * @param pRequestGeneratorConfig : pointer to
+ * HAL_DMA_MuxRequestGeneratorConfigTypeDef : contains the request generator
+ * parameters.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(
+ DMA_HandleTypeDef *hdma,
+ HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) {
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ assert_param(
+ IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+
+ assert_param(
+ IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+ assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(
+ pRequestGeneratorConfig->RequestNumber));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ /* Set the request generator new parameters */
+ hdma->DMAmuxRequestGen->RGCR =
+ pRequestGeneratorConfig->SignalID |
+ ((pRequestGeneratorConfig->RequestNumber - 1U)
+ << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) |
+ pRequestGeneratorConfig->Polarity;
+ /* Process UnLocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the DMAMUX request generator block used by the given DMA
+ * channel (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) {
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) {
+ /* Enable the request generator*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+ return HAL_OK;
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the DMAMUX request generator block used by the given DMA
+ * channel (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA
+ * channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(
+ DMA_HandleTypeDef *hdma) {
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) {
+ /* Disable the request generator*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+ return HAL_OK;
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles DMAMUX interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA channel.
+ * @retval None
+ */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) {
+ /* Check for DMAMUX Synchronization overrun */
+ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) {
+ /* Disable the synchro overrun interrupt */
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+ if (hdma->XferErrorCallback != NULL) {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+
+ if (hdma->DMAmuxRequestGen != 0) {
+ /* if using a DMAMUX request generator block Check for DMAMUX request
+ * generator overrun */
+ if ((hdma->DMAmuxRequestGenStatus->RGSR &
+ hdma->DMAmuxRequestGenStatusMask) != 0U) {
+ /* Disable the request gen overrun interrupt */
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+ if (hdma->XferErrorCallback != NULL) {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
index 56efc0d..ec22889 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
@@ -1,606 +1,607 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_exti.c
- * @author MCD Application Team
- * @brief EXTI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Extended Interrupts and events controller
- (EXTI) peripheral:
- * functionalities of the General Purpose Input/Output (EXTI)
- peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### EXTI Peripheral features #####
- ==============================================================================
- [..]
- (+) Each Exti line can be configured within this driver.
-
- (+) Exti line can be configured in 3 different modes
- (++) Interrupt
- (++) Event
- (++) Both of them
-
- (+) Configurable Exti lines can be configured with 3 different triggers
- (++) Rising
- (++) Falling
- (++) Both of them
-
- (+) When set in interrupt mode, configurable Exti lines have two different
- interrupt pending registers which allow to distinguish which transition
- occurs:
- (++) Rising edge pending interrupt
- (++) Falling
-
- (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
- be selected through multiplexer.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
- (++) Choose the interrupt line number by setting "Line" member from
- EXTI_ConfigTypeDef structure.
- (++) Configure the interrupt and/or event mode using "Mode" member from
- EXTI_ConfigTypeDef structure.
- (++) For configurable lines, configure rising and/or falling trigger
- "Trigger" member from EXTI_ConfigTypeDef structure.
- (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
- member from GPIO_InitTypeDef structure.
-
- (#) Get current Exti configuration of a dedicated line using
- HAL_EXTI_GetConfigLine().
- (++) Provide exiting handle as parameter.
- (++) Provide pointer on EXTI_ConfigTypeDef structure as second
- parameter.
-
- (#) Clear Exti configuration of a dedicated line using
- HAL_EXTI_GetConfigLine().
- (++) Provide exiting handle as parameter.
-
- (#) Register callback to treat Exti interrupts using
- HAL_EXTI_RegisterCallback().
- (++) Provide exiting handle as first parameter.
- (++) Provide which callback will be registered using one value from
- EXTI_CallbackIDTypeDef.
- (++) Provide callback function pointer.
-
- (#) Get interrupt pending bit using HAL_EXTI_GetPending().
-
- (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
-
- (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
-
- @endverbatim
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-/** MISRA C:2012 deviation rule has been granted for following rule:
- * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
- * of bounds [0,3] in following API :
- * HAL_EXTI_SetConfigLine
- * HAL_EXTI_GetConfigLine
- * HAL_EXTI_ClearConfigLine
- */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines
- * ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-#define EXTI_MODE_OFFSET \
- 0x08U /* 0x20: offset between MCU IMR/EMR registers \
- */
-#define EXTI_CONFIG_OFFSET \
- 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup EXTI_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_Exported_Functions_Group1
- * @brief Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @param pExtiConfig Pointer on EXTI configuration to be set.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti,
- EXTI_ConfigTypeDef *pExtiConfig) {
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check null pointer */
- if ((hexti == NULL) || (pExtiConfig == NULL)) {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(pExtiConfig->Line));
- assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
-
- /* Assign line number to handle */
- hexti->Line = pExtiConfig->Line;
-
- /* Compute line register offset */
- offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* Compute line position */
- linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
- /* Compute line mask */
- maskline = (1uL << linepos);
-
- /* Configure triggers for configurable lines */
- if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) {
- assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
- /* Configure rising trigger */
- regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) {
- regval |= maskline;
- } else {
- regval &= ~maskline;
- }
-
- /* Store rising trigger mode */
- *regaddr = regval;
-
- /* Configure falling trigger */
- regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) {
- regval |= maskline;
- } else {
- regval &= ~maskline;
- }
-
- /* Store falling trigger mode */
- *regaddr = regval;
-
- /* Configure gpio port selection in case of gpio exti line */
- if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) {
- assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = SYSCFG->EXTICR[linepos >> 2u];
- regval &= ~(SYSCFG_EXTICR1_EXTI0
- << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- regval |= (pExtiConfig->GPIOSel
- << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- SYSCFG->EXTICR[linepos >> 2u] = regval;
- }
- }
-
- /* Configure interrupt mode : read current mode */
- regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) {
- regval |= maskline;
- } else {
- regval &= ~maskline;
- }
-
- /* Store interrupt mode */
- *regaddr = regval;
-
- /* Configure event mode : read current mode */
- regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) {
- regval |= maskline;
- } else {
- regval &= ~maskline;
- }
-
- /* Store event mode */
- *regaddr = regval;
-
- return HAL_OK;
-}
-
-/**
- * @brief Get configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @param pExtiConfig Pointer on structure to store Exti configuration.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti,
- EXTI_ConfigTypeDef *pExtiConfig) {
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check null pointer */
- if ((hexti == NULL) || (pExtiConfig == NULL)) {
- return HAL_ERROR;
- }
-
- /* Check the parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
-
- /* Store handle line number to configuration structure */
- pExtiConfig->Line = hexti->Line;
-
- /* Compute line register offset and line mask */
- offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* Compute line position */
- linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
- /* Compute mask */
- maskline = (1uL << linepos);
-
- /* 1] Get core mode : interrupt */
- regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if selected line is enable */
- if ((regval & maskline) != 0x00u) {
- pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
- } else {
- pExtiConfig->Mode = EXTI_MODE_NONE;
- }
-
- /* Get event mode */
- regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if selected line is enable */
- if ((regval & maskline) != 0x00u) {
- pExtiConfig->Mode |= EXTI_MODE_EVENT;
- }
-
- /* Get default Trigger and GPIOSel configuration */
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- pExtiConfig->GPIOSel = 0x00u;
-
- /* 2] Get trigger for configurable lines : rising */
- if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) {
- regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if configuration of selected line is enable */
- if ((regval & maskline) != 0x00u) {
- pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
- }
-
- /* Get falling configuration */
- regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if configuration of selected line is enable */
- if ((regval & maskline) != 0x00u) {
- pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
- }
-
- /* Get Gpio port selection for gpio lines */
- if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) {
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = SYSCFG->EXTICR[linepos >> 2u];
- pExtiConfig->GPIOSel =
- ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Clear whole configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) {
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check null pointer */
- if (hexti == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
-
- /* compute line register offset and line mask */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* compute line position */
- linepos = (hexti->Line & EXTI_PIN_MASK);
- /* compute line mask */
- maskline = (1uL << linepos);
-
- /* 1] Clear interrupt mode */
- regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- /* 2] Clear event mode */
- regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- /* 3] Clear triggers in case of configurable lines */
- if ((hexti->Line & EXTI_CONFIG) != 0x00u) {
- regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- /* Get Gpio port selection for gpio lines */
- if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) {
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = SYSCFG->EXTICR[linepos >> 2u];
- regval &= ~(SYSCFG_EXTICR1_EXTI0
- << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- SYSCFG->EXTICR[linepos >> 2u] = regval;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Register callback for a dedicated Exti line.
- * @param hexti Exti handle.
- * @param CallbackID User callback identifier.
- * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
- * @param pPendingCbfn function pointer to be stored as callback.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti,
- EXTI_CallbackIDTypeDef CallbackID,
- void (*pPendingCbfn)(void)) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_EXTI_CB(CallbackID));
-
- switch (CallbackID) {
- /* set common callback */
- case HAL_EXTI_COMMON_CB_ID:
- hexti->PendingCallback = pPendingCbfn;
- break;
-
- default:
- hexti->PendingCallback = NULL;
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Store line number as handle private field.
- * @param hexti Exti handle.
- * @param ExtiLine Exti line number.
- * This parameter can be from 0 to @ref EXTI_LINE_NB.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti,
- uint32_t ExtiLine) {
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(ExtiLine));
-
- /* Check null pointer */
- if (hexti == NULL) {
- return HAL_ERROR;
- } else {
- /* Store line number as handle private field */
- hexti->Line = ExtiLine;
-
- return HAL_OK;
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup EXTI_Exported_Functions_Group2
- * @brief EXTI IO functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param hexti Exti handle.
- * @retval none.
- */
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) {
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t maskline;
- uint32_t offset;
-
- /* Compute line register offset */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* compute line mask */
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Get pending bit */
- regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = (*regaddr & maskline);
-
- if (regval != 0x00u) {
- /* Clear pending bit */
- *regaddr = maskline;
-
- /* Call pending callback */
- if (hexti->PendingCallback != NULL) {
- hexti->PendingCallback();
- }
- }
-}
-
-/**
- * @brief Get interrupt pending bit of a dedicated line.
- * @param hexti Exti handle.
- * @param Edge unused
- * @retval 1 if interrupt is pending else 0.
- */
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) {
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- UNUSED(Edge);
-
- /* Compute line register offset */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* Compute line position */
- linepos = (hexti->Line & EXTI_PIN_MASK);
- /* Compute line mask */
- maskline = (1uL << linepos);
-
- /* Get pending bit */
- regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
-
- /* return 1 if bit is set else 0 */
- regval = ((*regaddr & maskline) >> linepos);
- return regval;
-}
-
-/**
- * @brief Clear interrupt pending bit of a dedicated line.
- * @param hexti Exti handle.
- * @param Edge unused
- * @retval None.
- */
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) {
- __IO uint32_t *regaddr;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- UNUSED(Edge);
-
- /* Compute line register offset */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* Compute line mask */
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Get pending register address */
- regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
-
- /* Clear Pending bit */
- *regaddr = maskline;
-}
-
-/**
- * @brief Generate a software interrupt for a dedicated line.
- * @param hexti Exti handle.
- * @retval None.
- */
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) {
- __IO uint32_t *regaddr;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-
- /* compute line register offset */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- /* compute line mask */
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
- *regaddr = maskline;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_EXTI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Extended Interrupts and events controller
+ (EXTI) peripheral:
+ * functionalities of the General Purpose Input/Output (EXTI)
+ peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two different
+ interrupt pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected through multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second
+ parameter.
+
+ (#) Clear Exti configuration of a dedicated line using
+ HAL_EXTI_ClearConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using
+ HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+ * of bounds [0,3] in following API :
+ * HAL_EXTI_SetConfigLine
+ * HAL_EXTI_GetConfigLine
+ * HAL_EXTI_ClearConfigLine
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines
+ * ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+#define EXTI_MODE_OFFSET \
+ 0x08U /* 0x20: offset between MCU IMR/EMR registers \
+ */
+#define EXTI_CONFIG_OFFSET \
+ 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti,
+ EXTI_ConfigTypeDef *pExtiConfig) {
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL)) {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* Compute line register offset */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* Compute line position */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ /* Compute line mask */
+ maskline = (1uL << linepos);
+
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) {
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) {
+ regval |= maskline;
+ } else {
+ regval &= ~maskline;
+ }
+
+ /* Store rising trigger mode */
+ *regaddr = regval;
+
+ /* Configure falling trigger */
+ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) {
+ regval |= maskline;
+ } else {
+ regval &= ~maskline;
+ }
+
+ /* Store falling trigger mode */
+ *regaddr = regval;
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0
+ << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ regval |= (pExtiConfig->GPIOSel
+ << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ /* Configure interrupt mode : read current mode */
+ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) {
+ regval |= maskline;
+ } else {
+ regval &= ~maskline;
+ }
+
+ /* Store interrupt mode */
+ *regaddr = regval;
+
+ /* Configure event mode : read current mode */
+ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) {
+ regval |= maskline;
+ } else {
+ regval &= ~maskline;
+ }
+
+ /* Store event mode */
+ *regaddr = regval;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti,
+ EXTI_ConfigTypeDef *pExtiConfig) {
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL)) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configuration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* Compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* Compute line position */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ /* Compute mask */
+ maskline = (1uL << linepos);
+
+ /* 1] Get core mode : interrupt */
+ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0x00u) {
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ } else {
+ pExtiConfig->Mode = EXTI_MODE_NONE;
+ }
+
+ /* Get event mode */
+ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0x00u) {
+ pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ }
+
+ /* Get default Trigger and GPIOSel configuration */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) {
+ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0x00u) {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+
+ /* Get falling configuration */
+ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0x00u) {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ pExtiConfig->GPIOSel =
+ (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) &
+ SYSCFG_EXTICR1_EXTI0;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) {
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if (hexti == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* compute line position */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ /* compute line mask */
+ maskline = (1uL << linepos);
+
+ /* 1] Clear interrupt mode */
+ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 2] Clear event mode */
+ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0x00u) {
+ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0
+ << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Register callback for a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti,
+ EXTI_CallbackIDTypeDef CallbackID,
+ void (*pPendingCbfn)(void)) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_CB(CallbackID));
+
+ switch (CallbackID) {
+ /* set common callback */
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->PendingCallback = pPendingCbfn;
+ break;
+
+ default:
+ hexti->PendingCallback = NULL;
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti,
+ uint32_t ExtiLine) {
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL) {
+ return HAL_ERROR;
+ } else {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) {
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Compute line register offset */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get pending bit */
+ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0x00u) {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call pending callback */
+ if (hexti->PendingCallback != NULL) {
+ hexti->PendingCallback();
+ }
+ }
+}
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge unused
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) {
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ UNUSED(Edge);
+
+ /* Compute line register offset */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* Compute line position */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ /* Compute line mask */
+ maskline = (1uL << linepos);
+
+ /* Get pending bit */
+ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+
+ /* return 1 if bit is set else 0 */
+ regval = ((*regaddr & maskline) >> linepos);
+ return regval;
+}
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge unused
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) {
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ UNUSED(Edge);
+
+ /* Compute line register offset */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get pending register address */
+ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+
+ /* Clear Pending bit */
+ *regaddr = maskline;
+}
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) {
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+ /* compute line register offset */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ /* compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+ *regaddr = maskline;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c
index 835edb3..54a4f91 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c
@@ -1,3405 +1,3435 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_fdcan.c
- * @author MCD Application Team
- * @brief FDCAN HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Flexible DataRate Controller Area Network
- * (FDCAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Configuration and Control functions
- * + Peripheral State and Error functions
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
-
- (#) If needed , configure the reception filters and optional features
- using the following configuration functions:
- (++) HAL_FDCAN_ConfigFilter
- (++) HAL_FDCAN_ConfigGlobalFilter
- (++) HAL_FDCAN_ConfigExtendedIdMask
- (++) HAL_FDCAN_ConfigRxFifoOverwrite
- (++) HAL_FDCAN_ConfigRamWatchdog
- (++) HAL_FDCAN_ConfigTimestampCounter
- (++) HAL_FDCAN_EnableTimestampCounter
- (++) HAL_FDCAN_DisableTimestampCounter
- (++) HAL_FDCAN_ConfigTimeoutCounter
- (++) HAL_FDCAN_EnableTimeoutCounter
- (++) HAL_FDCAN_DisableTimeoutCounter
- (++) HAL_FDCAN_ConfigTxDelayCompensation
- (++) HAL_FDCAN_EnableTxDelayCompensation
- (++) HAL_FDCAN_DisableTxDelayCompensation
- (++) HAL_FDCAN_EnableISOMode
- (++) HAL_FDCAN_DisableISOMode
- (++) HAL_FDCAN_EnableEdgeFiltering
- (++) HAL_FDCAN_DisableEdgeFiltering
-
- (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
- the node is active on the bus: it can send and receive messages.
-
- (#) The following Tx control functions can only be called when the FDCAN
- module is started:
- (++) HAL_FDCAN_AddMessageToTxFifoQ
- (++) HAL_FDCAN_AbortTxRequest
-
- (#) After having submitted a Tx request in Tx Fifo or Queue, it is
- possible to get Tx buffer location used to place the Tx request thanks to
- HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
- It is then possible to abort later on the corresponding Tx Request
- using HAL_FDCAN_AbortTxRequest API.
-
- (#) When a message is received into the FDCAN message RAM, it can be
- retrieved using the HAL_FDCAN_GetRxMessage function.
-
- (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
- it to initialization mode and re-enabling access to configuration
- registers through the configuration functions listed here above.
-
- (#) All other control functions can be called any time after
- initialization phase, no matter if the FDCAN module is started or stopped.
-
- *** Polling mode operation ***
- ==============================
- [..]
- (#) Reception and transmission states can be monitored via the following
- functions:
- (++) HAL_FDCAN_IsTxBufferMessagePending
- (++) HAL_FDCAN_GetRxFifoFillLevel
- (++) HAL_FDCAN_GetTxFifoFreeLevel
-
- *** Interrupt mode operation ***
- ================================
- [..]
- (#) There are two interrupt lines: line 0 and 1.
- By default, all interrupts are assigned to line 0. Interrupt lines
- can be configured using HAL_FDCAN_ConfigInterruptLines function.
-
- (#) Notifications are activated using HAL_FDCAN_ActivateNotification
- function. Then, the process can be controlled through one of the
- available user callbacks: HAL_FDCAN_xxxCallback.
-
- *** Callback registration ***
- =============================================
-
- The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
- Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
- to register an interrupt callback.
-
- Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
- (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
- (+) HighPriorityMessageCallback : High Priority Message Callback.
- (+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
- (+) TimeoutOccurredCallback : Timeout Occurred Callback.
- (+) ErrorCallback : Error Callback.
- (+) MspInitCallback : FDCAN MspInit.
- (+) MspDeInitCallback : FDCAN MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
- For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
- TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use
- dedicated register callbacks : respectively
- HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_RegisterRxFifo0Callback(),
- HAL_FDCAN_RegisterRxFifo1Callback(),
- HAL_FDCAN_RegisterTxBufferCompleteCallback(),
- HAL_FDCAN_RegisterTxBufferAbortCallback() and
- HAL_FDCAN_RegisterErrorStatusCallback().
-
- Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
- weak function.
- HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
- (+) HighPriorityMessageCallback : High Priority Message Callback.
- (+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
- (+) TimeoutOccurredCallback : Timeout Occurred Callback.
- (+) ErrorCallback : Error Callback.
- (+) MspInitCallback : FDCAN MspInit.
- (+) MspDeInitCallback : FDCAN MspDeInit.
-
- For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
- TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
- unregister callbacks : respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
- HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
- HAL_FDCAN_UnRegisterTxBufferCompleteCallback(),
- HAL_FDCAN_UnRegisterTxBufferAbortCallback() and
- HAL_FDCAN_UnRegisterErrorStatusCallback().
-
- By default, after the HAL_FDCAN_Init() and when the state is
- HAL_FDCAN_STATE_RESET, all callbacks are set to the corresponding weak
- functions: examples HAL_FDCAN_ErrorCallback(). Exception done for MspInit and
- MspDeInit functions that are reset to the legacy weak function in the
- HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when these callbacks are null (not
- registered beforehand). if not, MspInit or MspDeInit are not null, the
- HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() keep and use the user MspInit/MspDeInit
- callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the
- Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks
- using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
- or HAL_FDCAN_Init() function.
-
- When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all
- callbacks are set to the corresponding weak functions.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-#if defined(FDCAN1)
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FDCAN FDCAN
- * @brief FDCAN HAL module driver
- * @{
- */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FDCAN_Private_Constants
- * @{
- */
-#define FDCAN_TIMEOUT_VALUE 10U
-
-#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
-#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
-#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
-#define FDCAN_ERROR_MASK \
- (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
-#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
-
-#define FDCAN_ELEMENT_MASK_STDID \
- ((uint32_t)0x1FFC0000U) /* Standard Identifier */
-#define FDCAN_ELEMENT_MASK_EXTID \
- ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
-#define FDCAN_ELEMENT_MASK_RTR \
- ((uint32_t)0x20000000U) /* Remote Transmission Request */
-#define FDCAN_ELEMENT_MASK_XTD \
- ((uint32_t)0x40000000U) /* Extended Identifier */
-#define FDCAN_ELEMENT_MASK_ESI \
- ((uint32_t)0x80000000U) /* Error State Indicator */
-#define FDCAN_ELEMENT_MASK_TS \
- ((uint32_t)0x0000FFFFU) /* Timestamp */
-#define FDCAN_ELEMENT_MASK_DLC \
- ((uint32_t)0x000F0000U) /* Data Length Code */
-#define FDCAN_ELEMENT_MASK_BRS \
- ((uint32_t)0x00100000U) /* Bit Rate Switch */
-#define FDCAN_ELEMENT_MASK_FDF \
- ((uint32_t)0x00200000U) /* FD Format */
-#define FDCAN_ELEMENT_MASK_EFC \
- ((uint32_t)0x00800000U) /* Event FIFO Control */
-#define FDCAN_ELEMENT_MASK_MM \
- ((uint32_t)0xFF000000U) /* Message Marker */
-#define FDCAN_ELEMENT_MASK_FIDX \
- ((uint32_t)0x7F000000U) /* Filter Index */
-#define FDCAN_ELEMENT_MASK_ANMF \
- ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
-#define FDCAN_ELEMENT_MASK_ET \
- ((uint32_t)0x00C00000U) /* Event type */
-
-#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
-#define SRAMCAN_FLE_NBR (8U) /* Max. Filter List Extended Number */
-#define SRAMCAN_RF0_NBR (3U) /* RX FIFO 0 Elements Number */
-#define SRAMCAN_RF1_NBR (3U) /* RX FIFO 1 Elements Number */
-#define SRAMCAN_TEF_NBR (3U) /* TX Event FIFO Elements Number */
-#define SRAMCAN_TFQ_NBR (3U) /* TX FIFO/Queue Elements Number */
-
-#define SRAMCAN_FLS_SIZE (1U * 4U) /* Filter Standard Element Size in bytes */
-#define SRAMCAN_FLE_SIZE (2U * 4U) /* Filter Extended Element Size in bytes */
-#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
-#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
-#define SRAMCAN_TEF_SIZE (2U * 4U) /* TX Event FIFO Elements Size in bytes */
-#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
-
-#define SRAMCAN_FLSSA \
- ((uint32_t)0) /* Filter List Standard Start \
- Address */
-#define SRAMCAN_FLESA \
- ((uint32_t)(SRAMCAN_FLSSA + \
- (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended \
- Start Address */
-#define SRAMCAN_RF0SA \
- ((uint32_t)(SRAMCAN_FLESA + \
- (SRAMCAN_FLE_NBR * \
- SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
-#define SRAMCAN_RF1SA \
- ((uint32_t)(SRAMCAN_RF0SA + \
- (SRAMCAN_RF0_NBR * \
- SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
-#define SRAMCAN_TEFSA \
- ((uint32_t)(SRAMCAN_RF1SA + \
- (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start \
- Address */
-#define SRAMCAN_TFQSA \
- ((uint32_t)(SRAMCAN_TEFSA + \
- (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start \
- Address */
-#define SRAMCAN_SIZE \
- ((uint32_t)(SRAMCAN_TFQSA + \
- (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FDCAN_Private_Variables
- * @{
- */
-static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7,
- 8, 12, 16, 20, 24, 32, 48, 64};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan,
- FDCAN_TxHeaderTypeDef *pTxHeader,
- uint8_t *pTxData, uint32_t BufferIndex);
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
- * @{
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and
-de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the FDCAN.
- (+) De-initialize the FDCAN.
- (+) Enter FDCAN peripheral in power down mode.
- (+) Exit power down mode.
- (+) Register callbacks.
- (+) Unregister callbacks.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FDCAN peripheral according to the specified
- * parameters in the FDCAN_InitTypeDef structure.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t tickstart;
-
- /* Check FDCAN handle */
- if (hfdcan == NULL) {
- return HAL_ERROR;
- }
-
- /* Check function parameters */
- assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
- if (hfdcan->Instance == FDCAN1) {
- assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider));
- }
- assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
- assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
- assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
- assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
- assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
- assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
- assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
- assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
- assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
- if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) {
- assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
- assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
- assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
- assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
- }
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR));
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR));
- assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- hfdcan->Lock = HAL_UNLOCKED;
-
- /* Reset callbacks to legacy functions */
- hfdcan->TxEventFifoCallback =
- HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
- hfdcan->RxFifo0Callback =
- HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
- hfdcan->RxFifo1Callback =
- HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
- hfdcan->TxFifoEmptyCallback =
- HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
- hfdcan->TxBufferCompleteCallback =
- HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
- TxBufferCompleteCallback */
- hfdcan->TxBufferAbortCallback =
- HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
- TxBufferAbortCallback */
- hfdcan->HighPriorityMessageCallback =
- HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
- HighPriorityMessageCallback */
- hfdcan->TimestampWraparoundCallback =
- HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
- TimestampWraparoundCallback */
- hfdcan->TimeoutOccurredCallback =
- HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
- TimeoutOccurredCallback */
- hfdcan->ErrorCallback =
- HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
- hfdcan->ErrorStatusCallback =
- HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
-
- if (hfdcan->MspInitCallback == NULL) {
- hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */
- }
-
- /* Init the low level hardware: CLOCK, NVIC */
- hfdcan->MspInitCallback(hfdcan);
- }
-#else
- if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- hfdcan->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware: CLOCK, NVIC */
- HAL_FDCAN_MspInit(hfdcan);
- }
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-
- /* Exit from Sleep mode */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check Sleep mode acknowledge */
- while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) {
- if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Request initialisation */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the INIT bit into CCCR register is set */
- while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) {
- /* Check for the Timeout */
- if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable configuration change */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
-
- /* Check FDCAN instance */
- if (hfdcan->Instance == FDCAN1) {
- /* Configure Clock divider */
- FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
- }
-
- /* Set the no automatic retransmission */
- if (hfdcan->Init.AutoRetransmission == ENABLE) {
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
- } else {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
- }
-
- /* Set the transmit pause feature */
- if (hfdcan->Init.TransmitPause == ENABLE) {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
- } else {
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
- }
-
- /* Set the Protocol Exception Handling */
- if (hfdcan->Init.ProtocolException == ENABLE) {
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
- } else {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
- }
-
- /* Set FDCAN Frame Format */
- MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS,
- hfdcan->Init.FrameFormat);
-
- /* Reset FDCAN Operation Mode */
- CLEAR_BIT(hfdcan->Instance->CCCR,
- (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
- CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
-
- /* Set FDCAN Operating Mode:
- | Normal | Restricted | Bus | Internal | External
- | | Operation | Monitoring | LoopBack | LoopBack
- CCCR.TEST | 0 | 0 | 0 | 1 | 1
- CCCR.MON | 0 | 0 | 1 | 1 | 0
- TEST.LBCK | 0 | 0 | 0 | 1 | 1
- CCCR.ASM | 0 | 1 | 0 | 0 | 0
- */
- if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) {
- /* Enable Restricted Operation mode */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
- } else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) {
- if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) {
- /* Enable write access to TEST register */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
-
- /* Enable LoopBack mode */
- SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
-
- if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
- }
- } else {
- /* Enable bus monitoring mode */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
- }
- } else {
- /* Nothing to do: normal mode */
- }
-
- /* Set the nominal bit timing register */
- hfdcan->Instance->NBTP =
- ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U)
- << FDCAN_NBTP_NSJW_Pos) |
- (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U)
- << FDCAN_NBTP_NTSEG1_Pos) |
- (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U)
- << FDCAN_NBTP_NTSEG2_Pos) |
- (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
-
- /* If FD operation with BRS is selected, set the data bit timing register */
- if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) {
- hfdcan->Instance->DBTP =
- ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U)
- << FDCAN_DBTP_DSJW_Pos) |
- (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) |
- (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) |
- (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
- }
-
- /* Select between Tx FIFO and Tx Queue operation modes */
- SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
-
- /* Calculate each RAM block address */
- FDCAN_CalcultateRamBlockAddresses(hfdcan);
-
- /* Initialize the Latest Tx request buffer index */
- hfdcan->LatestTxFifoQRequest = 0U;
-
- /* Initialize the error code */
- hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
-
- /* Initialize the FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the FDCAN peripheral registers to their default reset
- * values.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan) {
- /* Check FDCAN handle */
- if (hfdcan == NULL) {
- return HAL_ERROR;
- }
-
- /* Check function parameters */
- assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
-
- /* Stop the FDCAN module: return value is voluntary ignored */
- (void)HAL_FDCAN_Stop(hfdcan);
-
- /* Disable Interrupt lines */
- CLEAR_BIT(hfdcan->Instance->ILE,
- (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- if (hfdcan->MspDeInitCallback == NULL) {
- hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware: CLOCK, NVIC */
- hfdcan->MspDeInitCallback(hfdcan);
-#else
- /* DeInit the low level hardware: CLOCK, NVIC */
- HAL_FDCAN_MspDeInit(hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-
- /* Reset the FDCAN ErrorCode */
- hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_RESET;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FDCAN MSP.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the FDCAN MSP.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Enter FDCAN peripheral in sleep mode.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t tickstart;
-
- /* Request clock stop */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FDCAN is ready for power down */
- while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U) {
- if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Exit power down mode.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t tickstart;
-
- /* Reset clock stop request */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FDCAN exits sleep mode */
- while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) {
- if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enter normal operation */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Return function status */
- return HAL_OK;
-}
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-/**
- * @brief Register a FDCAN CallBack.
- * To be used instead of the weak predefined callback
- * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
- * the configuration information for FDCAN module
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
- * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message
- * callback ID
- * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound
- * callback ID
- * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred
- * callback ID
- * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
- * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(
- FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
- void (*pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- switch (CallbackID) {
- case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID:
- hfdcan->TxFifoEmptyCallback = pCallback;
- break;
-
- case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID:
- hfdcan->HighPriorityMessageCallback = pCallback;
- break;
-
- case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID:
- hfdcan->TimestampWraparoundCallback = pCallback;
- break;
-
- case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID:
- hfdcan->TimeoutOccurredCallback = pCallback;
- break;
-
- case HAL_FDCAN_ERROR_CALLBACK_CB_ID:
- hfdcan->ErrorCallback = pCallback;
- break;
-
- case HAL_FDCAN_MSPINIT_CB_ID:
- hfdcan->MspInitCallback = pCallback;
- break;
-
- case HAL_FDCAN_MSPDEINIT_CB_ID:
- hfdcan->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
- switch (CallbackID) {
- case HAL_FDCAN_MSPINIT_CB_ID:
- hfdcan->MspInitCallback = pCallback;
- break;
-
- case HAL_FDCAN_MSPDEINIT_CB_ID:
- hfdcan->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Unregister a FDCAN CallBack.
- * FDCAN callback is redirected to the weak predefined callback
- * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
- * the configuration information for FDCAN module
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
- * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message
- * callback ID
- * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound
- * callback ID
- * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred
- * callback ID
- * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
- * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(
- FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- switch (CallbackID) {
- case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID:
- hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
- break;
-
- case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID:
- hfdcan->HighPriorityMessageCallback =
- HAL_FDCAN_HighPriorityMessageCallback;
- break;
-
- case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID:
- hfdcan->TimestampWraparoundCallback =
- HAL_FDCAN_TimestampWraparoundCallback;
- break;
-
- case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID:
- hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
- break;
-
- case HAL_FDCAN_ERROR_CALLBACK_CB_ID:
- hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
- break;
-
- case HAL_FDCAN_MSPINIT_CB_ID:
- hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
- break;
-
- case HAL_FDCAN_MSPDEINIT_CB_ID:
- hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
- break;
-
- default:
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
- switch (CallbackID) {
- case HAL_FDCAN_MSPINIT_CB_ID:
- hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
- break;
-
- case HAL_FDCAN_MSPDEINIT_CB_ID:
- hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
- break;
-
- default:
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Register Tx Event Fifo FDCAN Callback
- * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback()
- * predefined callback
- * @param hfdcan FDCAN handle
- * @param pCallback pointer to the Tx Event Fifo Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->TxEventFifoCallback = pCallback;
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief UnRegister the Tx Event Fifo FDCAN Callback
- * Tx Event Fifo FDCAN Callback is redirected to the weak
- * HAL_FDCAN_TxEventFifoCallback() predefined callback
- * @param hfdcan FDCAN handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->TxEventFifoCallback =
- HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Register Rx Fifo 0 FDCAN Callback
- * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined
- * callback
- * @param hfdcan FDCAN handle
- * @param pCallback pointer to the Rx Fifo 0 Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->RxFifo0Callback = pCallback;
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief UnRegister the Rx Fifo 0 FDCAN Callback
- * Rx Fifo 0 FDCAN Callback is redirected to the weak
- * HAL_FDCAN_RxFifo0Callback() predefined callback
- * @param hfdcan FDCAN handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->RxFifo0Callback =
- HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Register Rx Fifo 1 FDCAN Callback
- * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined
- * callback
- * @param hfdcan FDCAN handle
- * @param pCallback pointer to the Rx Fifo 1 Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->RxFifo1Callback = pCallback;
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief UnRegister the Rx Fifo 1 FDCAN Callback
- * Rx Fifo 1 FDCAN Callback is redirected to the weak
- * HAL_FDCAN_RxFifo1Callback() predefined callback
- * @param hfdcan FDCAN handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->RxFifo1Callback =
- HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Register Tx Buffer Complete FDCAN Callback
- * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback()
- * predefined callback
- * @param hfdcan FDCAN handle
- * @param pCallback pointer to the Tx Buffer Complete Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(
- FDCAN_HandleTypeDef *hfdcan,
- pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->TxBufferCompleteCallback = pCallback;
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief UnRegister the Tx Buffer Complete FDCAN Callback
- * Tx Buffer Complete FDCAN Callback is redirected to
- * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
- * @param hfdcan FDCAN handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->TxBufferCompleteCallback =
- HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
- TxBufferCompleteCallback */
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Register Tx Buffer Abort FDCAN Callback
- * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback()
- * predefined callback
- * @param hfdcan FDCAN handle
- * @param pCallback pointer to the Tx Buffer Abort Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(
- FDCAN_HandleTypeDef *hfdcan,
- pFDCAN_TxBufferAbortCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->TxBufferAbortCallback = pCallback;
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief UnRegister the Tx Buffer Abort FDCAN Callback
- * Tx Buffer Abort FDCAN Callback is redirected to
- * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
- * @param hfdcan FDCAN handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->TxBufferAbortCallback =
- HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Register Error Status FDCAN Callback
- * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback()
- * predefined callback
- * @param hfdcan FDCAN handle
- * @param pCallback pointer to the Error Status Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(
- FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->ErrorStatusCallback = pCallback;
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief UnRegister the Error Status FDCAN Callback
- * Error Status FDCAN Callback is redirected to the weak
- * HAL_FDCAN_ErrorStatusCallback() predefined callback
- * @param hfdcan FDCAN handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- hfdcan->ErrorStatusCallback =
- HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
- } else {
- /* Update the error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
- * @brief FDCAN Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Configuration functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN
-reception filters
- (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global
-filter
- (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID
-mask
- (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO
-operation mode
- (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog
- (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp
-counter
- (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp
-counter
- (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp
-counter
- (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter
-value
- (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp
-counter to zero
- (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout
-counter
- (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter
- (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout
-counter
- (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter
-value
- (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter
-to its start value
- (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter
-delay compensation
- (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter
-delay compensation
- (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter
-delay compensation
- (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol
-mode
- (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol
-mode
- (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during
-bus integration
- (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering
-during bus integration
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the FDCAN reception filter according to the specified
- * parameters in the FDCAN_FilterTypeDef structure.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
- * contains the filter configuration information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan,
- FDCAN_FilterTypeDef *sFilterConfig) {
- uint32_t FilterElementW1;
- uint32_t FilterElementW2;
- uint32_t *FilterAddress;
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
-
- if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
- /* Check function parameters */
- assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
- assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
-
- if (sFilterConfig->IdType == FDCAN_STANDARD_ID) {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex,
- (hfdcan->Init.StdFiltersNbr - 1U)));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
- assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
-
- /* Build filter element */
- FilterElementW1 =
- ((sFilterConfig->FilterType << 30U) |
- (sFilterConfig->FilterConfig << 27U) |
- (sFilterConfig->FilterID1 << 16U) | sFilterConfig->FilterID2);
-
- /* Calculate filter address */
- FilterAddress =
- (uint32_t *)(hfdcan->msgRam.StandardFilterSA +
- (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
-
- /* Write filter element to the message RAM */
- *FilterAddress = FilterElementW1;
- } else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
- {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex,
- (hfdcan->Init.ExtFiltersNbr - 1U)));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
- assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
-
- /* Build first word of filter element */
- FilterElementW1 =
- ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
-
- /* Build second word of filter element */
- FilterElementW2 =
- ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
-
- /* Calculate filter address */
- FilterAddress =
- (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA +
- (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
-
- /* Write filter element to the message RAM */
- *FilterAddress = FilterElementW1;
- FilterAddress++;
- *FilterAddress = FilterElementW2;
- }
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the FDCAN global filter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param NonMatchingStd Defines how received messages with 11-bit IDs that
- * do not match any element of the filter list are treated.
- * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
- * @param NonMatchingExt Defines how received messages with 29-bit IDs that
- * do not match any element of the filter list are treated.
- * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
- * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
- * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
- * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
- * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t NonMatchingStd,
- uint32_t NonMatchingExt,
- uint32_t RejectRemoteStd,
- uint32_t RejectRemoteExt) {
- /* Check function parameters */
- assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
- assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
- assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
- assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Configure global filter */
- MODIFY_REG(hfdcan->Instance->RXGFC,
- (FDCAN_RXGFC_ANFS | FDCAN_RXGFC_ANFE | FDCAN_RXGFC_RRFS |
- FDCAN_RXGFC_RRFE),
- ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) |
- (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
- (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
- (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the extended ID mask.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param Mask Extended ID Mask.
- This parameter must be a number between 0 and 0x1FFFFFFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan,
- uint32_t Mask) {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Configure the extended ID mask */
- hfdcan->Instance->XIDAM = Mask;
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the Rx FIFO operation mode.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo Rx FIFO.
- * This parameter can be one of the following values:
- * @arg FDCAN_RX_FIFO0: Rx FIFO 0
- * @arg FDCAN_RX_FIFO1: Rx FIFO 1
- * @param OperationMode operation mode.
- * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo,
- uint32_t OperationMode) {
- /* Check function parameters */
- assert_param(IS_FDCAN_RX_FIFO(RxFifo));
- assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- if (RxFifo == FDCAN_RX_FIFO0) {
- /* Select FIFO 0 Operation Mode */
- MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM,
- (OperationMode << FDCAN_RXGFC_F0OM_Pos));
- } else /* RxFifo == FDCAN_RX_FIFO1 */
- {
- /* Select FIFO 1 Operation Mode */
- MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM,
- (OperationMode << FDCAN_RXGFC_F1OM_Pos));
- }
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the RAM watchdog.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param CounterStartValue Start value of the Message RAM Watchdog Counter,
- * This parameter must be a number between 0x00 and 0xFF,
- * with the reset value of 0x00 the counter is disabled.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan,
- uint32_t CounterStartValue) {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Configure the RAM watchdog counter start value */
- MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the timestamp counter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimestampPrescaler Timestamp Counter Prescaler.
- * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(
- FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler) {
- /* Check function parameters */
- assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Configure prescaler */
- MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the timestamp counter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimestampOperation Timestamp counter operation.
- * This parameter can be a value of @arg FDCAN_Timestamp.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(
- FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation) {
- /* Check function parameters */
- assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Enable timestamp counter */
- MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the timestamp counter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(
- FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Disable timestamp counter */
- CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get the timestamp counter value.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Timestamp counter value
- */
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) {
- return (uint16_t)(hfdcan->Instance->TSCV);
-}
-
-/**
- * @brief Reset the timestamp counter to zero.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) {
- if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) {
- /* Reset timestamp counter.
- Actually any write operation to TSCV clears the counter */
- CLEAR_REG(hfdcan->Instance->TSCV);
- } else {
- /* Update error code.
- Unable to reset external counter */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the timeout counter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimeoutOperation Timeout counter operation.
- * This parameter can be a value of @arg FDCAN_Timeout_Operation.
- * @param TimeoutPeriod Start value of the timeout down-counter.
- * This parameter must be a number between 0x0000 and 0xFFFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TimeoutOperation,
- uint32_t TimeoutPeriod) {
- /* Check function parameters */
- assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
- assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Select timeout operation and configure period */
- MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP),
- (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the timeout counter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Enable timeout counter */
- SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the timeout counter.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Disable timeout counter */
- CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get the timeout counter value.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Timeout counter value
- */
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
- return (uint16_t)(hfdcan->Instance->TOCV);
-}
-
-/**
- * @brief Reset the timeout counter to its start value.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
- if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS) {
- /* Reset timeout counter to start value */
- CLEAR_REG(hfdcan->Instance->TOCV);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code.
- Unable to reset counter: controlled only by FIFO empty state */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the transmitter delay compensation.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TdcOffset Transmitter Delay Compensation Offset.
- * This parameter must be a number between 0x00 and 0x7F.
- * @param TdcFilter Transmitter Delay Compensation Filter Window Length.
- * This parameter must be a number between 0x00 and 0x7F.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(
- FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter) {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
- assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
-
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Configure TDC offset and filter window */
- hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) |
- (TdcOffset << FDCAN_TDCR_TDCO_Pos));
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the transmitter delay compensation.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(
- FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Enable transmitter delay compensation */
- SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the transmitter delay compensation.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(
- FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Disable transmitter delay compensation */
- CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable ISO 11898-1 protocol mode.
- * CAN FD frame format is according to ISO 11898-1 standard.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Disable Non ISO protocol mode */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable ISO 11898-1 protocol mode.
- * CAN FD frame format is according to Bosch CAN FD specification V1.0.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Enable Non ISO protocol mode */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable edge filtering during bus integration.
- * Two consecutive dominant tq are required to detect an edge for hard
- * synchronization.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Enable edge filtering */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable edge filtering during bus integration.
- * One dominant tq is required to detect an edge for hard
- * synchronization.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Disable edge filtering */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
-@verbatim
- ==============================================================================
- ##### Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_Start : Start the FDCAN module
- (+) HAL_FDCAN_Stop : Stop the FDCAN module and
-enable access to configuration registers
- (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx
-FIFO/Queue and activate the corresponding transmission request
- (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of
-latest Tx FIFO/Queue request
- (+) HAL_FDCAN_AbortTxRequest : Abort transmission request
- (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the
-Rx FIFO zone into the message RAM
- (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from
-the Tx Event FIFO zone into the message RAM
- (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message
-status
- (+) HAL_FDCAN_GetProtocolStatus : Get protocol status
- (+) HAL_FDCAN_GetErrorCounters : Get error counter values
- (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission
-request is pending on the selected Tx buffer
- (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
- (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
- (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN
-peripheral entered Restricted Operation Mode
- (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation
-Mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the FDCAN module.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) {
- if (hfdcan->State == HAL_FDCAN_STATE_READY) {
- /* Change FDCAN peripheral state */
- hfdcan->State = HAL_FDCAN_STATE_BUSY;
-
- /* Request leave initialisation */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Reset the FDCAN ErrorCode */
- hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Stop the FDCAN module and enable access to configuration registers.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t Counter = 0U;
-
- if (hfdcan->State == HAL_FDCAN_STATE_BUSY) {
- /* Request initialisation */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Wait until the INIT bit into CCCR register is set */
- while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) {
- /* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- /* Increment counter */
- Counter++;
- }
-
- /* Reset counter */
- Counter = 0U;
-
- /* Exit from Sleep mode */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Wait until FDCAN exits sleep mode */
- while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) {
- /* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- /* Increment counter */
- Counter++;
- }
-
- /* Enable configuration change */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
-
- /* Reset Latest Tx FIFO/Queue Request Buffer Index */
- hfdcan->LatestTxFifoQRequest = 0U;
-
- /* Change FDCAN peripheral state */
- hfdcan->State = HAL_FDCAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Add a message to the Tx FIFO/Queue and activate the corresponding
- * transmission request
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
- * @param pTxData pointer to a buffer containing the payload of the Tx frame.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
- uint8_t *pTxData) {
- uint32_t PutIndex;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
- if (pTxHeader->IdType == FDCAN_STANDARD_ID) {
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
- } else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
- {
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
- }
- assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
- assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
- assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
- assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
- assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
- assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
-
- if (hfdcan->State == HAL_FDCAN_STATE_BUSY) {
- /* Check that the Tx FIFO/Queue is not full */
- if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
-
- return HAL_ERROR;
- } else {
- /* Retrieve the Tx FIFO PutIndex */
- PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >>
- FDCAN_TXFQS_TFQPI_Pos);
-
- /* Add the message to the Tx FIFO/Queue */
- FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
-
- /* Activate the corresponding transmission request */
- hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
-
- /* Store the Latest Tx FIFO/Queue Request Buffer Index */
- hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
- }
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get Tx buffer index of latest Tx FIFO/Queue request
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Tx buffer index of last Tx FIFO/Queue request
- * - Any value of @arg FDCAN_Tx_location if Tx request has been
- * submitted.
- * - 0 if no Tx FIFO/Queue request have been submitted.
- */
-uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan) {
- /* Return Last Tx FIFO/Queue Request Buffer */
- return hfdcan->LatestTxFifoQRequest;
-}
-
-/**
- * @brief Abort transmission request
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndex buffer index.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndex) {
- /* Check function parameters */
- assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex));
-
- if (hfdcan->State == HAL_FDCAN_STATE_BUSY) {
- /* Add cancellation request */
- hfdcan->Instance->TXBCR = BufferIndex;
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get an FDCAN frame from the Rx FIFO zone into the message RAM.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxLocation Location of the received message to be read.
- * This parameter can be a value of @arg FDCAN_Rx_location.
- * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
- * @param pRxData pointer to a buffer where the payload of the Rx frame will be
- * stored.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxLocation,
- FDCAN_RxHeaderTypeDef *pRxHeader,
- uint8_t *pRxData) {
- uint32_t *RxAddress;
- uint8_t *pData;
- uint32_t ByteCounter;
- uint32_t GetIndex;
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_RX_FIFO(RxLocation));
-
- if (state == HAL_FDCAN_STATE_BUSY) {
- if (RxLocation ==
- FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
- {
- /* Check that the Rx FIFO 0 is not empty */
- if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
-
- return HAL_ERROR;
- } else {
- /* Calculate Rx FIFO 0 element address */
- GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >>
- FDCAN_RXF0S_F0GI_Pos);
- RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA +
- (GetIndex * SRAMCAN_RF0_SIZE));
- }
- } else /* Rx element is assigned to the Rx FIFO 1 */
- {
- /* Check that the Rx FIFO 1 is not empty */
- if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
-
- return HAL_ERROR;
- } else {
- /* Calculate Rx FIFO 1 element address */
- GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >>
- FDCAN_RXF1S_F1GI_Pos);
- RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA +
- (GetIndex * SRAMCAN_RF1_SIZE));
- }
- }
-
- /* Retrieve IdType */
- pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
-
- /* Retrieve Identifier */
- if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
- {
- pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
- } else /* Extended ID element */
- {
- pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
- }
-
- /* Retrieve RxFrameType */
- pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
-
- /* Retrieve ErrorStateIndicator */
- pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
-
- /* Increment RxAddress pointer to second word of Rx FIFO element */
- RxAddress++;
-
- /* Retrieve RxTimestamp */
- pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
-
- /* Retrieve DataLength */
- pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
-
- /* Retrieve BitRateSwitch */
- pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
-
- /* Retrieve FDFormat */
- pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
-
- /* Retrieve FilterIndex */
- pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
-
- /* Retrieve NonMatchingFrame */
- pRxHeader->IsFilterMatchingFrame =
- ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
-
- /* Increment RxAddress pointer to payload of Rx FIFO element */
- RxAddress++;
-
- /* Retrieve Rx payload */
- pData = (uint8_t *)RxAddress;
- for (ByteCounter = 0;
- ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U];
- ByteCounter++) {
- pRxData[ByteCounter] = pData[ByteCounter];
- }
-
- if (RxLocation ==
- FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
- {
- /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it
- * increments the GetIndex */
- hfdcan->Instance->RXF0A = GetIndex;
- } else /* Rx element is assigned to the Rx FIFO 1 */
- {
- /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it
- * increments the GetIndex */
- hfdcan->Instance->RXF1A = GetIndex;
- }
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message
- * RAM.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan,
- FDCAN_TxEventFifoTypeDef *pTxEvent) {
- uint32_t *TxEventAddress;
- uint32_t GetIndex;
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
-
- if (state == HAL_FDCAN_STATE_BUSY) {
- /* Check that the Tx event FIFO is not empty */
- if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U) {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
-
- return HAL_ERROR;
- }
-
- /* Calculate Tx event FIFO element address */
- GetIndex =
- ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
- TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA +
- (GetIndex * SRAMCAN_TEF_SIZE));
-
- /* Retrieve IdType */
- pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
-
- /* Retrieve Identifier */
- if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
- {
- pTxEvent->Identifier =
- ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
- } else /* Extended ID element */
- {
- pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
- }
-
- /* Retrieve TxFrameType */
- pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
-
- /* Retrieve ErrorStateIndicator */
- pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
-
- /* Increment TxEventAddress pointer to second word of Tx Event FIFO element
- */
- TxEventAddress++;
-
- /* Retrieve TxTimestamp */
- pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
-
- /* Retrieve DataLength */
- pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
-
- /* Retrieve BitRateSwitch */
- pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
-
- /* Retrieve FDFormat */
- pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
-
- /* Retrieve EventType */
- pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
-
- /* Retrieve MessageMarker */
- pTxEvent->MessageMarker =
- ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
-
- /* Acknowledge the Tx Event FIFO that the oldest element is read so that it
- * increments the GetIndex */
- hfdcan->Instance->TXEFA = GetIndex;
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get high priority message status.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) {
- HpMsgStatus->FilterList =
- ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
- HpMsgStatus->FilterIndex =
- ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
- HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
- HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Get protocol status.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus) {
- uint32_t StatusReg;
-
- /* Read the protocol status register */
- StatusReg = READ_REG(hfdcan->Instance->PSR);
-
- /* Fill the protocol status structure */
- ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
- ProtocolStatus->DataLastErrorCode =
- ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
- ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
- ProtocolStatus->ErrorPassive =
- ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
- ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
- ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
- ProtocolStatus->RxESIflag =
- ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
- ProtocolStatus->RxBRSflag =
- ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
- ProtocolStatus->RxFDFflag =
- ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
- ProtocolStatus->ProtocolException =
- ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
- ProtocolStatus->TDCvalue =
- ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Get error counter values.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(
- FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters) {
- uint32_t CountersReg;
-
- /* Read the error counters register */
- CountersReg = READ_REG(hfdcan->Instance->ECR);
-
- /* Fill the error counters structure */
- ErrorCounters->TxErrorCnt =
- ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
- ErrorCounters->RxErrorCnt =
- ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
- ErrorCounters->RxErrorPassive =
- ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
- ErrorCounters->ErrorLogging =
- ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Check if a transmission request is pending on the selected Tx buffer.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TxBufferIndex Tx buffer index.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval Status
- * - 0 : No pending transmission request on TxBufferIndex list
- * - 1 : Pending transmission request on TxBufferIndex.
- */
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TxBufferIndex) {
- /* Check function parameters */
- assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
-
- /* Check pending transmission request on the selected buffer */
- if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) {
- return 0;
- }
- return 1;
-}
-
-/**
- * @brief Return Rx FIFO fill level.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo Rx FIFO.
- * This parameter can be one of the following values:
- * @arg FDCAN_RX_FIFO0: Rx FIFO 0
- * @arg FDCAN_RX_FIFO1: Rx FIFO 1
- * @retval Rx FIFO fill level.
- */
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo) {
- uint32_t FillLevel;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_RX_FIFO(RxFifo));
-
- if (RxFifo == FDCAN_RX_FIFO0) {
- FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
- } else /* RxFifo == FDCAN_RX_FIFO1 */
- {
- FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
- }
-
- /* Return Rx FIFO fill level */
- return FillLevel;
-}
-
-/**
- * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO
- * elements starting from Tx FIFO GetIndex.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Tx FIFO free level.
- */
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t FreeLevel;
-
- FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
-
- /* Return Tx FIFO free level */
- return FreeLevel;
-}
-
-/**
- * @brief Check if the FDCAN peripheral entered Restricted Operation Mode.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Status
- * - 0 : Normal FDCAN operation.
- * - 1 : Restricted Operation Mode active.
- */
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t OperationMode;
-
- /* Get Operation Mode */
- OperationMode =
- ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
-
- return OperationMode;
-}
-
-/**
- * @brief Exit Restricted Operation Mode.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(
- FDCAN_HandleTypeDef *hfdcan) {
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
-
- if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
- /* Exit Restricted Operation mode */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- *
-@verbatim
- ==============================================================================
- ##### Interrupts management #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either
-Interrupt line 0 or 1
- (+) HAL_FDCAN_ActivateNotification : Enable interrupts
- (+) HAL_FDCAN_DeactivateNotification : Disable interrupts
- (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Assign interrupts to either Interrupt line 0 or 1.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ITList indicates which interrupts group will be assigned to the
- * selected interrupt line. This parameter can be any combination of @arg
- * FDCAN_Interrupts_Group.
- * @param InterruptLine Interrupt line.
- * This parameter can be a value of @arg FDCAN_Interrupt_Line.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan,
- uint32_t ITList,
- uint32_t InterruptLine) {
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_IT_GROUP(ITList));
- assert_param(IS_FDCAN_IT_LINE(InterruptLine));
-
- if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
- /* Assign list of interrupts to the selected line */
- if (InterruptLine == FDCAN_INTERRUPT_LINE0) {
- CLEAR_BIT(hfdcan->Instance->ILS, ITList);
- } else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
- {
- SET_BIT(hfdcan->Instance->ILS, ITList);
- }
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable interrupts.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ActiveITs indicates which interrupts will be enabled.
- * This parameter can be any combination of @arg FDCAN_Interrupts.
- * @param BufferIndexes Tx Buffer Indexes.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * This parameter is ignored if ActiveITs does not include one of the
- * following:
- * - FDCAN_IT_TX_COMPLETE
- * - FDCAN_IT_TX_ABORT_COMPLETE
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan,
- uint32_t ActiveITs,
- uint32_t BufferIndexes) {
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
- uint32_t ITs_lines_selection;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_IT(ActiveITs));
- if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U) {
- assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
- }
-
- if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
- /* Get interrupts line selection */
- ITs_lines_selection = hfdcan->Instance->ILS;
-
- /* Enable Interrupt lines */
- if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) == 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) == 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) == 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) == 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) {
- /* Enable Interrupt line 0 */
- SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
- }
- if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) != 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) != 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) != 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) != 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) ||
- (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) {
- /* Enable Interrupt line 1 */
- SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
- }
-
- if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) {
- /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
- but interrupt will only occur if TC is enabled in IE register */
- SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
- }
-
- if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) {
- /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR
- register, but interrupt will only occur if TCF is enabled in IE
- register */
- SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
- }
-
- /* Enable the selected interrupts */
- __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable interrupts.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param InactiveITs indicates which interrupts will be disabled.
- * This parameter can be any combination of @arg FDCAN_Interrupts.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan,
- uint32_t InactiveITs) {
- HAL_FDCAN_StateTypeDef state = hfdcan->State;
- uint32_t ITs_enabled;
- uint32_t ITs_lines_selection;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_IT(InactiveITs));
-
- if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
- /* Disable the selected interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
-
- if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U) {
- /* Disable Tx Buffer Transmission Interrupts */
- CLEAR_REG(hfdcan->Instance->TXBTIE);
- }
-
- if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) {
- /* Disable Tx Buffer Cancellation Finished Interrupt */
- CLEAR_REG(hfdcan->Instance->TXBCIE);
- }
-
- /* Get interrupts enabled and interrupts line selection */
- ITs_enabled = hfdcan->Instance->IE;
- ITs_lines_selection = hfdcan->Instance->ILS;
-
- /* Check if some interrupts are still enabled on interrupt line 0 */
- if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) == 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) == 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) == 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) == 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) {
- /* Do nothing */
- } else /* no more interrupts enabled on interrupt line 0 */
- {
- /* Disable interrupt line 0 */
- CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
- }
-
- /* Check if some interrupts are still enabled on interrupt line 1 */
- if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) != 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) != 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) != 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) != 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) ||
- (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
- (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) {
- /* Do nothing */
- } else /* no more interrupts enabled on interrupt line 1 */
- {
- /* Disable interrupt line 1 */
- CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
- }
-
- /* Return function status */
- return HAL_OK;
- } else {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handles FDCAN interrupt request.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t TxEventFifoITs;
- uint32_t RxFifo0ITs;
- uint32_t RxFifo1ITs;
- uint32_t Errors;
- uint32_t ErrorStatusITs;
- uint32_t TransmittedBuffers;
- uint32_t AbortedBuffers;
-
- TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
- TxEventFifoITs &= hfdcan->Instance->IE;
- RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
- RxFifo0ITs &= hfdcan->Instance->IE;
- RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
- RxFifo1ITs &= hfdcan->Instance->IE;
- Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
- Errors &= hfdcan->Instance->IE;
- ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
- ErrorStatusITs &= hfdcan->Instance->IE;
-
- /* High Priority Message interrupt management *******************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) !=
- 0U) {
- /* Clear the High Priority Message flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->HighPriorityMessageCallback(hfdcan);
-#else
- /* High Priority Message Callback */
- HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
- }
-
- /* Transmission Abort interrupt management **********************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U) {
- /* List of aborted monitored buffers */
- AbortedBuffers = hfdcan->Instance->TXBCF;
- AbortedBuffers &= hfdcan->Instance->TXBCIE;
-
- /* Clear the Transmission Cancellation flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
-#else
- /* Transmission Cancellation Callback */
- HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
- }
-
- /* Tx event FIFO interrupts management **************************************/
- if (TxEventFifoITs != 0U) {
- /* Clear the Tx Event FIFO flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
-#else
- /* Tx Event FIFO Callback */
- HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
-
- /* Rx FIFO 0 interrupts management ******************************************/
- if (RxFifo0ITs != 0U) {
- /* Clear the Rx FIFO 0 flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
-#else
- /* Rx FIFO 0 Callback */
- HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
-
- /* Rx FIFO 1 interrupts management ******************************************/
- if (RxFifo1ITs != 0U) {
- /* Clear the Rx FIFO 1 flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
-#else
- /* Rx FIFO 1 Callback */
- HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
-
- /* Tx FIFO empty interrupt management ***************************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U) {
- /* Clear the Tx FIFO empty flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->TxFifoEmptyCallback(hfdcan);
-#else
- /* Tx FIFO empty Callback */
- HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
- }
-
- /* Transmission Complete interrupt management *******************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U) {
- /* List of transmitted monitored buffers */
- TransmittedBuffers = hfdcan->Instance->TXBTO;
- TransmittedBuffers &= hfdcan->Instance->TXBTIE;
-
- /* Clear the Transmission Complete flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
-#else
- /* Transmission Complete Callback */
- HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
- }
-
- /* Timestamp Wraparound interrupt management ********************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) !=
- 0U) {
- /* Clear the Timestamp Wraparound flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->TimestampWraparoundCallback(hfdcan);
-#else
- /* Timestamp Wraparound Callback */
- HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
- }
-
- /* Timeout Occurred interrupt management ************************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U) {
- /* Clear the Timeout Occurred flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->TimeoutOccurredCallback(hfdcan);
-#else
- /* Timeout Occurred Callback */
- HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
- }
-
- /* Message RAM access failure interrupt management **************************/
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U) {
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U) {
- /* Clear the Message RAM access failure flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
-
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
- }
- }
-
- /* Error Status interrupts management ***************************************/
- if (ErrorStatusITs != 0U) {
- /* Clear the Error flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
-
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
-#else
- /* Error Status Callback */
- HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
-
- /* Error interrupts management **********************************************/
- if (Errors != 0U) {
- /* Clear the Error flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
-
- /* Update error code */
- hfdcan->ErrorCode |= Errors;
- }
-
- if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) {
-#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->ErrorCallback(hfdcan);
-#else
- /* Error Callback */
- HAL_FDCAN_ErrorCallback(hfdcan);
-#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
- * @brief FDCAN Callback functions
- *
-@verbatim
- ==============================================================================
- ##### Callback functions #####
- ==============================================================================
- [..]
- This subsection provides the following callback functions:
- (+) HAL_FDCAN_TxEventFifoCallback
- (+) HAL_FDCAN_RxFifo0Callback
- (+) HAL_FDCAN_RxFifo1Callback
- (+) HAL_FDCAN_TxFifoEmptyCallback
- (+) HAL_FDCAN_TxBufferCompleteCallback
- (+) HAL_FDCAN_TxBufferAbortCallback
- (+) HAL_FDCAN_HighPriorityMessageCallback
- (+) HAL_FDCAN_TimestampWraparoundCallback
- (+) HAL_FDCAN_TimeoutOccurredCallback
- (+) HAL_FDCAN_ErrorCallback
- (+) HAL_FDCAN_ErrorStatusCallback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Tx Event callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are
- * signalled. This parameter can be any combination of @arg
- * FDCAN_Tx_Event_Fifo_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t TxEventFifoITs) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(TxEventFifoITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxEventFifoCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Rx FIFO 0 callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled.
- * This parameter can be any combination of @arg
- * FDCAN_Rx_Fifo0_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo0ITs) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(RxFifo0ITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx FIFO 1 callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
- * This parameter can be any combination of @arg
- * FDCAN_Rx_Fifo1_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t RxFifo1ITs) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(RxFifo1ITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx FIFO Empty callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Transmission Complete callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndexes Indexes of the transmitted buffers.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval None
- */
-__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(BufferIndexes);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief Transmission Cancellation callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndexes Indexes of the aborted buffers.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval None
- */
-__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t BufferIndexes) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(BufferIndexes);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Timestamp Wraparound callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TimestampWraparoundCallback could be implemented in
- the user file
- */
-}
-
-/**
- * @brief Timeout Occurred callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief High Priority Message callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_HighPriorityMessageCallback could be implemented in
- the user file
- */
-}
-
-/**
- * @brief Error callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Error status callback.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ErrorStatusITs indicates which Error Status interrupts are signaled.
- * This parameter can be any combination of @arg
- * FDCAN_Error_Status_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
- uint32_t ErrorStatusITs) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(ErrorStatusITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_ErrorStatusCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
- * @brief FDCAN Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) HAL_FDCAN_GetState() : Return the FDCAN state.
- (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Return the FDCAN state
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL state
- */
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) {
- /* Return FDCAN state */
- return hfdcan->State;
-}
-
-/**
- * @brief Return the FDCAN error code
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval FDCAN Error Code
- */
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan) {
- /* Return FDCAN error code */
- return hfdcan->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
- * @{
- */
-
-/**
- * @brief Calculate each RAM block start address and size
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval none
- */
-static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) {
- uint32_t RAMcounter;
- uint32_t SramCanInstanceBase = SRAMCAN_BASE;
-#if defined(FDCAN2)
-
- if (hfdcan->Instance == FDCAN2) {
- SramCanInstanceBase += SRAMCAN_SIZE;
- }
-#endif /* FDCAN2 */
-#if defined(FDCAN3)
- if (hfdcan->Instance == FDCAN3) {
- SramCanInstanceBase += SRAMCAN_SIZE * 2U;
- }
-#endif /* FDCAN3 */
-
- /* Standard filter list start address */
- hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
-
- /* Standard filter elements number */
- MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS,
- (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
-
- /* Extended filter list start address */
- hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
-
- /* Extended filter elements number */
- MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE,
- (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
-
- /* Rx FIFO 0 start address */
- hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
-
- /* Rx FIFO 1 start address */
- hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
-
- /* Tx event FIFO start address */
- hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
-
- /* Tx FIFO/queue start address */
- hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
-
- /* Flush the allocated Message RAM area */
- for (RAMcounter = SramCanInstanceBase;
- RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U) {
- *(uint32_t *)(RAMcounter) = 0x00000000U;
- }
-}
-
-/**
- * @brief Copy Tx message to the message RAM.
- * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
- * @param pTxData pointer to a buffer containing the payload of the Tx frame.
- * @param BufferIndex index of the buffer to be configured.
- * @retval none
- */
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan,
- FDCAN_TxHeaderTypeDef *pTxHeader,
- uint8_t *pTxData, uint32_t BufferIndex) {
- uint32_t TxElementW1;
- uint32_t TxElementW2;
- uint32_t *TxAddress;
- uint32_t ByteCounter;
-
- /* Build first word of Tx header element */
- if (pTxHeader->IdType == FDCAN_STANDARD_ID) {
- TxElementW1 = (pTxHeader->ErrorStateIndicator | FDCAN_STANDARD_ID |
- pTxHeader->TxFrameType | (pTxHeader->Identifier << 18U));
- } else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
- {
- TxElementW1 = (pTxHeader->ErrorStateIndicator | FDCAN_EXTENDED_ID |
- pTxHeader->TxFrameType | pTxHeader->Identifier);
- }
-
- /* Build second word of Tx header element */
- TxElementW2 =
- ((pTxHeader->MessageMarker << 24U) | pTxHeader->TxEventFifoControl |
- pTxHeader->FDFormat | pTxHeader->BitRateSwitch | pTxHeader->DataLength);
-
- /* Calculate Tx element address */
- TxAddress =
- (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
-
- /* Write Tx element header to the message RAM */
- *TxAddress = TxElementW1;
- TxAddress++;
- *TxAddress = TxElementW2;
- TxAddress++;
-
- /* Write Tx payload to the message RAM */
- for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U];
- ByteCounter += 4U) {
- *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
- ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
- ((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
- (uint32_t)pTxData[ByteCounter]);
- TxAddress++;
- }
-}
-
-/**
- * @}
- */
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* FDCAN1 */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_fdcan.c
+ * @author MCD Application Team
+ * @brief FDCAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible DataRate Controller Area Network
+ * (FDCAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Configuration and Control functions
+ * + Peripheral State and Error functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+ (#) If needed , configure the reception filters and optional features
+ using the following configuration functions:
+ (++) HAL_FDCAN_ConfigFilter
+ (++) HAL_FDCAN_ConfigGlobalFilter
+ (++) HAL_FDCAN_ConfigExtendedIdMask
+ (++) HAL_FDCAN_ConfigRxFifoOverwrite
+ (++) HAL_FDCAN_ConfigRamWatchdog
+ (++) HAL_FDCAN_ConfigTimestampCounter
+ (++) HAL_FDCAN_EnableTimestampCounter
+ (++) HAL_FDCAN_DisableTimestampCounter
+ (++) HAL_FDCAN_ConfigTimeoutCounter
+ (++) HAL_FDCAN_EnableTimeoutCounter
+ (++) HAL_FDCAN_DisableTimeoutCounter
+ (++) HAL_FDCAN_ConfigTxDelayCompensation
+ (++) HAL_FDCAN_EnableTxDelayCompensation
+ (++) HAL_FDCAN_DisableTxDelayCompensation
+ (++) HAL_FDCAN_EnableISOMode
+ (++) HAL_FDCAN_DisableISOMode
+ (++) HAL_FDCAN_EnableEdgeFiltering
+ (++) HAL_FDCAN_DisableEdgeFiltering
+
+ (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+ the node is active on the bus: it can send and receive messages.
+
+ (#) The following Tx control functions can only be called when the FDCAN
+ module is started:
+ (++) HAL_FDCAN_AddMessageToTxFifoQ
+ (++) HAL_FDCAN_AbortTxRequest
+
+ (#) After having submitted a Tx request in Tx Fifo or Queue, it is
+ possible to get Tx buffer location used to place the Tx request thanks to
+ HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+ It is then possible to abort later on the corresponding Tx Request
+ using HAL_FDCAN_AbortTxRequest API.
+
+ (#) When a message is received into the FDCAN message RAM, it can be
+ retrieved using the HAL_FDCAN_GetRxMessage function.
+
+ (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+ it to initialization mode and re-enabling access to configuration
+ registers through the configuration functions listed here above.
+
+ (#) All other control functions can be called any time after
+ initialization phase, no matter if the FDCAN module is started or stopped.
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception and transmission states can be monitored via the following
+ functions:
+ (++) HAL_FDCAN_IsTxBufferMessagePending
+ (++) HAL_FDCAN_GetRxFifoFillLevel
+ (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) There are two interrupt lines: line 0 and 1.
+ By default, all interrupts are assigned to line 0. Interrupt lines
+ can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+ (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+ function. Then, the process can be controlled through one of the
+ available user callbacks: HAL_FDCAN_xxxCallback.
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) HighPriorityMessageCallback : High Priority Message Callback.
+ (+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
+ (+) TimeoutOccurredCallback : Timeout Occurred Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : FDCAN MspInit.
+ (+) MspDeInitCallback : FDCAN MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+ TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use
+ dedicated register callbacks: respectively
+ HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_RegisterRxFifo0Callback(),
+ HAL_FDCAN_RegisterRxFifo1Callback(),
+ HAL_FDCAN_RegisterTxBufferCompleteCallback(),
+ HAL_FDCAN_RegisterTxBufferAbortCallback() and
+ HAL_FDCAN_RegisterErrorStatusCallback().
+
+ Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) HighPriorityMessageCallback : High Priority Message Callback.
+ (+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
+ (+) TimeoutOccurredCallback : Timeout Occurred Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : FDCAN MspInit.
+ (+) MspDeInitCallback : FDCAN MspDeInit.
+
+ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+ TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
+ unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
+ HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
+ HAL_FDCAN_UnRegisterTxBufferCompleteCallback(),
+ HAL_FDCAN_UnRegisterTxBufferAbortCallback() and
+ HAL_FDCAN_UnRegisterErrorStatusCallback().
+
+ By default, after the HAL_FDCAN_Init() and when the state is
+ HAL_FDCAN_STATE_RESET, all callbacks are set to the corresponding weak
+ functions: examples HAL_FDCAN_ErrorCallback(). Exception done for MspInit and
+ MspDeInit functions that are reset to the legacy weak function in the
+ HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when these callbacks are null (not
+ registered beforehand). if not, MspInit or MspDeInit are not null, the
+ HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() keep and use the user MspInit/MspDeInit
+ callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the
+ Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
+ or HAL_FDCAN_Init() function.
+
+ When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all
+ callbacks are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FDCAN FDCAN
+ * @brief FDCAN HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+ * @{
+ */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK \
+ (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+
+#define FDCAN_ELEMENT_MASK_STDID \
+ ((uint32_t)0x1FFC0000U) /* Standard Identifier */
+#define FDCAN_ELEMENT_MASK_EXTID \
+ ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
+#define FDCAN_ELEMENT_MASK_RTR \
+ ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD \
+ ((uint32_t)0x40000000U) /* Extended Identifier */
+#define FDCAN_ELEMENT_MASK_ESI \
+ ((uint32_t)0x80000000U) /* Error State Indicator */
+#define FDCAN_ELEMENT_MASK_TS \
+ ((uint32_t)0x0000FFFFU) /* Timestamp */
+#define FDCAN_ELEMENT_MASK_DLC \
+ ((uint32_t)0x000F0000U) /* Data Length Code */
+#define FDCAN_ELEMENT_MASK_BRS \
+ ((uint32_t)0x00100000U) /* Bit Rate Switch */
+#define FDCAN_ELEMENT_MASK_FDF \
+ ((uint32_t)0x00200000U) /* FD Format */
+#define FDCAN_ELEMENT_MASK_EFC \
+ ((uint32_t)0x00800000U) /* Event FIFO Control */
+#define FDCAN_ELEMENT_MASK_MM \
+ ((uint32_t)0xFF000000U) /* Message Marker */
+#define FDCAN_ELEMENT_MASK_FIDX \
+ ((uint32_t)0x7F000000U) /* Filter Index */
+#define FDCAN_ELEMENT_MASK_ANMF \
+ ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET \
+ ((uint32_t)0x00C00000U) /* Event type */
+
+#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
+#define SRAMCAN_FLE_NBR (8U) /* Max. Filter List Extended Number */
+#define SRAMCAN_RF0_NBR (3U) /* RX FIFO 0 Elements Number */
+#define SRAMCAN_RF1_NBR (3U) /* RX FIFO 1 Elements Number */
+#define SRAMCAN_TEF_NBR (3U) /* TX Event FIFO Elements Number */
+#define SRAMCAN_TFQ_NBR (3U) /* TX FIFO/Queue Elements Number */
+
+#define SRAMCAN_FLS_SIZE (1U * 4U) /* Filter Standard Element Size in bytes */
+#define SRAMCAN_FLE_SIZE (2U * 4U) /* Filter Extended Element Size in bytes */
+#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
+#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
+#define SRAMCAN_TEF_SIZE (2U * 4U) /* TX Event FIFO Elements Size in bytes */
+#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
+
+#define SRAMCAN_FLSSA \
+ ((uint32_t)0) /* Filter List Standard Start \
+ Address */
+#define SRAMCAN_FLESA \
+ ((uint32_t)(SRAMCAN_FLSSA + \
+ (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended \
+ Start Address */
+#define SRAMCAN_RF0SA \
+ ((uint32_t)(SRAMCAN_FLESA + \
+ (SRAMCAN_FLE_NBR * \
+ SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
+#define SRAMCAN_RF1SA \
+ ((uint32_t)(SRAMCAN_RF0SA + \
+ (SRAMCAN_RF0_NBR * \
+ SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
+#define SRAMCAN_TEFSA \
+ ((uint32_t)(SRAMCAN_RF1SA + \
+ (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start \
+ Address */
+#define SRAMCAN_TFQSA \
+ ((uint32_t)(SRAMCAN_TEFSA + \
+ (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start \
+ Address */
+#define SRAMCAN_SIZE \
+ ((uint32_t)(SRAMCAN_TFQSA + \
+ (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Variables
+ * @{
+ */
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 12, 16, 20, 24, 32, 48, 64};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+ * @{
+ */
+static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan,
+ const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData,
+ uint32_t BufferIndex);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+ * @{
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and
+de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the FDCAN.
+ (+) De-initialize the FDCAN.
+ (+) Enter FDCAN peripheral in power down mode.
+ (+) Exit power down mode.
+ (+) Register callbacks.
+ (+) Unregister callbacks.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FDCAN peripheral according to the specified
+ * parameters in the FDCAN_InitTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t tickstart;
+
+ /* Check FDCAN handle */
+ if (hfdcan == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+ if (hfdcan->Instance == FDCAN1) {
+ assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider));
+ }
+ assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+ assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+ assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+ assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+ assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+ assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) {
+ assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+ assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+ assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+ assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+ }
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR));
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR));
+ assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ hfdcan->Lock = HAL_UNLOCKED;
+
+ /* Reset callbacks to legacy functions */
+ hfdcan->TxEventFifoCallback =
+ HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */
+ hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */
+ hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */
+ hfdcan->TxFifoEmptyCallback =
+ HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */
+ hfdcan->TxBufferCompleteCallback =
+ HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */
+ hfdcan->TxBufferAbortCallback =
+ HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */
+ hfdcan->HighPriorityMessageCallback =
+ HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */
+ hfdcan->TimestampWraparoundCallback =
+ HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */
+ hfdcan->TimeoutOccurredCallback =
+ HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */
+ hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */
+ hfdcan->ErrorStatusCallback =
+ HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */
+
+ if (hfdcan->MspInitCallback == NULL) {
+ hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ hfdcan->MspInitCallback(hfdcan);
+ }
+#else
+ if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ hfdcan->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ HAL_FDCAN_MspInit(hfdcan);
+ }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+ /* Exit from Sleep mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check Sleep mode acknowledge */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Request initialisation */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the INIT bit into CCCR register is set */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable configuration change */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+ /* Check FDCAN instance */
+ if (hfdcan->Instance == FDCAN1) {
+ /* Configure Clock divider */
+ FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
+ }
+
+ /* Set the no automatic retransmission */
+ if (hfdcan->Init.AutoRetransmission == ENABLE) {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ } else {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ }
+
+ /* Set the transmit pause feature */
+ if (hfdcan->Init.TransmitPause == ENABLE) {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ } else {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ }
+
+ /* Set the Protocol Exception Handling */
+ if (hfdcan->Init.ProtocolException == ENABLE) {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ } else {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ }
+
+ /* Set FDCAN Frame Format */
+ MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS,
+ hfdcan->Init.FrameFormat);
+
+ /* Reset FDCAN Operation Mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR,
+ (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+ CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+ /* Set FDCAN Operating Mode:
+ | Normal | Restricted | Bus | Internal | External
+ | | Operation | Monitoring | LoopBack | LoopBack
+ CCCR.TEST | 0 | 0 | 0 | 1 | 1
+ CCCR.MON | 0 | 0 | 1 | 1 | 0
+ TEST.LBCK | 0 | 0 | 0 | 1 | 1
+ CCCR.ASM | 0 | 1 | 0 | 0 | 0
+ */
+ if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) {
+ /* Enable Restricted Operation mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+ } else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) {
+ if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) {
+ /* Enable write access to TEST register */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+ /* Enable LoopBack mode */
+ SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+ if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ }
+ } else {
+ /* Enable bus monitoring mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ }
+ } else {
+ /* Nothing to do: normal mode */
+ }
+
+ /* Set the nominal bit timing register */
+ hfdcan->Instance->NBTP =
+ ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U)
+ << FDCAN_NBTP_NSJW_Pos) |
+ (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U)
+ << FDCAN_NBTP_NTSEG1_Pos) |
+ (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U)
+ << FDCAN_NBTP_NTSEG2_Pos) |
+ (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+ /* If FD operation with BRS is selected, set the data bit timing register */
+ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) {
+ hfdcan->Instance->DBTP =
+ ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U)
+ << FDCAN_DBTP_DSJW_Pos) |
+ (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) |
+ (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) |
+ (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+ }
+
+ /* Select between Tx FIFO and Tx Queue operation modes */
+ SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+
+ /* Calculate each RAM block address */
+ FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+ /* Initialize the Latest Tx request buffer index */
+ hfdcan->LatestTxFifoQRequest = 0U;
+
+ /* Initialize the error code */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Initialize the FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the FDCAN peripheral registers to their default reset
+ * values.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan) {
+ /* Check FDCAN handle */
+ if (hfdcan == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+ /* Stop the FDCAN module: return value is voluntary ignored */
+ (void)HAL_FDCAN_Stop(hfdcan);
+
+ /* Disable Interrupt lines */
+ CLEAR_BIT(hfdcan->Instance->ILE,
+ (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ if (hfdcan->MspDeInitCallback == NULL) {
+ hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ hfdcan->MspDeInitCallback(hfdcan);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+ /* Reset the FDCAN ErrorCode */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FDCAN MSP.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the FDCAN MSP.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Enter FDCAN peripheral in sleep mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t tickstart;
+
+ /* Request clock stop */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FDCAN is ready for power down */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U) {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit power down mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t tickstart;
+
+ /* Reset clock stop request */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FDCAN exits sleep mode */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enter normal operation */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a FDCAN CallBack.
+ * To be used instead of the weak predefined callback
+ * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+ * the configuration information for FDCAN module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+ * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message
+ * callback ID
+ * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound
+ * callback ID
+ * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred
+ * callback ID
+ * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(
+ FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+ void (*pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID:
+ hfdcan->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID:
+ hfdcan->HighPriorityMessageCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID:
+ hfdcan->TimestampWraparoundCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID:
+ hfdcan->TimeoutOccurredCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_ERROR_CALLBACK_CB_ID:
+ hfdcan->ErrorCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_MSPINIT_CB_ID:
+ hfdcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID:
+ hfdcan->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_FDCAN_MSPINIT_CB_ID:
+ hfdcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID:
+ hfdcan->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a FDCAN CallBack.
+ * FDCAN callback is redirected to the weak predefined callback
+ * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+ * the configuration information for FDCAN module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+ * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message
+ * callback ID
+ * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound
+ * callback ID
+ * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred
+ * callback ID
+ * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(
+ FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID:
+ hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+ break;
+
+ case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID:
+ hfdcan->HighPriorityMessageCallback =
+ HAL_FDCAN_HighPriorityMessageCallback;
+ break;
+
+ case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID:
+ hfdcan->TimestampWraparoundCallback =
+ HAL_FDCAN_TimestampWraparoundCallback;
+ break;
+
+ case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID:
+ hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+ break;
+
+ case HAL_FDCAN_ERROR_CALLBACK_CB_ID:
+ hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+ break;
+
+ case HAL_FDCAN_MSPINIT_CB_ID:
+ hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID:
+ hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+ break;
+
+ default:
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (hfdcan->State == HAL_FDCAN_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_FDCAN_MSPINIT_CB_ID:
+ hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+ break;
+
+ case HAL_FDCAN_MSPDEINIT_CB_ID:
+ hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+ break;
+
+ default:
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Tx Event Fifo FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback()
+ * predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Tx Event Fifo Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->TxEventFifoCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Tx Event Fifo FDCAN Callback
+ * Tx Event Fifo FDCAN Callback is redirected to the weak
+ * HAL_FDCAN_TxEventFifoCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->TxEventFifoCallback =
+ HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Rx Fifo 0 FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined
+ * callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Rx Fifo 0 Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->RxFifo0Callback = pCallback;
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Rx Fifo 0 FDCAN Callback
+ * Rx Fifo 0 FDCAN Callback is redirected to the weak
+ * HAL_FDCAN_RxFifo0Callback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->RxFifo0Callback =
+ HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Rx Fifo 1 FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined
+ * callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Rx Fifo 1 Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->RxFifo1Callback = pCallback;
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Rx Fifo 1 FDCAN Callback
+ * Rx Fifo 1 FDCAN Callback is redirected to the weak
+ * HAL_FDCAN_RxFifo1Callback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->RxFifo1Callback =
+ HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Tx Buffer Complete FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback()
+ * predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Tx Buffer Complete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(
+ FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->TxBufferCompleteCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Tx Buffer Complete FDCAN Callback
+ * Tx Buffer Complete FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->TxBufferCompleteCallback =
+ HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
+ TxBufferCompleteCallback */
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Tx Buffer Abort FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback()
+ * predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Tx Buffer Abort Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(
+ FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferAbortCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->TxBufferAbortCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Tx Buffer Abort FDCAN Callback
+ * Tx Buffer Abort FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->TxBufferAbortCallback =
+ HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register Error Status FDCAN Callback
+ * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback()
+ * predefined callback
+ * @param hfdcan FDCAN handle
+ * @param pCallback pointer to the Error Status Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(
+ FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->ErrorStatusCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the Error Status FDCAN Callback
+ * Error Status FDCAN Callback is redirected to the weak
+ * HAL_FDCAN_ErrorStatusCallback() predefined callback
+ * @param hfdcan FDCAN handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ hfdcan->ErrorStatusCallback =
+ HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
+ } else {
+ /* Update the error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ * @brief FDCAN Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN
+reception filters
+ (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global
+filter
+ (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID
+mask
+ (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO
+operation mode
+ (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog
+ (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp
+counter
+ (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp
+counter
+ (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp
+counter
+ (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter
+value
+ (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp
+counter to zero
+ (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout
+counter
+ (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter
+ (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout
+counter
+ (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter
+value
+ (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter
+to its start value
+ (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter
+delay compensation
+ (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter
+delay compensation
+ (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter
+delay compensation
+ (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol
+mode
+ (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol
+mode
+ (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during
+bus integration
+ (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering
+during bus integration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the FDCAN reception filter according to the specified
+ * parameters in the FDCAN_FilterTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+ * contains the filter configuration information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(
+ FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) {
+ uint32_t FilterElementW1;
+ uint32_t FilterElementW2;
+ uint32_t *FilterAddress;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+ assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+
+ if (sFilterConfig->IdType == FDCAN_STANDARD_ID) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U),
+ hfdcan->Init.StdFiltersNbr));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+ assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+
+ /* Build filter element */
+ FilterElementW1 =
+ ((sFilterConfig->FilterType << 30U) |
+ (sFilterConfig->FilterConfig << 27U) |
+ (sFilterConfig->FilterID1 << 16U) | sFilterConfig->FilterID2);
+
+ /* Calculate filter address */
+ FilterAddress =
+ (uint32_t *)(hfdcan->msgRam.StandardFilterSA +
+ (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
+
+ /* Write filter element to the message RAM */
+ *FilterAddress = FilterElementW1;
+ } else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U),
+ hfdcan->Init.ExtFiltersNbr));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+ assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+
+ /* Build first word of filter element */
+ FilterElementW1 =
+ ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+ /* Build second word of filter element */
+ FilterElementW2 =
+ ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+
+ /* Calculate filter address */
+ FilterAddress =
+ (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA +
+ (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
+
+ /* Write filter element to the message RAM */
+ *FilterAddress = FilterElementW1;
+ FilterAddress++;
+ *FilterAddress = FilterElementW2;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the FDCAN global filter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param NonMatchingStd Defines how received messages with 11-bit IDs that
+ * do not match any element of the filter list are treated.
+ * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+ * @param NonMatchingExt Defines how received messages with 29-bit IDs that
+ * do not match any element of the filter list are treated.
+ * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+ * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+ * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+ * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+ * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t NonMatchingStd,
+ uint32_t NonMatchingExt,
+ uint32_t RejectRemoteStd,
+ uint32_t RejectRemoteExt) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+ assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+ assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+ assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Configure global filter */
+ MODIFY_REG(hfdcan->Instance->RXGFC,
+ (FDCAN_RXGFC_ANFS | FDCAN_RXGFC_ANFE | FDCAN_RXGFC_RRFS |
+ FDCAN_RXGFC_RRFE),
+ ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) |
+ (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
+ (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
+ (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the extended ID mask.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param Mask Extended ID Mask.
+ * This parameter must be a number between 0 and 0x1FFFFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t Mask) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Configure the extended ID mask */
+ hfdcan->Instance->XIDAM = Mask;
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the Rx FIFO operation mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be one of the following values:
+ * @arg FDCAN_RX_FIFO0: Rx FIFO 0
+ * @arg FDCAN_RX_FIFO1: Rx FIFO 1
+ * @param OperationMode operation mode.
+ * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo,
+ uint32_t OperationMode) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+ assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ if (RxFifo == FDCAN_RX_FIFO0) {
+ /* Select FIFO 0 Operation Mode */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM,
+ (OperationMode << FDCAN_RXGFC_F0OM_Pos));
+ } else /* RxFifo == FDCAN_RX_FIFO1 */
+ {
+ /* Select FIFO 1 Operation Mode */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM,
+ (OperationMode << FDCAN_RXGFC_F1OM_Pos));
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the RAM watchdog.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param CounterStartValue Start value of the Message RAM Watchdog Counter,
+ * This parameter must be a number between 0x00 and 0xFF,
+ * with the reset value of 0x00 the counter is disabled.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t CounterStartValue) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Configure the RAM watchdog counter start value */
+ MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimestampPrescaler Timestamp Counter Prescaler.
+ * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(
+ FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Configure prescaler */
+ MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimestampOperation Timestamp counter operation.
+ * This parameter can be a value of @arg FDCAN_Timestamp.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(
+ FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Enable timestamp counter */
+ MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(
+ FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Disable timestamp counter */
+ CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the timestamp counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Timestamp counter value
+ */
+uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) {
+ return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+ * @brief Reset the timestamp counter to zero.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) {
+ if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) {
+ /* Reset timestamp counter.
+ Actually any write operation to TSCV clears the counter */
+ CLEAR_REG(hfdcan->Instance->TSCV);
+ } else {
+ /* Update error code.
+ Unable to reset external counter */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimeoutOperation Timeout counter operation.
+ * This parameter can be a value of @arg FDCAN_Timeout_Operation.
+ * @param TimeoutPeriod Start value of the timeout down-counter.
+ * This parameter must be a number between 0x0000 and 0xFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TimeoutOperation,
+ uint32_t TimeoutPeriod) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+ assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Select timeout operation and configure period */
+ MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP),
+ (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Enable timeout counter */
+ SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Disable timeout counter */
+ CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the timeout counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Timeout counter value
+ */
+uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) {
+ return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+ * @brief Reset the timeout counter to its start value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) {
+ if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS) {
+ /* Reset timeout counter to start value */
+ CLEAR_REG(hfdcan->Instance->TOCV);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code.
+ Unable to reset counter: controlled only by FIFO empty state */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TdcOffset Transmitter Delay Compensation Offset.
+ * This parameter must be a number between 0x00 and 0x7F.
+ * @param TdcFilter Transmitter Delay Compensation Filter Window Length.
+ * This parameter must be a number between 0x00 and 0x7F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(
+ FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+ assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Configure TDC offset and filter window */
+ hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) |
+ (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(
+ FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Enable transmitter delay compensation */
+ SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(
+ FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Disable transmitter delay compensation */
+ CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable ISO 11898-1 protocol mode.
+ * CAN FD frame format is according to ISO 11898-1 standard.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Disable Non ISO protocol mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable ISO 11898-1 protocol mode.
+ * CAN FD frame format is according to Bosch CAN FD specification V1.0.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Enable Non ISO protocol mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable edge filtering during bus integration.
+ * Two consecutive dominant tq are required to detect an edge for hard
+ * synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Enable edge filtering */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable edge filtering during bus integration.
+ * One dominant tq is required to detect an edge for hard
+ * synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Disable edge filtering */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_Start : Start the FDCAN module
+ (+) HAL_FDCAN_Stop : Stop the FDCAN module and
+enable access to configuration registers
+ (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx
+FIFO/Queue and activate the corresponding transmission request
+ (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of
+latest Tx FIFO/Queue request
+ (+) HAL_FDCAN_AbortTxRequest : Abort transmission request
+ (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the
+Rx FIFO zone into the message RAM
+ (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from
+the Tx Event FIFO zone into the message RAM
+ (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message
+status
+ (+) HAL_FDCAN_GetProtocolStatus : Get protocol status
+ (+) HAL_FDCAN_GetErrorCounters : Get error counter values
+ (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission
+request is pending on the selected Tx buffer
+ (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+ (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
+ (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN
+peripheral entered Restricted Operation Mode
+ (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation
+Mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the FDCAN module.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) {
+ if (hfdcan->State == HAL_FDCAN_STATE_READY) {
+ /* Change FDCAN peripheral state */
+ hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Reset the FDCAN ErrorCode */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the FDCAN module and enable access to configuration registers.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t Counter = 0U;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY) {
+ /* Request initialisation */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Wait until the INIT bit into CCCR register is set */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Reset counter */
+ Counter = 0U;
+
+ /* Exit from Sleep mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Wait until FDCAN exits sleep mode */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable configuration change */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+ /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+ hfdcan->LatestTxFifoQRequest = 0U;
+
+ /* Change FDCAN peripheral state */
+ hfdcan->State = HAL_FDCAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Add a message to the Tx FIFO/Queue and activate the corresponding
+ * transmission request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(
+ FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData) {
+ uint32_t PutIndex;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID) {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+ } else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+ }
+ assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+ assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+ assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+ assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+ assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+ assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY) {
+ /* Check that the Tx FIFO/Queue is not full */
+ if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+ return HAL_ERROR;
+ } else {
+ /* Retrieve the Tx FIFO PutIndex */
+ PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >>
+ FDCAN_TXFQS_TFQPI_Pos);
+
+ /* Add the message to the Tx FIFO/Queue */
+ FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+ /* Activate the corresponding transmission request */
+ hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+ /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+ hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get Tx buffer index of latest Tx FIFO/Queue request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Tx buffer index of last Tx FIFO/Queue request
+ * - Any value of @arg FDCAN_Tx_location if Tx request has been
+ * submitted.
+ * - 0 if no Tx FIFO/Queue request have been submitted.
+ */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(
+ const FDCAN_HandleTypeDef *hfdcan) {
+ /* Return Last Tx FIFO/Queue Request Buffer */
+ return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+ * @brief Abort transmission request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndex buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndex) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY) {
+ /* Add cancellation request */
+ hfdcan->Instance->TXBCR = BufferIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get an FDCAN frame from the Rx FIFO zone into the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxLocation Location of the received message to be read.
+ * This parameter can be a value of @arg FDCAN_Rx_location.
+ * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+ * @param pRxData pointer to a buffer where the payload of the Rx frame will be
+ * stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxLocation,
+ FDCAN_RxHeaderTypeDef *pRxHeader,
+ uint8_t *pRxData) {
+ uint32_t *RxAddress;
+ uint8_t *pData;
+ uint32_t ByteCounter;
+ uint32_t GetIndex = 0;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxLocation));
+
+ if (state == HAL_FDCAN_STATE_BUSY) {
+ if (RxLocation ==
+ FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ } else {
+ /* Check that the Rx FIFO 0 is full & overwrite mode is on */
+ if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >>
+ FDCAN_RXF0S_F0F_Pos) == 1U) {
+ if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >>
+ FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) {
+ /* When overwrite status is on discard first message in FIFO */
+ GetIndex = 1U;
+ }
+ }
+
+ /* Calculate Rx FIFO 0 element index */
+ GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >>
+ FDCAN_RXF0S_F0GI_Pos);
+
+ /* Calculate Rx FIFO 0 element address */
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA +
+ (GetIndex * SRAMCAN_RF0_SIZE));
+ }
+ } else /* Rx element is assigned to the Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ } else {
+ /* Check that the Rx FIFO 1 is full & overwrite mode is on */
+ if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >>
+ FDCAN_RXF1S_F1F_Pos) == 1U) {
+ if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >>
+ FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) {
+ /* When overwrite status is on discard first message in FIFO */
+ GetIndex = 1U;
+ }
+ }
+
+ /* Calculate Rx FIFO 1 element index */
+ GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >>
+ FDCAN_RXF1S_F1GI_Pos);
+ /* Calculate Rx FIFO 1 element address */
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA +
+ (GetIndex * SRAMCAN_RF1_SIZE));
+ }
+ }
+
+ /* Retrieve IdType */
+ pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+ /* Retrieve Identifier */
+ if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ {
+ pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+ } else /* Extended ID element */
+ {
+ pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+ }
+
+ /* Retrieve RxFrameType */
+ pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+ /* Retrieve ErrorStateIndicator */
+ pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+ /* Increment RxAddress pointer to second word of Rx FIFO element */
+ RxAddress++;
+
+ /* Retrieve RxTimestamp */
+ pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+ /* Retrieve DataLength */
+ pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
+
+ /* Retrieve BitRateSwitch */
+ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+ /* Retrieve FDFormat */
+ pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+ /* Retrieve FilterIndex */
+ pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
+
+ /* Retrieve NonMatchingFrame */
+ pRxHeader->IsFilterMatchingFrame =
+ ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
+
+ /* Increment RxAddress pointer to payload of Rx FIFO element */
+ RxAddress++;
+
+ /* Retrieve Rx payload */
+ pData = (uint8_t *)RxAddress;
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength];
+ ByteCounter++) {
+ pRxData[ByteCounter] = pData[ByteCounter];
+ }
+
+ if (RxLocation ==
+ FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ {
+ /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it
+ * increments the GetIndex */
+ hfdcan->Instance->RXF0A = GetIndex;
+ } else /* Rx element is assigned to the Rx FIFO 1 */
+ {
+ /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it
+ * increments the GetIndex */
+ hfdcan->Instance->RXF1A = GetIndex;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message
+ * RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_TxEventFifoTypeDef *pTxEvent) {
+ uint32_t *TxEventAddress;
+ uint32_t GetIndex;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if (state == HAL_FDCAN_STATE_BUSY) {
+ /* Check that the Tx event FIFO is not empty */
+ if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U) {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Calculate Tx event FIFO element address */
+ GetIndex =
+ ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+ TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA +
+ (GetIndex * SRAMCAN_TEF_SIZE));
+
+ /* Retrieve IdType */
+ pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+ /* Retrieve Identifier */
+ if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ {
+ pTxEvent->Identifier =
+ ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+ } else /* Extended ID element */
+ {
+ pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+ }
+
+ /* Retrieve TxFrameType */
+ pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+ /* Retrieve ErrorStateIndicator */
+ pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+ /* Increment TxEventAddress pointer to second word of Tx Event FIFO element
+ */
+ TxEventAddress++;
+
+ /* Retrieve TxTimestamp */
+ pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+ /* Retrieve DataLength */
+ pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
+
+ /* Retrieve BitRateSwitch */
+ pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+ /* Retrieve FDFormat */
+ pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+ /* Retrieve EventType */
+ pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+ /* Retrieve MessageMarker */
+ pTxEvent->MessageMarker =
+ ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
+
+ /* Acknowledge the Tx Event FIFO that the oldest element is read so that it
+ * increments the GetIndex */
+ hfdcan->Instance->TXEFA = GetIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get high priority message status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(
+ const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) {
+ HpMsgStatus->FilterList =
+ ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+ HpMsgStatus->FilterIndex =
+ ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+ HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+ HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get protocol status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(
+ const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ProtocolStatusTypeDef *ProtocolStatus) {
+ uint32_t StatusReg;
+
+ /* Read the protocol status register */
+ StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+ /* Fill the protocol status structure */
+ ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+ ProtocolStatus->DataLastErrorCode =
+ ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+ ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+ ProtocolStatus->ErrorPassive =
+ ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+ ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+ ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+ ProtocolStatus->RxESIflag =
+ ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+ ProtocolStatus->RxBRSflag =
+ ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+ ProtocolStatus->RxFDFflag =
+ ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+ ProtocolStatus->ProtocolException =
+ ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+ ProtocolStatus->TDCvalue =
+ ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get error counter values.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(
+ const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ErrorCountersTypeDef *ErrorCounters) {
+ uint32_t CountersReg;
+
+ /* Read the error counters register */
+ CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+ /* Fill the error counters structure */
+ ErrorCounters->TxErrorCnt =
+ ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+ ErrorCounters->RxErrorCnt =
+ ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+ ErrorCounters->RxErrorPassive =
+ ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+ ErrorCounters->ErrorLogging =
+ ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx buffer.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TxBufferIndex Tx buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval Status
+ * - 0 : No pending transmission request on TxBufferIndex list.
+ * - 1 : Pending transmission request on TxBufferIndex.
+ */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TxBufferIndex) {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
+
+ /* Check pending transmission request on the selected buffer */
+ if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) {
+ return 0;
+ }
+ return 1;
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be one of the following values:
+ * @arg FDCAN_RX_FIFO0: Rx FIFO 0
+ * @arg FDCAN_RX_FIFO1: Rx FIFO 1
+ * @retval Rx FIFO fill level.
+ */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo) {
+ uint32_t FillLevel;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+ if (RxFifo == FDCAN_RX_FIFO0) {
+ FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+ } else /* RxFifo == FDCAN_RX_FIFO1 */
+ {
+ FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+ }
+
+ /* Return Rx FIFO fill level */
+ return FillLevel;
+}
+
+/**
+ * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO
+ * elements starting from Tx FIFO GetIndex.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Tx FIFO free level.
+ */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t FreeLevel;
+
+ FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+ /* Return Tx FIFO free level */
+ return FreeLevel;
+}
+
+/**
+ * @brief Check if the FDCAN peripheral entered Restricted Operation Mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Status
+ * - 0 : Normal FDCAN operation.
+ * - 1 : Restricted Operation Mode active.
+ */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(
+ const FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t OperationMode;
+
+ /* Get Operation Mode */
+ OperationMode =
+ ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+ return OperationMode;
+}
+
+/**
+ * @brief Exit Restricted Operation Mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(
+ FDCAN_HandleTypeDef *hfdcan) {
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
+ /* Exit Restricted Operation mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either
+Interrupt line 0 or 1
+ (+) HAL_FDCAN_ActivateNotification : Enable interrupts
+ (+) HAL_FDCAN_DeactivateNotification : Disable interrupts
+ (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Assign interrupts to either Interrupt line 0 or 1.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ITList indicates which interrupts group will be assigned to the
+ * selected interrupt line. This parameter can be any combination of @arg
+ * FDCAN_Interrupts_Group.
+ * @param InterruptLine Interrupt line.
+ * This parameter can be a value of @arg FDCAN_Interrupt_Line.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ITList,
+ uint32_t InterruptLine) {
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT_GROUP(ITList));
+ assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
+ /* Assign list of interrupts to the selected line */
+ if (InterruptLine == FDCAN_INTERRUPT_LINE0) {
+ CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+ } else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+ {
+ SET_BIT(hfdcan->Instance->ILS, ITList);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @param BufferIndexes Tx Buffer Indexes.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * This parameter is ignored if ActiveITs does not include one of the
+ * following:
+ * - FDCAN_IT_TX_COMPLETE
+ * - FDCAN_IT_TX_ABORT_COMPLETE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ActiveITs,
+ uint32_t BufferIndexes) {
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+ uint32_t ITs_lines_selection;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(ActiveITs));
+ if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U) {
+ assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
+ }
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
+ /* Get interrupts line selection */
+ ITs_lines_selection = hfdcan->Instance->ILS;
+
+ /* Enable Interrupt lines */
+ if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) == 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) == 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) == 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) == 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) {
+ /* Enable Interrupt line 0 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+ if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) != 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) != 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) != 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) != 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) ||
+ (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) {
+ /* Enable Interrupt line 1 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+
+ if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) {
+ /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+ but interrupt will only occur if TC is enabled in IE register */
+ SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+ }
+
+ if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) {
+ /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR
+ register, but interrupt will only occur if TCF is enabled in IE
+ register */
+ SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+ }
+
+ /* Enable the selected interrupts */
+ __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t InactiveITs) {
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+ uint32_t ITs_enabled;
+ uint32_t ITs_lines_selection;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(InactiveITs));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) {
+ /* Disable the selected interrupts */
+ __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+ if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U) {
+ /* Disable Tx Buffer Transmission Interrupts */
+ CLEAR_REG(hfdcan->Instance->TXBTIE);
+ }
+
+ if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) {
+ /* Disable Tx Buffer Cancellation Finished Interrupt */
+ CLEAR_REG(hfdcan->Instance->TXBCIE);
+ }
+
+ /* Get interrupts enabled and interrupts line selection */
+ ITs_enabled = hfdcan->Instance->IE;
+ ITs_lines_selection = hfdcan->Instance->ILS;
+
+ /* Check if some interrupts are still enabled on interrupt line 0 */
+ if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) == 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) == 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) == 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) == 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) {
+ /* Do nothing */
+ } else /* no more interrupts enabled on interrupt line 0 */
+ {
+ /* Disable interrupt line 0 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+
+ /* Check if some interrupts are still enabled on interrupt line 1 */
+ if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO0) != 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_RX_FIFO1) != 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_SMSG) != 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_MISC) != 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) ||
+ (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) &&
+ (((ITs_lines_selection)&FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) {
+ /* Do nothing */
+ } else /* no more interrupts enabled on interrupt line 1 */
+ {
+ /* Disable interrupt line 1 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ } else {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles FDCAN interrupt request.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t TxEventFifoITs;
+ uint32_t RxFifo0ITs;
+ uint32_t RxFifo1ITs;
+ uint32_t Errors;
+ uint32_t ErrorStatusITs;
+ uint32_t TransmittedBuffers;
+ uint32_t AbortedBuffers;
+ uint32_t itsource;
+ uint32_t itflag;
+
+ TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+ TxEventFifoITs &= hfdcan->Instance->IE;
+ RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+ RxFifo0ITs &= hfdcan->Instance->IE;
+ RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+ RxFifo1ITs &= hfdcan->Instance->IE;
+ Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+ Errors &= hfdcan->Instance->IE;
+ ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+ ErrorStatusITs &= hfdcan->Instance->IE;
+ itsource = hfdcan->Instance->IE;
+ itflag = hfdcan->Instance->IR;
+
+ /* High Priority Message interrupt management *******************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) !=
+ RESET) {
+ /* Clear the High Priority Message flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+ /* High Priority Message Callback */
+ HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Transmission Abort interrupt management **********************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) {
+ /* List of aborted monitored buffers */
+ AbortedBuffers = hfdcan->Instance->TXBCF;
+ AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+ /* Clear the Transmission Cancellation flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+ /* Transmission Cancellation Callback */
+ HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Tx event FIFO interrupts management **************************************/
+ if (TxEventFifoITs != 0U) {
+ /* Clear the Tx Event FIFO flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+ /* Tx Event FIFO Callback */
+ HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Rx FIFO 0 interrupts management ******************************************/
+ if (RxFifo0ITs != 0U) {
+ /* Clear the Rx FIFO 0 flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+ /* Rx FIFO 0 Callback */
+ HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Rx FIFO 1 interrupts management ******************************************/
+ if (RxFifo1ITs != 0U) {
+ /* Clear the Rx FIFO 1 flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+ /* Rx FIFO 1 Callback */
+ HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Tx FIFO empty interrupt management ***************************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET) {
+ /* Clear the Tx FIFO empty flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+ /* Tx FIFO empty Callback */
+ HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Transmission Complete interrupt management *******************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET) {
+ /* List of transmitted monitored buffers */
+ TransmittedBuffers = hfdcan->Instance->TXBTO;
+ TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+ /* Clear the Transmission Complete flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+ /* Transmission Complete Callback */
+ HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Timestamp Wraparound interrupt management ********************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) !=
+ RESET) {
+ /* Clear the Timestamp Wraparound flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+ /* Timestamp Wraparound Callback */
+ HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Timeout Occurred interrupt management ************************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) {
+ /* Clear the Timeout Occurred flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+ /* Timeout Occurred Callback */
+ HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Message RAM access failure interrupt management **************************/
+ if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) {
+ if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) {
+ /* Clear the Message RAM access failure flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+ }
+ }
+
+ /* Error Status interrupts management ***************************************/
+ if (ErrorStatusITs != 0U) {
+ /* Clear the Error flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+ /* Error Status Callback */
+ HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+
+ /* Error interrupts management **********************************************/
+ if (Errors != 0U) {
+ /* Clear the Error flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= Errors;
+ }
+
+ if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hfdcan->ErrorCallback(hfdcan);
+#else
+ /* Error Callback */
+ HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
+ * @brief FDCAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_FDCAN_TxEventFifoCallback
+ (+) HAL_FDCAN_RxFifo0Callback
+ (+) HAL_FDCAN_RxFifo1Callback
+ (+) HAL_FDCAN_TxFifoEmptyCallback
+ (+) HAL_FDCAN_TxBufferCompleteCallback
+ (+) HAL_FDCAN_TxBufferAbortCallback
+ (+) HAL_FDCAN_HighPriorityMessageCallback
+ (+) HAL_FDCAN_TimestampWraparoundCallback
+ (+) HAL_FDCAN_TimeoutOccurredCallback
+ (+) HAL_FDCAN_ErrorCallback
+ (+) HAL_FDCAN_ErrorStatusCallback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Tx Event callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+ * This parameter can be any combination of @arg
+ * FDCAN_Tx_Event_Fifo_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TxEventFifoITs) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(TxEventFifoITs);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxEventFifoCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+ * This parameter can be any combination of @arg
+ * FDCAN_Rx_Fifo0_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo0ITs) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(RxFifo0ITs);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+ * This parameter can be any combination of @arg
+ * FDCAN_Rx_Fifo1_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t RxFifo1ITs) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(RxFifo1ITs);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx FIFO Empty callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Transmission Complete callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndexes Indexes of the transmitted buffers.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(BufferIndexes);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Cancellation callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndexes Indexes of the aborted buffers.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t BufferIndexes) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(BufferIndexes);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Timestamp Wraparound callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TimestampWraparoundCallback could be implemented in
+ the user file
+ */
+}
+
+/**
+ * @brief Timeout Occurred callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief High Priority Message callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_HighPriorityMessageCallback could be implemented in
+ the user file
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error status callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ErrorStatusITs indicates which Error Status interrupts are signaled.
+ * This parameter can be any combination of @arg
+ * FDCAN_Error_Status_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t ErrorStatusITs) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(ErrorStatusITs);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ErrorStatusCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
+ * @brief FDCAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) HAL_FDCAN_GetState() : Return the FDCAN state.
+ (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the FDCAN state
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL state
+ */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) {
+ /* Return FDCAN state */
+ return hfdcan->State;
+}
+
+/**
+ * @brief Return the FDCAN error code
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval FDCAN Error Code
+ */
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) {
+ /* Return FDCAN error code */
+ return hfdcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate each RAM block start address and size
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval none
+ */
+static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) {
+ uint32_t RAMcounter;
+ uint32_t SramCanInstanceBase = SRAMCAN_BASE;
+#if defined(FDCAN2)
+
+ if (hfdcan->Instance == FDCAN2) {
+ SramCanInstanceBase += SRAMCAN_SIZE;
+ }
+#endif /* FDCAN2 */
+#if defined(FDCAN3)
+ if (hfdcan->Instance == FDCAN3) {
+ SramCanInstanceBase += SRAMCAN_SIZE * 2U;
+ }
+#endif /* FDCAN3 */
+
+ /* Standard filter list start address */
+ hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
+
+ /* Standard filter elements number */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS,
+ (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
+
+ /* Extended filter list start address */
+ hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
+
+ /* Extended filter elements number */
+ MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE,
+ (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
+
+ /* Rx FIFO 0 start address */
+ hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
+
+ /* Rx FIFO 1 start address */
+ hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
+
+ /* Tx event FIFO start address */
+ hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
+
+ /* Tx FIFO/queue start address */
+ hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
+
+ /* Flush the allocated Message RAM area */
+ for (RAMcounter = SramCanInstanceBase;
+ RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U) {
+ *(uint32_t *)(RAMcounter) = 0x00000000U;
+ }
+}
+
+/**
+ * @brief Copy Tx message to the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @param BufferIndex index of the buffer to be configured.
+ * @retval none
+ */
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan,
+ const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData,
+ uint32_t BufferIndex) {
+ uint32_t TxElementW1;
+ uint32_t TxElementW2;
+ uint32_t *TxAddress;
+ uint32_t ByteCounter;
+
+ /* Build first word of Tx header element */
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID) {
+ TxElementW1 = (pTxHeader->ErrorStateIndicator | FDCAN_STANDARD_ID |
+ pTxHeader->TxFrameType | (pTxHeader->Identifier << 18U));
+ } else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ TxElementW1 = (pTxHeader->ErrorStateIndicator | FDCAN_EXTENDED_ID |
+ pTxHeader->TxFrameType | pTxHeader->Identifier);
+ }
+
+ /* Build second word of Tx header element */
+ TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
+ pTxHeader->TxEventFifoControl | pTxHeader->FDFormat |
+ pTxHeader->BitRateSwitch | (pTxHeader->DataLength << 16U));
+
+ /* Calculate Tx element address */
+ TxAddress =
+ (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
+
+ /* Write Tx element header to the message RAM */
+ *TxAddress = TxElementW1;
+ TxAddress++;
+ *TxAddress = TxElementW2;
+ TxAddress++;
+
+ /* Write Tx payload to the message RAM */
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength];
+ ByteCounter += 4U) {
+ *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+ ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+ ((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
+ (uint32_t)pTxData[ByteCounter]);
+ TxAddress++;
+ }
+}
+
+/**
+ * @}
+ */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FDCAN1 */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c
index c0ada6a..14bfc00 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c
@@ -1,716 +1,738 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_flash.c
- * @author MCD Application Team
- * @brief FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the internal FLASH memory:
- * + Program operations functions
- * + Memory Control functions
- * + Peripheral Errors functions
- *
- @verbatim
- ==============================================================================
- ##### FLASH peripheral features #####
- ==============================================================================
-
- [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
- to the Flash memory. It implements the erase and program Flash memory
- operations and the read and write protection mechanisms.
-
- [..] The Flash memory interface accelerates code execution with a system of
- instruction prefetch and cache lines.
-
- [..] The FLASH main features are:
- (+) Flash memory read operations
- (+) Flash memory program/erase operations
- (+) Read / write protections
- (+) Option bytes programming
- (+) Prefetch on I-Code
- (+) 32 cache lines of 4*64 or 2*128 bits on I-Code
- (+) 8 cache lines of 4*64 or 2*128 bits on D-Code
- (+) Error code correction (ECC) : Data in flash are 72-bits word
- (8 bits added per double word)
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions and macros to configure and program the
- FLASH memory of all STM32G4xx devices.
-
- (#) Flash Memory IO Programming functions:
- (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
- HAL_FLASH_Lock() functions
- (++) Program functions: double word and fast program (full row
- programming)
- (++) There are two modes of programming :
- (+++) Polling mode using HAL_FLASH_Program() function
- (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-
- (#) Interrupts and flags management functions:
- (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
- (++) Callback functions are called when the flash operations are
- finished : HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
- HAL_FLASH_OperationErrorCallback()
- (++) Get error flag status by calling HAL_GetError()
-
- (#) Option bytes management functions:
- (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
- HAL_FLASH_OB_Lock() functions
- (++) Launch the reload of the option bytes using HAL_FLASH_Launch()
- function. In this case, a reset is generated
-
- [..]
- In addition to these functions, this driver includes a set of macros
- allowing to handle the following operations:
- (+) Set the latency
- (+) Enable/Disable the prefetch buffer
- (+) Enable/Disable the Instruction cache and the Data cache
- (+) Reset the Instruction cache and the Data cache
- (+) Enable/Disable the Flash power-down during low-power run and sleep
- modes
- (+) Enable/Disable the Flash interrupts
- (+) Monitor the Flash flags status
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASH FLASH
- * @brief FLASH HAL module driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-
-/**
- * @brief Variable used for Program/Erase sectors under interruption
- */
-FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED,
- .ErrorCode = HAL_FLASH_ERROR_NONE,
- .ProcedureOnGoing = FLASH_PROC_NONE,
- .Address = 0U,
- .Bank = FLASH_BANK_1,
- .Page = 0U,
- .NbPagesToErase = 0U,
- .CacheToReactivate = FLASH_CACHE_DISABLED};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
-static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
- *
-@verbatim
- ===============================================================================
- ##### Programming operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the FLASH
- program operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Program double word or fast program of a row at a specified address.
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program.
- * @param Address specifies the address to be programmed.
- * @param Data specifies the data to be programmed.
- * This parameter is the data for the double word program and the
- * address where are stored the data for the row fast program.
- *
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address,
- uint64_t Data) {
- HAL_StatusTypeDef status;
- uint32_t prog_bit = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) {
- /* Program double-word (64-bit) at a specified address */
- FLASH_Program_DoubleWord(Address, Data);
- prog_bit = FLASH_CR_PG;
- } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) ||
- (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) {
- /* Fast program a 32 row double-word (64-bit) at a specified address */
- FLASH_Program_Fast(Address, (uint32_t)Data);
-
- /* If it is the last row, the bit will be cleared at the end of the
- * operation */
- if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) {
- prog_bit = FLASH_CR_FSTPG;
- }
- } else {
- /* Nothing to do */
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG or FSTPG Bit */
- if (prog_bit != 0U) {
- CLEAR_BIT(FLASH->CR, prog_bit);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- /* return status */
- return status;
-}
-
-/**
- * @brief Program double word or fast program of a row at a specified address
- * with interrupt enabled.
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program.
- * @param Address specifies the address to be programmed.
- * @param Data specifies the data to be programmed.
- * This parameter is the data for the double word program and the
- * address where are stored the data for the row fast program.
- *
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address,
- uint64_t Data) {
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Reset error code */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
- if (status != HAL_OK) {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- } else {
- /* Set internal variables used by the IRQ handler */
- if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
- } else {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
- }
- pFlash.Address = Address;
-
- /* Enable End of Operation and Error interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
- if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) {
- /* Program double-word (64-bit) at a specified address */
- FLASH_Program_DoubleWord(Address, Data);
- } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) ||
- (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) {
- /* Fast program a 32 row double-word (64-bit) at a specified address */
- FLASH_Program_Fast(Address, (uint32_t)Data);
- } else {
- /* Nothing to do */
- }
- }
-
- return status;
-}
-
-/**
- * @brief Handle FLASH interrupt request.
- * @retval None
- */
-void HAL_FLASH_IRQHandler(void) {
- uint32_t tmp_page;
- uint32_t error;
- FLASH_ProcedureTypeDef procedure;
-
- /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit
- */
- CLEAR_BIT(FLASH->CR,
- (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
-#if defined(FLASH_OPTR_DBANK)
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
-#endif
-
- /* Disable the FSTPG Bit only if it is the last row programmed */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) {
- CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
- }
-
- /* Check FLASH operation error flags */
- error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
-
- if (error != 0U) {
- /* Save the error code */
- pFlash.ErrorCode |= error;
-
- /* Clear error programming flags */
- __HAL_FLASH_CLEAR_FLAG(error);
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches();
-
- /* FLASH error interrupt user callback */
- procedure = pFlash.ProcedureOnGoing;
- if (procedure == FLASH_PROC_PAGE_ERASE) {
- HAL_FLASH_OperationErrorCallback(pFlash.Page);
- } else if (procedure == FLASH_PROC_MASS_ERASE) {
- HAL_FLASH_OperationErrorCallback(pFlash.Bank);
- } else if ((procedure == FLASH_PROC_PROGRAM) ||
- (procedure == FLASH_PROC_PROGRAM_LAST)) {
- HAL_FLASH_OperationErrorCallback(pFlash.Address);
- } else {
- /* Nothing to do */
- }
-
- /*Stop the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) {
- /* Nb of pages to erased can be decreased */
- pFlash.NbPagesToErase--;
-
- /* Check if there are still pages to erase*/
- if (pFlash.NbPagesToErase != 0U) {
- /* Indicate user which page has been erased*/
- HAL_FLASH_EndOfOperationCallback(pFlash.Page);
-
- /* Increment page number */
- pFlash.Page++;
- tmp_page = pFlash.Page;
- FLASH_PageErase(tmp_page, pFlash.Bank);
- } else {
- /* No more pages to Erase */
- /* Reset Address and stop Erase pages procedure */
- pFlash.Page = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches();
-
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Page);
- }
- } else {
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches();
-
- procedure = pFlash.ProcedureOnGoing;
- if (procedure == FLASH_PROC_MASS_ERASE) {
- /* MassErase ended. Return the selected bank */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
- } else if ((procedure == FLASH_PROC_PROGRAM) ||
- (procedure == FLASH_PROC_PROGRAM_LAST)) {
- /* Program ended. Return the selected address */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- } else {
- /* Nothing to do */
- }
-
- /*Clear the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
-
- if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) {
- /* Disable End of Operation and Error interrupts */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- }
-}
-
-/**
- * @brief FLASH end of operation interrupt callback.
- * @param ReturnValue The value saved in this parameter depends on the ongoing
- * procedure:
- * @arg Mass Erase: Bank number which has been requested to erase
- * @arg Page Erase: Page which has been erased
- * (if 0xFFFFFFFF, it means that all the selected
- * pages have been erased)
- * @arg Program: Address which was selected for data program
- * @retval None
- */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief FLASH operation error interrupt callback.
- * @param ReturnValue The value saved in this parameter depends on the ongoing
- * procedure:
- * @arg Mass Erase: Bank number which has been requested to erase
- * @arg Page Erase: Page number which returned an error
- * @arg Program: Address which was selected for data program
- * @retval None
- */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- * @brief Management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- memory operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the FLASH control register access.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) {
- /* Authorize the FLASH Registers access */
- WRITE_REG(FLASH->KEYR, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR, FLASH_KEY2);
-
- /* verify Flash is unlocked */
- if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Lock the FLASH control register access.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_Lock(void) {
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Set the LOCK Bit to lock the FLASH Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-
- /* verify Flash is locked */
- if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) {
- status = HAL_OK;
- }
-
- return status;
-}
-
-/**
- * @brief Unlock the FLASH Option Bytes Registers access.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) {
- /* Authorizes the Option Byte register programming */
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
-
- /* verify option bytes are unlocked */
- if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Lock the FLASH Option Bytes Registers access.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) {
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
-
- /* Verify option bytes are locked */
- if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) {
- status = HAL_OK;
- }
-
- return status;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) {
- /* Set the bit to force the option byte reloading */
- SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
-
- /* Wait for last operation to be completed */
- return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors
-functions
- * @brief Peripheral Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the specific FLASH error flag.
- * @retval FLASH_ErrorCode. The returned value can be:
- * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
- * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
- * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
- * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
- * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
- * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
- * @arg HAL_FLASH_ERROR_NONE: No error set
- * @arg HAL_FLASH_ERROR_OP: FLASH Operation error
- * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
- * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
- * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
- * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
- * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
- * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
- * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
- * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
- * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
- */
-uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; }
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Wait for a FLASH operation to complete.
- * @param Timeout maximum flash operation timeout.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) {
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be
- reset. Even if the FLASH operation fails, the BUSY flag will be reset and
- an error flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
- uint32_t error;
-
- while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
- if ((HAL_GetTick() - tickstart) > Timeout) {
- return HAL_TIMEOUT;
- }
- }
-
- /* Check FLASH operation error flags */
- error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
- if (error != 0u) {
- /* Save the error code */
- pFlash.ErrorCode |= error;
-
- /* Clear error programming flags */
- __HAL_FLASH_CLEAR_FLAG(error);
-
- return HAL_ERROR;
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- /* If there is an error flag set */
- return HAL_OK;
-}
-
-/**
- * @brief Program double-word (64-bit) at a specified address.
- * @param Address specifies the address to be programmed.
- * @param Data specifies the data to be programmed.
- * @retval None
- */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) {
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Set PG bit */
- SET_BIT(FLASH->CR, FLASH_CR_PG);
-
- /* Program first word */
- *(uint32_t *)Address = (uint32_t)Data;
-
- /* Barrier to ensure programming is performed in 2 steps, in right order
- (independently of compiler optimization behavior) */
- __ISB();
-
- /* Program second word */
- *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
-}
-
-/**
- * @brief Fast program a row double-word (64-bit) at a specified address.
- * @param Address specifies the address to be programmed.
- * @param DataAddress specifies the address where the data are stored.
- * @retval None
- */
-static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) {
- uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
- uint32_t *dest_addr = (uint32_t *)Address;
- uint32_t *src_addr = (uint32_t *)DataAddress;
- uint32_t primask_bit;
-
- /* Check the parameters */
- assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
-
- /* Set FSTPG bit */
- SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
-
- /* Enter critical section: Disable interrupts to avoid any interruption during
- * the loop */
- primask_bit = __get_PRIMASK();
- __disable_irq();
-
- /* Program the double words of the row */
- do {
- *dest_addr = *src_addr;
- dest_addr++;
- src_addr++;
- row_index--;
- } while (row_index != 0U);
-
- /* Exit critical section: restore previous priority mask */
- __set_PRIMASK(primask_bit);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_flash.c
+ * @author MCD Application Team
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory
+ operations and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of
+ instruction prefetch and cache lines.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Option bytes programming
+ (+) Prefetch on I-Code
+ (+) 32 cache lines of 4*64 or 2*128 bits on I-Code
+ (+) 8 cache lines of 4*64 or 2*128 bits on D-Code
+ (+) Error code correction (ECC) : Data in flash are 72-bits word
+ (8 bits added per double word)
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the
+ FLASH memory of all STM32G4xx devices.
+
+ (#) Flash Memory IO Programming functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Program functions: double word and fast program (full row
+ programming)
+ (++) There are two modes of programming :
+ (+++) Polling mode using HAL_FLASH_Program() function
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+ (#) Interrupts and flags management functions:
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+ (++) Callback functions are called when the flash operations are
+ finished : HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+ HAL_FLASH_OperationErrorCallback()
+ (++) Get error flag status by calling HAL_GetError()
+
+ (#) Option bytes management functions:
+ (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+ HAL_FLASH_OB_Lock() functions
+ (++) Launch the reload of the option bytes using HAL_FLASH_Launch()
+ function. In this case, a reset is generated
+
+ [..]
+ In addition to these functions, this driver includes a set of macros
+ allowing to handle the following operations:
+ (+) Set the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the Instruction cache and the Data cache
+ (+) Reset the Instruction cache and the Data cache
+ (+) Enable/Disable the Flash power-down during low-power run and sleep
+ modes
+ (+) Enable/Disable the Flash interrupts
+ (+) Monitor the Flash flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+
+/**
+ * @brief Variable used for Program/Erase sectors under interruption
+ */
+FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED,
+ .ErrorCode = HAL_FLASH_ERROR_NONE,
+ .ProcedureOnGoing = FLASH_PROC_NONE,
+ .Address = 0U,
+ .Bank = FLASH_BANK_1,
+ .Page = 0U,
+ .NbPagesToErase = 0U,
+ .CacheToReactivate = FLASH_CACHE_DISABLED};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program double word or fast program of a row at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * This parameter is the data for the double word program and the
+ * address where are stored the data for the row fast program.
+ *
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address,
+ uint64_t Data) {
+ HAL_StatusTypeDef status;
+ uint32_t prog_bit = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Deactivate the data cache if they are activated to avoid data misbehavior
+ */
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ } else {
+ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ }
+ if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) {
+ /* Program double-word (64-bit) at a specified address */
+ FLASH_Program_DoubleWord(Address, Data);
+ prog_bit = FLASH_CR_PG;
+ } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) ||
+ (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) {
+ /* Fast program a 32 row double-word (64-bit) at a specified address */
+ FLASH_Program_Fast(Address, (uint32_t)Data);
+
+ /* If it is the last row, the bit will be cleared at the end of the
+ * operation */
+ if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) {
+ prog_bit = FLASH_CR_FSTPG;
+ }
+ } else {
+ /* Nothing to do */
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG or FSTPG Bit */
+ if (prog_bit != 0U) {
+ CLEAR_BIT(FLASH->CR, prog_bit);
+ }
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ /* return status */
+ return status;
+}
+
+/**
+ * @brief Program double word or fast program of a row at a specified address
+ * with interrupt enabled.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * This parameter is the data for the double word program and the
+ * address where are stored the data for the row fast program.
+ *
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address,
+ uint64_t Data) {
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Deactivate the data cache if they are activated to avoid data misbehavior
+ */
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ } else {
+ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK) {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ } else {
+ /* Set internal variables used by the IRQ handler */
+ if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
+ } else {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+ }
+ pFlash.Address = Address;
+
+ /* Enable End of Operation and Error interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) {
+ /* Program double-word (64-bit) at a specified address */
+ FLASH_Program_DoubleWord(Address, Data);
+ } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) ||
+ (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) {
+ /* Fast program a 32 row double-word (64-bit) at a specified address */
+ FLASH_Program_Fast(Address, (uint32_t)Data);
+ } else {
+ /* Nothing to do */
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handle FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void) {
+ uint32_t tmp_page;
+ uint32_t error;
+ FLASH_ProcedureTypeDef procedure;
+
+ /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit
+ */
+ CLEAR_BIT(FLASH->CR,
+ (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
+#if defined(FLASH_OPTR_DBANK)
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
+#endif
+
+ /* Disable the FSTPG Bit only if it is the last row programmed */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) {
+ CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
+ }
+
+ /* Check FLASH operation error flags */
+ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
+
+ if (error != 0U) {
+ /* Save the error code */
+ pFlash.ErrorCode |= error;
+
+ /* Clear error programming flags */
+ __HAL_FLASH_CLEAR_FLAG(error);
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
+
+ /* FLASH error interrupt user callback */
+ procedure = pFlash.ProcedureOnGoing;
+ if (procedure == FLASH_PROC_PAGE_ERASE) {
+ HAL_FLASH_OperationErrorCallback(pFlash.Page);
+ } else if (procedure == FLASH_PROC_MASS_ERASE) {
+ HAL_FLASH_OperationErrorCallback(pFlash.Bank);
+ } else if ((procedure == FLASH_PROC_PROGRAM) ||
+ (procedure == FLASH_PROC_PROGRAM_LAST)) {
+ HAL_FLASH_OperationErrorCallback(pFlash.Address);
+ } else {
+ /* Nothing to do */
+ }
+
+ /*Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) {
+ /* Nb of pages to erased can be decreased */
+ pFlash.NbPagesToErase--;
+
+ /* Check if there are still pages to erase*/
+ if (pFlash.NbPagesToErase != 0U) {
+ /* Indicate user which page has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+
+ /* Increment page number */
+ pFlash.Page++;
+ tmp_page = pFlash.Page;
+ FLASH_PageErase(tmp_page, pFlash.Bank);
+ } else {
+ /* No more pages to Erase */
+ /* Reset Address and stop Erase pages procedure */
+ pFlash.Page = 0xFFFFFFFFU;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
+
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+ }
+ } else {
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
+
+ procedure = pFlash.ProcedureOnGoing;
+ if (procedure == FLASH_PROC_MASS_ERASE) {
+ /* MassErase ended. Return the selected bank */
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+ } else if ((procedure == FLASH_PROC_PROGRAM) ||
+ (procedure == FLASH_PROC_PROGRAM_LAST)) {
+ /* Program ended. Return the selected address */
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ } else {
+ /* Nothing to do */
+ }
+
+ /*Clear the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) {
+ /* Disable End of Operation and Error interrupts */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+/**
+ * @brief FLASH end of operation interrupt callback.
+ * @param ReturnValue The value saved in this parameter depends on the ongoing
+ * procedure:
+ * @arg Mass Erase: Bank number which has been requested to erase
+ * @arg Page Erase: Page which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected
+ * pages have been erased)
+ * @arg Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback.
+ * @param ReturnValue The value saved in this parameter depends on the ongoing
+ * procedure:
+ * @arg Mass Erase: Bank number which has been requested to erase
+ * @arg Page Erase: Page number which returned an error
+ * @arg Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* verify Flash is unlocked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Lock the FLASH control register access.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void) {
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ /* verify Flash is locked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) {
+ status = HAL_OK;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unlock the FLASH Option Bytes Registers access.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+
+ /* verify option bytes are unlocked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Lock the FLASH Option Bytes Registers access.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) {
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+
+ /* Verify option bytes are locked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) {
+ status = HAL_OK;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) {
+ /* Set the bit to force the option byte reloading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+ /* Wait for last operation to be completed */
+ return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors
+functions
+ * @brief Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode. The returned value can be:
+ * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+ * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
+ * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
+ * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
+ * @arg HAL_FLASH_ERROR_NONE: No error set
+ * @arg HAL_FLASH_ERROR_OP: FLASH Operation error
+ * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
+ * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
+ * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
+ * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
+ * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
+ * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
+ * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
+ * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
+ */
+uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout maximum flash operation timeout.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) {
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be
+ reset. Even if the FLASH operation fails, the BUSY flag will be reset and
+ an error flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t error;
+
+ while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
+ if ((HAL_GetTick() - tickstart) > Timeout) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check FLASH operation error flags */
+ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
+ if (error != 0u) {
+ /* Save the error code */
+ pFlash.ErrorCode |= error;
+
+ /* Clear error programming flags */
+ __HAL_FLASH_CLEAR_FLAG(error);
+
+ return HAL_ERROR;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ /* If there is an error flag set */
+ return HAL_OK;
+}
+
+/**
+ * @brief Program double-word (64-bit) at a specified address.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) {
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Set PG bit */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* Program first word */
+ *(uint32_t *)Address = (uint32_t)Data;
+
+ /* Barrier to ensure programming is performed in 2 steps, in right order
+ (independently of compiler optimization behavior) */
+ __ISB();
+
+ /* Program second word */
+ *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
+}
+
+/**
+ * @brief Fast program a row double-word (64-bit) at a specified address.
+ * @param Address specifies the address to be programmed.
+ * @param DataAddress specifies the address where the data are stored.
+ * @retval None
+ */
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) {
+ uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
+ uint32_t *dest_addr = (uint32_t *)Address;
+ uint32_t *src_addr = (uint32_t *)DataAddress;
+ uint32_t primask_bit;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
+
+ /* Set FSTPG bit */
+ SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+
+ /* Enter critical section: Disable interrupts to avoid any interruption during
+ * the loop */
+ primask_bit = __get_PRIMASK();
+ __disable_irq();
+
+ /* Program the double words of the row */
+ do {
+ *dest_addr = *src_addr;
+ dest_addr++;
+ src_addr++;
+ row_index--;
+ } while (row_index != 0U);
+
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c
index 44b8efe..a647744 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c
@@ -1,1331 +1,1346 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_flash_ex.c
- * @author MCD Application Team
- * @brief Extended FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the FLASH extended peripheral:
- * + Extended programming operations functions
- *
- @verbatim
- ==============================================================================
- ##### Flash Extended features #####
- ==============================================================================
-
- [..] Comparing to other previous devices, the FLASH interface for STM32G4xx
- devices contains the following additional features
-
- (+) Capacity up to 512 Kbytes with dual bank architecture supporting
- read-while-write capability (RWW)
- (+) Dual bank 64-bits memory organization with possibility of single bank
- 128-bits
- (+) Protected areas including WRP, PCROP and Securable memory
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the FLASH memory
- of all STM32G4xx devices. It includes
- (#) Flash Memory Erase functions:
- (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
- HAL_FLASH_Lock() functions
- (++) Erase function: Erase pages, or mass erase banks
- (++) There are two modes of erase :
- (+++) Polling Mode using HAL_FLASHEx_Erase()
- (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-
- (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
- (++) Configure the write protection areas (WRP)
- (++) Set the Read protection Level (RDP)
- (++) Program the user Option Bytes
- (++) Configure the Proprietary Code ReadOut protection areas (PCROP)
- (++) Configure the Securable memory areas
- (++) Configure the Boot Lock
-
- (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig()
- to:
- (++) Get the configuration of write protection areas (WRP)
- (++) Get the level of read protection (RDP)
- (++) Get the value of the user Option Bytes
- (++) Get the configuration of Proprietary Code ReadOut Protection areas
- (PCROP)
- (++) Get the configuration of Securable memory areas
- (++) Get the status of Boot Lock
-
- (#) Activation of Securable memory area: Use
- HAL_FLASHEx_EnableSecMemProtection()
- (++) Deny the access to securable memory area
-
- (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or
- HAL_FLASHEx_DisableDebugger()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASHEx FLASHEx
- * @brief FLASH Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-static void FLASH_MassErase(uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea,
- uint32_t WRPStartOffset,
- uint32_t WRDPEndOffset);
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType,
- uint32_t UserConfig);
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig,
- uint32_t PCROPStartAddr,
- uint32_t PCROPEndAddr);
-static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset,
- uint32_t *WRDPEndOffset);
-static uint32_t FLASH_OB_GetRDP(void);
-static uint32_t FLASH_OB_GetUser(void);
-static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,
- uint32_t *PCROPEndAddr);
-static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank,
- uint32_t SecMemSize);
-static void FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize);
-static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
-static uint32_t FLASH_OB_GetBootLock(void);
-
-/**
- * @}
- */
-
-/* Exported functions -------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
- * @{
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### Extended programming operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the Extended
-FLASH programming operations Operations.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages.
- * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- * @param[out] PageError pointer to variable that contains the configuration
- * information on faulty page in case of error (0xFFFFFFFF means that
- * all the pages have been correctly erased).
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit,
- uint32_t *PageError) {
- HAL_StatusTypeDef status;
- uint32_t page_index;
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Deactivate the cache if they are activated to avoid data misbehavior */
- if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) {
- if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
- } else {
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
- }
- } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
- } else {
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
- }
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
- /* Mass erase to be done */
- FLASH_MassErase(pEraseInit->Banks);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-#if defined(FLASH_OPTR_DBANK)
- /* If the erase operation is completed, disable the MER1 and MER2 Bits */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
-#else
- /* If the erase operation is completed, disable the MER1 Bit */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
-#endif
- } else {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- for (page_index = pEraseInit->Page;
- page_index < (pEraseInit->Page + pEraseInit->NbPages);
- page_index++) {
- FLASH_PageErase(page_index, pEraseInit->Banks);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
-
- if (status != HAL_OK) {
- /* In case of error, stop erase procedure and return the faulty page
- */
- *PageError = page_index;
- break;
- }
- }
- }
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches();
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages with
- * interrupt enabled.
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Deactivate the cache if they are activated to avoid data misbehavior */
- if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) {
- if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
- } else {
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
- }
- } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
- } else {
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
- }
-
- /* Enable End of Operation and Error interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
- pFlash.Bank = pEraseInit->Banks;
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
- /* Mass erase to be done */
- pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
- FLASH_MassErase(pEraseInit->Banks);
- } else {
- /* Erase by page to be done */
- pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
- pFlash.NbPagesToErase = pEraseInit->NbPages;
- pFlash.Page = pEraseInit->Page;
-
- /*Erase 1st page and wait for IT */
- FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
- }
-
- return status;
-}
-
-/**
- * @brief Program Option bytes.
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @retval HAL_Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Write protection configuration */
- if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) {
- /* Configure of Write protection on the selected area */
- if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset,
- pOBInit->WRPEndOffset) != HAL_OK) {
- status = HAL_ERROR;
- }
- }
-
- /* Read protection configuration */
- if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) {
- /* Configure the Read protection level */
- if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) {
- status = HAL_ERROR;
- }
- }
-
- /* User Configuration */
- if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) {
- /* Configure the user option bytes */
- if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) {
- status = HAL_ERROR;
- }
- }
-
- /* PCROP Configuration */
- if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) {
- if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) {
- /* Configure the Proprietary code readout protection */
- if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr,
- pOBInit->PCROPEndAddr) != HAL_OK) {
- status = HAL_ERROR;
- }
- }
- }
-
- /* Securable memory Configuration */
- if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U) {
- /* Configure the securable memory area */
- if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK) {
- status = HAL_ERROR;
- }
- }
-
- /* Boot Entry Point Configuration */
- if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) {
- /* Configure the boot unique entry point option */
- if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK) {
- status = HAL_ERROR;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Get the Option bytes configuration.
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
- * configuration information.
- * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
- * which area is requested for the WRP and PCROP, else no information
- * will be returned.
- * @retval None
- */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) {
- pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
-
-#if defined(FLASH_OPTR_DBANK)
- if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) ||
- (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
- (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) ||
- (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
-#else
- if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) ||
- (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
-#endif
- {
- pOBInit->OptionType |= OPTIONBYTE_WRP;
- /* Get write protection on the selected area */
- FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset),
- &(pOBInit->WRPEndOffset));
- }
-
- /* Get Read protection level */
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
- /* Get the user option bytes */
- pOBInit->USERConfig = FLASH_OB_GetUser();
-
-#if defined(FLASH_OPTR_DBANK)
- if ((pOBInit->PCROPConfig == FLASH_BANK_1) ||
- (pOBInit->PCROPConfig == FLASH_BANK_2))
-#else
- if (pOBInit->PCROPConfig == FLASH_BANK_1)
-#endif
- {
- pOBInit->OptionType |= OPTIONBYTE_PCROP;
- /* Get the Proprietary code readout protection */
- FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr),
- &(pOBInit->PCROPEndAddr));
- }
-
- pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
-
- /* Get the boot entry point */
- pOBInit->BootEntryPoint = FLASH_OB_GetBootLock();
-
- /* Get the securable memory area configuration */
-#if defined(FLASH_OPTR_DBANK)
- if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2))
-#else
- if (pOBInit->SecBank == FLASH_BANK_1)
-#endif
- {
- pOBInit->OptionType |= OPTIONBYTE_SEC;
- FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
- }
-}
-
-/**
- * @brief Enable the FLASH Securable Memory protection.
- * @param Bank: Bank to be protected
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Bank1 to be protected
- * @arg FLASH_BANK_2: Bank2 to be protected (*)
- * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*)
- * @note (*) availability depends on devices
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) {
-#if defined(FLASH_OPTR_DBANK)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) {
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Bank));
-
- /* Enable the Securable Memory Protection Bit for the bank 1 if requested */
- if ((Bank & FLASH_BANK_1) != 0U) {
- SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
- }
-
- /* Enable the Securable Memory Protection Bit for the bank 2 if requested */
- if ((Bank & FLASH_BANK_2) != 0U) {
- SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2);
- }
- } else
-#endif
- {
- SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable Debugger.
- * @note After calling this API, flash interface allow debugger intrusion.
- * @retval None
- */
-void HAL_FLASHEx_EnableDebugger(void) { FLASH->ACR |= FLASH_ACR_DBG_SWEN; }
-
-/**
- * @brief Disable Debugger.
- * @note After calling this API, Debugger is disabled: it's no more possible
- * to break, see CPU register, etc...
- * @retval None
- */
-void HAL_FLASHEx_DisableDebugger(void) { FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; }
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-/**
- * @brief Mass erase of FLASH memory.
- * @param Banks Banks to be erased.
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Bank1 to be erased
- * @arg FLASH_BANK_2: Bank2 to be erased (*)
- * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*)
- * @note (*) availability depends on devices
- * @retval None
- */
-static void FLASH_MassErase(uint32_t Banks) {
-#if defined(FLASH_OPTR_DBANK)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
-#endif
- {
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
-
- /* Set the Mass Erase Bit for the bank 1 if requested */
- if ((Banks & FLASH_BANK_1) != 0U) {
- SET_BIT(FLASH->CR, FLASH_CR_MER1);
- }
-
-#if defined(FLASH_OPTR_DBANK)
- /* Set the Mass Erase Bit for the bank 2 if requested */
- if ((Banks & FLASH_BANK_2) != 0U) {
- SET_BIT(FLASH->CR, FLASH_CR_MER2);
- }
-#endif
- }
-#if defined(FLASH_OPTR_DBANK)
- else {
- SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
- }
-#endif
-
- /* Proceed to erase all sectors */
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
- * @brief Erase the specified FLASH memory page.
- * @param Page FLASH page to erase.
- * This parameter must be a value between 0 and (max number of pages in
- * the bank - 1).
- * @param Banks Bank where the page will be erased.
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Page in bank 1 to be erased
- * @arg FLASH_BANK_2: Page in bank 2 to be erased (*)
- * @note (*) availability depends on devices
- * @retval None
- */
-void FLASH_PageErase(uint32_t Page, uint32_t Banks) {
- /* Check the parameters */
- assert_param(IS_FLASH_PAGE(Page));
-
-#if defined(FLASH_OPTR_DBANK)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) {
- CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
- } else {
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
-
- if ((Banks & FLASH_BANK_1) != 0U) {
- CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
- } else {
- SET_BIT(FLASH->CR, FLASH_CR_BKER);
- }
- }
-#endif
-
- /* Proceed to erase the page */
- MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
- SET_BIT(FLASH->CR, FLASH_CR_PER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
- * @brief Flush the instruction and data caches.
- * @retval None
- */
-void FLASH_FlushCaches(void) {
- FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
-
- /* Flush instruction cache */
- if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
- (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) {
- /* Disable instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
- /* Reset instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_RESET();
- /* Enable instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
- }
-
- /* Flush data cache */
- if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
- (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) {
- /* Reset data cache */
- __HAL_FLASH_DATA_CACHE_RESET();
- /* Enable data cache */
- __HAL_FLASH_DATA_CACHE_ENABLE();
- }
-
- /* Reset internal variable */
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
-}
-
-/**
- * @brief Configure the write protection area into Option Bytes.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase Flash memory if the CPU debug
- * features are connected (JTAG or single wire) or boot code is being
- * executed from RAM or System flash, even if WRP is not activated.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @param WRPArea specifies the area to be configured.
- * This parameter can be one of the following values:
- * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
- * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
- * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*)
- * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*)
- * @note (*) availability depends on devices
- * @param WRPStartOffset specifies the start page of the write protected area.
- * This parameter can be page number between 0 and (max number of pages
- * in the bank - 1).
- * @param WRDPEndOffset specifies the end page of the write protected area.
- * This parameter can be page number between WRPStartOffset and (max
- * number of pages in the bank - 1).
- * @retval HAL_Status
- */
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea,
- uint32_t WRPStartOffset,
- uint32_t WRDPEndOffset) {
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_WRPAREA(WRPArea));
- assert_param(IS_FLASH_PAGE(WRPStartOffset));
- assert_param(IS_FLASH_PAGE(WRDPEndOffset));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- /* Configure the write protected area */
- if (WRPArea == OB_WRPAREA_BANK1_AREAA) {
- FLASH->WRP1AR =
- ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
- } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) {
- FLASH->WRP1BR =
- ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
- }
-#if defined(FLASH_OPTR_DBANK)
- else if (WRPArea == OB_WRPAREA_BANK2_AREAA) {
- FLASH->WRP2AR =
- ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset);
- } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) {
- FLASH->WRP2BR =
- ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
- }
-#endif
- else {
- /* Nothing to do */
- }
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-
- return status;
-}
-
-/**
- * @brief Set the read protection level into Option Bytes.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
- * to go back to level 1 or 0 !!!
- * @param RDPLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Memory Read protection
- * @arg OB_RDP_LEVEL_2: Full chip protection
- *
- * @retval HAL_Status
- */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) {
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(RDPLevel));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- /* Configure the RDP level in the option bytes register */
- MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-
- return status;
-}
-
-/**
- * @brief Program the FLASH User Option Bytes.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @param UserType The FLASH User Option Bytes to be modified.
- * This parameter can be a combination of @ref FLASH_OB_USER_Type.
- * @param UserConfig The selected User Option Bytes values:
- * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
- * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY ,
- * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
- * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
- * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
- * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1,
- * @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST,
- * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
- * @ref FLASH_OB_USER_NRST_MODE, @ref
- * FLASH_OB_USER_INTERNAL_RESET_HOLDER
- * @note (*) availability depends on devices
- * @retval HAL_Status
- */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType,
- uint32_t UserConfig) {
- uint32_t optr_reg_val = 0;
- uint32_t optr_reg_mask = 0;
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_USER_TYPE(UserType));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- if ((UserType & OB_USER_BOR_LEV) != 0U) {
- /* BOR level option byte should be modified */
- assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
-
- /* Set value and mask for BOR level option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
- optr_reg_mask |= FLASH_OPTR_BOR_LEV;
- }
-
- if ((UserType & OB_USER_nRST_STOP) != 0U) {
- /* nRST_STOP option byte should be modified */
- assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
-
- /* Set value and mask for nRST_STOP option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
- optr_reg_mask |= FLASH_OPTR_nRST_STOP;
- }
-
- if ((UserType & OB_USER_nRST_STDBY) != 0U) {
- /* nRST_STDBY option byte should be modified */
- assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
-
- /* Set value and mask for nRST_STDBY option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
- optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
- }
-
- if ((UserType & OB_USER_nRST_SHDW) != 0U) {
- /* nRST_SHDW option byte should be modified */
- assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
-
- /* Set value and mask for nRST_SHDW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
- optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
- }
-
- if ((UserType & OB_USER_IWDG_SW) != 0U) {
- /* IWDG_SW option byte should be modified */
- assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
-
- /* Set value and mask for IWDG_SW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
- optr_reg_mask |= FLASH_OPTR_IWDG_SW;
- }
-
- if ((UserType & OB_USER_IWDG_STOP) != 0U) {
- /* IWDG_STOP option byte should be modified */
- assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
-
- /* Set value and mask for IWDG_STOP option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
- optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
- }
-
- if ((UserType & OB_USER_IWDG_STDBY) != 0U) {
- /* IWDG_STDBY option byte should be modified */
- assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
-
- /* Set value and mask for IWDG_STDBY option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
- optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
- }
-
- if ((UserType & OB_USER_WWDG_SW) != 0U) {
- /* WWDG_SW option byte should be modified */
- assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
-
- /* Set value and mask for WWDG_SW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
- optr_reg_mask |= FLASH_OPTR_WWDG_SW;
- }
-
-#if defined(FLASH_OPTR_BFB2)
- if ((UserType & OB_USER_BFB2) != 0U) {
- /* BFB2 option byte should be modified */
- assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
-
- /* Set value and mask for BFB2 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
- optr_reg_mask |= FLASH_OPTR_BFB2;
- }
-#endif
-
- if ((UserType & OB_USER_nBOOT1) != 0U) {
- /* nBOOT1 option byte should be modified */
- assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
-
- /* Set value and mask for nBOOT1 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
- optr_reg_mask |= FLASH_OPTR_nBOOT1;
- }
-
- if ((UserType & OB_USER_SRAM_PE) != 0U) {
- /* SRAM_PE option byte should be modified */
- assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE));
-
- /* Set value and mask for SRAM_PE option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE);
- optr_reg_mask |= FLASH_OPTR_SRAM_PE;
- }
-
- if ((UserType & OB_USER_CCMSRAM_RST) != 0U) {
- /* CCMSRAM_RST option byte should be modified */
- assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST));
-
- /* Set value and mask for CCMSRAM_RST option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST);
- optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
- }
-
- if ((UserType & OB_USER_nSWBOOT0) != 0U) {
- /* nSWBOOT0 option byte should be modified */
- assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
-
- /* Set value and mask for nSWBOOT0 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
- optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
- }
-
- if ((UserType & OB_USER_nBOOT0) != 0U) {
- /* nBOOT0 option byte should be modified */
- assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
-
- /* Set value and mask for nBOOT0 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
- optr_reg_mask |= FLASH_OPTR_nBOOT0;
- }
-
- if ((UserType & OB_USER_NRST_MODE) != 0U) {
- /* Reset Configuration option byte should be modified */
- assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE));
-
- /* Set value and mask for Reset Configuration option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE);
- optr_reg_mask |= FLASH_OPTR_NRST_MODE;
- }
-
- if ((UserType & OB_USER_IRHEN) != 0U) {
- /* IRH option byte should be modified */
- assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN));
-
- /* Set value and mask for IRH option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN);
- optr_reg_mask |= FLASH_OPTR_IRHEN;
- }
-
- /* Configure the option bytes register */
- MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-
- return status;
-}
-
-/**
- * @brief Configure the Proprietary code readout protection area into Option
- * Bytes.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @param PCROPConfig specifies the configuration (Bank to be configured and
- * PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1 or
- * FLASH_BANK_2 (*) with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
- * @note (*) availability depends on devices
- * @param PCROPStartAddr specifies the start address of the Proprietary code
- * readout protection. This parameter can be an address between begin and end of
- * the bank.
- * @param PCROPEndAddr specifies the end address of the Proprietary code
- * readout protection. This parameter can be an address between PCROPStartAddr
- * and end of the bank.
- * @retval HAL_Status
- */
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig,
- uint32_t PCROPStartAddr,
- uint32_t PCROPEndAddr) {
- HAL_StatusTypeDef status;
- uint32_t reg_value;
- uint32_t bank1_addr;
-#if defined(FLASH_OPTR_DBANK)
- uint32_t bank2_addr;
-#endif
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
- assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
- assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
- assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
-#if defined(FLASH_OPTR_DBANK)
- /* Get the information about the bank swapping */
- if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) {
- bank1_addr = FLASH_BASE;
- bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
- } else {
- bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
- bank2_addr = FLASH_BASE;
- }
-#else
- bank1_addr = FLASH_BASE;
-#endif
-
-#if defined(FLASH_OPTR_DBANK)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) {
- /* Configure the Proprietary code readout protection */
- if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) {
- reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
- } else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) {
- reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
- } else {
- /* Nothing to do */
- }
- } else
-#endif
- {
- /* Configure the Proprietary code readout protection */
- if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) {
- reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
- MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
- MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
- }
-#if defined(FLASH_OPTR_DBANK)
- else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) {
- reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
- MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
- MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
- }
-#endif
- else {
- /* Nothing to do */
- }
- }
-
- MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP,
- (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-
- return status;
-}
-
-/**
- * @brief Configure the Securable memory area into Option Bytes.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @param SecBank specifies bank of securable memory area to be configured.
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Securable memory in Bank1 to be configured
- * @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*)
- * @note (*) availability depends on devices
- * @param SecSize specifies the number of pages of the Securable memory area,
- * starting from first page of the bank.
- * This parameter can be page number between 0 and (max number of pages
- * in the bank - 1)
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank,
- uint32_t SecSize) {
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank));
- assert_param(IS_OB_SECMEM_SIZE(SecSize));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- /* Configure the write protected area */
- if (SecBank == FLASH_BANK_1) {
- MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize);
- }
-#if defined(FLASH_OPTR_DBANK)
- else if (SecBank == FLASH_BANK_2) {
- MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize);
- } else {
- /* Nothing to do */
- }
-#endif
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-
- return status;
-}
-
-/**
- * @brief Configure the Boot Lock into Option Bytes.
- * @note To configure any option bytes, the option lock bit OPTLOCK must be
- * cleared with the call of HAL_FLASH_OB_Unlock() function.
- * @note New option bytes configuration will be taken into account in two
- * cases:
- * - after an option bytes launch through the call of
- * HAL_FLASH_OB_Launch()
- * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
- * @param BootLockConfig specifies the boot lock configuration.
- * This parameter can be one of the following values:
- * @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock
- * @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock
- *
- * @retval HAL_Status
- */
-static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig) {
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK) {
- MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-
- return status;
-}
-
-/**
- * @brief Return the Securable memory area configuration into Option Bytes.
- * @param[in] SecBank specifies the bank where securable memory area is
- located.
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Securable memory in Bank1
- * @arg FLASH_BANK_2: Securable memory in Bank2 (*)
- * @note (*) availability depends on devices
- * @param[out] SecSize specifies the number of pages used in the securable
- memory area of the bank.
- * @retval None
- */
-static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize) {
- /* Get the configuration of the securable memory area */
- if (SecBank == FLASH_BANK_1) {
- *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1);
- }
-#if defined(FLASH_OPTR_DBANK)
- else if (SecBank == FLASH_BANK_2) {
- *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2);
- } else {
- /* Nothing to do */
- }
-#endif
-}
-
-/**
- * @brief Return the Boot Lock configuration into Option Byte.
- * @retval BootLockConfig.
- * This return value can be one of the following values:
- * @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled
- * @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled
- */
-static uint32_t FLASH_OB_GetBootLock(void) {
- return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK);
-}
-
-/**
- * @brief Return the Write Protection configuration into Option Bytes.
- * @param[in] WRPArea specifies the area to be returned.
- * This parameter can be one of the following values:
- * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
- * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
- * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to
- * STM32G43x/STM32G44x devices)
- * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to
- * STM32G43x/STM32G44x devices)
- * @param[out] WRPStartOffset specifies the address where to copied the start
- * page of the write protected area.
- * @param[out] WRDPEndOffset specifies the address where to copied the end page
- * of the write protected area.
- * @retval None
- */
-static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset,
- uint32_t *WRDPEndOffset) {
- /* Get the configuration of the write protected area */
- if (WRPArea == OB_WRPAREA_BANK1_AREAA) {
- *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >>
- FLASH_WRP1AR_WRP1A_END_Pos);
- } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) {
- *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >>
- FLASH_WRP1BR_WRP1B_END_Pos);
- }
-#if defined(FLASH_OPTR_DBANK)
- else if (WRPArea == OB_WRPAREA_BANK2_AREAA) {
- *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >>
- FLASH_WRP2AR_WRP2A_END_Pos);
- } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) {
- *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >>
- FLASH_WRP2BR_WRP2B_END_Pos);
- }
-#endif
- else {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief Return the FLASH Read Protection level into Option Bytes.
- * @retval RDP_Level
- * This return value can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Read protection of the memory
- * @arg OB_RDP_LEVEL_2: Full chip protection
- */
-static uint32_t FLASH_OB_GetRDP(void) {
- uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
-
- if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) {
- return (OB_RDP_LEVEL_1);
- } else {
- return rdp_level;
- }
-}
-
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval OB_user_config
- * This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL,
- * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
- * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
- * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
- * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
- * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*),
- * @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
- * @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref
- * FLASH_OB_USER_nBOOT0,
- * @ref FLASH_OB_USER_NRST_MODE, @ref
- * FLASH_OB_USER_INTERNAL_RESET_HOLDER
- * @note (*) availability depends on devices
- */
-static uint32_t FLASH_OB_GetUser(void) {
- uint32_t user_config = READ_REG(FLASH->OPTR);
- CLEAR_BIT(user_config, FLASH_OPTR_RDP);
-
- return user_config;
-}
-
-/**
- * @brief Return the FLASH PCROP configuration into Option Bytes.
- * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured
- * and PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1
- * or FLASH_BANK_2 with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
- * @param[out] PCROPStartAddr specifies the address where to copied the start
- * address of the Proprietary code readout protection.
- * @param[out] PCROPEndAddr specifies the address where to copied the end
- * address of the Proprietary code readout protection.
- * @retval None
- */
-static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,
- uint32_t *PCROPEndAddr) {
- uint32_t reg_value;
- uint32_t bank1_addr;
-#if defined(FLASH_OPTR_DBANK)
- uint32_t bank2_addr;
-
- /* Get the information about the bank swapping */
- if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) {
- bank1_addr = FLASH_BASE;
- bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
- } else {
- bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
- bank2_addr = FLASH_BASE;
- }
-#else
- bank1_addr = FLASH_BASE;
-#endif
-
-#if defined(FLASH_OPTR_DBANK)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) {
- if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) {
- reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
- *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
-
- reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
- *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
- } else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) {
- reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
- *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
-
- reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
- *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
- } else {
- /* Nothing to do */
- }
- } else
-#endif
- {
- if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) {
- reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
- *PCROPStartAddr = (reg_value << 3) + bank1_addr;
-
- reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
- *PCROPEndAddr = (reg_value << 3) + bank1_addr;
- }
-#if defined(FLASH_OPTR_DBANK)
- else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) {
- reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
- *PCROPStartAddr = (reg_value << 3) + bank2_addr;
-
- reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
- *PCROPEndAddr = (reg_value << 3) + bank2_addr;
- }
-#endif
- else {
- /* Nothing to do */
- }
- }
-
- *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @brief Extended FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH extended peripheral:
+ * + Extended programming operations functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FLASH interface for STM32G4xx
+ devices contains the following additional features
+
+ (+) Capacity up to 512 Kbytes with dual bank architecture supporting
+ read-while-write capability (RWW)
+ (+) Dual bank 64-bits memory organization with possibility of single bank
+ 128-bits
+ (+) Protected areas including WRP, PCROP and Securable memory
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32G4xx devices. It includes
+ (#) Flash Memory Erase functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Erase function: Erase pages, or mass erase banks
+ (++) There are two modes of erase :
+ (+++) Polling Mode using HAL_FLASHEx_Erase()
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+ (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
+ (++) Configure the write protection areas (WRP)
+ (++) Set the Read protection Level (RDP)
+ (++) Program the user Option Bytes
+ (++) Configure the Proprietary Code ReadOut protection areas (PCROP)
+ (++) Configure the Securable memory areas
+ (++) Configure the Boot Lock
+
+ (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig()
+ to:
+ (++) Get the configuration of write protection areas (WRP)
+ (++) Get the level of read protection (RDP)
+ (++) Get the value of the user Option Bytes
+ (++) Get the configuration of Proprietary Code ReadOut Protection areas
+ (PCROP)
+ (++) Get the configuration of Securable memory areas
+ (++) Get the status of Boot Lock
+
+ (#) Activation of Securable memory area: Use
+ HAL_FLASHEx_EnableSecMemProtection()
+ (++) Deny the access to securable memory area
+
+ (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or
+ HAL_FLASHEx_DisableDebugger()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+static void FLASH_MassErase(uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea,
+ uint32_t WRPStartOffset,
+ uint32_t WRDPEndOffset);
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType,
+ uint32_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig,
+ uint32_t PCROPStartAddr,
+ uint32_t PCROPEndAddr);
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset,
+ uint32_t *WRDPEndOffset);
+static uint32_t FLASH_OB_GetRDP(void);
+static uint32_t FLASH_OB_GetUser(void);
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,
+ uint32_t *PCROPEndAddr);
+static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank,
+ uint32_t SecMemSize);
+static void FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize);
+static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
+static uint32_t FLASH_OB_GetBootLock(void);
+
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the Extended
+FLASH programming operations Operations.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages.
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ * @param[out] PageError pointer to variable that contains the configuration
+ * information on faulty page in case of error (0xFFFFFFFF means that
+ * all the pages have been correctly erased).
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit,
+ uint32_t *PageError) {
+ HAL_StatusTypeDef status;
+ uint32_t page_index;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Deactivate the cache if they are activated to avoid data misbehavior */
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) {
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+ } else {
+ pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+ }
+ } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ } else {
+ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ }
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
+ /* Mass erase to be done */
+ FLASH_MassErase(pEraseInit->Banks);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+#if defined(FLASH_OPTR_DBANK)
+ /* If the erase operation is completed, disable the MER1 and MER2 Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+#else
+ /* If the erase operation is completed, disable the MER1 Bit */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
+#endif
+ } else {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFFU;
+
+ for (page_index = pEraseInit->Page;
+ page_index < (pEraseInit->Page + pEraseInit->NbPages);
+ page_index++) {
+ FLASH_PageErase(page_index, pEraseInit->Banks);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
+
+ if (status != HAL_OK) {
+ /* In case of error, stop erase procedure and return the faulty page
+ */
+ *PageError = page_index;
+ break;
+ }
+ }
+ }
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages with
+ * interrupt enabled.
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Deactivate the cache if they are activated to avoid data misbehavior */
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) {
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+ } else {
+ pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+ }
+ } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ } else {
+ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ }
+
+ /* Enable End of Operation and Error interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ pFlash.Bank = pEraseInit->Banks;
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
+ /* Mass erase to be done */
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
+ FLASH_MassErase(pEraseInit->Banks);
+ } else {
+ /* Erase by page to be done */
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
+ pFlash.NbPagesToErase = pEraseInit->NbPages;
+ pFlash.Page = pEraseInit->Page;
+
+ /*Erase 1st page and wait for IT */
+ FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program Option bytes.
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @retval HAL_Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Write protection configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) {
+ /* Configure of Write protection on the selected area */
+ if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset,
+ pOBInit->WRPEndOffset) != HAL_OK) {
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Read protection configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) {
+ /* Configure the Read protection level */
+ if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) {
+ status = HAL_ERROR;
+ }
+ }
+
+ /* User Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) {
+ /* Configure the user option bytes */
+ if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) {
+ status = HAL_ERROR;
+ }
+ }
+
+ /* PCROP Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) {
+ if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) {
+ /* Configure the Proprietary code readout protection */
+ if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr,
+ pOBInit->PCROPEndAddr) != HAL_OK) {
+ status = HAL_ERROR;
+ }
+ }
+ }
+
+ /* Securable memory Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U) {
+ /* Configure the securable memory area */
+ if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK) {
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Boot Entry Point Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) {
+ /* Configure the boot unique entry point option */
+ if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK) {
+ status = HAL_ERROR;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option bytes configuration.
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
+ * configuration information.
+ * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
+ * which area is requested for the WRP and PCROP, else no information
+ * will be returned.
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) {
+ pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+
+#if defined(FLASH_OPTR_DBANK)
+ if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) ||
+ (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
+ (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) ||
+ (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
+#else
+ if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) ||
+ (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
+#endif
+ {
+ pOBInit->OptionType |= OPTIONBYTE_WRP;
+ /* Get write protection on the selected area */
+ FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset),
+ &(pOBInit->WRPEndOffset));
+ }
+
+ /* Get Read protection level */
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /* Get the user option bytes */
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+
+#if defined(FLASH_OPTR_DBANK)
+ if ((pOBInit->PCROPConfig == FLASH_BANK_1) ||
+ (pOBInit->PCROPConfig == FLASH_BANK_2))
+#else
+ if (pOBInit->PCROPConfig == FLASH_BANK_1)
+#endif
+ {
+ pOBInit->OptionType |= OPTIONBYTE_PCROP;
+ /* Get the Proprietary code readout protection */
+ FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr),
+ &(pOBInit->PCROPEndAddr));
+ }
+
+ pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
+
+ /* Get the boot entry point */
+ pOBInit->BootEntryPoint = FLASH_OB_GetBootLock();
+
+ /* Get the securable memory area configuration */
+#if defined(FLASH_OPTR_DBANK)
+ if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2))
+#else
+ if (pOBInit->SecBank == FLASH_BANK_1)
+#endif
+ {
+ pOBInit->OptionType |= OPTIONBYTE_SEC;
+ FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
+ }
+}
+
+/**
+ * @brief Enable the FLASH Securable Memory protection.
+ * @param Bank: Bank to be protected
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be protected
+ * @arg FLASH_BANK_2: Bank2 to be protected (*)
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*)
+ * @note (*) availability depends on devices
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) {
+#if defined(FLASH_OPTR_DBANK)
+ if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) {
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Bank));
+
+ /* Enable the Securable Memory Protection Bit for the bank 1 if requested */
+ if ((Bank & FLASH_BANK_1) != 0U) {
+ SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+ }
+
+ /* Enable the Securable Memory Protection Bit for the bank 2 if requested */
+ if ((Bank & FLASH_BANK_2) != 0U) {
+ SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2);
+ }
+ } else {
+ SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+ }
+#else
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Bank);
+ SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+#endif /* FLASH_OPTR_DBANK */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable Debugger.
+ * @note After calling this API, flash interface allow debugger intrusion.
+ * @retval None
+ */
+void HAL_FLASHEx_EnableDebugger(void) { FLASH->ACR |= FLASH_ACR_DBG_SWEN; }
+
+/**
+ * @brief Disable Debugger.
+ * @note After calling this API, Debugger is disabled: it's no more possible
+ * to break, see CPU register, etc...
+ * @retval None
+ */
+void HAL_FLASHEx_DisableDebugger(void) { FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+/**
+ * @brief Mass erase of FLASH memory.
+ * @param Banks Banks to be erased.
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ * @arg FLASH_BANK_2: Bank2 to be erased (*)
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*)
+ * @note (*) availability depends on devices
+ * @retval None
+ */
+static void FLASH_MassErase(uint32_t Banks) {
+#if defined(FLASH_OPTR_DBANK)
+ if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
+#endif
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Set the Mass Erase Bit for the bank 1 if requested */
+ if ((Banks & FLASH_BANK_1) != 0U) {
+ SET_BIT(FLASH->CR, FLASH_CR_MER1);
+ }
+
+#if defined(FLASH_OPTR_DBANK)
+ /* Set the Mass Erase Bit for the bank 2 if requested */
+ if ((Banks & FLASH_BANK_2) != 0U) {
+ SET_BIT(FLASH->CR, FLASH_CR_MER2);
+ }
+#endif
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else {
+ SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+ }
+#endif
+
+ /* Proceed to erase all sectors */
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @brief Erase the specified FLASH memory page.
+ * @param Page FLASH page to erase.
+ * This parameter must be a value between 0 and (max number of pages in
+ * the bank - 1).
+ * @param Banks Bank where the page will be erased.
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Page in bank 1 to be erased
+ * @arg FLASH_BANK_2: Page in bank 2 to be erased (*)
+ * @note (*) availability depends on devices
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks) {
+ /* Check the parameters */
+ assert_param(IS_FLASH_PAGE(Page));
+
+#if defined(FLASH_OPTR_DBANK)
+ if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) {
+ CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+ } else {
+ assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+
+ if ((Banks & FLASH_BANK_1) != 0U) {
+ CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+ } else {
+ SET_BIT(FLASH->CR, FLASH_CR_BKER);
+ }
+ }
+#else
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Banks);
+#endif /* FLASH_OPTR_DBANK */
+
+ /* Proceed to erase the page */
+ MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @brief Flush the instruction and data caches.
+ * @retval None
+ */
+void FLASH_FlushCaches(void) {
+ FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
+
+ /* Flush instruction cache */
+ if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
+ (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) {
+ /* Disable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ /* Reset instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ /* Enable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+
+ /* Flush data cache */
+ if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
+ (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) {
+ /* Reset data cache */
+ __HAL_FLASH_DATA_CACHE_RESET();
+ /* Enable data cache */
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+ }
+
+ /* Reset internal variable */
+ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+}
+
+/**
+ * @brief Configure the write protection area into Option Bytes.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase Flash memory if the CPU debug
+ * features are connected (JTAG or single wire) or boot code is being
+ * executed from RAM or System flash, even if WRP is not activated.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @param WRPArea specifies the area to be configured.
+ * This parameter can be one of the following values:
+ * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+ * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+ * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*)
+ * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*)
+ * @note (*) availability depends on devices
+ * @param WRPStartOffset specifies the start page of the write protected area.
+ * This parameter can be page number between 0 and (max number of pages
+ * in the bank - 1).
+ * @param WRDPEndOffset specifies the end page of the write protected area.
+ * This parameter can be page number between WRPStartOffset and (max
+ * number of pages in the bank - 1).
+ * @retval HAL_Status
+ */
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea,
+ uint32_t WRPStartOffset,
+ uint32_t WRDPEndOffset) {
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRPAREA(WRPArea));
+ assert_param(IS_FLASH_PAGE(WRPStartOffset));
+ assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+ /* Configure the write protected area */
+ if (WRPArea == OB_WRPAREA_BANK1_AREAA) {
+ FLASH->WRP1AR =
+ ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
+ } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) {
+ FLASH->WRP1BR =
+ ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else if (WRPArea == OB_WRPAREA_BANK2_AREAA) {
+ FLASH->WRP2AR =
+ ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset);
+ } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) {
+ FLASH->WRP2BR =
+ ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
+ }
+#endif
+ else {
+ /* Nothing to do */
+ }
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set the read protection level into Option Bytes.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
+ * to go back to level 1 or 0 !!!
+ * @param RDPLevel specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Memory Read protection
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ *
+ * @retval HAL_Status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) {
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+ /* Configure the RDP level in the option bytes register */
+ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Bytes.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @param UserType The FLASH User Option Bytes to be modified.
+ * This parameter can be a combination of @ref FLASH_OB_USER_Type.
+ * @param UserConfig The selected User Option Bytes values:
+ * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+ * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY ,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+ * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+ * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
+ * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1,
+ * @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST,
+ * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+ * @ref FLASH_OB_USER_NRST_MODE, @ref
+ * FLASH_OB_USER_INTERNAL_RESET_HOLDER
+ * @note (*) availability depends on devices
+ * @retval HAL_Status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType,
+ uint32_t UserConfig) {
+ uint32_t optr_reg_val = 0;
+ uint32_t optr_reg_mask = 0;
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_OB_USER_TYPE(UserType));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+#if defined(FLASH_OPTR_PB4_PUPEN)
+ if ((UserType & OB_USER_PB4_PUPEN) != 0U) {
+ /* PB4_PUPEN option byte should be modified */
+ assert_param(IS_OB_USER_PB4_PUPEN(UserConfig & FLASH_OPTR_PB4_PUPEN));
+
+ /* Set value and mask for PB4_PUPEN option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_PB4_PUPEN);
+ optr_reg_mask |= FLASH_OPTR_PB4_PUPEN;
+ }
+#endif /* FLASH_OPTR_PB4_PUPEN */
+
+ if ((UserType & OB_USER_BOR_LEV) != 0U) {
+ /* BOR level option byte should be modified */
+ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
+
+ /* Set value and mask for BOR level option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
+ optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+ }
+
+ if ((UserType & OB_USER_nRST_STOP) != 0U) {
+ /* nRST_STOP option byte should be modified */
+ assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
+
+ /* Set value and mask for nRST_STOP option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
+ optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+ }
+
+ if ((UserType & OB_USER_nRST_STDBY) != 0U) {
+ /* nRST_STDBY option byte should be modified */
+ assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
+
+ /* Set value and mask for nRST_STDBY option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
+ optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+ }
+
+ if ((UserType & OB_USER_nRST_SHDW) != 0U) {
+ /* nRST_SHDW option byte should be modified */
+ assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
+
+ /* Set value and mask for nRST_SHDW option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
+ optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+ }
+
+ if ((UserType & OB_USER_IWDG_SW) != 0U) {
+ /* IWDG_SW option byte should be modified */
+ assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
+
+ /* Set value and mask for IWDG_SW option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
+ optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+ }
+
+ if ((UserType & OB_USER_IWDG_STOP) != 0U) {
+ /* IWDG_STOP option byte should be modified */
+ assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
+
+ /* Set value and mask for IWDG_STOP option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
+ optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+ }
+
+ if ((UserType & OB_USER_IWDG_STDBY) != 0U) {
+ /* IWDG_STDBY option byte should be modified */
+ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
+
+ /* Set value and mask for IWDG_STDBY option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
+ optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+ }
+
+ if ((UserType & OB_USER_WWDG_SW) != 0U) {
+ /* WWDG_SW option byte should be modified */
+ assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
+
+ /* Set value and mask for WWDG_SW option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
+ optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+ }
+
+#if defined(FLASH_OPTR_BFB2)
+ if ((UserType & OB_USER_BFB2) != 0U) {
+ /* BFB2 option byte should be modified */
+ assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
+
+ /* Set value and mask for BFB2 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
+ optr_reg_mask |= FLASH_OPTR_BFB2;
+ }
+#endif
+
+ if ((UserType & OB_USER_nBOOT1) != 0U) {
+ /* nBOOT1 option byte should be modified */
+ assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
+
+ /* Set value and mask for nBOOT1 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
+ optr_reg_mask |= FLASH_OPTR_nBOOT1;
+ }
+
+ if ((UserType & OB_USER_SRAM_PE) != 0U) {
+ /* SRAM_PE option byte should be modified */
+ assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE));
+
+ /* Set value and mask for SRAM_PE option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE);
+ optr_reg_mask |= FLASH_OPTR_SRAM_PE;
+ }
+ if ((UserType & OB_USER_CCMSRAM_RST) != 0U) {
+ /* CCMSRAM_RST option byte should be modified */
+ assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST));
+
+ /* Set value and mask for CCMSRAM_RST option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST);
+ optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
+ }
+ if ((UserType & OB_USER_nSWBOOT0) != 0U) {
+ /* nSWBOOT0 option byte should be modified */
+ assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
+
+ /* Set value and mask for nSWBOOT0 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
+ optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+ }
+
+ if ((UserType & OB_USER_nBOOT0) != 0U) {
+ /* nBOOT0 option byte should be modified */
+ assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
+
+ /* Set value and mask for nBOOT0 option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
+ optr_reg_mask |= FLASH_OPTR_nBOOT0;
+ }
+
+ if ((UserType & OB_USER_NRST_MODE) != 0U) {
+ /* Reset Configuration option byte should be modified */
+ assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE));
+
+ /* Set value and mask for Reset Configuration option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE);
+ optr_reg_mask |= FLASH_OPTR_NRST_MODE;
+ }
+
+ if ((UserType & OB_USER_IRHEN) != 0U) {
+ /* IRH option byte should be modified */
+ assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN));
+
+ /* Set value and mask for IRH option byte */
+ optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN);
+ optr_reg_mask |= FLASH_OPTR_IRHEN;
+ }
+
+ /* Configure the option bytes register */
+ MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the Proprietary code readout protection area into Option
+ * Bytes.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @param PCROPConfig specifies the configuration (Bank to be configured and
+ * PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1 or
+ * FLASH_BANK_2 (*) with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
+ * @note (*) availability depends on devices
+ * @param PCROPStartAddr specifies the start address of the Proprietary code
+ * readout protection. This parameter can be an address between begin and end of
+ * the bank.
+ * @param PCROPEndAddr specifies the end address of the Proprietary code
+ * readout protection. This parameter can be an address between PCROPStartAddr
+ * and end of the bank.
+ * @retval HAL_Status
+ */
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig,
+ uint32_t PCROPStartAddr,
+ uint32_t PCROPEndAddr) {
+ HAL_StatusTypeDef status;
+ uint32_t reg_value;
+ uint32_t bank1_addr;
+#if defined(FLASH_OPTR_DBANK)
+ uint32_t bank2_addr;
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
+ assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+#if defined(FLASH_OPTR_DBANK)
+ /* Get the information about the bank swapping */
+ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) {
+ bank1_addr = FLASH_BASE;
+ bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+ } else {
+ bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+ bank2_addr = FLASH_BASE;
+ }
+#else
+ bank1_addr = FLASH_BASE;
+#endif
+
+#if defined(FLASH_OPTR_DBANK)
+ if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) {
+ /* Configure the Proprietary code readout protection */
+ if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) {
+ reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
+ MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+
+ reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
+ MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+ } else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) {
+ reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
+ MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+
+ reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
+ MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+ } else {
+ /* Nothing to do */
+ }
+ } else
+#endif
+ {
+ /* Configure the Proprietary code readout protection */
+ if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) {
+ reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
+ MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+
+ reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
+ MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) {
+ reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
+ MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+
+ reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
+ MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+ }
+#endif
+ else {
+ /* Nothing to do */
+ }
+ }
+
+ MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP,
+ (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the Securable memory area into Option Bytes.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @param SecBank specifies bank of securable memory area to be configured.
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Securable memory in Bank1 to be configured
+ * @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*)
+ * @note (*) availability depends on devices
+ * @param SecSize specifies the number of pages of the Securable memory area,
+ * starting from first page of the bank.
+ * This parameter can be page number between 0 and (max number of pages
+ * in the bank - 1)
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank,
+ uint32_t SecSize) {
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank));
+ assert_param(IS_OB_SECMEM_SIZE(SecSize));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+ /* Configure the write protected area */
+ if (SecBank == FLASH_BANK_1) {
+ MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize);
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else if (SecBank == FLASH_BANK_2) {
+ MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize);
+ } else {
+ /* Nothing to do */
+ }
+#endif
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the Boot Lock into Option Bytes.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account in two
+ * cases:
+ * - after an option bytes launch through the call of
+ * HAL_FLASH_OB_Launch()
+ * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ * @param BootLockConfig specifies the boot lock configuration.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock
+ * @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock
+ *
+ * @retval HAL_Status
+ */
+static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig) {
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK) {
+ MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig);
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return the Securable memory area configuration into Option Bytes.
+ * @param[in] SecBank specifies the bank where securable memory area is
+ located.
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Securable memory in Bank1
+ * @arg FLASH_BANK_2: Securable memory in Bank2 (*)
+ * @note (*) availability depends on devices
+ * @param[out] SecSize specifies the number of pages used in the securable
+ memory area of the bank.
+ * @retval None
+ */
+static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize) {
+ /* Get the configuration of the securable memory area */
+ if (SecBank == FLASH_BANK_1) {
+ *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1);
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else if (SecBank == FLASH_BANK_2) {
+ *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2);
+ } else {
+ /* Nothing to do */
+ }
+#endif
+}
+
+/**
+ * @brief Return the Boot Lock configuration into Option Byte.
+ * @retval BootLockConfig.
+ * This return value can be one of the following values:
+ * @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled
+ * @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled
+ */
+static uint32_t FLASH_OB_GetBootLock(void) {
+ return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK);
+}
+
+/**
+ * @brief Return the Write Protection configuration into Option Bytes.
+ * @param[in] WRPArea specifies the area to be returned.
+ * This parameter can be one of the following values:
+ * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+ * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+ * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to
+ * STM32G43x/STM32G44x devices)
+ * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to
+ * STM32G43x/STM32G44x devices)
+ * @param[out] WRPStartOffset specifies the address where to copied the start
+ * page of the write protected area.
+ * @param[out] WRDPEndOffset specifies the address where to copied the end page
+ * of the write protected area.
+ * @retval None
+ */
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset,
+ uint32_t *WRDPEndOffset) {
+ /* Get the configuration of the write protected area */
+ if (WRPArea == OB_WRPAREA_BANK1_AREAA) {
+ *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
+ *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >>
+ FLASH_WRP1AR_WRP1A_END_Pos);
+ } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) {
+ *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
+ *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >>
+ FLASH_WRP1BR_WRP1B_END_Pos);
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else if (WRPArea == OB_WRPAREA_BANK2_AREAA) {
+ *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
+ *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >>
+ FLASH_WRP2AR_WRP2A_END_Pos);
+ } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) {
+ *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
+ *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >>
+ FLASH_WRP2BR_WRP2B_END_Pos);
+ }
+#endif
+ else {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief Return the FLASH Read Protection level into Option Bytes.
+ * @retval RDP_Level
+ * This return value can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ */
+static uint32_t FLASH_OB_GetRDP(void) {
+ uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
+
+ if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) {
+ return (OB_RDP_LEVEL_1);
+ } else {
+ return rdp_level;
+ }
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval OB_user_config
+ * This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+ * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+ * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+ * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
+ * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*),
+ * @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
+ * @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref
+ * FLASH_OB_USER_nBOOT0,
+ * @ref FLASH_OB_USER_NRST_MODE, @ref
+ * FLASH_OB_USER_INTERNAL_RESET_HOLDER
+ * @note (*) availability depends on devices
+ */
+static uint32_t FLASH_OB_GetUser(void) {
+ uint32_t user_config = READ_REG(FLASH->OPTR);
+ CLEAR_BIT(user_config, FLASH_OPTR_RDP);
+
+ return user_config;
+}
+
+/**
+ * @brief Return the FLASH PCROP configuration into Option Bytes.
+ * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured
+ * and PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1
+ * or FLASH_BANK_2 with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
+ * @param[out] PCROPStartAddr specifies the address where to copied the start
+ * address of the Proprietary code readout protection.
+ * @param[out] PCROPEndAddr specifies the address where to copied the end
+ * address of the Proprietary code readout protection.
+ * @retval None
+ */
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,
+ uint32_t *PCROPEndAddr) {
+ uint32_t reg_value;
+ uint32_t bank1_addr;
+#if defined(FLASH_OPTR_DBANK)
+ uint32_t bank2_addr;
+
+ /* Get the information about the bank swapping */
+ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) {
+ bank1_addr = FLASH_BASE;
+ bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+ } else {
+ bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+ bank2_addr = FLASH_BASE;
+ }
+#else
+ bank1_addr = FLASH_BASE;
+#endif
+
+#if defined(FLASH_OPTR_DBANK)
+ if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) {
+ if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) {
+ reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+ *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
+
+ reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+ *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
+ } else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) {
+ reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+ *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
+
+ reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+ *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
+ } else {
+ /* Nothing to do */
+ }
+ } else
+#endif
+ {
+ if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) {
+ reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+ *PCROPStartAddr = (reg_value << 3) + bank1_addr;
+
+ reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+ *PCROPEndAddr = (reg_value << 3) + bank1_addr;
+ }
+#if defined(FLASH_OPTR_DBANK)
+ else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) {
+ reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+ *PCROPStartAddr = (reg_value << 3) + bank2_addr;
+
+ reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+ *PCROPEndAddr = (reg_value << 3) + bank2_addr;
+ }
+#endif
+ else {
+ /* Nothing to do */
+ }
+ }
+
+ *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c
index 6dc98e2..b92d3db 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c
@@ -1,246 +1,246 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_flash_ramfunc.c
- * @author MCD Application Team
- * @brief FLASH RAMFUNC driver.
- * This file provides a Flash firmware functions which should be
- * executed from internal SRAM
- * + FLASH Power Down in Run mode
- * + FLASH DBANK User Option Byte
- *
- *
- @verbatim
- ==============================================================================
- ##### Flash RAM functions #####
- ==============================================================================
-
- *** ARM Compiler ***
- --------------------
- [..] RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate
- source module. Using the 'Options for File' dialog you can simply
- change the 'Code / Const' area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the
- Options for Target' dialog.
-
- *** ICCARM Compiler ***
- -----------------------
- [..] RAM functions are defined using a specific toolchain keyword
- "__ramfunc".
-
- *** GNU Compiler ***
- --------------------
- [..] RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
- * @brief FLASH functions executed from RAM
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features
-functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### ramfunc functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions that should be executed from
-RAM.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the Power down in Run Mode
- * @note This function should be called and executed from SRAM memory.
- * @retval None
- */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) {
- /* Enable the Power Down in Run mode*/
- __HAL_FLASH_POWER_DOWN_ENABLE();
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Power down in Run Mode
- * @note This function should be called and executed from SRAM memory.
- * @retval None
- */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) {
- /* Disable the Power Down in Run mode*/
- __HAL_FLASH_POWER_DOWN_DISABLE();
-
- return HAL_OK;
-}
-
-#if defined(FLASH_OPTR_DBANK)
-/**
- * @brief Program the FLASH DBANK User Option Byte.
- *
- * @note To configure the user option bytes, the option lock bit OPTLOCK must
- * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To modify the DBANK option byte, no PCROP region should be defined.
- * To deactivate PCROP, user should perform RDP changing.
- *
- * @param DBankConfig The FLASH DBANK User Option Byte value.
- * This parameter can be one of the following values:
- * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
- * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
- *
- * @retval HAL_Status
- */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) {
- uint32_t count, reg;
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check if the PCROP is disabled */
- reg = FLASH->PCROP1SR;
- if (reg > FLASH->PCROP1ER) {
- reg = FLASH->PCROP2SR;
- if (reg > FLASH->PCROP2ER) {
- /* Disable Flash prefetch */
- __HAL_FLASH_PREFETCH_BUFFER_DISABLE();
-
- if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) {
- /* Disable Flash instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
- /* Flush Flash instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_RESET();
- }
-
- if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
- /* Disable Flash data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
-
- /* Flush Flash data cache */
- __HAL_FLASH_DATA_CACHE_RESET();
- }
-
- /* Disable WRP zone A of 1st bank if needed */
- reg = FLASH->WRP1AR;
- if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
- ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) {
- MODIFY_REG(FLASH->WRP1AR,
- (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
- FLASH_WRP1AR_WRP1A_STRT);
- }
-
- /* Disable WRP zone B of 1st bank if needed */
- reg = FLASH->WRP1BR;
- if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
- ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) {
- MODIFY_REG(FLASH->WRP1BR,
- (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
- FLASH_WRP1BR_WRP1B_STRT);
- }
-
- /* Disable WRP zone A of 2nd bank if needed */
- reg = FLASH->WRP2AR;
- if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
- ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) {
- MODIFY_REG(FLASH->WRP2AR,
- (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
- FLASH_WRP2AR_WRP2A_STRT);
- }
-
- /* Disable WRP zone B of 2nd bank if needed */
- reg = FLASH->WRP2BR;
- if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
- ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) {
- MODIFY_REG(FLASH->WRP2BR,
- (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
- FLASH_WRP2BR_WRP2B_STRT);
- }
-
- /* Modify the DBANK user option byte */
- MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- /* 8 is the number of required instruction cycles for the below loop
- * statement (timeout expressed in ms) */
- count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
- do {
- if (count == 0U) {
- break;
- }
- count--;
- } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
-
- /* If the option byte program operation is completed, disable the OPTSTRT
- * Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Set the bit to force the option byte reloading */
- SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_flash_ramfunc.c
+ * @author MCD Application Team
+ * @brief FLASH RAMFUNC driver.
+ * This file provides a Flash firmware functions which should be
+ * executed from internal SRAM
+ * + FLASH Power Down in Run mode
+ * + FLASH DBANK User Option Byte
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash RAM functions #####
+ ==============================================================================
+
+ *** ARM Compiler ***
+ --------------------
+ [..] RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate
+ source module. Using the 'Options for File' dialog you can simply
+ change the 'Code / Const' area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the
+ Options for Target' dialog.
+
+ *** ICCARM Compiler ***
+ -----------------------
+ [..] RAM functions are defined using a specific toolchain keyword
+ "__ramfunc".
+
+ *** GNU Compiler ***
+ --------------------
+ [..] RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
+ * @brief FLASH functions executed from RAM
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features
+functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### ramfunc functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions that should be executed from
+RAM.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the Power down in Run Mode
+ * @note This function should be called and executed from SRAM memory.
+ * @retval None
+ */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) {
+ /* Enable the Power Down in Run mode*/
+ __HAL_FLASH_POWER_DOWN_ENABLE();
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Power down in Run Mode
+ * @note This function should be called and executed from SRAM memory.
+ * @retval None
+ */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) {
+ /* Disable the Power Down in Run mode*/
+ __HAL_FLASH_POWER_DOWN_DISABLE();
+
+ return HAL_OK;
+}
+
+#if defined(FLASH_OPTR_DBANK)
+/**
+ * @brief Program the FLASH DBANK User Option Byte.
+ *
+ * @note To configure the user option bytes, the option lock bit OPTLOCK must
+ * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+ * @note To modify the DBANK option byte, no PCROP region should be defined.
+ * To deactivate PCROP, user should perform RDP changing.
+ *
+ * @param DBankConfig The FLASH DBANK User Option Byte value.
+ * This parameter can be one of the following values:
+ * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
+ * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
+ *
+ * @retval HAL_Status
+ */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) {
+ uint32_t count, reg;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check if the PCROP is disabled */
+ reg = FLASH->PCROP1SR;
+ if (reg > FLASH->PCROP1ER) {
+ reg = FLASH->PCROP2SR;
+ if (reg > FLASH->PCROP2ER) {
+ /* Disable Flash prefetch */
+ __HAL_FLASH_PREFETCH_BUFFER_DISABLE();
+
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) {
+ /* Disable Flash instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+
+ /* Flush Flash instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ }
+
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) {
+ /* Disable Flash data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+
+ /* Flush Flash data cache */
+ __HAL_FLASH_DATA_CACHE_RESET();
+ }
+
+ /* Disable WRP zone A of 1st bank if needed */
+ reg = FLASH->WRP1AR;
+ if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
+ ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) {
+ MODIFY_REG(FLASH->WRP1AR,
+ (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
+ FLASH_WRP1AR_WRP1A_STRT);
+ }
+
+ /* Disable WRP zone B of 1st bank if needed */
+ reg = FLASH->WRP1BR;
+ if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
+ ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) {
+ MODIFY_REG(FLASH->WRP1BR,
+ (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
+ FLASH_WRP1BR_WRP1B_STRT);
+ }
+
+ /* Disable WRP zone A of 2nd bank if needed */
+ reg = FLASH->WRP2AR;
+ if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
+ ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) {
+ MODIFY_REG(FLASH->WRP2AR,
+ (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
+ FLASH_WRP2AR_WRP2A_STRT);
+ }
+
+ /* Disable WRP zone B of 2nd bank if needed */
+ reg = FLASH->WRP2BR;
+ if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
+ ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) {
+ MODIFY_REG(FLASH->WRP2BR,
+ (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
+ FLASH_WRP2BR_WRP2B_STRT);
+ }
+
+ /* Modify the DBANK user option byte */
+ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
+
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ /* 8 is the number of required instruction cycles for the below loop
+ * statement (timeout expressed in ms) */
+ count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
+ do {
+ if (count == 0U) {
+ break;
+ }
+ count--;
+ } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
+
+ /* If the option byte program operation is completed, disable the OPTSTRT
+ * Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Set the bit to force the option byte reloading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
index 9919b35..5157c50 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
@@ -1,523 +1,523 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_gpio.c
- * @author MCD Application Team
- * @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO)
- peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral features #####
- ==============================================================================
- [..]
- (+) Each port bit of the general-purpose I/O (GPIO) ports can be
- individually configured by software in several modes:
- (++) Input mode
- (++) Analog mode
- (++) Output mode
- (++) Alternate function mode
- (++) External interrupt/event lines
-
- (+) During and just after reset, the alternate functions and external
- interrupt lines are not active and the I/O ports are configured in input
- floating mode.
-
- (+) All GPIO pins have weak internal pull-up and pull-down resistors, which
- can be activated or not.
-
- (+) In Output or Alternate mode, each IO can be configured on open-drain or
- push-pull type and the IO speed can be selected depending on the VDD value.
-
- (+) The microcontroller IO pins are connected to onboard peripherals/modules
- through a multiplexer that allows only one peripheral alternate function (AF)
- connected to an IO pin at a time. In this way, there can be no conflict
- between peripherals sharing the same IO pin.
-
- (+) All ports have external interrupt/event capability. To use external
- interrupt lines, the port must be configured in input mode. All available GPIO
- pins are connected to the 16 external interrupt/event lines from EXTI0 to
- EXTI15.
-
- (+) The external interrupt/event controller consists of up to 44 edge
- detectors (16 lines are connected to GPIO) for generating event/interrupt
- requests (each input line can be independently configured to select the type
- (interrupt or event) and the corresponding trigger event (rising or falling or
- both). Each line can also be masked independently.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the GPIO AHB clock using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE().
-
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef
- structure
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from
- GPIO_InitTypeDef structure.
- (++) In case of Output or alternate function mode selection: the speed
- is configured through "Speed" member from GPIO_InitTypeDef structure.
- (++) In alternate mode is selection, the alternate function connected to
- the IO is configured through "Alternate" member from GPIO_InitTypeDef
- structure.
- (++) Analog mode is required when a pin is to be used as ADC channel
- or DAC output.
- (++) In case of external interrupt/event selection the "Mode" member
- from GPIO_InitTypeDef structure select the type (interrupt or event) and the
- corresponding trigger event (rising or falling or both).
-
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ
- priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it
- using HAL_NVIC_EnableIRQ().
-
- (#) To get the level of a pin configured in input mode use
- HAL_GPIO_ReadPin().
-
- (#) To set/reset the level of a pin configured in output mode use
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except
- JTAG pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general
- purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE
- has priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PF0 and PF1, respectively, when the HSE oscillator is
- off. The HSE has priority over the GPIO function.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-/** MISRA C:2012 deviation rule has been granted for following rules:
- * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
- * range of the shift operator in following API :
- * HAL_GPIO_Init
- * HAL_GPIO_DeInit
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_NUMBER (16U)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup GPIO_Exported_Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization
-functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the GPIOx peripheral according to the specified parameters
- * in the GPIO_Init.
- * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
- * STM32G4xx family
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
- uint32_t position = 0x00U;
- uint32_t iocurrent;
- uint32_t temp;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
- /* Configure the port pins */
- while (((GPIO_Init->Pin) >> position) != 0U) {
- /* Get current io position */
- iocurrent = (GPIO_Init->Pin) & (1UL << position);
-
- if (iocurrent != 0x00u) {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Output or Alternate function mode selection */
- if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
- ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
- temp |= (GPIO_Init->Speed << (position * 2U));
- GPIOx->OSPEEDR = temp;
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- temp &= ~(GPIO_OTYPER_OT0 << position);
- temp |=
- (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
- GPIOx->OTYPER = temp;
- }
-
- if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) {
- /* Check the Pull parameter */
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
- temp |= ((GPIO_Init->Pull) << (position * 2U));
- GPIOx->PUPDR = temp;
- }
-
- /* In case of Alternate function mode selection */
- if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3U];
- temp &= ~(0xFU << ((position & 0x07U) * 4U));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3U] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- GPIOx->MODER = temp;
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- temp = SYSCFG->EXTICR[position >> 2U];
- temp &= ~(0x0FUL << (4U * (position & 0x03U)));
- temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
- SYSCFG->EXTICR[position >> 2U] = temp;
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) {
- temp |= iocurrent;
- }
- EXTI->RTSR1 = temp;
-
- temp = EXTI->FTSR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) {
- temp |= iocurrent;
- }
- EXTI->FTSR1 = temp;
-
- temp = EXTI->EMR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) {
- temp |= iocurrent;
- }
- EXTI->EMR1 = temp;
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) {
- temp |= iocurrent;
- }
- EXTI->IMR1 = temp;
- }
- }
-
- position++;
- }
-}
-
-/**
- * @brief De-initialize the GPIOx peripheral registers to their default reset
- * values.
- * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
- * STM32G4xx family
- * @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_PIN_x where x can be
- * (0..15).
- * @retval None
- */
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) {
- uint32_t position = 0x00U;
- uint32_t iocurrent;
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Configure the port pins */
- while ((GPIO_Pin >> position) != 0U) {
- /* Get current io position */
- iocurrent = (GPIO_Pin) & (1UL << position);
-
- if (iocurrent != 0x00u) {
- /*------------------------- EXTI Mode Configuration --------------------*/
- /* Clear the External Interrupt or Event for the current IO */
-
- tmp = SYSCFG->EXTICR[position >> 2U];
- tmp &= (0x0FUL << (4U * (position & 0x03U)));
- if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) {
- /* Clear EXTI line configuration */
- EXTI->IMR1 &= ~(iocurrent);
- EXTI->EMR1 &= ~(iocurrent);
-
- /* Clear Rising Falling edge configuration */
- EXTI->FTSR1 &= ~(iocurrent);
- EXTI->RTSR1 &= ~(iocurrent);
-
- tmp = 0x0FUL << (4U * (position & 0x03U));
- SYSCFG->EXTICR[position >> 2U] &= ~tmp;
- }
-
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO in Analog Mode */
- GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
-
- /* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
-
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position);
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
- }
-
- position++;
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read the specified input port pin.
- * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
- * STM32G4xx family
- * @param GPIO_Pin specifies the port bit to read.
- * This parameter can be any combination of GPIO_PIN_x where x can be
- * (0..15).
- * @retval The input port pin value.
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
- GPIO_PinState bitstatus;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != 0x00U) {
- bitstatus = GPIO_PIN_SET;
- } else {
- bitstatus = GPIO_PIN_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Set or clear the selected data port bit.
- *
- * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic
- * read/modify accesses. In this way, there is no risk of an IRQ occurring
- * between the read and the modify access.
- *
- * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
- * STM32G4xx family
- * @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_PIN_x where x can be
- * (0..15).
- * @param PinState specifies the value to be written to the selected bit.
- * This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
- GPIO_PinState PinState) {
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if (PinState != GPIO_PIN_RESET) {
- GPIOx->BSRR = (uint32_t)GPIO_Pin;
- } else {
- GPIOx->BRR = (uint32_t)GPIO_Pin;
- }
-}
-
-/**
- * @brief Toggle the specified GPIO pin.
- * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
- * STM32G4xx family
- * @param GPIO_Pin specifies the pin to be toggled.
- * This parameter can be any combination of GPIO_PIN_x where x can be
- * (0..15).
- * @retval None
- */
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
- uint32_t odr;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* get current Output Data Register value */
- odr = GPIOx->ODR;
-
- /* Set selected pins that were at low level, and reset ones that were high */
- GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
-}
-
-/**
- * @brief Lock GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
- * STM32G4xx family
- * @param GPIO_Pin specifies the port bits to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be
- * (0..15).
- * @retval None
- */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
- __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Apply lock key write sequence */
- tmp |= GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Read LCKK register. This read is mandatory to complete key lock sequence */
- tmp = GPIOx->LCKR;
-
- /* read again in order to confirm lock is active */
- if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) {
- return HAL_OK;
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) {
- /* EXTI line interrupt detected */
- if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- }
-}
-
-/**
- * @brief EXTI line detection callback.
- * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI
- * line.
- * @retval None
- */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(GPIO_Pin);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO)
+ peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be
+ individually configured by software in several modes:
+ (++) Input mode
+ (++) Analog mode
+ (++) Output mode
+ (++) Alternate function mode
+ (++) External interrupt/event lines
+
+ (+) During and just after reset, the alternate functions and external
+ interrupt lines are not active and the I/O ports are configured in input
+ floating mode.
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which
+ can be activated or not.
+
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or
+ push-pull type and the IO speed can be selected depending on the VDD value.
+
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules
+ through a multiplexer that allows only one peripheral alternate function (AF)
+ connected to an IO pin at a time. In this way, there can be no conflict
+ between peripherals sharing the same IO pin.
+
+ (+) All ports have external interrupt/event capability. To use external
+ interrupt lines, the port must be configured in input mode. All available GPIO
+ pins are connected to the 16 external interrupt/event lines from EXTI0 to
+ EXTI15.
+
+ (+) The external interrupt/event controller consists of up to 44 edge
+ detectors (16 lines are connected to GPIO) for generating event/interrupt
+ requests (each input line can be independently configured to select the type
+ (interrupt or event) and the corresponding trigger event (rising or falling or
+ both). Each line can also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef
+ structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from
+ GPIO_InitTypeDef structure.
+ (++) In case of Output or alternate function mode selection: the speed
+ is configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to
+ the IO is configured through "Alternate" member from GPIO_InitTypeDef
+ structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member
+ from GPIO_InitTypeDef structure select the type (interrupt or event) and the
+ corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ
+ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it
+ using HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use
+ HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except
+ JTAG pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general
+ purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE
+ has priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PF0 and PF1, respectively, when the HSE oscillator is
+ off. The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+ * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+ * range of the shift operator in following API :
+ * HAL_GPIO_Init
+ * HAL_GPIO_DeInit
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+#define GPIO_NUMBER (16U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization
+functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the GPIOx peripheral according to the specified parameters
+ * in the GPIO_Init.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
+ * STM32G4xx family
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
+ uint32_t position = 0x00U;
+ uint32_t iocurrent;
+ uint32_t temp;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+ /* Configure the port pins */
+ while (((GPIO_Init->Pin) >> position) != 0U) {
+ /* Get current io position */
+ iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+ if (iocurrent != 0x00u) {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Output or Alternate function mode selection */
+ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+ temp |= (GPIO_Init->Speed << (position * 2U));
+ GPIOx->OSPEEDR = temp;
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT0 << position);
+ temp |=
+ (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ GPIOx->OTYPER = temp;
+ }
+
+ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) {
+ /* Check the Pull parameter */
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
+ GPIOx->PUPDR = temp;
+ }
+
+ /* In case of Alternate function mode selection */
+ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ temp = SYSCFG->EXTICR[position >> 2U];
+ temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ SYSCFG->EXTICR[position >> 2U] = temp;
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) {
+ temp |= iocurrent;
+ }
+ EXTI->RTSR1 = temp;
+
+ temp = EXTI->FTSR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) {
+ temp |= iocurrent;
+ }
+ EXTI->FTSR1 = temp;
+
+ temp = EXTI->EMR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) {
+ temp |= iocurrent;
+ }
+ EXTI->EMR1 = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) {
+ temp |= iocurrent;
+ }
+ EXTI->IMR1 = temp;
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @brief De-initialize the GPIOx peripheral registers to their default reset
+ * values.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
+ * STM32G4xx family
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) {
+ uint32_t position = 0x00U;
+ uint32_t iocurrent;
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U) {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1UL << position);
+
+ if (iocurrent != 0x00u) {
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+
+ tmp = SYSCFG->EXTICR[position >> 2U];
+ tmp &= (0x0FUL << (4U * (position & 0x03U)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) {
+ /* Clear EXTI line configuration */
+ EXTI->IMR1 &= ~(iocurrent);
+ EXTI->EMR1 &= ~(iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->FTSR1 &= ~(iocurrent);
+ EXTI->RTSR1 &= ~(iocurrent);
+
+ tmp = 0x0FUL << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+ }
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO in Analog Mode */
+ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position);
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the specified input port pin.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
+ * STM32G4xx family
+ * @param GPIO_Pin specifies the port bit to read.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != 0x00U) {
+ bitstatus = GPIO_PIN_SET;
+ } else {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Set or clear the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic
+ * read/modify accesses. In this way, there is no risk of an IRQ occurring
+ * between the read and the modify access.
+ *
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
+ * STM32G4xx family
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15).
+ * @param PinState specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
+ GPIO_PinState PinState) {
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if (PinState != GPIO_PIN_RESET) {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ } else {
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Toggle the specified GPIO pin.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
+ * STM32G4xx family
+ * @param GPIO_Pin specifies the pin to be toggled.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15).
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
+ uint32_t odr;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* get current Output Data Register value */
+ odr = GPIOx->ODR;
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+ * @brief Lock GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral for
+ * STM32G4xx family
+ * @param GPIO_Pin specifies the port bits to be locked.
+ * This parameter can be any combination of GPIO_PIN_x where x can be
+ * (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */
+ tmp = GPIOx->LCKR;
+
+ /* read again in order to confirm lock is active */
+ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) {
+ return HAL_OK;
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) {
+ /* EXTI line interrupt detected */
+ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI
+ * line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c
new file mode 100644
index 0000000..f557325
--- /dev/null
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c
@@ -0,0 +1,271 @@
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Start functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+
+ (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+ active even if the main clock fails.
+
+ (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+ disabled. The counter starts counting down from the reset value (0xFFF).
+ When it reaches the end of count value (0x000) a reset signal is
+ generated (IWDG reset).
+
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ the IWDG_RLR value is reloaded into the counter and the watchdog reset
+ is prevented.
+
+ (+) The IWDG is implemented in the VDD voltage domain that is still
+ functional in STOP and STANDBY mode (IWDG reset can wake up the CPU from
+ STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ (+) Debug mode: When the microcontroller enters debug mode (core halted),
+ the IWDG counter either continues to work normally or stops, depending
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+ The IWDG timeout may vary due to LSI clock frequency dispersion.
+ STM32G4xx devices provide the capability to measure the LSI clock
+ frequency (LSI clock is internally connected to TIM16 CH1 input
+ capture). The measured value can be used to have an IWDG timeout with an
+ acceptable accuracy.
+
+ [..] Default timeout value (necessary for IWDG_SR status register update):
+ Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+ This frequency being subject to variations as mentioned above, the
+ default timeout value (defined through constant
+ HAL_IWDG_DEFAULT_TIMEOUT below) may become too short or too long. In such
+ cases, this default timeout value can be tuned by redefining the constant
+ LSI_VALUE at user-application level (based, for instance, on the measured LSI
+ clock frequency as explained above).
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts counting down.
+ (++) Enable write access to configuration registers:
+ IWDG_PR, IWDG_RLR and IWDG_WINR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
+ reloaded, then the IWDG will start counting down from this value.
+ (++) Depending on window parameter:
+ (+++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function with exact time base.
+ (+++) Else modify Window register. This will automatically reload
+ watchdog counter.
+ (++) Wait for status flags to be reset.
+
+ (#) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver:
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+ the reload register
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+/* Status register needs up to 5 LSI clock periods divided by the clock
+ prescaler to be updated. The number of LSI clock periods is upper-rounded to
+ 6 for the timeout value calculation.
+ The timeout value is calculated using the highest prescaler (256) and
+ the LSI_VALUE constant. The value of this constant can be changed by the user
+ to take into account possible LSI clock period variations.
+ The timeout value is multiplied by 1000 to be converted in milliseconds.
+ LSI startup time is also considered here by adding LSI_STARTUP_TIME
+ converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT \
+ (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @brief Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Start functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters in the
+ IWDG_InitTypeDef of associated handle.
+ (+) Manage Window option.
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ is reloaded in order to exit function with correct time base.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * watchdog is refreshed in order to have correct time base.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) {
+ uint32_t tickstart;
+
+ /* Check the IWDG handle allocation */
+ if (hiwdg == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+ /* Enable IWDG. LSI is turned on automatically */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+ 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the Prescaler & Reload values to work with */
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+ /* Check pending flag, if previous update not done, return timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) {
+ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) {
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* If window parameter is different than current value, modify window
+ register */
+ if (hiwdg->Instance->WINR != hiwdg->Init.Window) {
+ /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+ even if window feature is disabled, Watchdog will be reloaded by writing
+ windows register */
+ hiwdg->Instance->WINR = hiwdg->Init.Window;
+ } else {
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the IWDG.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) {
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c
index 2743e84..46349eb 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c
@@ -1,2029 +1,2061 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pcd.c
- * @author MCD Application Team
- * @brief PCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The PCD HAL driver can be used as follows:
-
- (#) Declare a PCD_HandleTypeDef handle structure, for example:
- PCD_HandleTypeDef hpcd;
-
- (#) Fill parameters of Init structure in HCD handle
-
- (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device
- core, ...)
-
- (#) Initialize the PCD low level resources through the HAL_PCD_MspInit()
- API:
- (##) Enable the PCD/USB Low Level interface clock using
- (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS
- peripheral
-
- (##) Initialize the related GPIO clocks
- (##) Configure PCD pin-out
- (##) Configure PCD NVIC interrupt
-
- (#)Associate the Upper USB device stack to the HAL PCD Driver:
- (##) hpcd.pData = pdev;
-
- (#)Enable PCD transmission and reception:
- (##) HAL_PCD_Start();
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCD PCD
- * @brief PCD HAL module driver
- * @{
- */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(USB)
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
- * @{
- */
-
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-#if (USE_USB_DOUBLE_BUFFER == 1U)
-static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
- PCD_EPTypeDef *ep,
- uint16_t wEPVal);
-static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
- PCD_EPTypeDef *ep, uint16_t wEPVal);
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization
-functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and initialize the associated
- * handle.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) {
- uint8_t i;
-
- /* Check the PCD handle allocation */
- if (hpcd == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
- if (hpcd->State == HAL_PCD_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- hpcd->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SOFCallback = HAL_PCD_SOFCallback;
- hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
- hpcd->ResetCallback = HAL_PCD_ResetCallback;
- hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
- hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
- hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
- hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
- hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
- hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
- hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
- hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
- hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
- hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
-
- if (hpcd->MspInitCallback == NULL) {
- hpcd->MspInitCallback = HAL_PCD_MspInit;
- }
-
- /* Init the low level hardware */
- hpcd->MspInitCallback(hpcd);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
-#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
-
- /* Init endpoints structures */
- for (i = 0U; i < hpcd->Init.dev_endpoints; i++) {
- /* Init ep structure */
- hpcd->IN_ep[i].is_in = 1U;
- hpcd->IN_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is activated */
- hpcd->IN_ep[i].type = EP_TYPE_CTRL;
- hpcd->IN_ep[i].maxpacket = 0U;
- hpcd->IN_ep[i].xfer_buff = 0U;
- hpcd->IN_ep[i].xfer_len = 0U;
- }
-
- for (i = 0U; i < hpcd->Init.dev_endpoints; i++) {
- hpcd->OUT_ep[i].is_in = 0U;
- hpcd->OUT_ep[i].num = i;
- /* Control until ep is activated */
- hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
- hpcd->OUT_ep[i].maxpacket = 0U;
- hpcd->OUT_ep[i].xfer_buff = 0U;
- hpcd->OUT_ep[i].xfer_len = 0U;
- }
-
- /* Init Device */
- (void)USB_DevInit(hpcd->Instance, hpcd->Init);
-
- hpcd->USB_Address = 0U;
- hpcd->State = HAL_PCD_STATE_READY;
-
- /* Activate LPM */
- if (hpcd->Init.lpm_enable == 1U) {
- (void)HAL_PCDEx_ActivateLPM(hpcd);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the PCD peripheral.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) {
- /* Check the PCD handle allocation */
- if (hpcd == NULL) {
- return HAL_ERROR;
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Stop Device */
- if (USB_StopDevice(hpcd->Instance) != HAL_OK) {
- return HAL_ERROR;
- }
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- if (hpcd->MspDeInitCallback == NULL) {
- hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware */
- hpcd->MspDeInitCallback(hpcd);
-#else
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_PCD_MspDeInit(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- hpcd->State = HAL_PCD_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the PCD MSP.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes PCD MSP.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implemented in the user file
- */
-}
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/**
- * @brief Register a User USB PCD Callback
- * To be used instead of the weak predefined callback
- * @param hpcd USB PCD handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
- * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
- * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
- * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
- * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
- * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
- * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
- * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
- pPCD_CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- switch (CallbackID) {
- case HAL_PCD_SOF_CB_ID:
- hpcd->SOFCallback = pCallback;
- break;
-
- case HAL_PCD_SETUPSTAGE_CB_ID:
- hpcd->SetupStageCallback = pCallback;
- break;
-
- case HAL_PCD_RESET_CB_ID:
- hpcd->ResetCallback = pCallback;
- break;
-
- case HAL_PCD_SUSPEND_CB_ID:
- hpcd->SuspendCallback = pCallback;
- break;
-
- case HAL_PCD_RESUME_CB_ID:
- hpcd->ResumeCallback = pCallback;
- break;
-
- case HAL_PCD_CONNECT_CB_ID:
- hpcd->ConnectCallback = pCallback;
- break;
-
- case HAL_PCD_DISCONNECT_CB_ID:
- hpcd->DisconnectCallback = pCallback;
- break;
-
- case HAL_PCD_MSPINIT_CB_ID:
- hpcd->MspInitCallback = pCallback;
- break;
-
- case HAL_PCD_MSPDEINIT_CB_ID:
- hpcd->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (hpcd->State == HAL_PCD_STATE_RESET) {
- switch (CallbackID) {
- case HAL_PCD_MSPINIT_CB_ID:
- hpcd->MspInitCallback = pCallback;
- break;
-
- case HAL_PCD_MSPDEINIT_CB_ID:
- hpcd->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
- return status;
-}
-
-/**
- * @brief Unregister an USB PCD Callback
- * USB PCD callabck is redirected to the weak predefined callback
- * @param hpcd USB PCD handle
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
- * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
- * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
- * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
- * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
- * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
- * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
- * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(
- PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- /* Setup Legacy weak Callbacks */
- if (hpcd->State == HAL_PCD_STATE_READY) {
- switch (CallbackID) {
- case HAL_PCD_SOF_CB_ID:
- hpcd->SOFCallback = HAL_PCD_SOFCallback;
- break;
-
- case HAL_PCD_SETUPSTAGE_CB_ID:
- hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
- break;
-
- case HAL_PCD_RESET_CB_ID:
- hpcd->ResetCallback = HAL_PCD_ResetCallback;
- break;
-
- case HAL_PCD_SUSPEND_CB_ID:
- hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
- break;
-
- case HAL_PCD_RESUME_CB_ID:
- hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
- break;
-
- case HAL_PCD_CONNECT_CB_ID:
- hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
- break;
-
- case HAL_PCD_DISCONNECT_CB_ID:
- hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
- break;
-
- case HAL_PCD_MSPINIT_CB_ID:
- hpcd->MspInitCallback = HAL_PCD_MspInit;
- break;
-
- case HAL_PCD_MSPDEINIT_CB_ID:
- hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
- break;
-
- default:
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (hpcd->State == HAL_PCD_STATE_RESET) {
- switch (CallbackID) {
- case HAL_PCD_MSPINIT_CB_ID:
- hpcd->MspInitCallback = HAL_PCD_MspInit;
- break;
-
- case HAL_PCD_MSPDEINIT_CB_ID:
- hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
- break;
-
- default:
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
- return status;
-}
-
-/**
- * @brief Register USB PCD Data OUT Stage Callback
- * To be used instead of the weak HAL_PCD_DataOutStageCallback()
- * predefined callback
- * @param hpcd PCD handle
- * @param pCallback pointer to the USB PCD Data OUT Stage Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(
- PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->DataOutStageCallback = pCallback;
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Unregister the USB PCD Data OUT Stage Callback
- * USB PCD Data OUT Stage Callback is redirected to the weak
- * HAL_PCD_DataOutStageCallback() predefined callback
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(
- PCD_HandleTypeDef *hpcd) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->DataOutStageCallback =
- HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Register USB PCD Data IN Stage Callback
- * To be used instead of the weak HAL_PCD_DataInStageCallback()
- * predefined callback
- * @param hpcd PCD handle
- * @param pCallback pointer to the USB PCD Data IN Stage Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(
- PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->DataInStageCallback = pCallback;
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Unregister the USB PCD Data IN Stage Callback
- * USB PCD Data OUT Stage Callback is redirected to the weak
- * HAL_PCD_DataInStageCallback() predefined callback
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(
- PCD_HandleTypeDef *hpcd) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->DataInStageCallback =
- HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Register USB PCD Iso OUT incomplete Callback
- * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback()
- * predefined callback
- * @param hpcd PCD handle
- * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(
- PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->ISOOUTIncompleteCallback = pCallback;
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Unregister the USB PCD Iso OUT incomplete Callback
- * USB PCD Iso OUT incomplete Callback is redirected
- * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(
- PCD_HandleTypeDef *hpcd) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->ISOOUTIncompleteCallback =
- HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak
- ISOOUTIncompleteCallback */
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Register USB PCD Iso IN incomplete Callback
- * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback()
- * predefined callback
- * @param hpcd PCD handle
- * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(
- PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->ISOINIncompleteCallback = pCallback;
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Unregister the USB PCD Iso IN incomplete Callback
- * USB PCD Iso IN incomplete Callback is redirected
- * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(
- PCD_HandleTypeDef *hpcd) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->ISOINIncompleteCallback =
- HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback
- */
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Register USB PCD BCD Callback
- * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined
- * callback
- * @param hpcd PCD handle
- * @param pCallback pointer to the USB PCD BCD Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(
- PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->BCDCallback = pCallback;
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Unregister the USB PCD BCD Callback
- * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback()
- * predefined callback
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->BCDCallback =
- HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Register USB PCD LPM Callback
- * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined
- * callback
- * @param hpcd PCD handle
- * @param pCallback pointer to the USB PCD LPM Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(
- PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->LPMCallback = pCallback;
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-
-/**
- * @brief Unregister the USB PCD LPM Callback
- * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback()
- * predefined callback
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hpcd);
-
- if (hpcd->State == HAL_PCD_STATE_READY) {
- hpcd->LPMCallback =
- HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
- } else {
- /* Update the error code */
- hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hpcd);
-
- return status;
-}
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the USB device
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) {
- __HAL_LOCK(hpcd);
- __HAL_PCD_ENABLE(hpcd);
- (void)USB_DevConnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the USB device.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) {
- __HAL_LOCK(hpcd);
- __HAL_PCD_DISABLE(hpcd);
- (void)USB_DevDisconnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles PCD interrupt request.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) {
- uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
-
- if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) {
- /* servicing of the endpoint correct transfer interrupt */
- /* clear of the CTR flag into the sub */
- (void)PCD_EP_ISR_Handler(hpcd);
-
- return;
- }
-
- if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->ResetCallback(hpcd);
-#else
- HAL_PCD_ResetCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- (void)HAL_PCD_SetAddress(hpcd, 0U);
-
- return;
- }
-
- if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
-
- return;
- }
-
- if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
-
- return;
- }
-
- if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) {
- hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
- hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
-
- if (hpcd->LPM_State == LPM_L1) {
- hpcd->LPM_State = LPM_L0;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
-#else
- HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->ResumeCallback(hpcd);
-#else
- HAL_PCD_ResumeCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
-
- return;
- }
-
- if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) {
- /* Force low-power mode in the macrocell */
- hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
-
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
- hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SuspendCallback(hpcd);
-#else
- HAL_PCD_SuspendCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- return;
- }
-
- /* Handle LPM Interrupt */
- if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
- if (hpcd->LPM_State == LPM_L0) {
- /* Force suspend and low-power mode before going to L1 state*/
- hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
- hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
-
- hpcd->LPM_State = LPM_L1;
- hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
-#else
- HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- } else {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SuspendCallback(hpcd);
-#else
- HAL_PCD_SuspendCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
-
- return;
- }
-
- if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SOFCallback(hpcd);
-#else
- HAL_PCD_SOFCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- return;
- }
-
- if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) {
- /* clear ESOF flag in ISTR */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
-
- return;
- }
-}
-
-/**
- * @brief Data OUT stage callback.
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
-__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd,
- uint8_t epnum) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Data IN stage callback
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
-__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd,
- uint8_t epnum) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DataInStageCallback could be implemented in the user
- file
- */
-}
-/**
- * @brief Setup stage callback
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SetupStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Start Of Frame callback.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SOFCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Reset callback.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ResetCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Suspend event callback.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SuspendCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Resume event callback.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ResumeCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO OUT callback.
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
-__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd,
- uint8_t epnum) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief Incomplete ISO IN callback.
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
-__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd,
- uint8_t epnum) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ISOINIncompleteCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Connection event callback.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ConnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Disconnection event callback.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DisconnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Connect the USB device
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) {
- __HAL_LOCK(hpcd);
- (void)USB_DevConnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disconnect the USB device.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) {
- __HAL_LOCK(hpcd);
- (void)USB_DevDisconnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the USB Device address.
- * @param hpcd PCD handle
- * @param address new device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) {
- __HAL_LOCK(hpcd);
- hpcd->USB_Address = address;
- (void)USB_SetDevAddress(hpcd->Instance, address);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-/**
- * @brief Open and configure an endpoint.
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param ep_mps endpoint max packet size
- * @param ep_type endpoint type
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type) {
- HAL_StatusTypeDef ret = HAL_OK;
- PCD_EPTypeDef *ep;
-
- if ((ep_addr & 0x80U) == 0x80U) {
- ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 1U;
- } else {
- ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 0U;
- }
-
- ep->num = ep_addr & EP_ADDR_MSK;
- ep->maxpacket = ep_mps;
- ep->type = ep_type;
-
- if (ep->is_in != 0U) {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
- /* Set initial data PID. */
- if (ep_type == EP_TYPE_BULK) {
- ep->data_pid_start = 0U;
- }
-
- __HAL_LOCK(hpcd);
- (void)USB_ActivateEndpoint(hpcd->Instance, ep);
- __HAL_UNLOCK(hpcd);
-
- return ret;
-}
-
-/**
- * @brief Deactivate an endpoint.
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) {
- PCD_EPTypeDef *ep;
-
- if ((ep_addr & 0x80U) == 0x80U) {
- ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 1U;
- } else {
- ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 0U;
- }
- ep->num = ep_addr & EP_ADDR_MSK;
-
- __HAL_LOCK(hpcd);
- (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data.
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param pBuf pointer to the reception buffer
- * @param len amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len) {
- PCD_EPTypeDef *ep;
-
- ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0U;
- ep->is_in = 0U;
- ep->num = ep_addr & EP_ADDR_MSK;
-
- if ((ep_addr & EP_ADDR_MSK) == 0U) {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- } else {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Get Received Data Size
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval Data Size
- */
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) {
- return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
-}
-/**
- * @brief Send an amount of data
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param pBuf pointer to the transmission buffer
- * @param len amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len) {
- PCD_EPTypeDef *ep;
-
- ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_fill_db = 1U;
- ep->xfer_len_db = len;
- ep->xfer_count = 0U;
- ep->is_in = 1U;
- ep->num = ep_addr & EP_ADDR_MSK;
-
- if ((ep_addr & EP_ADDR_MSK) == 0U) {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- } else {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set a STALL condition over an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd,
- uint8_t ep_addr) {
- PCD_EPTypeDef *ep;
-
- if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) {
- return HAL_ERROR;
- }
-
- if ((0x80U & ep_addr) == 0x80U) {
- ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 1U;
- } else {
- ep = &hpcd->OUT_ep[ep_addr];
- ep->is_in = 0U;
- }
-
- ep->is_stall = 1U;
- ep->num = ep_addr & EP_ADDR_MSK;
-
- __HAL_LOCK(hpcd);
-
- (void)USB_EPSetStall(hpcd->Instance, ep);
-
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Clear a STALL condition over in an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd,
- uint8_t ep_addr) {
- PCD_EPTypeDef *ep;
-
- if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) {
- return HAL_ERROR;
- }
-
- if ((0x80U & ep_addr) == 0x80U) {
- ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 1U;
- } else {
- ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
- ep->is_in = 0U;
- }
-
- ep->is_stall = 0U;
- ep->num = ep_addr & EP_ADDR_MSK;
-
- __HAL_LOCK(hpcd);
- (void)USB_EPClearStall(hpcd->Instance, ep);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Flush an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(ep_addr);
-
- return HAL_OK;
-}
-
-/**
- * @brief Activate remote wakeup signalling
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) {
- return (USB_ActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
- * @brief De-activate remote wakeup signalling.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) {
- return (USB_DeActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the PCD handle state.
- * @param hpcd PCD handle
- * @retval HAL state
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) {
- return hpcd->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
- * @{
- */
-
-/**
- * @brief This function handles PCD Endpoint interrupt request.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) {
- PCD_EPTypeDef *ep;
- uint16_t count;
- uint16_t wIstr;
- uint16_t wEPVal;
- uint16_t TxPctSize;
- uint8_t epindex;
-
- /* stay in loop while pending interrupts */
- while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) {
- wIstr = hpcd->Instance->ISTR;
-
- /* extract highest priority endpoint number */
- epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
- if (epindex == 0U) {
- /* Decode and service control endpoint interrupt */
-
- /* DIR bit = origin of the interrupt */
- if ((wIstr & USB_ISTR_DIR) == 0U) {
- /* DIR = 0 */
-
- /* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1) always */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- ep = &hpcd->IN_ep[0];
-
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff += ep->xfer_count;
-
- /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, 0U);
-#else
- HAL_PCD_DataInStageCallback(hpcd, 0U);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) {
- hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
- hpcd->USB_Address = 0U;
- }
- } else {
- /* DIR = 1 */
-
- /* DIR = 1 & CTR_RX => SETUP or OUT int */
- /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
- ep = &hpcd->OUT_ep[0];
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
- if ((wEPVal & USB_EP_SETUP) != 0U) {
- /* Get SETUP Packet */
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress,
- (uint16_t)ep->xfer_count);
-
- /* SETUP bit kept frozen while CTR_RX = 1 */
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
- /* Process SETUP Packet*/
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SetupStageCallback(hpcd);
-#else
- HAL_PCD_SetupStageCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
- /* Get Control Data OUT Packet */
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress,
- (uint16_t)ep->xfer_count);
-
- ep->xfer_buff += ep->xfer_count;
-
- /* Process Control Data OUT Packet */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataOutStageCallback(hpcd, 0U);
-#else
- HAL_PCD_DataOutStageCallback(hpcd, 0U);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
-
- if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) ==
- 0U) {
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
- }
- }
- }
- } else {
- /* Decode and service non control endpoints interrupt */
- /* process related endpoint register */
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
-
- if ((wEPVal & USB_EP_CTR_RX) != 0U) {
- /* clear int flag */
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
- ep = &hpcd->OUT_ep[epindex];
-
- /* OUT Single Buffering */
- if (ep->doublebuffer == 0U) {
- count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- if (count != 0U) {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
- }
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- else {
- /* manage double buffer bulk out */
- if (ep->type == EP_TYPE_BULK) {
- count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
- } else /* manage double buffer iso out */
- {
- /* free EP OUT Buffer */
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
-
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) !=
- 0U) {
- /* read from endpoint BUF0Addr buffer */
- count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
- if (count != 0U) {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
- }
- } else {
- /* read from endpoint BUF1Addr buffer */
- count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
- if (count != 0U) {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
- }
- }
- }
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- /* multi-packet on the NON control OUT endpoint */
- ep->xfer_count += count;
- ep->xfer_buff += count;
-
- if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) {
- /* RX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataOutStageCallback(hpcd, ep->num);
-#else
- HAL_PCD_DataOutStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- } else {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
- }
-
- if ((wEPVal & USB_EP_CTR_TX) != 0U) {
- ep = &hpcd->IN_ep[epindex];
-
- /* clear int flag */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
-
- if (ep->type != EP_TYPE_BULK) {
- ep->xfer_len = 0U;
-
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- if (ep->doublebuffer != 0U) {
- if ((wEPVal & USB_EP_DTOG_TX) != 0U) {
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
- } else {
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
- }
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
-#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- } else {
- /* Manage Bulk Single Buffer Transaction */
- if ((wEPVal & USB_EP_KIND) == 0U) {
- /* multi-packet on the NON control IN endpoint */
- TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_len > TxPctSize) {
- ep->xfer_len -= TxPctSize;
- } else {
- ep->xfer_len = 0U;
- }
-
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U) {
- /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
-#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- } else {
- /* Transfer is not yet Done */
- ep->xfer_buff += TxPctSize;
- ep->xfer_count += TxPctSize;
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
- else {
- (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
- }
- }
- }
- }
-
- return HAL_OK;
-}
-
-#if (USE_USB_DOUBLE_BUFFER == 1U)
-/**
- * @brief Manage double buffer bulk out transaction from ISR
- * @param hpcd PCD handle
- * @param ep current endpoint handle
- * @param wEPVal Last snapshot of EPRx register value taken in ISR
- * @retval HAL status
- */
-static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
- PCD_EPTypeDef *ep, uint16_t wEPVal) {
- uint16_t count;
-
- /* Manage Buffer0 OUT */
- if ((wEPVal & USB_EP_DTOG_RX) != 0U) {
- /* Get count of received Data on buffer0 */
- count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_len >= count) {
- ep->xfer_len -= count;
- } else {
- ep->xfer_len = 0U;
- }
-
- if (ep->xfer_len == 0U) {
- /* set NAK to OUT endpoint since double buffer is enabled */
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
- }
-
- /* Check if Buffer1 is in blocked state which requires to toggle */
- if ((wEPVal & USB_EP_DTOG_TX) != 0U) {
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
- }
-
- if (count != 0U) {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
- }
- }
- /* Manage Buffer 1 DTOG_RX=0 */
- else {
- /* Get count of received data */
- count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_len >= count) {
- ep->xfer_len -= count;
- } else {
- ep->xfer_len = 0U;
- }
-
- if (ep->xfer_len == 0U) {
- /* set NAK on the current endpoint */
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
- }
-
- /*Need to FreeUser Buffer*/
- if ((wEPVal & USB_EP_DTOG_TX) == 0U) {
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
- }
-
- if (count != 0U) {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
- }
- }
-
- return count;
-}
-
-/**
- * @brief Manage double buffer bulk IN transaction from ISR
- * @param hpcd PCD handle
- * @param ep current endpoint handle
- * @param wEPVal Last snapshot of EPRx register value taken in ISR
- * @retval HAL status
- */
-static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
- PCD_EPTypeDef *ep,
- uint16_t wEPVal) {
- uint32_t len;
- uint16_t TxPctSize;
-
- /* Data Buffer0 ACK received */
- if ((wEPVal & USB_EP_DTOG_TX) != 0U) {
- /* multi-packet on the NON control IN endpoint */
- TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_len > TxPctSize) {
- ep->xfer_len -= TxPctSize;
- } else {
- ep->xfer_len = 0U;
- }
-
- /* Transfer is completed */
- if (ep->xfer_len == 0U) {
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-
- /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
-#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- if ((wEPVal & USB_EP_DTOG_RX) != 0U) {
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
- }
- } else /* Transfer is not yet Done */
- {
- /* need to Free USB Buff */
- if ((wEPVal & USB_EP_DTOG_RX) != 0U) {
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
- }
-
- /* Still there is data to Fill in the next Buffer */
- if (ep->xfer_fill_db == 1U) {
- ep->xfer_buff += TxPctSize;
- ep->xfer_count += TxPctSize;
-
- /* Calculate the len of the new buffer to fill */
- if (ep->xfer_len_db >= ep->maxpacket) {
- len = ep->maxpacket;
- ep->xfer_len_db -= len;
- } else if (ep->xfer_len_db == 0U) {
- len = TxPctSize;
- ep->xfer_fill_db = 0U;
- } else {
- ep->xfer_fill_db = 0U;
- len = ep->xfer_len_db;
- ep->xfer_len_db = 0U;
- }
-
- /* Write remaining Data to Buffer */
- /* Set the Double buffer counter for pma buffer1 */
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
- /* Copy user buffer to USB PMA */
- USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0,
- (uint16_t)len);
- }
- }
- } else /* Data Buffer1 ACK received */
- {
- /* multi-packet on the NON control IN endpoint */
- TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_len >= TxPctSize) {
- ep->xfer_len -= TxPctSize;
- } else {
- ep->xfer_len = 0U;
- }
-
- /* Transfer is completed */
- if (ep->xfer_len == 0U) {
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-
- /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
-#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- /* need to Free USB Buff */
- if ((wEPVal & USB_EP_DTOG_RX) == 0U) {
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
- }
- } else /* Transfer is not yet Done */
- {
- /* need to Free USB Buff */
- if ((wEPVal & USB_EP_DTOG_RX) == 0U) {
- PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
- }
-
- /* Still there is data to Fill in the next Buffer */
- if (ep->xfer_fill_db == 1U) {
- ep->xfer_buff += TxPctSize;
- ep->xfer_count += TxPctSize;
-
- /* Calculate the len of the new buffer to fill */
- if (ep->xfer_len_db >= ep->maxpacket) {
- len = ep->maxpacket;
- ep->xfer_len_db -= len;
- } else if (ep->xfer_len_db == 0U) {
- len = TxPctSize;
- ep->xfer_fill_db = 0U;
- } else {
- len = ep->xfer_len_db;
- ep->xfer_len_db = 0U;
- ep->xfer_fill_db = 0;
- }
-
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
- /* Copy the user buffer to USB PMA */
- USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1,
- (uint16_t)len);
- }
- }
- }
-
- /*enable endpoint IN*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
-
- return HAL_OK;
-}
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
-/**
- * @}
- */
-#endif /* defined (USB) */
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pcd.c
+ * @author MCD Application Team
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device
+ core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit()
+ API:
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable PCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCD PCD
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(USB)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
+ PCD_EPTypeDef *ep,
+ uint16_t wEPVal);
+static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
+ PCD_EPTypeDef *ep, uint16_t wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization
+functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and initialize the associated
+ * handle.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) {
+ uint8_t i;
+
+ /* Check the PCD handle allocation */
+ if (hpcd == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+ if (hpcd->State == HAL_PCD_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+ if (hpcd->MspInitCallback == NULL) {
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hpcd->MspInitCallback(hpcd);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Disable the Interrupts */
+ __HAL_PCD_DISABLE(hpcd);
+
+ /* Init endpoints structures */
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1U;
+ hpcd->IN_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
+ }
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) {
+ hpcd->OUT_ep[i].is_in = 0U;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
+ }
+
+ /* Init Device */
+ (void)USB_DevInit(hpcd->Instance, hpcd->Init);
+
+ hpcd->USB_Address = 0U;
+ hpcd->State = HAL_PCD_STATE_READY;
+
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1U) {
+ (void)HAL_PCDEx_ActivateLPM(hpcd);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) {
+ /* Check the PCD handle allocation */
+ if (hpcd == NULL) {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Stop Device */
+ if (USB_StopDevice(hpcd->Instance) != HAL_OK) {
+ return HAL_ERROR;
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ if (hpcd->MspDeInitCallback == NULL) {
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hpcd->MspDeInitCallback(hpcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB PCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_PCD_SOF_CB_ID:
+ hpcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID:
+ hpcd->SetupStageCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID:
+ hpcd->ResetCallback = pCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID:
+ hpcd->SuspendCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID:
+ hpcd->ResumeCallback = pCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID:
+ hpcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID:
+ hpcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID:
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID:
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (hpcd->State == HAL_PCD_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_PCD_MSPINIT_CB_ID:
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID:
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB PCD Callback
+ * USB PCD callback is redirected to the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(
+ PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_PCD_SOF_CB_ID:
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID:
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID:
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID:
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID:
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID:
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID:
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID:
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID:
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default:
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (hpcd->State == HAL_PCD_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_PCD_MSPINIT_CB_ID:
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID:
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default:
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data OUT Stage Callback
+ * To be used instead of the weak HAL_PCD_DataOutStageCallback()
+ * predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data OUT Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->DataOutStageCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Data OUT Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak
+ * HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(
+ PCD_HandleTypeDef *hpcd) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->DataOutStageCallback =
+ HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data IN Stage Callback
+ * To be used instead of the weak HAL_PCD_DataInStageCallback()
+ * predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data IN Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->DataInStageCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Data IN Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak
+ * HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(
+ PCD_HandleTypeDef *hpcd) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->DataInStageCallback =
+ HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso OUT incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback()
+ * predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->ISOOUTIncompleteCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Iso OUT incomplete Callback
+ * USB PCD Iso OUT incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(
+ PCD_HandleTypeDef *hpcd) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->ISOOUTIncompleteCallback =
+ HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak
+ ISOOUTIncompleteCallback */
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso IN incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback()
+ * predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->ISOINIncompleteCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD Iso IN incomplete Callback
+ * USB PCD Iso IN incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(
+ PCD_HandleTypeDef *hpcd) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->ISOINIncompleteCallback =
+ HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback
+ */
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD BCD Callback
+ * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined
+ * callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD BCD Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->BCDCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD BCD Callback
+ * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback()
+ * predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->BCDCallback =
+ HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD LPM Callback
+ * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined
+ * callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD LPM Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(
+ PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->LPMCallback = pCallback;
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Unregister the USB PCD LPM Callback
+ * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback()
+ * predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY) {
+ hpcd->LPMCallback =
+ HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
+ } else {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the USB device
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) {
+ __HAL_LOCK(hpcd);
+ __HAL_PCD_ENABLE(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) {
+ __HAL_LOCK(hpcd);
+ __HAL_PCD_DISABLE(hpcd);
+ (void)USB_DevDisconnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles PCD interrupt request.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) {
+ uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+
+ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) {
+ /* servicing of the endpoint correct transfer interrupt */
+ /* clear of the CTR flag into the sub */
+ (void)PCD_EP_ISR_Handler(hpcd);
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResetCallback(hpcd);
+#else
+ HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ (void)HAL_PCD_SetAddress(hpcd, 0U);
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) {
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+
+ if (hpcd->LPM_State == LPM_L1) {
+ hpcd->LPM_State = LPM_L0;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResumeCallback(hpcd);
+#else
+ HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) {
+ /* Force low-power mode in the macrocell */
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
+ HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
+ }
+
+ /* Handle LPM Interrupt */
+ if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
+ if (hpcd->LPM_State == LPM_L0) {
+ /* Force suspend and low-power mode before going to L1 state*/
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+
+ hpcd->LPM_State = LPM_L1;
+ hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
+ HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback(hpcd);
+#else
+ HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
+ }
+
+ if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) {
+ /* clear ESOF flag in ISTR */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+
+ return;
+ }
+}
+
+/**
+ * @brief Data OUT stage callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ uint8_t epnum) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Data IN stage callback
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd,
+ uint8_t epnum) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user
+ file
+ */
+}
+/**
+ * @brief Setup stage callback
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd,
+ uint8_t epnum) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd,
+ uint8_t epnum) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Connection event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) {
+ __HAL_LOCK(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) {
+ __HAL_LOCK(hpcd);
+ (void)USB_DevDisconnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address.
+ * @param hpcd PCD handle
+ * @param address new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) {
+ __HAL_LOCK(hpcd);
+ hpcd->USB_Address = address;
+ (void)USB_SetDevAddress(hpcd->Instance, address);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type) {
+ HAL_StatusTypeDef ret = HAL_OK;
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80U) == 0x80U) {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ } else {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
+ }
+
+ ep->num = ep_addr & EP_ADDR_MSK;
+ ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
+ ep->type = ep_type;
+
+ /* Set initial data PID. */
+ if (ep_type == EP_TYPE_BULK) {
+ ep->data_pid_start = 0U;
+ }
+
+ __HAL_LOCK(hpcd);
+ (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+
+ return ret;
+}
+
+/**
+ * @brief Deactivate an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) {
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80U) == 0x80U) {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ } else {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
+ }
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+ (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len) {
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 0U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval Data Size
+ */
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) {
+ return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+}
+/**
+ * @brief Send an amount of data
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len) {
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_fill_db = 1U;
+ ep->xfer_len_db = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 1U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd,
+ uint8_t ep_addr) {
+ PCD_EPTypeDef *ep;
+
+ if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) {
+ return HAL_ERROR;
+ }
+
+ if ((0x80U & ep_addr) == 0x80U) {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ } else {
+ ep = &hpcd->OUT_ep[ep_addr];
+ ep->is_in = 0U;
+ }
+
+ ep->is_stall = 1U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+
+ (void)USB_EPSetStall(hpcd->Instance, ep);
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd,
+ uint8_t ep_addr) {
+ PCD_EPTypeDef *ep;
+
+ if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) {
+ return HAL_ERROR;
+ }
+
+ if ((0x80U & ep_addr) == 0x80U) {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
+ } else {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
+ }
+
+ ep->is_stall = 0U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+ (void)USB_EPClearStall(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort an USB EP transaction.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) {
+ HAL_StatusTypeDef ret;
+ PCD_EPTypeDef *ep;
+
+ if ((0x80U & ep_addr) == 0x80U) {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ } else {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ }
+
+ /* Stop Xfer */
+ ret = USB_EPStopXfer(hpcd->Instance, ep);
+
+ return ret;
+}
+
+/**
+ * @brief Flush an endpoint
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) {
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x80U) == 0x80U) {
+ (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+ } else {
+ (void)USB_FlushRxFifo(hpcd->Instance);
+ }
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate remote wakeup signalling
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) {
+ return (USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+ * @brief De-activate remote wakeup signalling.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) {
+ return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD handle state.
+ * @param hpcd PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) {
+ return hpcd->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief This function handles PCD Endpoint interrupt request.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) {
+ PCD_EPTypeDef *ep;
+ uint16_t count;
+ uint16_t wIstr;
+ uint16_t wEPVal;
+ uint16_t TxPctSize;
+ uint8_t epindex;
+
+#if (USE_USB_DOUBLE_BUFFER != 1U)
+ count = 0U;
+#endif /* USE_USB_DOUBLE_BUFFER */
+
+ /* stay in loop while pending interrupts */
+ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) {
+ wIstr = hpcd->Instance->ISTR;
+
+ /* extract highest priority endpoint number */
+ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (epindex == 0U) {
+ /* Decode and service control endpoint interrupt */
+
+ /* DIR bit = origin of the interrupt */
+ if ((wIstr & USB_ISTR_DIR) == 0U) {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ ep = &hpcd->IN_ep[0];
+
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff += ep->xfer_count;
+
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, 0U);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, 0U);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) {
+ hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->USB_Address = 0U;
+ }
+ } else {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+ ep = &hpcd->OUT_ep[0];
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if ((wEPVal & USB_EP_SETUP) != 0U) {
+ /* Get SETUP Packet */
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress,
+ (uint16_t)ep->xfer_count);
+
+ /* SETUP bit kept frozen while CTR_RX = 1 */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Process SETUP Packet*/
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
+ HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Get Control Data OUT Packet */
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress,
+ (uint16_t)ep->xfer_count);
+
+ ep->xfer_buff += ep->xfer_count;
+
+ /* Process Control Data OUT Packet */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, 0U);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, 0U);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if (((wEPVal & USB_EP_SETUP) == 0U) &&
+ ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) {
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
+ }
+ }
+ } else {
+ /* Decode and service non control endpoints interrupt */
+ /* process related endpoint register */
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
+
+ if ((wEPVal & USB_EP_CTR_RX) != 0U) {
+ /* clear int flag */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
+ ep = &hpcd->OUT_ep[epindex];
+
+ /* OUT Single Buffering */
+ if (ep->doublebuffer == 0U) {
+ count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if (count != 0U) {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else {
+ /* manage double buffer bulk out */
+ if (ep->type == EP_TYPE_BULK) {
+ count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
+ } else /* manage double buffer iso out */
+ {
+ /* free EP OUT Buffer */
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) !=
+ 0U) {
+ /* read from endpoint BUF0Addr buffer */
+ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+ if (count != 0U) {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ } else {
+ /* read from endpoint BUF1Addr buffer */
+ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+ if (count != 0U) {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ /* multi-packet on the NON control OUT endpoint */
+ ep->xfer_count += count;
+ ep->xfer_buff += count;
+
+ if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) {
+ /* RX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else {
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+ }
+ }
+
+ if ((wEPVal & USB_EP_CTR_TX) != 0U) {
+ ep = &hpcd->IN_ep[epindex];
+
+ /* clear int flag */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
+
+ if (ep->type == EP_TYPE_ISOC) {
+ ep->xfer_len = 0U;
+
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ if (ep->doublebuffer != 0U) {
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U) {
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ } else {
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else {
+ /* Manage Single Buffer Transaction */
+ if ((wEPVal & USB_EP_KIND) == 0U) {
+ /* Multi-packet on the NON control IN endpoint */
+ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len > TxPctSize) {
+ ep->xfer_len -= TxPctSize;
+ } else {
+ ep->xfer_len = 0U;
+ }
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U) {
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else {
+ /* Transfer is not yet Done */
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
+ else {
+ (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+/**
+ * @brief Manage double buffer bulk out transaction from ISR
+ * @param hpcd PCD handle
+ * @param ep current endpoint handle
+ * @param wEPVal Last snapshot of EPRx register value taken in ISR
+ * @retval HAL status
+ */
+static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
+ PCD_EPTypeDef *ep, uint16_t wEPVal) {
+ uint16_t count;
+
+ /* Manage Buffer0 OUT */
+ if ((wEPVal & USB_EP_DTOG_RX) != 0U) {
+ /* Get count of received Data on buffer0 */
+ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len >= count) {
+ ep->xfer_len -= count;
+ } else {
+ ep->xfer_len = 0U;
+ }
+
+ if (ep->xfer_len == 0U) {
+ /* Set NAK to OUT endpoint since double buffer is enabled */
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+ }
+
+ /* Check if Buffer1 is in blocked state which requires to toggle */
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U) {
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+ }
+
+ if (count != 0U) {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ /* Manage Buffer 1 DTOG_RX=0 */
+ else {
+ /* Get count of received data */
+ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len >= count) {
+ ep->xfer_len -= count;
+ } else {
+ ep->xfer_len = 0U;
+ }
+
+ if (ep->xfer_len == 0U) {
+ /* Set NAK on the current endpoint */
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+ }
+
+ /* Need to FreeUser Buffer */
+ if ((wEPVal & USB_EP_DTOG_TX) == 0U) {
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+ }
+
+ if (count != 0U) {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+
+ return count;
+}
+
+/**
+ * @brief Manage double buffer bulk IN transaction from ISR
+ * @param hpcd PCD handle
+ * @param ep current endpoint handle
+ * @param wEPVal Last snapshot of EPRx register value taken in ISR
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
+ PCD_EPTypeDef *ep,
+ uint16_t wEPVal) {
+ uint32_t len;
+ uint16_t TxPctSize;
+
+ /* Data Buffer0 ACK received */
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U) {
+ /* multi-packet on the NON control IN endpoint */
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len > TxPctSize) {
+ ep->xfer_len -= TxPctSize;
+ } else {
+ ep->xfer_len = 0U;
+ }
+
+ /* Transfer is completed */
+ if (ep->xfer_len == 0U) {
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
+ if (ep->type == EP_TYPE_BULK) {
+ /* Set Bulk endpoint in NAK state */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((wEPVal & USB_EP_DTOG_RX) != 0U) {
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+ }
+
+ return HAL_OK;
+ } else /* Transfer is not yet Done */
+ {
+ /* Need to Free USB Buffer */
+ if ((wEPVal & USB_EP_DTOG_RX) != 0U) {
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+ }
+
+ /* Still there is data to Fill in the next Buffer */
+ if (ep->xfer_fill_db == 1U) {
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
+
+ /* Calculate the len of the new buffer to fill */
+ if (ep->xfer_len_db >= ep->maxpacket) {
+ len = ep->maxpacket;
+ ep->xfer_len_db -= len;
+ } else if (ep->xfer_len_db == 0U) {
+ len = TxPctSize;
+ ep->xfer_fill_db = 0U;
+ } else {
+ ep->xfer_fill_db = 0U;
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Write remaining Data to Buffer */
+ /* Set the Double buffer counter for pma buffer0 */
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+ /* Copy user buffer to USB PMA */
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0,
+ (uint16_t)len);
+ }
+ }
+ } else /* Data Buffer1 ACK received */
+ {
+ /* multi-packet on the NON control IN endpoint */
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len >= TxPctSize) {
+ ep->xfer_len -= TxPctSize;
+ } else {
+ ep->xfer_len = 0U;
+ }
+
+ /* Transfer is completed */
+ if (ep->xfer_len == 0U) {
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
+ if (ep->type == EP_TYPE_BULK) {
+ /* Set Bulk endpoint in NAK state */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ /* need to Free USB Buff */
+ if ((wEPVal & USB_EP_DTOG_RX) == 0U) {
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+ }
+
+ return HAL_OK;
+ } else /* Transfer is not yet Done */
+ {
+ /* Need to Free USB Buffer */
+ if ((wEPVal & USB_EP_DTOG_RX) == 0U) {
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+ }
+
+ /* Still there is data to Fill in the next Buffer */
+ if (ep->xfer_fill_db == 1U) {
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
+
+ /* Calculate the len of the new buffer to fill */
+ if (ep->xfer_len_db >= ep->maxpacket) {
+ len = ep->maxpacket;
+ ep->xfer_len_db -= len;
+ } else if (ep->xfer_len_db == 0U) {
+ len = TxPctSize;
+ ep->xfer_fill_db = 0U;
+ } else {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ ep->xfer_fill_db = 0;
+ }
+
+ /* Set the Double buffer counter for pma buffer1 */
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+ /* Copy the user buffer to USB PMA */
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1,
+ (uint16_t)len);
+ }
+ }
+ }
+
+ /* Enable endpoint IN */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+
+ return HAL_OK;
+}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c
index fec40d3..ff6dd39 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c
@@ -1,313 +1,310 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pcd_ex.c
- * @author MCD Application Team
- * @brief PCD Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Extended features functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCDEx PCDEx
- * @brief PCD Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(USB)
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief PCDEx control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Update FIFO configuration
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure PMA for EP
- * @param hpcd Device instance
- * @param ep_addr endpoint address
- * @param ep_kind endpoint Kind
- * USB_SNG_BUF: Single Buffer used
- * USB_DBL_BUF: Double Buffer used
- * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
- * this parameter is 16-bit value providing the address
- * in PMA allocated to endpoint.
- * In case of double buffer endpoint this parameter
- * is a 32-bit value providing the endpoint buffer 0 address
- * in the LSB part of 32-bit value and endpoint buffer 1
- * address in the MSB part of 32-bit value.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
- uint16_t ep_kind, uint32_t pmaadress) {
- PCD_EPTypeDef *ep;
-
- /* initialize ep structure*/
- if ((0x80U & ep_addr) == 0x80U) {
- ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
- } else {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- /* Here we check if the endpoint is single or double Buffer*/
- if (ep_kind == PCD_SNG_BUF) {
- /* Single Buffer */
- ep->doublebuffer = 0U;
- /* Configure the PMA */
- ep->pmaadress = (uint16_t)pmaadress;
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- else /* USB_DBL_BUF */
- {
- /* Double Buffer Endpoint */
- ep->doublebuffer = 1U;
- /* Configure the PMA */
- ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
- ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- return HAL_OK;
-}
-
-/**
- * @brief Activate BatteryCharging feature.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) {
- USB_TypeDef *USBx = hpcd->Instance;
- hpcd->battery_charging_active = 1U;
-
- /* Enable BCD feature */
- USBx->BCDR |= USB_BCDR_BCDEN;
-
- /* Enable DCD : Data Contact Detect */
- USBx->BCDR &= ~(USB_BCDR_PDEN);
- USBx->BCDR &= ~(USB_BCDR_SDEN);
- USBx->BCDR |= USB_BCDR_DCDEN;
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate BatteryCharging feature.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) {
- USB_TypeDef *USBx = hpcd->Instance;
- hpcd->battery_charging_active = 0U;
-
- /* Disable BCD feature */
- USBx->BCDR &= ~(USB_BCDR_BCDEN);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle BatteryCharging Process.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) {
- USB_TypeDef *USBx = hpcd->Instance;
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait Detect flag or a timeout is happen */
- while ((USBx->BCDR & USB_BCDR_DCDET) == 0U) {
- /* Check for the Timeout */
- if ((HAL_GetTick() - tickstart) > 1000U) {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- return;
- }
- }
-
- HAL_Delay(200U);
-
- /* Data Pin Contact ? Check Detect flag */
- if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
- /* Primary detection: checks if connected to Standard Downstream Port
- (without charging capability) */
- USBx->BCDR &= ~(USB_BCDR_DCDEN);
- HAL_Delay(50U);
- USBx->BCDR |= (USB_BCDR_PDEN);
- HAL_Delay(50U);
-
- /* If Charger detect ? */
- if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) {
- /* Start secondary detection to check connection to Charging Downstream
- Port or Dedicated Charging Port */
- USBx->BCDR &= ~(USB_BCDR_PDEN);
- HAL_Delay(50U);
- USBx->BCDR |= (USB_BCDR_SDEN);
- HAL_Delay(50U);
-
- /* If CDP ? */
- if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) {
- /* Dedicated Downstream Port DCP */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- } else {
- /* Charging Downstream Port CDP */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
- } else /* NO */
- {
- /* Standard Downstream Port */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
-
- /* Battery Charging capability discovery finished Start Enumeration */
- (void)HAL_PCDEx_DeActivateBCD(hpcd);
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Activate LPM feature.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) {
- USB_TypeDef *USBx = hpcd->Instance;
- hpcd->lpm_active = 1U;
- hpcd->LPM_State = LPM_L0;
-
- USBx->LPMCSR |= USB_LPMCSR_LMPEN;
- USBx->LPMCSR |= USB_LPMCSR_LPMACK;
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate LPM feature.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) {
- USB_TypeDef *USBx = hpcd->Instance;
-
- hpcd->lpm_active = 0U;
-
- USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
- USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
-
- return HAL_OK;
-}
-
-/**
- * @brief Send LPM message to user layer callback.
- * @param hpcd PCD handle
- * @param msg LPM message
- * @retval HAL status
- */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd,
- PCD_LPM_MsgTypeDef msg) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(msg);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCDEx_LPM_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Send BatteryCharging message to user layer callback.
- * @param hpcd PCD handle
- * @param msg LPM message
- * @retval HAL status
- */
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd,
- PCD_BCD_MsgTypeDef msg) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(msg);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCDEx_BCD_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB) */
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @brief PCD Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(USB)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update FIFO configuration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure PMA for EP
+ * @param hpcd Device instance
+ * @param ep_addr endpoint address
+ * @param ep_kind endpoint Kind
+ * USB_SNG_BUF: Single Buffer used
+ * USB_DBL_BUF: Double Buffer used
+ * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
+ * this parameter is 16-bit value providing the address
+ * in PMA allocated to endpoint.
+ * In case of double buffer endpoint this parameter
+ * is a 32-bit value providing the endpoint buffer 0 address
+ * in the LSB part of 32-bit value and endpoint buffer 1
+ * address in the MSB part of 32-bit value.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+ uint16_t ep_kind, uint32_t pmaadress) {
+ PCD_EPTypeDef *ep;
+
+ /* initialize ep structure*/
+ if ((0x80U & ep_addr) == 0x80U) {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ } else {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ /* Here we check if the endpoint is single or double Buffer*/
+ if (ep_kind == PCD_SNG_BUF) {
+ /* Single Buffer */
+ ep->doublebuffer = 0U;
+ /* Configure the PMA */
+ ep->pmaadress = (uint16_t)pmaadress;
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else /* USB_DBL_BUF */
+ {
+ /* Double Buffer Endpoint */
+ ep->doublebuffer = 1U;
+ /* Configure the PMA */
+ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
+ ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate BatteryCharging feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) {
+ USB_TypeDef *USBx = hpcd->Instance;
+ hpcd->battery_charging_active = 1U;
+
+ /* Enable BCD feature */
+ USBx->BCDR |= USB_BCDR_BCDEN;
+
+ /* Enable DCD : Data Contact Detect */
+ USBx->BCDR &= ~(USB_BCDR_PDEN);
+ USBx->BCDR &= ~(USB_BCDR_SDEN);
+ USBx->BCDR |= USB_BCDR_DCDEN;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate BatteryCharging feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) {
+ USB_TypeDef *USBx = hpcd->Instance;
+ hpcd->battery_charging_active = 0U;
+
+ /* Disable BCD feature */
+ USBx->BCDR &= ~(USB_BCDR_BCDEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BatteryCharging Process.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) {
+ USB_TypeDef *USBx = hpcd->Instance;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait for Min DCD Timeout */
+ HAL_Delay(300U);
+
+ /* Data Pin Contact ? Check Detect flag */
+ if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ /* Primary detection: checks if connected to Standard Downstream Port
+ (without charging capability) */
+ USBx->BCDR &= ~(USB_BCDR_DCDEN);
+ HAL_Delay(50U);
+ USBx->BCDR |= (USB_BCDR_PDEN);
+ HAL_Delay(50U);
+
+ /* If Charger detect ? */
+ if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) {
+ /* Start secondary detection to check connection to Charging Downstream
+ Port or Dedicated Charging Port */
+ USBx->BCDR &= ~(USB_BCDR_PDEN);
+ HAL_Delay(50U);
+ USBx->BCDR |= (USB_BCDR_SDEN);
+ HAL_Delay(50U);
+
+ /* If CDP ? */
+ if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) {
+ /* Dedicated Downstream Port DCP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else {
+ /* Charging Downstream Port CDP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ } else /* NO */
+ {
+ /* Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ /* Battery Charging capability discovery finished Start Enumeration */
+ (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+ /* Check for the Timeout, else start USB Device */
+ if ((HAL_GetTick() - tickstart) > 1000U) {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ } else {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Activate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) {
+ USB_TypeDef *USBx = hpcd->Instance;
+ hpcd->lpm_active = 1U;
+ hpcd->LPM_State = LPM_L0;
+
+ USBx->LPMCSR |= USB_LPMCSR_LMPEN;
+ USBx->LPMCSR |= USB_LPMCSR_LPMACK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) {
+ USB_TypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = 0U;
+
+ USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
+ USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Send LPM message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd,
+ PCD_LPM_MsgTypeDef msg) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_LPM_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Send BatteryCharging message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd,
+ PCD_BCD_MsgTypeDef msg) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_BCD_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
index e6e7e0d..9dfaf8a 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
@@ -1,636 +1,636 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pwr.c
- * @author MCD Application Team
- * @brief PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWR PWR
- * @brief PWR HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Defines PWR Private Defines
- * @{
- */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
- * @{
- */
-#define PVD_MODE_IT \
- ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold \
- crossing */
-#define PVD_MODE_EVT \
- ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing \
- */
-#define PVD_RISING_EDGE \
- ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
-#define PVD_FALLING_EDGE \
- ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization
-functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the HAL PWR peripheral registers to their default reset
- * values.
- * @retval None
- */
-void HAL_PWR_DeInit(void) {
- __HAL_RCC_PWR_FORCE_RESET();
- __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
- * @brief Enable access to the backup domain
- * (RTC registers, RTC backup data registers).
- * @note After reset, the backup domain is protected against
- * possible unwanted write accesses.
- * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up
- * domain. In order to set or modify the RTC clock, the backup domain access
- * must be disabled.
- * @note LSEON bit that switches on and off the LSE crystal belongs as well to
- * the back-up domain.
- * @retval None
- */
-void HAL_PWR_EnableBkUpAccess(void) { SET_BIT(PWR->CR1, PWR_CR1_DBP); }
-
-/**
- * @brief Disable access to the backup domain
- * (RTC registers, RTC backup data registers).
- * @retval None
- */
-void HAL_PWR_DisableBkUpAccess(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); }
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
-
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-
- [..]
- *** PVD configuration ***
- =========================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2
-register).
-
- (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled. This is done through
- __HAL_PVD_EXTI_ENABLE_IT() macro.
- (+) The PVD is stopped in Standby mode.
-
-
- *** WakeUp pin configuration ***
- ================================
- [..]
- (+) WakeUp pins are used to wakeup the system from Standby mode or
-Shutdown mode. The polarity of these pins can be set to configure event
-detection on high level (rising edge) or low level (falling edge).
-
-
-
- *** Low Power modes configuration ***
- =====================================
- [..]
- The devices feature 8 low-power modes:
- (+) Low-power Run mode: core and peripherals are running, main regulator
-off, low power regulator on.
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and
-low power regulators on.
- (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept
-running, main regulator off, low power regulator on.
- (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low
-power regulators on.
- (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
-off, low power regulator on.
- (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE,
-SRAM2 content preserved, main regulator off, low power regulator on.
- (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE,
-main and low power regulators off.
- (+) Shutdown mode: all clocks are stopped except LSE, main and low power
-regulators off.
-
-
- *** Low-power run mode ***
- ==========================
- [..]
- (+) Entry: (from main run mode)
- (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having
-decreased the system clock below 2 MHz.
-
- (+) Exit:
- (++) clear LPR bit then wait for REGLP bit to be reset with
-HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency
-be increased above 2 MHz.
-
-
- *** Sleep mode / Low-power sleep mode ***
- =========================================
- [..]
- (+) Entry:
- The Sleep mode / Low-power Sleep mode is entered through
-HAL_PWR_EnterSLEEPMode() API in specifying whether or not the regulator is
-forced to low-power mode and if exit is interrupt or event-triggered.
- (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
- (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power
-mode). In the latter case, the system clock frequency must have been decreased
-below 2 MHz beforehand.
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
- (+) WFI Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored
-interrupt controller (NVIC) or any wake-up event.
-
- (+) WFE Exit:
- (++) Any wake-up event such as an EXTI line configured in event mode.
-
- [..] When exiting the Low-power sleep mode by issuing an interrupt or a
-wakeup event, the MCU is in Low-power Run mode.
-
- *** Stop 0, Stop 1 modes ***
- ===============================
- [..]
- (+) Entry:
- The Stop 0, Stop 1 modes are entered through the following API's:
- (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or
-HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons
-HAL_PWR_EnterSTOPMode().
- (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
- (++) PWR_MAINREGULATOR_ON
- (++) PWR_LOWPOWERREGULATOR_ON
- (+) Exit (interrupt or event-triggered, specified when entering STOP
-mode):
- (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
- (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
-
- (+) WFI Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt
-mode.
- (++) Some specific communication peripherals (USART, LPUART, I2C)
-interrupts when programmed in wakeup mode.
- (+) WFE Exit:
- (++) Any EXTI Line (Internal or External) configured in Event mode.
-
- [..]
- When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or
-in Low-power Run mode depending on the LPR bit setting.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode offers two options:
- (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps
-voltage regulator in low power mode). SRAM and registers contents are lost
-except for the SRAM2 content, the RTC registers, RTC backup registers and
-Standby circuitry.
- (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage
-regulator then disabled). SRAM and register contents are lost except for the RTC
-registers, RTC backup registers and Standby circuitry.
-
- (++) Entry:
- (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode()
-API. SRAM1 and register contents are lost except for registers in the Backup
-domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is
-set in PWR_CR3 register. To enable this feature, the user can resort to
-HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit.
-
- (++) Exit:
- (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event,
-time-stamp event, external reset in NRST pin, IWDG reset.
-
- [..] After waking up from Standby mode, program execution restarts in
-the same way as after a Reset.
-
-
- *** Shutdown mode ***
- ======================
- [..]
- In Shutdown mode,
- voltage regulator is disabled, all clocks are off except LSE, RRS bit is
-cleared. SRAM and registers contents are lost except for backup domain
-registers.
-
- (+) Entry:
- The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode()
-API.
-
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event,
-time-stamp event, external reset in NRST pin.
-
- [..] After waking up from Shutdown mode, program execution restarts in
-the same way as after a Reset.
-
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event or a time-stamp event, without depending on
- an external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
-
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is
-necessary to configure the RTC to generate the RTC alarm using the
-HAL_RTC_SetAlarm_IT() function.
-
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp
-event, it is necessary to configure the RTC to detect the tamper or time stamp
-event using the HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT()
-functions.
-
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is
-necessary to configure the RTC to generate the RTC WakeUp event using the
-HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector
- * (PVD).
- * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the
- * PVD configuration information.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage thresholds corresponding to each
- * detection level.
- * @retval None
- */
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) {
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
- /* Set PLS bits according to PVDLevel value */
- MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
-
- /* Clear any previous config. Keep it clear if no event or IT mode is selected
- */
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) {
- __HAL_PWR_PVD_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) {
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) {
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) {
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the Power Voltage Detector (PVD).
- * @retval None
- */
-void HAL_PWR_EnablePVD(void) { SET_BIT(PWR->CR2, PWR_CR2_PVDE); }
-
-/**
- * @brief Disable the Power Voltage Detector (PVD).
- * @retval None
- */
-void HAL_PWR_DisablePVD(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); }
-
-/**
- * @brief Enable the WakeUp PINx functionality.
- * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
- * This parameter can be one of the following legacy values which set
- * the default polarity i.e. detection on high level (rising edge):
- * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
- * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
- *
- * or one of the following value where the user can explicitly specify
- * the enabled pin and the chosen polarity:
- * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
- * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
- * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
- * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
- * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
- * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
- * @retval None
- */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) {
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
-
- /* Specifies the Wake-Up pin polarity for the event detection
- (rising or falling edge) */
- MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity),
- (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
-
- /* Enable wake-up pin */
- SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
- * This parameter can be one of the following values:
- * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
- * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
- * @retval None
- */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) {
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
- CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
-}
-
-/**
- * @brief Enter Sleep or Low-power Sleep mode.
- * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in
- * Run mode.
- * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep
- * mode. This parameter can be one of the following values:
- * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
- * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator
- * in low-power mode)
- * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if
- * not yet in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with
- * Regulator set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure
- * the Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR
- * register. Additionally, the clock frequency must be reduced below 2 MHz.
- * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock
- * frequency must be done before calling HAL_PWR_EnterSLEEPMode() API.
- * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode.
- * To move in Run mode, the user must resort to
- * HAL_PWREx_DisableLowPowerRunMode() API.
- * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE
- * instruction. This parameter can be one of the following values:
- * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode
- * with WFI instruction
- * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode
- * with WFE instruction
- * @note When WFI entry is used, tick interrupt have to be disabled if not
- * desired as the interrupt wake up source.
- * @retval None
- */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) {
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Set Regulator parameter */
- if (Regulator == PWR_MAINREGULATOR_ON) {
- /* If in low-power run mode at this point, exit it */
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) {
- (void)HAL_PWREx_DisableLowPowerRunMode();
- }
- /* Regulator now in main mode. */
- } else {
- /* If in run mode, first move to low-power run mode.
- The system clock frequency must be below 2 MHz at this point. */
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U) {
- HAL_PWREx_EnableLowPowerRunMode();
- }
- }
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if (SLEEPEntry == PWR_SLEEPENTRY_WFI) {
- /* Request Wait For Interrupt */
- __WFI();
- } else {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-}
-
-/**
- * @brief Enter Stop mode
- * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
- * legacy code running on devices where only "Stop mode" is mentioned with main
- * or low power regulator ON.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped; the PLL,
- * the HSI and the HSE oscillators are disabled. Some peripherals with
- * the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to
- * receive a frame, and switch off the HSI after receiving the frame if it is
- * not a wakeup frame. In this case, the HSI clock is propagated only to the
- * peripheral requesting it. SRAM1, SRAM2 and register contents are preserved.
- * The BOR is available.
- * The voltage regulator can be configured either in normal (Stop 0) or
- * low-power mode (Stop 1).
- * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup
- * event, the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode (Stop 1), an
- * additional startup delay is incurred when waking up. By keeping the internal
- * regulator ON during Stop mode (Stop 0), the consumption is higher although
- * the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
- * This parameter can be one of the following values:
- * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
- * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power
- * regulator ON)
- * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE
- * instruction. This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI
- * instruction.
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE
- * instruction.
- * @retval None
- */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) {
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
-
- if (Regulator == PWR_LOWPOWERREGULATOR_ON) {
- HAL_PWREx_EnterSTOP1Mode(STOPEntry);
- } else {
- HAL_PWREx_EnterSTOP0Mode(STOPEntry);
- }
-}
-
-/**
- * @brief Enter Standby mode.
- * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched
- * off. The voltage regulator is disabled, except when SRAM2 content is
- * preserved in which case the regulator is in low-power mode. SRAM1 and
- * register contents are lost except for registers in the Backup domain and
- * Standby circuitry. SRAM2 content can be preserved if the bit RRS is
- * set in PWR_CR3 register. To enable this feature, the user can resort to
- * HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit. The BOR is
- * available.
- * @note The I/Os can be configured either with a pull-up or pull-down or can
- * be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and
- * HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and Pull Down
- * state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown()
- * disable the same. These states are effective in Standby mode only if APC bit
- * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
- * @retval None
- */
-void HAL_PWR_EnterSTANDBYMode(void) {
- /* Set Stand-by mode */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-/* This option is used to ensure that store operations are completed */
-#if defined(__CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread
- * mode.
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
- * processor re-enters SLEEP mode when an interruption handling is over. Setting
- * this bit is useful when the processor is expected to run only on
- * interruptions handling.
- * @retval None
- */
-void HAL_PWR_EnableSleepOnExit(void) {
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Disable Sleep-On-Exit feature when returning from Handler mode to
- * Thread mode.
- * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
- * processor re-enters SLEEP mode when an interruption handling is over.
- * @retval None
- */
-void HAL_PWR_DisableSleepOnExit(void) {
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enable CORTEX M4 SEVONPEND bit.
- * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_EnableSEVOnPend(void) {
- /* Set SEVONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Disable CORTEX M4 SEVONPEND bit.
- * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_DisableSEVOnPend(void) {
- /* Clear SEVONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief PWR PVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWR_PVDCallback(void) {
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_PWR_PVDCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pwr.c
+ * @author MCD Application Team
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Defines PWR Private Defines
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT \
+ ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold \
+ crossing */
+#define PVD_MODE_EVT \
+ ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing \
+ */
+#define PVD_RISING_EDGE \
+ ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
+#define PVD_FALLING_EDGE \
+ ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization
+functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitialize the HAL PWR peripheral registers to their default reset
+ * values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void) {
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief Enable access to the backup domain
+ * (RTC registers, RTC backup data registers).
+ * @note After reset, the backup domain is protected against
+ * possible unwanted write accesses.
+ * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up
+ * domain. In order to set or modify the RTC clock, the backup domain access
+ * must be disabled.
+ * @note LSEON bit that switches on and off the LSE crystal belongs as well to
+ * the back-up domain.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void) { SET_BIT(PWR->CR1, PWR_CR1_DBP); }
+
+/**
+ * @brief Disable access to the backup domain
+ * (RTC registers, RTC backup data registers).
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); }
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ [..]
+ *** PVD configuration ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2
+register).
+
+ (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PVD_EXTI_ENABLE_IT() macro.
+ (+) The PVD is stopped in Standby mode.
+
+
+ *** WakeUp pin configuration ***
+ ================================
+ [..]
+ (+) WakeUp pins are used to wakeup the system from Standby mode or
+Shutdown mode. The polarity of these pins can be set to configure event
+detection on high level (rising edge) or low level (falling edge).
+
+
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ The devices feature 8 low-power modes:
+ (+) Low-power Run mode: core and peripherals are running, main regulator
+off, low power regulator on.
+ (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and
+low power regulators on.
+ (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept
+running, main regulator off, low power regulator on.
+ (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low
+power regulators on.
+ (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
+off, low power regulator on.
+ (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE,
+SRAM2 content preserved, main regulator off, low power regulator on.
+ (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE,
+main and low power regulators off.
+ (+) Shutdown mode: all clocks are stopped except LSE, main and low power
+regulators off.
+
+
+ *** Low-power run mode ***
+ ==========================
+ [..]
+ (+) Entry: (from main run mode)
+ (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having
+decreased the system clock below 2 MHz.
+
+ (+) Exit:
+ (++) clear LPR bit then wait for REGLP bit to be reset with
+HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency
+be increased above 2 MHz.
+
+
+ *** Sleep mode / Low-power sleep mode ***
+ =========================================
+ [..]
+ (+) Entry:
+ The Sleep mode / Low-power Sleep mode is entered through
+HAL_PWR_EnterSLEEPMode() API in specifying whether or not the regulator is
+forced to low-power mode and if exit is interrupt or event-triggered.
+ (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
+ (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power
+mode). In the latter case, the system clock frequency must have been decreased
+below 2 MHz beforehand.
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ (+) WFI Exit:
+ (++) Any peripheral interrupt acknowledged by the nested vectored
+interrupt controller (NVIC) or any wake-up event.
+
+ (+) WFE Exit:
+ (++) Any wake-up event such as an EXTI line configured in event mode.
+
+ [..] When exiting the Low-power sleep mode by issuing an interrupt or a
+wakeup event, the MCU is in Low-power Run mode.
+
+ *** Stop 0, Stop 1 modes ***
+ ===============================
+ [..]
+ (+) Entry:
+ The Stop 0, Stop 1 modes are entered through the following API's:
+ (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or
+HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons
+HAL_PWR_EnterSTOPMode().
+ (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
+ (++) PWR_MAINREGULATOR_ON
+ (++) PWR_LOWPOWERREGULATOR_ON
+ (+) Exit (interrupt or event-triggered, specified when entering STOP
+mode):
+ (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+ (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+
+ (+) WFI Exit:
+ (++) Any EXTI Line (Internal or External) configured in Interrupt
+mode.
+ (++) Some specific communication peripherals (USART, LPUART, I2C)
+interrupts when programmed in wakeup mode.
+ (+) WFE Exit:
+ (++) Any EXTI Line (Internal or External) configured in Event mode.
+
+ [..]
+ When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or
+in Low-power Run mode depending on the LPR bit setting.
+
+ *** Standby mode ***
+ ====================
+ [..]
+ The Standby mode offers two options:
+ (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps
+voltage regulator in low power mode). SRAM and registers contents are lost
+except for the SRAM2 content, the RTC registers, RTC backup registers and
+Standby circuitry.
+ (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage
+regulator then disabled). SRAM and register contents are lost except for the RTC
+registers, RTC backup registers and Standby circuitry.
+
+ (++) Entry:
+ (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode()
+API. SRAM1 and register contents are lost except for registers in the Backup
+domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is
+set in PWR_CR3 register. To enable this feature, the user can resort to
+HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit.
+
+ (++) Exit:
+ (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event,
+time-stamp event, external reset in NRST pin, IWDG reset.
+
+ [..] After waking up from Standby mode, program execution restarts in
+the same way as after a Reset.
+
+
+ *** Shutdown mode ***
+ ======================
+ [..]
+ In Shutdown mode,
+ voltage regulator is disabled, all clocks are off except LSE, RRS bit is
+cleared. SRAM and registers contents are lost except for backup domain
+registers.
+
+ (+) Entry:
+ The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode()
+API.
+
+ (+) Exit:
+ (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event,
+time-stamp event, external reset in NRST pin.
+
+ [..] After waking up from Shutdown mode, program execution restarts in
+the same way as after a Reset.
+
+
+ *** Auto-wakeup (AWU) from low-power mode ***
+ =============================================
+ [..]
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+ Wakeup event, a tamper event or a time-stamp event, without depending on
+ an external interrupt (Auto-wakeup mode).
+
+ (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
+
+
+ (++) To wake up from the Stop mode with an RTC alarm event, it is
+necessary to configure the RTC to generate the RTC alarm using the
+HAL_RTC_SetAlarm_IT() function.
+
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp
+event, it is necessary to configure the RTC to detect the tamper or time stamp
+event using the HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT()
+functions.
+
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is
+necessary to configure the RTC to generate the RTC WakeUp event using the
+HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * (PVD).
+ * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the
+ * PVD configuration information.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage thresholds corresponding to each
+ * detection level.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) {
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected
+ */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+
+ /* Configure interrupt mode */
+ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) {
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) {
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the Power Voltage Detector (PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void) { SET_BIT(PWR->CR2, PWR_CR2_PVDE); }
+
+/**
+ * @brief Disable the Power Voltage Detector (PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); }
+
+/**
+ * @brief Enable the WakeUp PINx functionality.
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+ * This parameter can be one of the following legacy values which set
+ * the default polarity i.e. detection on high level (rising edge):
+ * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+ * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
+ *
+ * or one of the following value where the user can explicitly specify
+ * the enabled pin and the chosen polarity:
+ * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
+ * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
+ * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
+ * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+ * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) {
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+
+ /* Specifies the Wake-Up pin polarity for the event detection
+ (rising or falling edge) */
+ MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity),
+ (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
+
+ /* Enable wake-up pin */
+ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+ * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) {
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+ CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
+}
+
+/**
+ * @brief Enter Sleep or Low-power Sleep mode.
+ * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in
+ * Run mode.
+ * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep
+ * mode. This parameter can be one of the following values:
+ * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+ * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator
+ * in low-power mode)
+ * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if
+ * not yet in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with
+ * Regulator set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure
+ * the Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR
+ * register. Additionally, the clock frequency must be reduced below 2 MHz.
+ * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock
+ * frequency must be done before calling HAL_PWR_EnterSLEEPMode() API.
+ * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode.
+ * To move in Run mode, the user must resort to
+ * HAL_PWREx_DisableLowPowerRunMode() API.
+ * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE
+ * instruction. This parameter can be one of the following values:
+ * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode
+ * with WFI instruction
+ * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode
+ * with WFE instruction
+ * @note When WFI entry is used, tick interrupt have to be disabled if not
+ * desired as the interrupt wake up source.
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) {
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Set Regulator parameter */
+ if (Regulator == PWR_MAINREGULATOR_ON) {
+ /* If in low-power run mode at this point, exit it */
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) {
+ (void)HAL_PWREx_DisableLowPowerRunMode();
+ }
+ /* Regulator now in main mode. */
+ } else {
+ /* If in run mode, first move to low-power run mode.
+ The system clock frequency must be below 2 MHz at this point. */
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U) {
+ HAL_PWREx_EnableLowPowerRunMode();
+ }
+ }
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if (SLEEPEntry == PWR_SLEEPENTRY_WFI) {
+ /* Request Wait For Interrupt */
+ __WFI();
+ } else {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enter Stop mode
+ * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
+ * legacy code running on devices where only "Stop mode" is mentioned with main
+ * or low power regulator ON.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note All clocks in the VCORE domain are stopped; the PLL,
+ * the HSI and the HSE oscillators are disabled. Some peripherals with
+ * the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to
+ * receive a frame, and switch off the HSI after receiving the frame if it is
+ * not a wakeup frame. In this case, the HSI clock is propagated only to the
+ * peripheral requesting it. SRAM1, SRAM2 and register contents are preserved.
+ * The BOR is available.
+ * The voltage regulator can be configured either in normal (Stop 0) or
+ * low-power mode (Stop 1).
+ * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup
+ * event, the HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode (Stop 1), an
+ * additional startup delay is incurred when waking up. By keeping the internal
+ * regulator ON during Stop mode (Stop 0), the consumption is higher although
+ * the startup time is reduced.
+ * @param Regulator: Specifies the regulator state in Stop mode.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
+ * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power
+ * regulator ON)
+ * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE
+ * instruction. This parameter can be one of the following values:
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI
+ * instruction.
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE
+ * instruction.
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) {
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+
+ if (Regulator == PWR_LOWPOWERREGULATOR_ON) {
+ HAL_PWREx_EnterSTOP1Mode(STOPEntry);
+ } else {
+ HAL_PWREx_EnterSTOP0Mode(STOPEntry);
+ }
+}
+
+/**
+ * @brief Enter Standby mode.
+ * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched
+ * off. The voltage regulator is disabled, except when SRAM2 content is
+ * preserved in which case the regulator is in low-power mode. SRAM1 and
+ * register contents are lost except for registers in the Backup domain and
+ * Standby circuitry. SRAM2 content can be preserved if the bit RRS is
+ * set in PWR_CR3 register. To enable this feature, the user can resort to
+ * HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit. The BOR is
+ * available.
+ * @note The I/Os can be configured either with a pull-up or pull-down or can
+ * be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and
+ * HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and Pull Down
+ * state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown()
+ * disable the same. These states are effective in Standby mode only if APC bit
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void) {
+ /* Set Stand-by mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined(__CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread
+ * mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+ * processor re-enters SLEEP mode when an interruption handling is over. Setting
+ * this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void) {
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Disable Sleep-On-Exit feature when returning from Handler mode to
+ * Thread mode.
+ * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
+ * processor re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void) {
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enable CORTEX M4 SEVONPEND bit.
+ * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void) {
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Disable CORTEX M4 SEVONPEND bit.
+ * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void) {
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void) {
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_PWR_PVDCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
index 8865381..08061c8 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
@@ -1,1078 +1,1082 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_pwr_ex.c
- * @author MCD Application Team
- * @brief Extended PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Extended Initialization and de-initialization functions
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWREx PWREx
- * @brief PWR Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#if defined(STM32G471xx) || defined(STM32G473xx) || defined(STM32G474xx) || \
- defined(STM32G483xx) || defined(STM32G484xx)
-#define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */
-#define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */
-#elif defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32GBK1CB) || \
- defined(STM32G491xx) || defined(STM32G4A1xx)
-#define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */
-#define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */
-#endif
-
-/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
- * @{
- */
-
-/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
- * @{
- */
-#define PVM_MODE_IT \
- 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */
-#define PVM_MODE_EVT \
- 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */
-#define PVM_RISING_EDGE \
- 0x00000001U /*!< Mask for rising edge set as PVM trigger */
-#define PVM_FALLING_EDGE \
- 0x00000002U /*!< Mask for falling edge set as PVM trigger */
-/**
- * @}
- */
-
-/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
- * @{
- */
-#define PWR_FLAG_SETTING_DELAY_US \
- 50UL /*!< Time out value for REGLPF and VOSF flags setting */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
- * @{
- */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control
-functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Initialization and de-initialization
-functions #####
- ===============================================================================
- [..]
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return Voltage Scaling Range.
- * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or
- * PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when
- * applicable)
- */
-uint32_t HAL_PWREx_GetVoltageRange(void) {
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) {
- return PWR_REGULATOR_VOLTAGE_SCALE2;
- } else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) {
- /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
- return PWR_REGULATOR_VOLTAGE_SCALE1;
- } else {
- return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
- }
-}
-
-/**
- * @brief Configure the main internal regulator output voltage.
- * @param VoltageScaling: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption.
- * This parameter can be one of the following values:
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available,
- * Regulator voltage output range 1 boost mode, typical output voltage at 1.28
- * V, system frequency up to 170 MHz.
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output
- * range 1 mode, typical output voltage at 1.2 V, system frequency up to 150
- * MHz.
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output
- * range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
- * @note When moving from Range 1 to Range 2, the system frequency must be
- * decreased to a value below 26 MHz before calling
- * HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1,
- * the system frequency can be increased to a value up to 150 MHz after calling
- * HAL_PWREx_ControlVoltageScaling() API. When moving from Range 1 to Boost Mode
- * Range 1, the system frequency can be increased to a value up to 170 MHz after
- * calling HAL_PWREx_ControlVoltageScaling() API.
- * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
- * cleared before returning the status. If the flag is not cleared within
- * 50 microseconds, HAL_TIMEOUT status is reported.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) {
- uint32_t wait_loop_index;
-
- assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-
- if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) {
- /* If current range is range 2 */
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) {
- /* Make sure Range 1 Boost is enabled */
- CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
-
- /* Set Range 1 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
-
- /* Wait until VOSF is cleared */
- wait_loop_index =
- ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) &&
- (wait_loop_index != 0U)) {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) {
- return HAL_TIMEOUT;
- }
- }
- /* If current range is range 1 normal or boost mode */
- else {
- /* Enable Range 1 Boost (no issue if bit already reset) */
- CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
- }
- } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) {
- /* If current range is range 2 */
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) {
- /* Make sure Range 1 Boost is disabled */
- SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
-
- /* Set Range 1 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
-
- /* Wait until VOSF is cleared */
- wait_loop_index =
- ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) &&
- (wait_loop_index != 0U)) {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) {
- return HAL_TIMEOUT;
- }
- }
- /* If current range is range 1 normal or boost mode */
- else {
- /* Disable Range 1 Boost (no issue if bit already set) */
- SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
- }
- } else {
- /* Set Range 2 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
- /* No need to wait for VOSF to be cleared for this transition */
- /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable battery charging.
- * When VDD is present, charge the external battery on VBAT through an
- * internal resistor.
- * @param ResistorSelection: specifies the resistor impedance.
- * This parameter can be one of the following values:
- * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
- * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
- * @retval None
- */
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) {
- assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
-
- /* Specify resistor selection */
- MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
-
- /* Enable battery charging */
- SET_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-/**
- * @brief Disable battery charging.
- * @retval None
- */
-void HAL_PWREx_DisableBatteryCharging(void) {
- CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-/**
- * @brief Enable Internal Wake-up Line.
- * @retval None
- */
-void HAL_PWREx_EnableInternalWakeUpLine(void) {
- SET_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-/**
- * @brief Disable Internal Wake-up Line.
- * @retval None
- */
-void HAL_PWREx_DisableInternalWakeUpLine(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-/**
- * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
- * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O
- * in pull-up state in Standby and Shutdown modes.
- * @note This state is effective in Standby and Shutdown modes only if APC bit
- * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
- * @note The configuration is lost when exiting the Shutdown mode due to the
- * power-on reset, maintained when exiting the Standby mode.
- * @note To avoid any conflict at Standby and Shutdown modes exits, the
- * corresponding PDy bit of PWR_PDCRx register is cleared unless it is reserved.
- * @note Even if a PUy bit to set is reserved, the other PUy bits entered as
- * input parameter at the same time are set.
- * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ...,
- * PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO
- * peripheral.
- * @param GPIONumber: Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to set
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber) {
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO) {
- case PWR_GPIO_A:
- SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
- CLEAR_BIT(PWR->PDCRA,
- (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
- break;
- case PWR_GPIO_B:
- SET_BIT(PWR->PUCRB, GPIONumber);
- CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
- break;
- case PWR_GPIO_C:
- SET_BIT(PWR->PUCRC, GPIONumber);
- CLEAR_BIT(PWR->PDCRC, GPIONumber);
- break;
- case PWR_GPIO_D:
- SET_BIT(PWR->PUCRD, GPIONumber);
- CLEAR_BIT(PWR->PDCRD, GPIONumber);
- break;
- case PWR_GPIO_E:
- SET_BIT(PWR->PUCRE, GPIONumber);
- CLEAR_BIT(PWR->PDCRE, GPIONumber);
- break;
- case PWR_GPIO_F:
- SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
- CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
- break;
- case PWR_GPIO_G:
- SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
- CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) &
- (~(PWR_GPIO_BIT_10))));
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
- * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure
- * the I/O in pull-up state in Standby and Shutdown modes.
- * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as
- * input parameter at the same time are reset.
- * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ...,
- * PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO
- * peripheral.
- * @param GPIONumber: Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to reset
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,
- uint32_t GPIONumber) {
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO) {
- case PWR_GPIO_A:
- CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
- break;
- case PWR_GPIO_B:
- CLEAR_BIT(PWR->PUCRB, GPIONumber);
- break;
- case PWR_GPIO_C:
- CLEAR_BIT(PWR->PUCRC, GPIONumber);
- break;
- case PWR_GPIO_D:
- CLEAR_BIT(PWR->PUCRD, GPIONumber);
- break;
- case PWR_GPIO_E:
- CLEAR_BIT(PWR->PUCRE, GPIONumber);
- break;
- case PWR_GPIO_F:
- CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
- break;
- case PWR_GPIO_G:
- CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
- * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O
- * in pull-down state in Standby and Shutdown modes.
- * @note This state is effective in Standby and Shutdown modes only if APC bit
- * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
- * @note The configuration is lost when exiting the Shutdown mode due to the
- * power-on reset, maintained when exiting the Standby mode.
- * @note To avoid any conflict at Standby and Shutdown modes exits, the
- * corresponding PUy bit of PWR_PUCRx register is cleared unless it is reserved.
- * @note Even if a PDy bit to set is reserved, the other PDy bits entered as
- * input parameter at the same time are set.
- * @param GPIO: Specify the IO port. This parameter can be
- * PWR_GPIO_A..PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the
- * GPIO peripheral.
- * @param GPIONumber: Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to set
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber) {
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO) {
- case PWR_GPIO_A:
- SET_BIT(PWR->PDCRA,
- (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
- CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
- break;
- case PWR_GPIO_B:
- SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
- CLEAR_BIT(PWR->PUCRB, GPIONumber);
- break;
- case PWR_GPIO_C:
- SET_BIT(PWR->PDCRC, GPIONumber);
- CLEAR_BIT(PWR->PUCRC, GPIONumber);
- break;
- case PWR_GPIO_D:
- SET_BIT(PWR->PDCRD, GPIONumber);
- CLEAR_BIT(PWR->PUCRD, GPIONumber);
- break;
- case PWR_GPIO_E:
- SET_BIT(PWR->PDCRE, GPIONumber);
- CLEAR_BIT(PWR->PUCRE, GPIONumber);
- break;
- case PWR_GPIO_F:
- SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
- CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
- break;
- case PWR_GPIO_G:
- SET_BIT(PWR->PDCRG,
- ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
- CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
- * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure
- * the I/O in pull-down state in Standby and Shutdown modes.
- * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as
- * input parameter at the same time are reset.
- * @param GPIO: Specifies the IO port. This parameter can be
- * PWR_GPIO_A..PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the
- * GPIO peripheral.
- * @param GPIONumber: Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to reset
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,
- uint32_t GPIONumber) {
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO) {
- case PWR_GPIO_A:
- CLEAR_BIT(PWR->PDCRA,
- (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
- break;
- case PWR_GPIO_B:
- CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
- break;
- case PWR_GPIO_C:
- CLEAR_BIT(PWR->PDCRC, GPIONumber);
- break;
- case PWR_GPIO_D:
- CLEAR_BIT(PWR->PDCRD, GPIONumber);
- break;
- case PWR_GPIO_E:
- CLEAR_BIT(PWR->PDCRE, GPIONumber);
- break;
- case PWR_GPIO_F:
- CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
- break;
- case PWR_GPIO_G:
- CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) &
- (~(PWR_GPIO_BIT_10))));
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Enable pull-up and pull-down configuration.
- * @note When APC bit is set, the I/O pull-up and pull-down configurations
- * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby and
- * Shutdown modes.
- * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the
- * corresponding PDy bit of PWR_PDCRx register is also set (pull-down
- * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and
- * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict when setting
- * PUy or PDy bit.
- * @retval None
- */
-void HAL_PWREx_EnablePullUpPullDownConfig(void) {
- SET_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-/**
- * @brief Disable pull-up and pull-down configuration.
- * @note When APC bit is cleared, the I/O pull-up and pull-down configurations
- * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and
- * Shutdown modes.
- * @retval None
- */
-void HAL_PWREx_DisablePullUpPullDownConfig(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-/**
- * @brief Enable SRAM2 content retention in Standby mode.
- * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
- * Standby mode and its content is kept.
- * @retval None
- */
-void HAL_PWREx_EnableSRAM2ContentRetention(void) {
- SET_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-/**
- * @brief Disable SRAM2 content retention in Standby mode.
- * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
- * and its content is lost.
- * @retval None
- */
-void HAL_PWREx_DisableSRAM2ContentRetention(void) {
- CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-#if defined(PWR_CR2_PVME1)
-/**
- * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum
- * voltage.
- * @retval None
- */
-void HAL_PWREx_EnablePVM1(void) { SET_BIT(PWR->CR2, PWR_PVM_1); }
-
-/**
- * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum
- * voltage.
- * @retval None
- */
-void HAL_PWREx_DisablePVM1(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_1); }
-#endif /* PWR_CR2_PVME1 */
-
-#if defined(PWR_CR2_PVME2)
-/**
- * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum
- * voltage.
- * @retval None
- */
-void HAL_PWREx_EnablePVM2(void) { SET_BIT(PWR->CR2, PWR_PVM_2); }
-
-/**
- * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum
- * voltage.
- * @retval None
- */
-void HAL_PWREx_DisablePVM2(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_2); }
-#endif /* PWR_CR2_PVME2 */
-
-/**
- * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum
- * voltage 1.62V.
- * @retval None
- */
-void HAL_PWREx_EnablePVM3(void) { SET_BIT(PWR->CR2, PWR_PVM_3); }
-
-/**
- * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum
- * voltage 1.62V.
- * @retval None
- */
-void HAL_PWREx_DisablePVM3(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_3); }
-
-/**
- * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum
- * voltage 1.8V.
- * @retval None
- */
-void HAL_PWREx_EnablePVM4(void) { SET_BIT(PWR->CR2, PWR_PVM_4); }
-
-/**
- * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum
- * voltage 1.8V.
- * @retval None
- */
-void HAL_PWREx_DisablePVM4(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_4); }
-
-/**
- * @brief Configure the Peripheral Voltage Monitoring (PVM).
- * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
- * PVM configuration information.
- * @note The API configures a single PVM according to the information contained
- * in the input structure. To configure several PVMs, the API must be
- * singly called for each PVM used.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage thresholds corresponding to each
- * detection level and to each monitored supply.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
- assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
-
- /* Configure EXTI 35 to 38 interrupts if so required:
- scan through PVMType to detect which PVMx is set and
- configure the corresponding EXTI line accordingly. */
- switch (sConfigPVM->PVMType) {
-#if defined(PWR_CR2_PVME1)
- case PWR_PVM_1:
- /* Clear any previous config. Keep it clear if no event or IT mode is
- * selected */
- __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM1_EXTI_DISABLE_IT();
- __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
- __HAL_PWR_PVM1_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
- __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
- __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
- }
-
- if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
- __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-#endif /* PWR_CR2_PVME1 */
-
-#if defined(PWR_CR2_PVME2)
- case PWR_PVM_2:
- /* Clear any previous config. Keep it clear if no event or IT mode is
- * selected */
- __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM2_EXTI_DISABLE_IT();
- __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
- __HAL_PWR_PVM2_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
- __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
- __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
- }
-
- if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
- __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-#endif /* PWR_CR2_PVME2 */
-
- case PWR_PVM_3:
- /* Clear any previous config. Keep it clear if no event or IT mode is
- * selected */
- __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM3_EXTI_DISABLE_IT();
- __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
- __HAL_PWR_PVM3_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
- __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
- __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
- }
-
- if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
- __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-
- case PWR_PVM_4:
- /* Clear any previous config. Keep it clear if no event or IT mode is
- * selected */
- __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM4_EXTI_DISABLE_IT();
- __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
- __HAL_PWR_PVM4_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
- __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
- __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
- }
-
- if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
- __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Enter Low-power Run mode
- * @note In Low-power Run mode, all I/O pins keep the same state as in Run
- * mode.
- * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can
- * optionally configure the Flash in power-down monde in setting the RUN_PD bit
- * in FLASH_ACR register. Additionally, the clock frequency must be reduced
- * below 2 MHz. Setting RUN_PD in FLASH_ACR then appropriately reducing the
- * clock frequency must be done before calling HAL_PWREx_EnableLowPowerRunMode()
- * API.
- * @retval None
- */
-void HAL_PWREx_EnableLowPowerRunMode(void) {
- /* Set Regulator parameter */
- SET_BIT(PWR->CR1, PWR_CR1_LPR);
-}
-
-/**
- * @brief Exit Low-power Run mode.
- * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function
- * checks that REGLPF has been properly reset (otherwise,
- * HAL_PWREx_DisableLowPowerRunMode returns HAL_TIMEOUT status). The system
- * clock frequency can then be increased above 2 MHz.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) {
- uint32_t wait_loop_index;
-
- /* Clear LPR bit */
- CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
-
- /* Wait until REGLPF is reset */
- wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) &&
- (wait_loop_index != 0U)) {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) {
- return HAL_TIMEOUT;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Enter Stop 0 mode.
- * @note In Stop 0 mode, main and low voltage regulators are ON.
- * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped; the PLL, the HSI
- * and the HSE oscillators are disabled. Some peripherals with the wakeup
- * capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a
- * frame, and switch off the HSI after receiving the frame if it is not a wakeup
- * frame. In this case, the HSI clock is propagated only to the peripheral
- * requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is
- * available.
- * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock if STOPWUCK bit in
- * RCC_CFGR register is set; the HSI oscillator is selected if STOPWUCK is
- * cleared.
- * @note By keeping the internal regulator ON during Stop 0 mode, the
- * consumption is higher although the startup time is reduced.
- * @param STOPEntry specifies if Stop mode in entered with WFI or WFE
- * instruction. This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) {
- /* Check the parameters */
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Stop 0 mode with Main Regulator */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if (STOPEntry == PWR_STOPENTRY_WFI) {
- /* Request Wait For Interrupt */
- __WFI();
- } else {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Enter Stop 1 mode.
- * @note In Stop 1 mode, only low power voltage regulator is ON.
- * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped; the PLL, the HSI
- * and the HSE oscillators are disabled. Some peripherals with the wakeup
- * capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a
- * frame, and switch off the HSI after receiving the frame if it is not a wakeup
- * frame. In this case, the HSI clock is propagated only to the peripheral
- * requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is
- * available.
- * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock if STOPWUCK bit in
- * RCC_CFGR register is set.
- * @note Due to low power mode, an additional startup delay is incurred when
- * waking up from Stop 1 mode.
- * @param STOPEntry specifies if Stop mode in entered with WFI or WFE
- * instruction. This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) {
- /* Check the parameters */
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Stop 1 mode with Low-Power Regulator */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if (STOPEntry == PWR_STOPENTRY_WFI) {
- /* Request Wait For Interrupt */
- __WFI();
- } else {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Enter Shutdown mode.
- * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators
- * are switched off. The voltage regulator is disabled and Vcore domain is
- * powered off. SRAM1, SRAM2 and registers contents are lost except for
- * registers in the Backup domain. The BOR is not available.
- * @note The I/Os can be configured either with a pull-up or pull-down or can
- * be kept in analog state.
- * @retval None
- */
-void HAL_PWREx_EnterSHUTDOWNMode(void) {
- /* Set Shutdown mode */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-/* This option is used to ensure that store operations are completed */
-#if defined(__CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @brief This function handles the PWR PVD/PVMx interrupt request.
- * @note This API should be called under the PVD_PVM_IRQHandler().
- * @retval None
- */
-void HAL_PWREx_PVD_PVM_IRQHandler(void) {
- /* Check PWR exti flag */
- if (__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PVD exti pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
- /* Next, successively check PVMx exti flags */
-#if defined(PWR_CR2_PVME1)
- if (__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) {
- /* PWR PVM1 interrupt user callback */
- HAL_PWREx_PVM1Callback();
-
- /* Clear PVM1 exti pending bit */
- __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
- }
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
- if (__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U) {
- /* PWR PVM2 interrupt user callback */
- HAL_PWREx_PVM2Callback();
-
- /* Clear PVM2 exti pending bit */
- __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
- }
-#endif /* PWR_CR2_PVME2 */
- if (__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) {
- /* PWR PVM3 interrupt user callback */
- HAL_PWREx_PVM3Callback();
-
- /* Clear PVM3 exti pending bit */
- __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
- }
- if (__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U) {
- /* PWR PVM4 interrupt user callback */
- HAL_PWREx_PVM4Callback();
-
- /* Clear PVM4 exti pending bit */
- __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
- }
-}
-
-#if defined(PWR_CR2_PVME1)
-/**
- * @brief PWR PVM1 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM1Callback(void) {
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM1Callback() API can be implemented in the user file
- */
-}
-#endif /* PWR_CR2_PVME1 */
-
-#if defined(PWR_CR2_PVME2)
-/**
- * @brief PWR PVM2 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM2Callback(void) {
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM2Callback() API can be implemented in the user file
- */
-}
-#endif /* PWR_CR2_PVME2 */
-
-/**
- * @brief PWR PVM3 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM3Callback(void) {
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM3Callback() API can be implemented in the user file
- */
-}
-
-/**
- * @brief PWR PVM4 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM4Callback(void) {
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM4Callback() API can be implemented in the user file
- */
-}
-
-#if defined(PWR_CR3_UCPD_STDBY)
-/**
- * @brief Enable UCPD configuration memorization in Standby.
- * @retval None
- */
-void HAL_PWREx_EnableUCPDStandbyMode(void) {
- /* Memorize UCPD configuration when entering standby mode */
- SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
-}
-
-/**
- * @brief Disable UCPD configuration memorization in Standby.
- * @note This function must be called on exiting the Standby mode and before
- * any UCPD configuration update.
- * @retval None
- */
-void HAL_PWREx_DisableUCPDStandbyMode(void) {
- /* Write 0 immediately after Standby exit when using UCPD,
- and before writing any UCPD registers */
- CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
-}
-#endif /* PWR_CR3_UCPD_STDBY */
-
-#if defined(PWR_CR3_UCPD_DBDIS)
-/**
- * @brief Enable the USB Type-C dead battery pull-down behavior
- * on UCPDx_CC1 and UCPDx_CC2 pins
- * @retval None
- */
-void HAL_PWREx_EnableUCPDDeadBattery(void) {
- /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
- CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
-}
-
-/**
- * @brief Disable the USB Type-C dead battery pull-down behavior
- * on UCPDx_CC1 and UCPDx_CC2 pins
- * @note After exiting reset, the USB Type-C dead battery behavior will be
- * enabled, which may have a pull-down effect on CC1 and CC2 pins. It is
- * recommended to disable it in all cases, either to stop this pull-down or to
- * hand over control to the UCPD (which should therefore be initialized before
- * doing the disable).
- * @retval None
- */
-void HAL_PWREx_DisableUCPDDeadBattery(void) {
- /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
- SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
-}
-#endif /* PWR_CR3_UCPD_DBDIS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx
+ * @brief PWR Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#if defined(STM32G471xx) || defined(STM32G473xx) || defined(STM32G414xx) || \
+ defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
+#define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */
+#define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G431xx) || \
+ defined(STM32G441xx) || defined(STM32GBK1CB) || defined(STM32G491xx) || \
+ defined(STM32G4A1xx)
+#define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */
+#define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */
+#endif /* STM32G471xx || STM32G473xx || STM32G414xx || STM32G474xx || \
+ STM32G483xx || STM32G484xx */
+
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+ * @{
+ */
+
+/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
+ * @{
+ */
+#define PVM_MODE_IT \
+ 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */
+#define PVM_MODE_EVT \
+ 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */
+#define PVM_RISING_EDGE \
+ 0x00000001U /*!< Mask for rising edge set as PVM trigger */
+#define PVM_FALLING_EDGE \
+ 0x00000002U /*!< Mask for falling edge set as PVM trigger */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
+ * @{
+ */
+#define PWR_FLAG_SETTING_DELAY_US \
+ 50UL /*!< Time out value for REGLPF and VOSF flags setting */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control
+functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Initialization and de-initialization
+functions #####
+ ===============================================================================
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return Voltage Scaling Range.
+ * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or
+ * PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when
+ * applicable)
+ */
+uint32_t HAL_PWREx_GetVoltageRange(void) {
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) {
+ return PWR_REGULATOR_VOLTAGE_SCALE2;
+ } else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) {
+ /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
+ return PWR_REGULATOR_VOLTAGE_SCALE1;
+ } else {
+ return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
+ }
+}
+
+/**
+ * @brief Configure the main internal regulator output voltage.
+ * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available,
+ * Regulator voltage output range 1 boost mode, typical output voltage at 1.28
+ * V, system frequency up to 170 MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output
+ * range 1 mode, typical output voltage at 1.2 V, system frequency up to 150
+ * MHz.
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output
+ * range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
+ * @note When moving from Range 1 to Range 2, the system frequency must be
+ * decreased to a value below 26 MHz before calling
+ * HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1,
+ * the system frequency can be increased to a value up to 150 MHz after calling
+ * HAL_PWREx_ControlVoltageScaling() API. When moving from Range 1 to Boost Mode
+ * Range 1, the system frequency can be increased to a value up to 170 MHz after
+ * calling HAL_PWREx_ControlVoltageScaling() API.
+ * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
+ * cleared before returning the status. If the flag is not cleared within
+ * 50 microseconds, HAL_TIMEOUT status is reported.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) {
+ uint32_t wait_loop_index;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) {
+ /* If current range is range 2 */
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) {
+ /* Make sure Range 1 Boost is enabled */
+ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+
+ /* Set Range 1 */
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Wait until VOSF is cleared */
+ wait_loop_index =
+ ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) &&
+ (wait_loop_index != 0U)) {
+ wait_loop_index--;
+ }
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* If current range is range 1 normal or boost mode */
+ else {
+ /* Enable Range 1 Boost (no issue if bit already reset) */
+ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+ }
+ } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) {
+ /* If current range is range 2 */
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) {
+ /* Make sure Range 1 Boost is disabled */
+ SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+
+ /* Set Range 1 */
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Wait until VOSF is cleared */
+ wait_loop_index =
+ ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) &&
+ (wait_loop_index != 0U)) {
+ wait_loop_index--;
+ }
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* If current range is range 1 normal or boost mode */
+ else {
+ /* Disable Range 1 Boost (no issue if bit already set) */
+ SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+ }
+ } else {
+ /* Set Range 2 */
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
+ /* No need to wait for VOSF to be cleared for this transition */
+ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable battery charging.
+ * When VDD is present, charge the external battery on VBAT through an
+ * internal resistor.
+ * @param ResistorSelection: specifies the resistor impedance.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
+ * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
+ * @retval None
+ */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) {
+ assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
+
+ /* Specify resistor selection */
+ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
+
+ /* Enable battery charging */
+ SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+ * @brief Disable battery charging.
+ * @retval None
+ */
+void HAL_PWREx_DisableBatteryCharging(void) {
+ CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+ * @brief Enable Internal Wake-up Line.
+ * @retval None
+ */
+void HAL_PWREx_EnableInternalWakeUpLine(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+ * @brief Disable Internal Wake-up Line.
+ * @retval None
+ */
+void HAL_PWREx_DisableInternalWakeUpLine(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+ * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
+ * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O
+ * in pull-up state in Standby and Shutdown modes.
+ * @note This state is effective in Standby and Shutdown modes only if APC bit
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @note The configuration is lost when exiting the Shutdown mode due to the
+ * power-on reset, maintained when exiting the Standby mode.
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the
+ * corresponding PDy bit of PWR_PDCRx register is cleared unless it is reserved.
+ * @note Even if a PUy bit to set is reserved, the other PUy bits entered as
+ * input parameter at the same time are set.
+ * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ...,
+ * PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO
+ * peripheral.
+ * @param GPIONumber: Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ * I/O pins are available) or the logical OR of several of them to set
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO) {
+ case PWR_GPIO_A:
+ SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+ CLEAR_BIT(PWR->PDCRA,
+ (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
+ break;
+ case PWR_GPIO_B:
+ SET_BIT(PWR->PUCRB, GPIONumber);
+ CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+ break;
+ case PWR_GPIO_C:
+ SET_BIT(PWR->PUCRC, GPIONumber);
+ CLEAR_BIT(PWR->PDCRC, GPIONumber);
+ break;
+ case PWR_GPIO_D:
+ SET_BIT(PWR->PUCRD, GPIONumber);
+ CLEAR_BIT(PWR->PDCRD, GPIONumber);
+ break;
+ case PWR_GPIO_E:
+ SET_BIT(PWR->PUCRE, GPIONumber);
+ CLEAR_BIT(PWR->PDCRE, GPIONumber);
+ break;
+ case PWR_GPIO_F:
+ SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ break;
+ case PWR_GPIO_G:
+ SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) &
+ (~(PWR_GPIO_BIT_10))));
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
+ * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure
+ * the I/O in pull-up state in Standby and Shutdown modes.
+ * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as
+ * input parameter at the same time are reset.
+ * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ...,
+ * PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO
+ * peripheral.
+ * @param GPIONumber: Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ * I/O pins are available) or the logical OR of several of them to reset
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO) {
+ case PWR_GPIO_A:
+ CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+ break;
+ case PWR_GPIO_B:
+ CLEAR_BIT(PWR->PUCRB, GPIONumber);
+ break;
+ case PWR_GPIO_C:
+ CLEAR_BIT(PWR->PUCRC, GPIONumber);
+ break;
+ case PWR_GPIO_D:
+ CLEAR_BIT(PWR->PUCRD, GPIONumber);
+ break;
+ case PWR_GPIO_E:
+ CLEAR_BIT(PWR->PUCRE, GPIONumber);
+ break;
+ case PWR_GPIO_F:
+ CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ break;
+ case PWR_GPIO_G:
+ CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
+ * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O
+ * in pull-down state in Standby and Shutdown modes.
+ * @note This state is effective in Standby and Shutdown modes only if APC bit
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @note The configuration is lost when exiting the Shutdown mode due to the
+ * power-on reset, maintained when exiting the Standby mode.
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the
+ * corresponding PUy bit of PWR_PUCRx register is cleared unless it is reserved.
+ * @note Even if a PDy bit to set is reserved, the other PDy bits entered as
+ * input parameter at the same time are set.
+ * @param GPIO: Specify the IO port. This parameter can be
+ * PWR_GPIO_A..PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the
+ * GPIO peripheral.
+ * @param GPIONumber: Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ * I/O pins are available) or the logical OR of several of them to set
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO) {
+ case PWR_GPIO_A:
+ SET_BIT(PWR->PDCRA,
+ (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
+ CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+ break;
+ case PWR_GPIO_B:
+ SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+ CLEAR_BIT(PWR->PUCRB, GPIONumber);
+ break;
+ case PWR_GPIO_C:
+ SET_BIT(PWR->PDCRC, GPIONumber);
+ CLEAR_BIT(PWR->PUCRC, GPIONumber);
+ break;
+ case PWR_GPIO_D:
+ SET_BIT(PWR->PDCRD, GPIONumber);
+ CLEAR_BIT(PWR->PUCRD, GPIONumber);
+ break;
+ case PWR_GPIO_E:
+ SET_BIT(PWR->PDCRE, GPIONumber);
+ CLEAR_BIT(PWR->PUCRE, GPIONumber);
+ break;
+ case PWR_GPIO_F:
+ SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ break;
+ case PWR_GPIO_G:
+ SET_BIT(PWR->PDCRG,
+ ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+ CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
+ * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure
+ * the I/O in pull-down state in Standby and Shutdown modes.
+ * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as
+ * input parameter at the same time are reset.
+ * @param GPIO: Specifies the IO port. This parameter can be
+ * PWR_GPIO_A..PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the
+ * GPIO peripheral.
+ * @param GPIONumber: Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ * I/O pins are available) or the logical OR of several of them to reset
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,
+ uint32_t GPIONumber) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO) {
+ case PWR_GPIO_A:
+ CLEAR_BIT(PWR->PDCRA,
+ (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
+ break;
+ case PWR_GPIO_B:
+ CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+ break;
+ case PWR_GPIO_C:
+ CLEAR_BIT(PWR->PDCRC, GPIONumber);
+ break;
+ case PWR_GPIO_D:
+ CLEAR_BIT(PWR->PDCRD, GPIONumber);
+ break;
+ case PWR_GPIO_E:
+ CLEAR_BIT(PWR->PDCRE, GPIONumber);
+ break;
+ case PWR_GPIO_F:
+ CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ break;
+ case PWR_GPIO_G:
+ CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) &
+ (~(PWR_GPIO_BIT_10))));
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable pull-up and pull-down configuration.
+ * @note When APC bit is set, the I/O pull-up and pull-down configurations
+ * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby and
+ * Shutdown modes.
+ * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the
+ * corresponding PDy bit of PWR_PDCRx register is also set (pull-down
+ * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and
+ * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict when setting
+ * PUy or PDy bit.
+ * @retval None
+ */
+void HAL_PWREx_EnablePullUpPullDownConfig(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+ * @brief Disable pull-up and pull-down configuration.
+ * @note When APC bit is cleared, the I/O pull-up and pull-down configurations
+ * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and
+ * Shutdown modes.
+ * @retval None
+ */
+void HAL_PWREx_DisablePullUpPullDownConfig(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+#if defined(SRAM2_BASE)
+/**
+ * @brief Enable SRAM2 content retention in Standby mode.
+ * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
+ * Standby mode and its content is kept.
+ * @retval None
+ */
+void HAL_PWREx_EnableSRAM2ContentRetention(void) {
+ SET_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+ * @brief Disable SRAM2 content retention in Standby mode.
+ * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
+ * and its content is lost.
+ * @retval None
+ */
+void HAL_PWREx_DisableSRAM2ContentRetention(void) {
+ CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+#endif /* SRAM2_BASE */
+
+#if defined(PWR_CR2_PVME1)
+/**
+ * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum
+ * voltage.
+ * @retval None
+ */
+void HAL_PWREx_EnablePVM1(void) { SET_BIT(PWR->CR2, PWR_PVM_1); }
+
+/**
+ * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum
+ * voltage.
+ * @retval None
+ */
+void HAL_PWREx_DisablePVM1(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_1); }
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+/**
+ * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum
+ * voltage.
+ * @retval None
+ */
+void HAL_PWREx_EnablePVM2(void) { SET_BIT(PWR->CR2, PWR_PVM_2); }
+
+/**
+ * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum
+ * voltage.
+ * @retval None
+ */
+void HAL_PWREx_DisablePVM2(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_2); }
+#endif /* PWR_CR2_PVME2 */
+
+/**
+ * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum
+ * voltage 1.62V.
+ * @retval None
+ */
+void HAL_PWREx_EnablePVM3(void) { SET_BIT(PWR->CR2, PWR_PVM_3); }
+
+/**
+ * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum
+ * voltage 1.62V.
+ * @retval None
+ */
+void HAL_PWREx_DisablePVM3(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_3); }
+
+/**
+ * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum
+ * voltage 1.8V.
+ * @retval None
+ */
+void HAL_PWREx_EnablePVM4(void) { SET_BIT(PWR->CR2, PWR_PVM_4); }
+
+/**
+ * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum
+ * voltage 1.8V.
+ * @retval None
+ */
+void HAL_PWREx_DisablePVM4(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_4); }
+
+/**
+ * @brief Configure the Peripheral Voltage Monitoring (PVM).
+ * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
+ * PVM configuration information.
+ * @note The API configures a single PVM according to the information contained
+ * in the input structure. To configure several PVMs, the API must be
+ * singly called for each PVM used.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage thresholds corresponding to each
+ * detection level and to each monitored supply.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
+ assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
+
+ /* Configure EXTI 35 to 38 interrupts if so required:
+ scan through PVMType to detect which PVMx is set and
+ configure the corresponding EXTI line accordingly. */
+ switch (sConfigPVM->PVMType) {
+#if defined(PWR_CR2_PVME1)
+ case PWR_PVM_1:
+ /* Clear any previous config. Keep it clear if no event or IT mode is
+ * selected */
+ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVM1_EXTI_DISABLE_IT();
+ __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
+ __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
+
+ /* Configure interrupt mode */
+ if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
+ __HAL_PWR_PVM1_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
+ __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
+ __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
+ __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
+ }
+ break;
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+ case PWR_PVM_2:
+ /* Clear any previous config. Keep it clear if no event or IT mode is
+ * selected */
+ __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVM2_EXTI_DISABLE_IT();
+ __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
+ __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
+
+ /* Configure interrupt mode */
+ if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
+ __HAL_PWR_PVM2_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
+ __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
+ __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
+ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
+ }
+ break;
+#endif /* PWR_CR2_PVME2 */
+
+ case PWR_PVM_3:
+ /* Clear any previous config. Keep it clear if no event or IT mode is
+ * selected */
+ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVM3_EXTI_DISABLE_IT();
+ __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
+ __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
+
+ /* Configure interrupt mode */
+ if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
+ __HAL_PWR_PVM3_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
+ __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
+ __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
+ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
+ }
+ break;
+
+ case PWR_PVM_4:
+ /* Clear any previous config. Keep it clear if no event or IT mode is
+ * selected */
+ __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVM4_EXTI_DISABLE_IT();
+ __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
+ __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
+
+ /* Configure interrupt mode */
+ if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) {
+ __HAL_PWR_PVM4_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) {
+ __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) {
+ __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) {
+ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
+ }
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enter Low-power Run mode
+ * @note In Low-power Run mode, all I/O pins keep the same state as in Run
+ * mode.
+ * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can
+ * optionally configure the Flash in power-down monde in setting the RUN_PD bit
+ * in FLASH_ACR register. Additionally, the clock frequency must be reduced
+ * below 2 MHz. Setting RUN_PD in FLASH_ACR then appropriately reducing the
+ * clock frequency must be done before calling HAL_PWREx_EnableLowPowerRunMode()
+ * API.
+ * @retval None
+ */
+void HAL_PWREx_EnableLowPowerRunMode(void) {
+ /* Set Regulator parameter */
+ SET_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+ * @brief Exit Low-power Run mode.
+ * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function
+ * checks that REGLPF has been properly reset (otherwise,
+ * HAL_PWREx_DisableLowPowerRunMode returns HAL_TIMEOUT status). The system
+ * clock frequency can then be increased above 2 MHz.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) {
+ uint32_t wait_loop_index;
+
+ /* Clear LPR bit */
+ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+
+ /* Wait until REGLPF is reset */
+ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) &&
+ (wait_loop_index != 0U)) {
+ wait_loop_index--;
+ }
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enter Stop 0 mode.
+ * @note In Stop 0 mode, main and low voltage regulators are ON.
+ * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
+ * @note All clocks in the VCORE domain are stopped; the PLL, the HSI
+ * and the HSE oscillators are disabled. Some peripherals with the wakeup
+ * capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a
+ * frame, and switch off the HSI after receiving the frame if it is not a wakeup
+ * frame. In this case, the HSI clock is propagated only to the peripheral
+ * requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is
+ * available.
+ * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
+ * the HSI RC oscillator is selected as system clock if STOPWUCK bit in
+ * RCC_CFGR register is set; the HSI oscillator is selected if STOPWUCK is
+ * cleared.
+ * @note By keeping the internal regulator ON during Stop 0 mode, the
+ * consumption is higher although the startup time is reduced.
+ * @param STOPEntry specifies if Stop mode in entered with WFI or WFE
+ * instruction. This parameter can be one of the following values:
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) {
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Stop 0 mode with Main Regulator */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry --------------------------------------------------*/
+ if (STOPEntry == PWR_STOPENTRY_WFI) {
+ /* Request Wait For Interrupt */
+ __WFI();
+ } else {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enter Stop 1 mode.
+ * @note In Stop 1 mode, only low power voltage regulator is ON.
+ * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
+ * @note All clocks in the VCORE domain are stopped; the PLL, the HSI
+ * and the HSE oscillators are disabled. Some peripherals with the wakeup
+ * capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a
+ * frame, and switch off the HSI after receiving the frame if it is not a wakeup
+ * frame. In this case, the HSI clock is propagated only to the peripheral
+ * requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is
+ * available.
+ * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
+ * the HSI RC oscillator is selected as system clock if STOPWUCK bit in
+ * RCC_CFGR register is set.
+ * @note Due to low power mode, an additional startup delay is incurred when
+ * waking up from Stop 1 mode.
+ * @param STOPEntry specifies if Stop mode in entered with WFI or WFE
+ * instruction. This parameter can be one of the following values:
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) {
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Stop 1 mode with Low-Power Regulator */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry --------------------------------------------------*/
+ if (STOPEntry == PWR_STOPENTRY_WFI) {
+ /* Request Wait For Interrupt */
+ __WFI();
+ } else {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enter Shutdown mode.
+ * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators
+ * are switched off. The voltage regulator is disabled and Vcore domain is
+ * powered off. SRAM1, SRAM2 and registers contents are lost except for
+ * registers in the Backup domain. The BOR is not available.
+ * @note The I/Os can be configured either with a pull-up or pull-down or can
+ * be kept in analog state.
+ * @retval None
+ */
+void HAL_PWREx_EnterSHUTDOWNMode(void) {
+ /* Set Shutdown mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined(__CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief This function handles the PWR PVD/PVMx interrupt request.
+ * @note This API should be called under the PVD_PVM_IRQHandler().
+ * @retval None
+ */
+void HAL_PWREx_PVD_PVM_IRQHandler(void) {
+ /* Check PWR exti flag */
+ if (__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PVD exti pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ }
+ /* Next, successively check PVMx exti flags */
+#if defined(PWR_CR2_PVME1)
+ if (__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) {
+ /* PWR PVM1 interrupt user callback */
+ HAL_PWREx_PVM1Callback();
+
+ /* Clear PVM1 exti pending bit */
+ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
+ }
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+ if (__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U) {
+ /* PWR PVM2 interrupt user callback */
+ HAL_PWREx_PVM2Callback();
+
+ /* Clear PVM2 exti pending bit */
+ __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
+ }
+#endif /* PWR_CR2_PVME2 */
+ if (__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) {
+ /* PWR PVM3 interrupt user callback */
+ HAL_PWREx_PVM3Callback();
+
+ /* Clear PVM3 exti pending bit */
+ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
+ }
+ if (__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U) {
+ /* PWR PVM4 interrupt user callback */
+ HAL_PWREx_PVM4Callback();
+
+ /* Clear PVM4 exti pending bit */
+ __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
+ }
+}
+
+#if defined(PWR_CR2_PVME1)
+/**
+ * @brief PWR PVM1 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_PVM1Callback(void) {
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_PVM1Callback() API can be implemented in the user file
+ */
+}
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+/**
+ * @brief PWR PVM2 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_PVM2Callback(void) {
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_PVM2Callback() API can be implemented in the user file
+ */
+}
+#endif /* PWR_CR2_PVME2 */
+
+/**
+ * @brief PWR PVM3 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_PVM3Callback(void) {
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_PVM3Callback() API can be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR PVM4 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_PVM4Callback(void) {
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_PWREx_PVM4Callback() API can be implemented in the user file
+ */
+}
+
+#if defined(PWR_CR3_UCPD_STDBY)
+/**
+ * @brief Enable UCPD configuration memorization in Standby.
+ * @retval None
+ */
+void HAL_PWREx_EnableUCPDStandbyMode(void) {
+ /* Memorize UCPD configuration when entering standby mode */
+ SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+
+/**
+ * @brief Disable UCPD configuration memorization in Standby.
+ * @note This function must be called on exiting the Standby mode and before
+ * any UCPD configuration update.
+ * @retval None
+ */
+void HAL_PWREx_DisableUCPDStandbyMode(void) {
+ /* Write 0 immediately after Standby exit when using UCPD,
+ and before writing any UCPD registers */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+#endif /* PWR_CR3_UCPD_STDBY */
+
+#if defined(PWR_CR3_UCPD_DBDIS)
+/**
+ * @brief Enable the USB Type-C dead battery pull-down behavior
+ * on UCPDx_CC1 and UCPDx_CC2 pins
+ * @retval None
+ */
+void HAL_PWREx_EnableUCPDDeadBattery(void) {
+ /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+
+/**
+ * @brief Disable the USB Type-C dead battery pull-down behavior
+ * on UCPDx_CC1 and UCPDx_CC2 pins
+ * @note After exiting reset, the USB Type-C dead battery behavior will be
+ * enabled, which may have a pull-down effect on CC1 and CC2 pins. It is
+ * recommended to disable it in all cases, either to stop this pull-down or to
+ * hand over control to the UCPD (which should therefore be initialized before
+ * doing the disable).
+ * @retval None
+ */
+void HAL_PWREx_DisableUCPDDeadBattery(void) {
+ /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
+ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+#endif /* PWR_CR3_UCPD_DBDIS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
index 6a4df41..d79db07 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
@@ -1,1346 +1,1345 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_rcc.c
- * @author MCD Application Team
- * @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### RCC specific features #####
- ==============================================================================
- [..]
- After reset the device is running from High Speed Internal oscillator
- (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
- and I-Cache are disabled, and all peripherals are off except internal
- SRAM, Flash and JTAG.
-
- (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
- all peripherals mapped on these buses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and
- FLASH.
- (+) All GPIOs are in analog mode, except the JTAG pins which
- are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB buses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some
- TIMERs, UCPD, I2S, I2C, LPTIM, ADC, QSPI)
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCC RCC
- * @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
-
-#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) \
- (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
-
-#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) \
- (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
-
-#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) \
- (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
-
-#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
- (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_Private_Functions RCC Private Functions
- * @{
- */
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization
- functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the internal and
- external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System
- buses clocks (SYSCLK, AHB, APB1 and APB2).
-
- [..] Internal/external clock and PLL configuration
- (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly
- or through the PLL as System clock source.
-
- (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG
- and/or RTC clock source.
-
- (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used
- directly or through the PLL as System clock source. Can be used also optionally
- as RTC clock source.
-
- (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as
- RTC clock source.
-
- (+) PLL (clocked by HSI, HSE) providing up to three independent output
- clocks:
- (++) The first output is used to generate the high speed system clock
- (up to 170 MHz).
- (++) The second output is used to generate the clock for the USB (48
- MHz), the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S.
- (++) The third output is used to generate a clock for ADC
-
- (+) CSS (Clock security system): once enabled, if a HSE clock failure
- occurs (HSE used directly or through PLL as System clock source), the System
- clock is automatically switched to HSI and an interrupt is generated if
- enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
-
- (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE,
- HSE, main PLL clock, system clock or RC48 clock (through a configurable
- prescaler) on PA8 pin.
-
- [..] System, AHB and APB buses clocks configuration
- (+) Several clock sources can be used to drive the System clock
- (SYSCLK): HSI, HSE and main PLL. The AHB clock (HCLK) is derived from System
- clock through configurable prescaler and used to clock the CPU, memory and
- peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2)
- clocks are derived from AHB clock through configurable prescalers and used to
- clock the peripherals mapped on these buses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of
- these clocks.
-
- -@- All the peripheral clocks are derived from the System clock
- (SYSCLK) except:
-
- (+@) RTC: the RTC clock can be derived either from the LSI, LSE or
- HSE clock divided by 2 to 31. You have to use __HAL_RCC_RTC_ENABLE() and
- HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
- (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
- to work correctly, while the RNG peripheral requires a frequency
- equal or lower than to 48 MHz. This clock is derived of the main
- PLL through PLLQ divider. You have to enable the peripheral clock and use
- HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
- (+@) IWDG clock which is always the LSI clock.
-
-
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170
- MHz. The clock source frequency should be adapted depending on the device
- voltage range as listed in the Reference Manual "Clock source frequency versus
- voltage scaling" chapter.
-
- @endverbatim
-
- Table 1. HCLK clock frequency for STM32G4xx devices
- +----------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) | |
- |----------------------------------------------------------| | | voltage range
- 1 | voltage range 1 | voltage range 2 | | | boost mode 1.28
- V | normal mode 1.2 V | 1.0 V |
- |-----------------|-------------------|-------------------|------------------|
- |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK
- <= 13 |
- |-----------------|-------------------|-------------------|------------------|
- |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK
- <= 26 |
- |-----------------|-------------------|-------------------|------------------|
- |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | -
- |
- |-----------------|-------------------|-------------------|------------------|
- |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | -
- |
- |-----------------|-------------------|-------------------|------------------|
- |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | -
- |
- +----------------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 OFF
- * - All interrupts disabled
- * - All interrupt and reset flags cleared
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_DeInit(void) {
- uint32_t tickstart;
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Set HSION bit to the reset value */
- SET_BIT(RCC->CR, RCC_CR_HSION);
-
- /* Wait till HSI is ready */
- while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set HSITRIM[6:0] bits to the reset value */
- SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Reset CFGR register (HSI is selected as system clock source) */
- RCC->CFGR = 0x00000001u;
-
- /* Wait till HSI is ready */
- while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HSI_VALUE;
-
- /* Adapt Systick interrupt period */
- if (HAL_InitTick(uwTickPrio) != HAL_OK) {
- return HAL_ERROR;
- }
-
- /* Clear CR register in 2 steps: first to clear HSEON in case bypass was
- * enabled */
- RCC->CR = RCC_CR_HSION;
-
- /* Then again to HSEBYP in case bypass was enabled */
- RCC->CR = RCC_CR_HSION;
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is OFF */
- while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
-
- /* once PLL is OFF, reset PLLCFGR register to default value */
- RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4;
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIER);
-
- /* Clear all interrupt flags */
- WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
-
- /* Clear all reset flags */
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the RCC Oscillators according to the specified parameters
- * in the RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
- uint32_t tickstart;
- uint32_t temp_sysclksrc;
- uint32_t temp_pllckcfg;
-
- /* Check Null pointer */
- if (RCC_OscInitStruct == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) ==
- RCC_OSCILLATORTYPE_HSE) {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
- temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
-
- /* When the HSE is used as system clock or clock source for PLL in these
- * cases it is not allowed to be disabled */
- if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) &&
- (temp_pllckcfg == RCC_PLLSOURCE_HSE)) ||
- (temp_sysclksrc == RCC_CFGR_SWS_HSE)) {
- if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) &&
- (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) {
- return HAL_ERROR;
- }
- } else {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
- /* Check the HSE State */
- if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- } else {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) ==
- RCC_OSCILLATORTYPE_HSI) {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(
- IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is
- * selected as system clock */
- temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
- if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) &&
- (temp_pllckcfg == RCC_PLLSOURCE_HSI)) ||
- (temp_sysclksrc == RCC_CFGR_SWS_HSI)) {
- /* When HSI is used as system clock it will not be disabled */
- if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) &&
- (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(
- RCC_OscInitStruct->HSICalibrationValue);
-
- /* Adapt Systick interrupt period */
- if (HAL_InitTick(uwTickPrio) != HAL_OK) {
- return HAL_ERROR;
- }
- }
- } else {
- /* Check the HSI State */
- if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(
- RCC_OscInitStruct->HSICalibrationValue);
- } else {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) ==
- RCC_OSCILLATORTYPE_LSI) {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- } else {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is disabled */
- while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) ==
- RCC_OSCILLATORTYPE_LSE) {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain if necessary */
- if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
- if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-
- /* Check the LSE State */
- if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- } else {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is disabled */
- while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Restore clock configuration if changed */
- if (pwrclkchanged == SET) {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*------------------------------ HSI48 Configuration -----------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) ==
- RCC_OSCILLATORTYPE_HSI48) {
- /* Check the parameters */
- assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
-
- /* Check the HSI48 State */
- if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) {
- /* Enable the Internal Low Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI48 is ready */
- while (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- } else {
- /* Disable the Internal Low Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI48 is disabled */
- while (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-
- if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) {
- /* Check if the PLL is used as system clock or not */
- if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
- if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
- assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
- assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division
- * factors. */
- __HAL_RCC_PLL_CONFIG(
- RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR);
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Enable PLL System Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- } else {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Disable all PLL outputs to save power if no PLLs on */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK |
- RCC_PLL_ADCCLK);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
- } else {
- /* Check if there is a request to disable the PLL used as System clock
- * source */
- if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) {
- return HAL_ERROR;
- } else {
- /* Do not return HAL_ERROR if request repeats the current configuration
- */
- temp_pllckcfg = RCC->PLLCFGR;
- if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) !=
- RCC_OscInitStruct->PLL.PLLSource) ||
- (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) !=
- (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
- (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) !=
- ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
- (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) !=
- ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
- (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) !=
- ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U)
- << RCC_PLLCFGR_PLLQ_Pos)) ||
- (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) !=
- ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U)
- << RCC_PLLCFGR_PLLR_Pos))) {
- return HAL_ERROR;
- }
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the CPU, AHB and APB buses clocks according to the
- * specified parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency FLASH Latency
- * This parameter can be one of the following values:
- * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
- * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
- * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles
- * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles
- * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles
- * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles
- * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles
- * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles
- * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles
- * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles
- * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles
- * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles
- * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles
- * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles
- * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles
- * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock
- * Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this
- * function
- *
- * @note The HSI is used by default as system clock source after
- * startup from Reset, wake-up from STANDBY mode. After restart from
- * Reset, the HSI frequency is set to its default value 16 MHz.
- *
- * @note The HSI can be selected as system clock source after
- * from STOP modes or in case of failure of the HSE used directly or
- * indirectly as system clock (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL
- * locked). If a clock source which is not yet ready is selected, the switch
- * will occur when the clock source is ready.
- *
- * @note You can use HAL_RCC_GetClockConfig() function to know which clock is
- * currently used as system clock source.
- *
- * @note Depending on the device voltage range, the software has to set
- * correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed
- * frequency (for more details refer to section above
- * "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
- uint32_t FLatency) {
- uint32_t tickstart;
- uint32_t pllfreq;
- uint32_t hpre = RCC_SYSCLK_DIV1;
-
- /* Check Null pointer */
- if (RCC_ClkInitStruct == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states
- (LATENCY) must be correctly programmed according to the frequency of the CPU
- clock (HCLK) and the supply voltage of the device. */
-
- /* Increasing the number of wait states because of higher CPU frequency */
- if (FLatency > __HAL_FLASH_GET_LATENCY()) {
- /* Program the new number of wait states to the LATENCY bits in the
- * FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access
- the Flash memory by reading the FLASH_ACR register */
- if (__HAL_FLASH_GET_LATENCY() != FLatency) {
- return HAL_ERROR;
- }
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) ==
- RCC_CLOCKTYPE_SYSCLK) {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* PLL is selected as System Clock Source */
- if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) {
- /* Check the PLL ready flag */
- if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) {
- return HAL_ERROR;
- }
- /* Undershoot management when selection PLL as SYSCLK source and frequency
- * above 80Mhz */
- /* Compute target PLL output frequency */
- pllfreq = RCC_GetSysClockFreqFromPLLSource();
-
- /* Intermediate step with HCLK prescaler 2 necessary before to go over
- * 80Mhz */
- if (pllfreq > 80000000U) {
- if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
- (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) ==
- RCC_CLOCKTYPE_HCLK) &&
- (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
- hpre = RCC_SYSCLK_DIV2;
- }
- }
- } else {
- /* HSE is selected as System Clock Source */
- if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) {
- /* Check the HSE ready flag */
- if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else {
- /* Check the HSI ready flag */
- if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) {
- return HAL_ERROR;
- }
- }
- /* Overshoot management when going down from PLL as SYSCLK source and
- * frequency above 80Mhz */
- pllfreq = HAL_RCC_GetSysClockFreq();
-
- /* Intermediate step with HCLK prescaler 2 necessary before to go under
- * 80Mhz */
- if (pllfreq > 80000000U) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
- hpre = RCC_SYSCLK_DIV2;
- }
- }
-
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() !=
- (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) ==
- RCC_CLOCKTYPE_HCLK) {
- /* Set the highest APB divider in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) ==
- RCC_CLOCKTYPE_PCLK1) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- }
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) ==
- RCC_CLOCKTYPE_PCLK2) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- } else {
- /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK
- * prescaler 1 */
- if (hpre == RCC_SYSCLK_DIV2) {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if (FLatency < __HAL_FLASH_GET_LATENCY()) {
- /* Program the new number of wait states to the LATENCY bits in the
- * FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access
- the Flash memory by polling the FLASH_ACR register */
- tickstart = HAL_GetTick();
-
- while (__HAL_FLASH_GET_LATENCY() != FLatency) {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) ==
- RCC_CLOCKTYPE_PCLK1) {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) ==
- RCC_CLOCKTYPE_PCLK2) {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2,
- ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock =
- HAL_RCC_GetSysClockFreq() >>
- (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] &
- 0x1FU);
-
- /* Configure the source of time base considering new system clocks settings*/
- return HAL_InitTick(uwTickPrio);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to:
-
- (+) Output clock to MCO pin.
- (+) Retrieve current clock frequencies.
- (+) Enable the Clock Security System.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Select the clock source to output on MCO pin(PA8/PG10).
- * @note PA8/PG10 should be configured in alternate function mode.
- * @note The default configuration of the GPIOG pin 10 (PG10) is set to reset
- * mode (NRST pin) and user shall set the NRST_MODE Bit in the FLASH OPTR
- * register to be able to use it as an MCO pin. The @ref HAL_FLASHEx_OBProgram()
- * API can be used to configure the NRST_MODE Bit value.
- * @param RCC_MCOx specifies the output direction for the clock source.
- * For STM32G4xx family this parameter can have only one value:
- * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8).
- * @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10).
- * @param RCC_MCOSource specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on
- * MCO
- * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO
- * source
- * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
- * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO
- * source
- * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
- * for devices with HSI48
- * @param RCC_MCODiv specifies the MCO prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
- * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
- * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
- * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
- * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
- * @retval None
- */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource,
- uint32_t RCC_MCODiv) {
- GPIO_InitTypeDef gpio_initstruct;
- uint32_t mcoindex;
- uint32_t mco_gpio_index;
- GPIO_TypeDef *mco_gpio_port;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
-
- /* Common GPIO init parameters */
- gpio_initstruct.Mode = GPIO_MODE_AF_PP;
- gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- gpio_initstruct.Pull = GPIO_NOPULL;
-
- /* Get MCOx selection */
- mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
-
- /* Get MCOx GPIO Port */
- mco_gpio_port = (GPIO_TypeDef *)RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
-
- /* MCOx Clock Enable */
- mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
- SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index));
-
- /* Configure the MCOx pin in alternate function mode */
- gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
- gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
- HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
-
- if (mcoindex == RCC_MCO1_INDEX) {
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
- /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler
- */
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE),
- (RCC_MCOSource | RCC_MCODiv));
- }
-}
-
-/**
- * @brief Return the SYSCLK frequency.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on
- * HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on
- * HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on
- * HSE_VALUE(**), HSI_VALUE(*) Value multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file
- * (default value 16 MHz) but the real value may vary depending on the
- * variations in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file
- * (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using
- * fractional value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other
- * parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this
- * function will be incorrect.
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void) {
- uint32_t pllvco, pllsource, pllr, pllm;
- uint32_t sysclockfreq;
-
- if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) {
- /* HSI used as system clock source */
- sysclockfreq = HSI_VALUE;
- } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) {
- /* HSE used as system clock source */
- sysclockfreq = HSE_VALUE;
- } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) {
- /* PLL used as system clock source */
-
- /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
- pllm =
- (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
-
- switch (pllsource) {
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllvco =
- (HSE_VALUE / pllm) *
- (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
- break;
-
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- default:
- pllvco =
- (HSI_VALUE / pllm) *
- (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
- break;
- }
- pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) +
- 1U) *
- 2U;
- sysclockfreq = pllvco / pllr;
- } else {
- sysclockfreq = 0U;
- }
-
- return sysclockfreq;
-}
-
-/**
- * @brief Return the HCLK frequency.
- * @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function
- * will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock
- * Frequency.
- * @retval HCLK frequency in Hz
- */
-uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; }
-
-/**
- * @brief Return the PCLK1 frequency.
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this
- * function will be incorrect.
- * @retval PCLK1 frequency in Hz
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void) {
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >>
- (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >>
- RCC_CFGR_PPRE1_Pos] &
- 0x1FU));
-}
-
-/**
- * @brief Return the PCLK2 frequency.
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this
- * function will be incorrect.
- * @retval PCLK2 frequency in Hz
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void) {
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >>
- (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >>
- RCC_CFGR_PPRE2_Pos] &
- 0x1FU));
-}
-
-/**
- * @brief Configure the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * will be configured.
- * @retval None
- */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != (void *)NULL);
-
- /* Set all possible values for the Oscillator type parameter ---------------*/
- RCC_OscInitStruct->OscillatorType =
- RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE |
- RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
-
- /* Get the HSE configuration -----------------------------------------------*/
- if (READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- } else if (READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- } else {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
-
- /* Get the HSI configuration -----------------------------------------------*/
- if (READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- } else {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue =
- READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;
-
- /* Get the LSE configuration -----------------------------------------------*/
- if (READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- } else if (READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- } else {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if (READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- } else {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
- /* Get the HSI48 configuration ---------------------------------------------*/
- if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
- } else {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
- }
-
- /* Get the PLL configuration -----------------------------------------------*/
- if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- } else {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLM =
- (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
- RCC_OscInitStruct->PLL.PLLN =
- READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- RCC_OscInitStruct->PLL.PLLQ =
- (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)
- << 1U);
- RCC_OscInitStruct->PLL.PLLR =
- (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U)
- << 1U);
- RCC_OscInitStruct->PLL.PLLP =
- READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
-}
-
-/**
- * @brief Configure the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
- * will be configured.
- * @param pFLatency Pointer on the Flash Latency.
- * @retval None
- */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
- uint32_t *pFLatency) {
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != (void *)NULL);
- assert_param(pFLatency != (void *)NULL);
-
- /* Set all possible values for the Clock type parameter --------------------*/
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
- RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider =
- (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = __HAL_FLASH_GET_LATENCY();
-}
-
-/**
- * @brief Enable the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @note The Clock Security System can only be cleared by reset.
- * @retval None
- */
-void HAL_RCC_EnableCSS(void) { SET_BIT(RCC->CR, RCC_CR_CSSON); }
-
-/**
- * @brief Enable the LSE Clock Security System.
- * @note If a failure is detected on the external 32 kHz oscillator,
- * the LSE clock is no longer supplied to the RTC but no hardware action
- * is made to the registers. If enabled, an interrupt will be generated
- * and handle through @ref RCCEx_EXTI_LINE_LSECSS
- * @note The Clock Security System can only be cleared by reset or after a LSE
- * failure detection.
- * @retval None
- */
-void HAL_RCC_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); }
-
-/**
- * @brief Disable the LSE Clock Security System.
- * @note After LSE failure detection, the software must disable LSECSSON
- * @note The Clock Security System can only be cleared by reset otherwise.
- * @retval None
- */
-void HAL_RCC_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); }
-
-/**
- * @brief Handle the RCC Clock Security System interrupt request.
- * @note This API should be called under the NMI_Handler().
- * @retval None
- */
-void HAL_RCC_NMI_IRQHandler(void) {
- /* Check RCC CSSF interrupt flag */
- if (__HAL_RCC_GET_IT(RCC_IT_CSS)) {
- /* RCC Clock Security System interrupt user callback */
- HAL_RCC_CSSCallback();
-
- /* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
- }
-}
-
-/**
- * @brief RCC Clock Security System interrupt callback.
- * @retval none
- */
-__weak void HAL_RCC_CSSCallback(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RCC_CSSCallback should be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup RCC_Private_Functions
- * @{
- */
-
-/**
- * @brief Compute SYSCLK frequency based on PLL SYSCLK source.
- * @retval SYSCLK frequency
- */
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void) {
- uint32_t pllvco, pllsource, pllr, pllm;
- uint32_t sysclockfreq;
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
- pllm =
- (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
-
- switch (pllsource) {
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos);
- break;
-
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- default:
- pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos);
- break;
- }
-
- pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) +
- 1U) *
- 2U;
- sysclockfreq = pllvco / pllr;
-
- return sysclockfreq;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_rcc.c
+ * @author MCD Application Team
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from High Speed Internal oscillator
+ (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
+ and I-Cache are disabled, and all peripherals are off except internal
+ SRAM, Flash and JTAG.
+
+ (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
+ all peripherals mapped on these buses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and
+ FLASH.
+ (+) All GPIOs are in analog mode, except the JTAG pins which
+ are assigned to be used for debug purpose.
+
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB buses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some
+ TIMERs, UCPD, I2S, I2C, LPTIM, ADC, QSPI)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
+
+#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) \
+ (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
+
+#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) \
+ (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
+
+#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) \
+ (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
+
+#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
+ (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_Private_Functions RCC Private Functions
+ * @{
+ */
+static uint32_t RCC_GetSysClockFreqFromPLLSource(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization
+ functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal and
+ external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System
+ buses clocks (SYSCLK, AHB, APB1 and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly
+ or through the PLL as System clock source.
+
+ (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG
+ and/or RTC clock source.
+
+ (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used
+ directly or through the PLL as System clock source. Can be used also optionally
+ as RTC clock source.
+
+ (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as
+ RTC clock source.
+
+ (+) PLL (clocked by HSI, HSE) providing up to three independent output
+ clocks:
+ (++) The first output is used to generate the high speed system clock
+ (up to 170 MHz).
+ (++) The second output is used to generate the clock for the USB (48
+ MHz), the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S.
+ (++) The third output is used to generate a clock for ADC
+
+ (+) CSS (Clock security system): once enabled, if a HSE clock failure
+ occurs (HSE used directly or through PLL as System clock source), the System
+ clock is automatically switched to HSI and an interrupt is generated if
+ enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+ exception vector.
+
+ (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE,
+ HSE, main PLL clock, system clock or RC48 clock (through a configurable
+ prescaler) on PA8 pin.
+
+ [..] System, AHB and APB buses clocks configuration
+ (+) Several clock sources can be used to drive the System clock
+ (SYSCLK): HSI, HSE and main PLL. The AHB clock (HCLK) is derived from System
+ clock through configurable prescaler and used to clock the CPU, memory and
+ peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2)
+ clocks are derived from AHB clock through configurable prescalers and used to
+ clock the peripherals mapped on these buses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of
+ these clocks.
+
+ -@- All the peripheral clocks are derived from the System clock
+ (SYSCLK) except:
+
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or
+ HSE clock divided by 2 to 31. You have to use __HAL_RCC_RTC_ENABLE() and
+ HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+ (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
+ to work correctly, while the RNG peripheral requires a frequency
+ equal or lower than to 48 MHz. This clock is derived of the main
+ PLL through PLLQ divider. You have to enable the peripheral clock and use
+ HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+ (+@) IWDG clock which is always the LSI clock.
+
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170
+ MHz. The clock source frequency should be adapted depending on the device
+ voltage range as listed in the Reference Manual "Clock source frequency versus
+ voltage scaling" chapter.
+
+ @endverbatim
+
+ Table 1. HCLK clock frequency for STM32G4xx devices
+ +----------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) | |
+ |----------------------------------------------------------| | | voltage range
+ 1 | voltage range 1 | voltage range 2 | | | boost mode 1.28
+ V | normal mode 1.2 V | 1.0 V |
+ |-----------------|-------------------|-------------------|------------------|
+ |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK
+ <= 13 |
+ |-----------------|-------------------|-------------------|------------------|
+ |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK
+ <= 26 |
+ |-----------------|-------------------|-------------------|------------------|
+ |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | -
+ |
+ |-----------------|-------------------|-------------------|------------------|
+ |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | -
+ |
+ |-----------------|-------------------|-------------------|------------------|
+ |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | -
+ |
+ +----------------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE, PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO1 OFF
+ * - All interrupts disabled
+ * - All interrupt and reset flags cleared
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_DeInit(void) {
+ uint32_t tickstart;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Set HSION bit to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set HSITRIM[6:0] bits to the reset value */
+ SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Reset CFGR register (HSI is selected as system clock source) */
+ RCC->CFGR = 0x00000001u;
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK) {
+ return HAL_ERROR;
+ }
+
+ /* Clear CR register in 2 steps: first to clear HSEON in case bypass was
+ * enabled */
+ RCC->CR = RCC_CR_HSION;
+
+ /* Then again to HSEBYP in case bypass was enabled */
+ RCC->CR = RCC_CR_HSION;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is OFF */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* once PLL is OFF, reset PLLCFGR register to default value */
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4;
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIER);
+
+ /* Clear all interrupt flags */
+ WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
+
+ /* Clear all reset flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
+ uint32_t tickstart;
+ uint32_t temp_sysclksrc;
+ uint32_t temp_pllckcfg;
+
+ /* Check Null pointer */
+ if (RCC_OscInitStruct == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) ==
+ RCC_OSCILLATORTYPE_HSE) {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+
+ /* When the HSE is used as system clock or clock source for PLL in these
+ * cases it is not allowed to be disabled */
+ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) &&
+ (temp_pllckcfg == RCC_PLLSOURCE_HSE)) ||
+ (temp_sysclksrc == RCC_CFGR_SWS_HSE)) {
+ if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) &&
+ (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) {
+ return HAL_ERROR;
+ }
+ } else {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ } else {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) ==
+ RCC_OSCILLATORTYPE_HSI) {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(
+ IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is
+ * selected as system clock */
+ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) &&
+ (temp_pllckcfg == RCC_PLLSOURCE_HSI)) ||
+ (temp_sysclksrc == RCC_CFGR_SWS_HSI)) {
+ /* When HSI is used as system clock it will not be disabled */
+ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) &&
+ (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(
+ RCC_OscInitStruct->HSICalibrationValue);
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK) {
+ return HAL_ERROR;
+ }
+ }
+ } else {
+ /* Check the HSI State */
+ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(
+ RCC_OscInitStruct->HSICalibrationValue);
+ } else {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) ==
+ RCC_OSCILLATORTYPE_LSI) {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ } else {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) ==
+ RCC_OSCILLATORTYPE_LSE) {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain if necessary */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+
+ /* Check the LSE State */
+ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ } else {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET) {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+
+ /*------------------------------ HSI48 Configuration -----------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) ==
+ RCC_OSCILLATORTYPE_HSI48) {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+ /* Check the HSI48 State */
+ if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) {
+ /* Enable the Internal Low Speed oscillator (HSI48). */
+ __HAL_RCC_HSI48_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI48 is ready */
+ while (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ } else {
+ /* Disable the Internal Low Speed oscillator (HSI48). */
+ __HAL_RCC_HSI48_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI48 is disabled */
+ while (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+
+ if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) {
+ /* Check if the PLL is used as system clock or not */
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
+ if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division
+ * factors. */
+ __HAL_RCC_PLL_CONFIG(
+ RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR);
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Enable PLL System Clock output. */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ } else {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Unselect PLL clock source and disable outputs to save power */
+ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK |
+ RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
+ }
+ } else {
+ /* Check if there is a request to disable the PLL used as System clock
+ * source */
+ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) {
+ return HAL_ERROR;
+ } else {
+ /* Do not return HAL_ERROR if request repeats the current configuration
+ */
+ temp_pllckcfg = RCC->PLLCFGR;
+ if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) !=
+ RCC_OscInitStruct->PLL.PLLSource) ||
+ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) !=
+ (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
+ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) !=
+ ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
+ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) !=
+ ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
+ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) !=
+ ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U)
+ << RCC_PLLCFGR_PLLQ_Pos)) ||
+ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) !=
+ ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U)
+ << RCC_PLLCFGR_PLLR_Pos))) {
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CPU, AHB and APB buses clocks according to the
+ * specified parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles
+ * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles
+ * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles
+ * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles
+ * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles
+ * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles
+ * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles
+ * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles
+ * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles
+ * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles
+ * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles
+ * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles
+ * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock
+ * Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this
+ * function
+ *
+ * @note The HSI is used by default as system clock source after
+ * startup from Reset, wake-up from STANDBY mode. After restart from
+ * Reset, the HSI frequency is set to its default value 16 MHz.
+ *
+ * @note The HSI can be selected as system clock source after
+ * from STOP modes or in case of failure of the HSE used directly or
+ * indirectly as system clock (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL
+ * locked). If a clock source which is not yet ready is selected, the switch
+ * will occur when the clock source is ready.
+ *
+ * @note You can use HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ *
+ * @note Depending on the device voltage range, the software has to set
+ * correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed
+ * frequency (for more details refer to section above
+ * "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
+ uint32_t FLatency) {
+ uint32_t tickstart;
+ uint32_t pllfreq;
+ uint32_t hpre = RCC_SYSCLK_DIV1;
+
+ /* Check Null pointer */
+ if (RCC_ClkInitStruct == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states
+ (LATENCY) must be correctly programmed according to the frequency of the CPU
+ clock (HCLK) and the supply voltage of the device. */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (FLatency > __HAL_FLASH_GET_LATENCY()) {
+ /* Program the new number of wait states to the LATENCY bits in the
+ * FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access
+ the Flash memory by reading the FLASH_ACR register */
+ if (__HAL_FLASH_GET_LATENCY() != FLatency) {
+ return HAL_ERROR;
+ }
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) ==
+ RCC_CLOCKTYPE_SYSCLK) {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* PLL is selected as System Clock Source */
+ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) {
+ /* Check the PLL ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) {
+ return HAL_ERROR;
+ }
+ /* Undershoot management when selection PLL as SYSCLK source and frequency
+ * above 80Mhz */
+ /* Compute target PLL output frequency */
+ pllfreq = RCC_GetSysClockFreqFromPLLSource();
+
+ /* Intermediate step with HCLK prescaler 2 necessary before to go over
+ * 80Mhz */
+ if (pllfreq > 80000000U) {
+ if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
+ (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) ==
+ RCC_CLOCKTYPE_HCLK) &&
+ (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
+ hpre = RCC_SYSCLK_DIV2;
+ }
+ }
+ } else {
+ /* HSE is selected as System Clock Source */
+ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) {
+ /* Check the HSE ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else {
+ /* Check the HSI ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) {
+ return HAL_ERROR;
+ }
+ }
+ /* Overshoot management when going down from PLL as SYSCLK source and
+ * frequency above 80Mhz */
+ pllfreq = HAL_RCC_GetSysClockFreq();
+
+ /* Intermediate step with HCLK prescaler 2 necessary before to go under
+ * 80Mhz */
+ if (pllfreq > 80000000U) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
+ hpre = RCC_SYSCLK_DIV2;
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() !=
+ (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) ==
+ RCC_CLOCKTYPE_HCLK) {
+ /* Set the highest APB divider in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) ==
+ RCC_CLOCKTYPE_PCLK1) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ }
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) ==
+ RCC_CLOCKTYPE_PCLK2) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
+ }
+
+ /* Set the new HCLK clock divider */
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ } else {
+ /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK
+ * prescaler 1 */
+ if (hpre == RCC_SYSCLK_DIV2) {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (FLatency < __HAL_FLASH_GET_LATENCY()) {
+ /* Program the new number of wait states to the LATENCY bits in the
+ * FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access
+ the Flash memory by polling the FLASH_ACR register */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_FLASH_GET_LATENCY() != FLatency) {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) ==
+ RCC_CLOCKTYPE_PCLK1) {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) ==
+ RCC_CLOCKTYPE_PCLK2) {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2,
+ ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock =
+ HAL_RCC_GetSysClockFreq() >>
+ (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] &
+ 0x1FU);
+
+ /* Configure the source of time base considering new system clocks settings*/
+ return HAL_InitTick(uwTickPrio);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to:
+
+ (+) Output clock to MCO pin.
+ (+) Retrieve current clock frequencies.
+ (+) Enable the Clock Security System.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Select the clock source to output on MCO pin(PA8/PG10).
+ * @note PA8/PG10 should be configured in alternate function mode.
+ * @note The default configuration of the GPIOG pin 10 (PG10) is set to reset
+ * mode (NRST pin) and user shall set the NRST_MODE Bit in the FLASH OPTR
+ * register to be able to use it as an MCO pin. The @ref HAL_FLASHEx_OBProgram()
+ * API can be used to configure the NRST_MODE Bit value.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * For STM32G4xx family this parameter can have only one value:
+ * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8).
+ * @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on
+ * MCO
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO
+ * source
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO
+ * source
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
+ * for devices with HSI48
+ * @param RCC_MCODiv specifies the MCO prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
+ * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
+ * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
+ * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource,
+ uint32_t RCC_MCODiv) {
+ GPIO_InitTypeDef gpio_initstruct;
+ uint32_t mcoindex;
+ uint32_t mco_gpio_index;
+ GPIO_TypeDef *mco_gpio_port;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+
+ /* Common GPIO init parameters */
+ gpio_initstruct.Mode = GPIO_MODE_AF_PP;
+ gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ gpio_initstruct.Pull = GPIO_NOPULL;
+
+ /* Get MCOx selection */
+ mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
+
+ /* Get MCOx GPIO Port */
+ mco_gpio_port = (GPIO_TypeDef *)RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
+
+ /* MCOx Clock Enable */
+ mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
+ SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index));
+
+ /* Configure the MCOx pin in alternate function mode */
+ gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
+ gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+ HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+
+ if (mcoindex == RCC_MCO1_INDEX) {
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+ /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler
+ */
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE),
+ (RCC_MCOSource | RCC_MCODiv));
+ }
+}
+
+/**
+ * @brief Return the SYSCLK frequency.
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on
+ * HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on
+ * HSE_VALUE(**)
+ * @note If SYSCLK source is PLL, function returns values based on
+ * HSE_VALUE(**), HSI_VALUE(*) Value multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file
+ * (default value 16 MHz) but the real value may vary depending on the
+ * variations in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file
+ * (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other
+ * parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this
+ * function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void) {
+ uint32_t pllvco, pllsource, pllr, pllm;
+ uint32_t sysclockfreq;
+
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) {
+ /* HSI used as system clock source */
+ sysclockfreq = HSI_VALUE;
+ } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) {
+ /* HSE used as system clock source */
+ sysclockfreq = HSE_VALUE;
+ } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) {
+ /* PLL used as system clock source */
+
+ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+ pllm =
+ (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
+
+ switch (pllsource) {
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllvco =
+ (HSE_VALUE / pllm) *
+ (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ break;
+
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllvco =
+ (HSI_VALUE / pllm) *
+ (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ break;
+ }
+ pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) +
+ 1U) *
+ 2U;
+ sysclockfreq = pllvco / pllr;
+ } else {
+ sysclockfreq = 0U;
+ }
+
+ return sysclockfreq;
+}
+
+/**
+ * @brief Return the HCLK frequency.
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function
+ * will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock
+ * Frequency.
+ * @retval HCLK frequency in Hz
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; }
+
+/**
+ * @brief Return the PCLK1 frequency.
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this
+ * function will be incorrect.
+ * @retval PCLK1 frequency in Hz
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void) {
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >>
+ (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >>
+ RCC_CFGR_PPRE1_Pos] &
+ 0x1FU));
+}
+
+/**
+ * @brief Return the PCLK2 frequency.
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this
+ * function will be incorrect.
+ * @retval PCLK2 frequency in Hz
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void) {
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >>
+ (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >>
+ RCC_CFGR_PPRE2_Pos] &
+ 0x1FU));
+}
+
+/**
+ * @brief Configure the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != (void *)NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType =
+ RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE |
+ RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if (READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ } else if (READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ } else {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if (READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ } else {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue =
+ READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ } else if (READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ } else {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if (READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ } else {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the HSI48 configuration ---------------------------------------------*/
+ if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) {
+ RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+ } else {
+ RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ } else {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM =
+ (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
+ RCC_OscInitStruct->PLL.PLLN =
+ READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ RCC_OscInitStruct->PLL.PLLQ =
+ (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)
+ << 1U);
+ RCC_OscInitStruct->PLL.PLLR =
+ (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U)
+ << 1U);
+ RCC_OscInitStruct->PLL.PLLP =
+ READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+}
+
+/**
+ * @brief Configure the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct,
+ uint32_t *pFLatency) {
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != (void *)NULL);
+ assert_param(pFLatency != (void *)NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider =
+ (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = __HAL_FLASH_GET_LATENCY();
+}
+
+/**
+ * @brief Enable the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @note The Clock Security System can only be cleared by reset.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void) { SET_BIT(RCC->CR, RCC_CR_CSSON); }
+
+/**
+ * @brief Enable the LSE Clock Security System.
+ * @note If a failure is detected on the external 32 kHz oscillator,
+ * the LSE clock is no longer supplied to the RTC but no hardware action
+ * is made to the registers. If enabled, an interrupt will be generated
+ * and handle through @ref RCCEx_EXTI_LINE_LSECSS
+ * @note The Clock Security System can only be cleared by reset or after a LSE
+ * failure detection.
+ * @retval None
+ */
+void HAL_RCC_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); }
+
+/**
+ * @brief Disable the LSE Clock Security System.
+ * @note After LSE failure detection, the software must disable LSECSSON
+ * @note The Clock Security System can only be cleared by reset otherwise.
+ * @retval None
+ */
+void HAL_RCC_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); }
+
+/**
+ * @brief Handle the RCC Clock Security System interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void) {
+ /* Check RCC CSSF interrupt flag */
+ if (__HAL_RCC_GET_IT(RCC_IT_CSS)) {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Compute SYSCLK frequency based on PLL SYSCLK source.
+ * @retval SYSCLK frequency
+ */
+static uint32_t RCC_GetSysClockFreqFromPLLSource(void) {
+ uint32_t pllvco, pllsource, pllr, pllm;
+ uint32_t sysclockfreq;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+ pllm =
+ (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
+
+ switch (pllsource) {
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos);
+ break;
+
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos);
+ break;
+ }
+
+ pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) +
+ 1U) *
+ 2U;
+ sysclockfreq = pllvco / pllr;
+
+ return sysclockfreq;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
index cb387d8..dcb2430 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
@@ -1,1742 +1,1793 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_rcc_ex.c
- * @author MCD Application Team
- * @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities RCC extended peripheral:
- * + Extended Peripheral Control functions
- * + Extended Clock management functions
- * + Extended Clock Recovery System Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- *in the root directory of this software component. If no LICENSE file comes
- *with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCCEx RCCEx
- * @brief RCC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-
-#define DIVIDER_P_UPDATE 0U
-#define DIVIDER_Q_UPDATE 1U
-#define DIVIDER_R_UPDATE 2U
-
-#define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define LSCO_GPIO_PORT GPIOA
-#define LSCO_PIN GPIO_PIN_2
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
- * @{
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control
-functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC
-Clocks frequencies.
- [..]
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is
-used to select the RTC clock source; in this case the Backup domain will be
-reset in order to modify the RTC Clock source, as consequence RTC registers
-(including the backup registers) are set to their reset values.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the RCC extended peripherals clocks according to the
- * specified parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains a field PeriphClockSelection which can be a combination of
- * the following values:
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for
- * devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for
- * devices with UART5)
- * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for
- * devices with I2C4)
- * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for
- * devices with FDCAN)
- * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for
- * devices with USB)
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral
- * clock (only for devices with ADC3, ADC4, ADC5)
- * @arg @ref RCC_PERIPHCLK_QSPI QuadSPI peripheral clock (only for
- * devices with QuadSPI)
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source: in this case the access to Backup domain is
- * enabled.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(
- RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
- uint32_t tmpregister;
- uint32_t tickstart;
- HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
- HAL_StatusTypeDef status = HAL_OK; /* Final status */
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*-------------------------- RTC clock source configuration
- * ----------------------*/
- if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) ==
- RCC_PERIPHCLK_RTC) {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock */
- if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while ((PWR->CR1 & PWR_CR1_DBP) == 0U) {
- if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
- ret = HAL_TIMEOUT;
- break;
- }
- }
-
- if (ret == HAL_OK) {
- /* Reset the Backup domain only if the RTC Clock source selection is
- * modified from default */
- tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
-
- if ((tmpregister != RCC_RTCCLKSOURCE_NONE) &&
- (tmpregister != PeriphClkInit->RTCClockSelection)) {
- /* Store the content of BDCR register before the reset of Backup Domain
- */
- tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset
- */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpregister;
- }
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain
- * reset */
- if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) {
- if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
- ret = HAL_TIMEOUT;
- break;
- }
- }
- }
-
- if (ret == HAL_OK) {
- /* Apply new RTC clock source selection */
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- } else {
- /* set overall return value */
- status = ret;
- }
- } else {
- /* set overall return value */
- status = ret;
- }
-
- /* Restore clock configuration if changed */
- if (pwrclkchanged == SET) {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*-------------------------- USART1 clock source configuration
- * -------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) ==
- RCC_PERIPHCLK_USART1) {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- }
-
- /*-------------------------- USART2 clock source configuration
- * -------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) ==
- RCC_PERIPHCLK_USART2) {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- }
-
- /*-------------------------- USART3 clock source configuration
- * -------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) ==
- RCC_PERIPHCLK_USART3) {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- }
-
-#if defined(UART4)
- /*-------------------------- UART4 clock source configuration
- * --------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) ==
- RCC_PERIPHCLK_UART4) {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- }
-#endif /* UART4 */
-
-#if defined(UART5)
-
- /*-------------------------- UART5 clock source configuration
- * --------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) ==
- RCC_PERIPHCLK_UART5) {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- }
-
-#endif /* UART5 */
-
- /*-------------------------- LPUART1 clock source configuration
- * ------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) ==
- RCC_PERIPHCLK_LPUART1) {
- /* Check the parameters */
- assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
-
- /* Configure the LPUAR1 clock source */
- __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
- }
-
- /*-------------------------- I2C1 clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) ==
- RCC_PERIPHCLK_I2C1) {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- }
-
- /*-------------------------- I2C2 clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) ==
- RCC_PERIPHCLK_I2C2) {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- }
-
- /*-------------------------- I2C3 clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) ==
- RCC_PERIPHCLK_I2C3) {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- }
-
-#if defined(I2C4)
-
- /*-------------------------- I2C4 clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) ==
- RCC_PERIPHCLK_I2C4) {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- }
-
-#endif /* I2C4 */
-
- /*-------------------------- LPTIM1 clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) ==
- RCC_PERIPHCLK_LPTIM1) {
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
-
- /* Configure the LPTIM1 clock source */
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- }
-
- /*-------------------------- SAI1 clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) ==
- RCC_PERIPHCLK_SAI1) {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
- /* Configure the SAI1 interface clock source */
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
-
- if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-
- /*-------------------------- I2S clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) ==
- RCC_PERIPHCLK_I2S) {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure the I2S interface clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
-
- if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-
-#if defined(FDCAN1)
- /*-------------------------- FDCAN clock source configuration
- * ---------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) ==
- RCC_PERIPHCLK_FDCAN) {
- /* Check the parameters */
- assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
-
- /* Configure the FDCAN interface clock source */
- __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
-
- if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-#endif /* FDCAN1 */
-
-#if defined(USB)
-
- /*-------------------------- USB clock source configuration
- * ----------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) ==
- (RCC_PERIPHCLK_USB)) {
- assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
- __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
-
- if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-
-#endif /* USB */
-
- /*-------------------------- RNG clock source configuration
- * ----------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) ==
- (RCC_PERIPHCLK_RNG)) {
- assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
- __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
-
- if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-
- /*-------------------------- ADC12 clock source configuration
- * ----------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) ==
- RCC_PERIPHCLK_ADC12) {
- /* Check the parameters */
- assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
-
- /* Configure the ADC12 interface clock source */
- __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
-
- if (PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) {
- /* Enable PLLADCCLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
- }
- }
-
-#if defined(ADC345_COMMON)
- /*-------------------------- ADC345 clock source configuration
- * ----------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) ==
- RCC_PERIPHCLK_ADC345) {
- /* Check the parameters */
- assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
-
- /* Configure the ADC345 interface clock source */
- __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
-
- if (PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL) {
- /* Enable PLLADCCLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
- }
- }
-#endif /* ADC345_COMMON */
-
-#if defined(QUADSPI)
-
- /*-------------------------- QuadSPIx clock source configuration
- * ----------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) ==
- RCC_PERIPHCLK_QSPI) {
- /* Check the parameters */
- assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
-
- /* Configure the QuadSPI clock source */
- __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
-
- if (PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL) {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-
-#endif /* QUADSPI */
-
- return status;
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration
- * registers.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * returns the configuration information for the Extended Peripherals
- * clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2,
- * I2C3, I2C4, LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
- * @retval None
- */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
- /* Set all possible values for the extended clock type parameter------------*/
-
-#if defined(STM32G474xx) || defined(STM32G484xx)
-
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
- RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG |
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 |
- RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_RTC;
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S |
- RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | RCC_PERIPHCLK_QSPI |
- RCC_PERIPHCLK_RTC;
-
-#elif defined(STM32G473xx) || defined(STM32G483xx)
-
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
- RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | RCC_PERIPHCLK_QSPI |
- RCC_PERIPHCLK_RTC;
-
-#elif defined(STM32G471xx)
-
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
- RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC;
-#elif defined(STM32G431xx) || defined(STM32G441xx)
-
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 |
- RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 |
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN |
- RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 |
- RCC_PERIPHCLK_RTC;
-#elif defined(STM32GBK1CB)
-
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |
- RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG |
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC;
-
-#endif /* STM32G431xx */
-
- /* Get the USART1 clock source ---------------------------------------------*/
- PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
- /* Get the USART2 clock source ---------------------------------------------*/
- PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
- /* Get the USART3 clock source ---------------------------------------------*/
- PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
-
-#if defined(UART4)
- /* Get the UART4 clock source ----------------------------------------------*/
- PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
-#endif /* UART4 */
-
-#if defined(UART5)
- /* Get the UART5 clock source ----------------------------------------------*/
- PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
-#endif /* UART5 */
-
- /* Get the LPUART1 clock source --------------------------------------------*/
- PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
-
- /* Get the I2C1 clock source -----------------------------------------------*/
- PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
-
- /* Get the I2C2 clock source ----------------------------------------------*/
- PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
-
- /* Get the I2C3 clock source -----------------------------------------------*/
- PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
-
-#if defined(I2C4)
- /* Get the I2C4 clock source -----------------------------------------------*/
- PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
-#endif /* I2C4 */
-
- /* Get the LPTIM1 clock source ---------------------------------------------*/
- PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
-
- /* Get the SAI1 clock source -----------------------------------------------*/
- PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
-
- /* Get the I2S clock source -----------------------------------------------*/
- PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-
-#if defined(FDCAN1)
- /* Get the FDCAN clock source
- * -----------------------------------------------*/
- PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
-#endif /* FDCAN1 */
-
-#if defined(USB)
- /* Get the USB clock source ------------------------------------------------*/
- PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
-#endif /* USB */
-
- /* Get the RNG clock source ------------------------------------------------*/
- PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
-
- /* Get the ADC12 clock source
- * -----------------------------------------------*/
- PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
-
-#if defined(ADC345_COMMON)
- /* Get the ADC345 clock source
- * ----------------------------------------------*/
- PeriphClkInit->Adc345ClockSelection = __HAL_RCC_GET_ADC345_SOURCE();
-#endif /* ADC345_COMMON */
-
-#if defined(QUADSPI)
- /* Get the QuadSPIclock source --------------------------------------------*/
- PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
-#endif /* QUADSPI */
-
- /* Get the RTC clock source ------------------------------------------------*/
- PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
-}
-
-/**
- * @brief Return the peripheral clock frequency for peripherals with clock
- * source from PLL
- * @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk Peripheral clock identifier
- * This parameter can be one of the following values:
- * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for
- * devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for
- * devices with UART5)
- * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for
- * devices with I2C4)
- * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S SPI peripheral clock
- * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for
- * devices with FDCAN)
- * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for
- * devices with USB)
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral
- * clock (only for devices with ADC3, ADC4, ADC5)
- * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock (only for
- * devices with QSPI)
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @retval Frequency in Hz
- */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) {
- uint32_t frequency = 0U;
- uint32_t srcclk;
- uint32_t pllvco, plln, pllp;
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
- if (PeriphClk == RCC_PERIPHCLK_RTC) {
- /* Get the current RTC source */
- srcclk = __HAL_RCC_GET_RTC_SOURCE();
-
- /* Check if LSE is ready and if RTC clock selection is LSE */
- if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_RTCCLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Check if LSI is ready and if RTC clock selection is LSI */
- else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) &&
- (srcclk == RCC_RTCCLKSOURCE_LSI)) {
- frequency = LSI_VALUE;
- }
- /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
- else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) &&
- (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) {
- frequency = HSE_VALUE / 32U;
- }
- /* Clock not enabled for RTC*/
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- } else {
- /* Other external peripheral clock source than RTC */
-
- /* Compute PLL clock input */
- if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */
- {
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) {
- pllvco = HSI_VALUE;
- } else {
- pllvco = 0U;
- }
- } else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */
- {
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) {
- pllvco = HSE_VALUE;
- } else {
- pllvco = 0U;
- }
- } else /* No source */
- {
- pllvco = 0U;
- }
-
- /* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >>
- RCC_PLLCFGR_PLLM_Pos) +
- 1U));
-
- switch (PeriphClk) {
- case RCC_PERIPHCLK_USART1:
- /* Get the current USART1 source */
- srcclk = __HAL_RCC_GET_USART1_SOURCE();
-
- if (srcclk == RCC_USART1CLKSOURCE_PCLK2) {
- frequency = HAL_RCC_GetPCLK2Freq();
- } else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_USART1CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_USART1CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for USART1 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_USART2:
- /* Get the current USART2 source */
- srcclk = __HAL_RCC_GET_USART2_SOURCE();
-
- if (srcclk == RCC_USART2CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_USART2CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_USART2CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for USART2 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_USART3:
- /* Get the current USART3 source */
- srcclk = __HAL_RCC_GET_USART3_SOURCE();
-
- if (srcclk == RCC_USART3CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_USART3CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_USART3CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for USART3 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#if defined(UART4)
- case RCC_PERIPHCLK_UART4:
- /* Get the current UART4 source */
- srcclk = __HAL_RCC_GET_UART4_SOURCE();
-
- if (srcclk == RCC_UART4CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_UART4CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_UART4CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for UART4 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-#endif /* UART4 */
-
-#if defined(UART5)
- case RCC_PERIPHCLK_UART5:
- /* Get the current UART5 source */
- srcclk = __HAL_RCC_GET_UART5_SOURCE();
-
- if (srcclk == RCC_UART5CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_UART5CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_UART5CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for UART5 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-#endif /* UART5 */
-
- case RCC_PERIPHCLK_LPUART1:
- /* Get the current LPUART1 source */
- srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
-
- if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_LPUART1CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_LPUART1CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for LPUART1 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_I2C1:
- /* Get the current I2C1 source */
- srcclk = __HAL_RCC_GET_I2C1_SOURCE();
-
- if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_I2C1CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C1 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_I2C2:
- /* Get the current I2C2 source */
- srcclk = __HAL_RCC_GET_I2C2_SOURCE();
-
- if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_I2C2CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C2 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_I2C3:
- /* Get the current I2C3 source */
- srcclk = __HAL_RCC_GET_I2C3_SOURCE();
-
- if (srcclk == RCC_I2C3CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_I2C3CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C3 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#if defined(I2C4)
-
- case RCC_PERIPHCLK_I2C4:
- /* Get the current I2C4 source */
- srcclk = __HAL_RCC_GET_I2C4_SOURCE();
-
- if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_I2C4CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2C4 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#endif /* I2C4 */
-
- case RCC_PERIPHCLK_LPTIM1:
- /* Get the current LPTIM1 source */
- srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
-
- if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) &&
- (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) {
- frequency = LSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
- (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) {
- frequency = LSE_VALUE;
- }
- /* Clock not enabled for LPTIM1 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_SAI1:
- /* Get the current SAI1 source */
- srcclk = __HAL_RCC_GET_SAI1_SOURCE();
-
- if (srcclk == RCC_SAI1CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if (srcclk == RCC_SAI1CLKSOURCE_PLL) {
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) {
- /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos;
- frequency =
- (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
- RCC_PLLCFGR_PLLQ_Pos) +
- 1U)
- << 1U);
- }
- } else if (srcclk == RCC_SAI1CLKSOURCE_EXT) {
- /* External clock used.*/
- frequency = EXTERNAL_CLOCK_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_SAI1CLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for SAI1 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_I2S:
- /* Get the current I2Sx source */
- srcclk = __HAL_RCC_GET_I2S_SOURCE();
-
- if (srcclk == RCC_I2SCLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else if (srcclk == RCC_I2SCLKSOURCE_PLL) {
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) {
- /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos;
- frequency =
- (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
- RCC_PLLCFGR_PLLQ_Pos) +
- 1U)
- << 1U);
- }
- } else if (srcclk == RCC_I2SCLKSOURCE_EXT) {
- /* External clock used.*/
- frequency = EXTERNAL_CLOCK_VALUE;
- } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
- (srcclk == RCC_I2SCLKSOURCE_HSI)) {
- frequency = HSI_VALUE;
- }
- /* Clock not enabled for I2S */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#if defined(FDCAN1)
- case RCC_PERIPHCLK_FDCAN:
- /* Get the current FDCANx source */
- srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
-
- if (srcclk == RCC_FDCANCLKSOURCE_PCLK1) {
- frequency = HAL_RCC_GetPCLK1Freq();
- } else if (srcclk == RCC_FDCANCLKSOURCE_HSE) {
- frequency = HSE_VALUE;
- } else if (srcclk == RCC_FDCANCLKSOURCE_PLL) {
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) {
- /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos;
- frequency =
- (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
- RCC_PLLCFGR_PLLQ_Pos) +
- 1U)
- << 1U);
- }
- }
- /* Clock not enabled for FDCAN */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-#endif /* FDCAN1 */
-
-#if defined(USB)
-
- case RCC_PERIPHCLK_USB:
- /* Get the current USB source */
- srcclk = __HAL_RCC_GET_USB_SOURCE();
-
- if (srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */
- {
- /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
- plln =
- READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- frequency =
- (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
- RCC_PLLCFGR_PLLQ_Pos) +
- 1U)
- << 1U);
- } else if ((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) &&
- (srcclk == RCC_USBCLKSOURCE_HSI48)) /* HSI48 ? */
- {
- frequency = HSI48_VALUE;
- } else /* No clock source */
- {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#endif /* USB */
-
- case RCC_PERIPHCLK_RNG:
- /* Get the current RNG source */
- srcclk = __HAL_RCC_GET_RNG_SOURCE();
-
- if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */
- {
- /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
- plln =
- READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- frequency =
- (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
- RCC_PLLCFGR_PLLQ_Pos) +
- 1U)
- << 1U);
- } else if ((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) &&
- (srcclk == RCC_RNGCLKSOURCE_HSI48)) /* HSI48 ? */
- {
- frequency = HSI48_VALUE;
- } else /* No clock source */
- {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
- case RCC_PERIPHCLK_ADC12:
- /* Get the current ADC12 source */
- srcclk = __HAL_RCC_GET_ADC12_SOURCE();
-
- if (srcclk == RCC_ADC12CLKSOURCE_PLL) {
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) {
- /* f(PLLP) = f(VCO input) * PLLN / PLLP */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos;
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >>
- RCC_PLLCFGR_PLLPDIV_Pos;
- if (pllp == 0U) {
- if (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) {
- pllp = 17U;
- } else {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- } else if (srcclk == RCC_ADC12CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Clock not enabled for ADC12 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#if defined(ADC345_COMMON)
- case RCC_PERIPHCLK_ADC345:
- /* Get the current ADC345 source */
- srcclk = __HAL_RCC_GET_ADC345_SOURCE();
-
- if (srcclk == RCC_ADC345CLKSOURCE_PLL) {
- if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) {
- /* f(PLLP) = f(VCO input) * PLLN / PLLP */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
- RCC_PLLCFGR_PLLN_Pos;
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >>
- RCC_PLLCFGR_PLLPDIV_Pos;
- if (pllp == 0U) {
- if (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) {
- pllp = 17U;
- } else {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- } else if (srcclk == RCC_ADC345CLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Clock not enabled for ADC345 */
- else {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-#endif /* ADC345_COMMON */
-
-#if defined(QUADSPI)
-
- case RCC_PERIPHCLK_QSPI:
- /* Get the current QSPI source */
- srcclk = __HAL_RCC_GET_QSPI_SOURCE();
-
- if (srcclk == RCC_QSPICLKSOURCE_PLL) /* PLL ? */
- {
- /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
- plln =
- READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- frequency =
- (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
- RCC_PLLCFGR_PLLQ_Pos) +
- 1U)
- << 1U);
- } else if (srcclk == RCC_QSPICLKSOURCE_HSI) {
- frequency = HSI_VALUE;
- } else if (srcclk == RCC_QSPICLKSOURCE_SYSCLK) {
- frequency = HAL_RCC_GetSysClockFreq();
- } else /* No clock source */
- {
- /* nothing to do: frequency already initialized to 0 */
- }
- break;
-
-#endif /* QUADSPI */
-
- default:
- break;
- }
- }
-
- return (frequency);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management
-functions
- * @brief Extended Clock management functions
- *
-@verbatim
- ===============================================================================
- ##### Extended clock management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the
- activation or deactivation of LSE CSS,
- Low speed clock output and clock after wake-up from STOP mode.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the LSE Clock Security System.
- * @note Prior to enable the LSE Clock Security System, LSE oscillator is to
- * be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be
- * selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
- * @retval None
- */
-void HAL_RCCEx_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); }
-
-/**
- * @brief Disable the LSE Clock Security System.
- * @note LSE Clock Security System can only be disabled after a LSE failure
- * detection.
- * @retval None
- */
-void HAL_RCCEx_DisableLSECSS(void) {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-
- /* Disable LSE CSS IT if any */
- __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
-}
-
-/**
- * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI
- * line.
- * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
- * @retval None
- */
-void HAL_RCCEx_EnableLSECSS_IT(void) {
- /* Enable LSE CSS */
- SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-
- /* Enable LSE CSS IT */
- __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
-
- /* Enable IT on EXTI Line 19 */
- __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
- __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
-}
-
-/**
- * @brief Handle the RCC LSE Clock Security System interrupt request.
- * @retval None
- */
-void HAL_RCCEx_LSECSS_IRQHandler(void) {
- /* Check RCC LSE CSSF flag */
- if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) {
- /* RCC LSE Clock Security System interrupt user callback */
- HAL_RCCEx_LSECSS_Callback();
-
- /* Clear RCC LSE CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
- }
-}
-
-/**
- * @brief RCCEx LSE Clock Security System interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_LSECSS_Callback(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user
- file
- */
-}
-
-/**
- * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
- * @param LSCOSource specifies the Low Speed clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
- * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
- * @retval None
- */
-void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) {
- GPIO_InitTypeDef GPIO_InitStruct;
- FlagStatus pwrclkchanged = RESET;
- FlagStatus backupchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
-
- /* LSCO Pin Clock Enable */
- __LSCO_CLK_ENABLE();
-
- /* Configure the LSCO pin in analog mode */
- GPIO_InitStruct.Pin = LSCO_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
-
- /* Update LSCOSEL clock source in Backup Domain control register */
- if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
- if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
- HAL_PWR_EnableBkUpAccess();
- backupchanged = SET;
- }
-
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN,
- LSCOSource | RCC_BDCR_LSCOEN);
-
- if (backupchanged == SET) {
- HAL_PWR_DisableBkUpAccess();
- }
- if (pwrclkchanged == SET) {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
-}
-
-/**
- * @brief Disable the Low Speed clock output.
- * @retval None
- */
-void HAL_RCCEx_DisableLSCO(void) {
- FlagStatus pwrclkchanged = RESET;
- FlagStatus backupchanged = RESET;
-
- /* Update LSCOEN bit in Backup Domain control register */
- if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
- if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
- /* Enable access to the backup domain */
- HAL_PWR_EnableBkUpAccess();
- backupchanged = SET;
- }
-
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-
- /* Restore previous configuration */
- if (backupchanged == SET) {
- /* Disable access to the backup domain */
- HAL_PWR_DisableBkUpAccess();
- }
- if (pwrclkchanged == SET) {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
-}
-
-/**
- * @}
- */
-
-#if defined(CRS)
-
-/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System
-Control functions
- * @brief Extended Clock Recovery System Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Clock Recovery System Control functions #####
- ===============================================================================
- [..]
- For devices with Clock Recovery System feature (CRS), RCC Extension HAL
-driver can be used as follows:
-
- (#) In System clock config, HSI48 needs to be enabled
-
- (#) Enable CRS clock in IP MSP init which will use CRS functions
-
- (#) Call CRS functions as follows:
- (##) Prepare synchronization configuration necessary for HSI48
-calibration
- (+++) Default values can be set for frequency Error Measurement
-(reload and error limit) and also HSI48 oscillator smooth trimming.
- (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used
-to calculate directly reload value with target and sychronization frequencies
-values
- (##) Call function HAL_RCCEx_CRSConfig which
- (+++) Resets CRS registers to their default values.
- (+++) Configures CRS registers with synchronization configuration
- (+++) Enables automatic calibration and frequency error counter
-feature Note: When using USB LPM (Link Power Management) and the device is in
-Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC
-signal will therefore be provided to the CRS to calibrate the HSI48 on the run.
-To guarantee the required clock precision after waking up from Sleep mode, the
-LSE or reference clock on the GPIOs should be used as SYNC signal.
-
- (##) A polling function is provided to wait for complete
-synchronization
- (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
- (+++) According to CRS status, user can decide to adjust again the
-calibration or continue application if synchronization is OK
-
- (#) User can retrieve information related to synchronization in calling
-function HAL_RCCEx_CRSGetSynchronizationInfo()
-
- (#) Regarding synchronization status and synchronization information, user
-can try a new calibration in changing synchronization configuration and call
-again HAL_RCCEx_CRSConfig. Note: When the SYNC event is detected during the
-downcounting phase (before reaching the zero value), it means that the actual
-frequency is lower than the target (and so, that the TRIM value should be
- incremented), while when it is detected during the upcounting phase
-it means that the actual frequency is higher (and that the TRIM value should be
-decremented).
-
- (#) In interrupt mode, user can resort to the available macros
-(__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler
-(CRS_IRQn/CRS_IRQHandler)
- (++) Call function HAL_RCCEx_CRSConfig()
- (++) Enable CRS_IRQn (thanks to NVIC functions)
- (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
- (++) Implement CRS status management in the following user
-callbacks called from HAL_RCCEx_CRS_IRQHandler():
- (+++) HAL_RCCEx_CRS_SyncOkCallback()
- (+++) HAL_RCCEx_CRS_SyncWarnCallback()
- (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
- (+++) HAL_RCCEx_CRS_ErrorCallback()
-
- (#) To force a SYNC EVENT, user can use the function
-HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called
-before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start automatic synchronization for polling mode
- * @param pInit Pointer on RCC_CRSInitTypeDef structure
- * @retval None
- */
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) {
- uint32_t value;
-
- /* Check the parameters */
- assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
- assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
- assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
- assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
- assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
- assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
-
- /* CONFIGURATION */
-
- /* Before configuration, reset CRS registers to their default values*/
- __HAL_RCC_CRS_FORCE_RESET();
- __HAL_RCC_CRS_RELEASE_RESET();
-
- /* Set the SYNCDIV[2:0] bits according to Prescaler value */
- /* Set the SYNCSRC[1:0] bits according to Source value */
- /* Set the SYNCSPOL bit according to Polarity value */
- value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
- /* Set the RELOAD[15:0] bits according to ReloadValue value */
- value |= pInit->ReloadValue;
- /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
- value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
- WRITE_REG(CRS->CFGR, value);
-
- /* Adjust HSI48 oscillator smooth trimming */
- /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
- MODIFY_REG(CRS->CR, CRS_CR_TRIM,
- (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
-
- /* START AUTOMATIC SYNCHRONIZATION*/
-
- /* Enable Automatic trimming & Frequency error counter */
- SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
-}
-
-/**
- * @brief Generate the software synchronization event
- * @retval None
- */
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) {
- SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
- * @brief Return synchronization info
- * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
- * @retval None
- */
-void HAL_RCCEx_CRSGetSynchronizationInfo(
- RCC_CRSSynchroInfoTypeDef *pSynchroInfo) {
- /* Check the parameter */
- assert_param(pSynchroInfo != (void *)NULL);
-
- /* Get the reload value */
- pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-
- /* Get HSI48 oscillator smooth trimming */
- pSynchroInfo->HSI48CalibrationValue =
- (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
-
- /* Get Frequency error capture */
- pSynchroInfo->FreqErrorCapture =
- (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
-
- /* Get Frequency error direction */
- pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
- * @brief Wait for CRS Synchronization status.
- * @param Timeout Duration of the timeout
- * @note Timeout is based on the maximum time to receive a SYNC event based on
- * synchronization frequency.
- * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
- * @retval Combination of Synchronization status
- * This parameter can be a combination of the following values:
- * @arg @ref RCC_CRS_TIMEOUT
- * @arg @ref RCC_CRS_SYNCOK
- * @arg @ref RCC_CRS_SYNCWARN
- * @arg @ref RCC_CRS_SYNCERR
- * @arg @ref RCC_CRS_SYNCMISS
- * @arg @ref RCC_CRS_TRIMOVF
- */
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) {
- uint32_t crsstatus = RCC_CRS_NONE;
- uint32_t tickstart;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for CRS flag or timeout detection */
- do {
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) {
- crsstatus = RCC_CRS_TIMEOUT;
- }
- }
- /* Check CRS SYNCOK flag */
- if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) {
- /* CRS SYNC event OK */
- crsstatus |= RCC_CRS_SYNCOK;
-
- /* Clear CRS SYNC event OK bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
- }
-
- /* Check CRS SYNCWARN flag */
- if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) {
- /* CRS SYNC warning */
- crsstatus |= RCC_CRS_SYNCWARN;
-
- /* Clear CRS SYNCWARN bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
- }
-
- /* Check CRS TRIM overflow flag */
- if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) {
- /* CRS SYNC Error */
- crsstatus |= RCC_CRS_TRIMOVF;
-
- /* Clear CRS Error bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
- }
-
- /* Check CRS Error flag */
- if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) {
- /* CRS SYNC Error */
- crsstatus |= RCC_CRS_SYNCERR;
-
- /* Clear CRS Error bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
- }
-
- /* Check CRS SYNC Missed flag */
- if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) {
- /* CRS SYNC Missed */
- crsstatus |= RCC_CRS_SYNCMISS;
-
- /* Clear CRS SYNC Missed bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
- }
-
- /* Check CRS Expected SYNC flag */
- if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) {
- /* frequency error counter reached a zero value */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
- }
- } while (RCC_CRS_NONE == crsstatus);
-
- return crsstatus;
-}
-
-/**
- * @brief Handle the Clock Recovery System interrupt request.
- * @retval None
- */
-void HAL_RCCEx_CRS_IRQHandler(void) {
- uint32_t crserror = RCC_CRS_NONE;
- /* Get current IT flags and IT sources values */
- uint32_t itflags = READ_REG(CRS->ISR);
- uint32_t itsources = READ_REG(CRS->CR);
-
- /* Check CRS SYNCOK flag */
- if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) &&
- ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) {
- /* Clear CRS SYNC event OK flag */
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-
- /* user callback */
- HAL_RCCEx_CRS_SyncOkCallback();
- }
- /* Check CRS SYNCWARN flag */
- else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) &&
- ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) {
- /* Clear CRS SYNCWARN flag */
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-
- /* user callback */
- HAL_RCCEx_CRS_SyncWarnCallback();
- }
- /* Check CRS Expected SYNC flag */
- else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) &&
- ((itsources & RCC_CRS_IT_ESYNC) != 0U)) {
- /* frequency error counter reached a zero value */
- WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-
- /* user callback */
- HAL_RCCEx_CRS_ExpectedSyncCallback();
- }
- /* Check CRS Error flags */
- else {
- if (((itflags & RCC_CRS_FLAG_ERR) != 0U) &&
- ((itsources & RCC_CRS_IT_ERR) != 0U)) {
- if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) {
- crserror |= RCC_CRS_SYNCERR;
- }
- if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) {
- crserror |= RCC_CRS_SYNCMISS;
- }
- if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) {
- crserror |= RCC_CRS_TRIMOVF;
- }
-
- /* Clear CRS Error flags */
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-
- /* user error callback */
- HAL_RCCEx_CRS_ErrorCallback(crserror);
- }
- }
-}
-
-/**
- * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_SyncOkCallback(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the
- user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the
- user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) {
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in
- the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System Error interrupt callback.
- * @param Error Combination of Error status.
- * This parameter can be a combination of the following values:
- * @arg @ref RCC_CRS_SYNCERR
- * @arg @ref RCC_CRS_SYNCMISS
- * @arg @ref RCC_CRS_TRIMOVF
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Error);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the
- user file
- */
-}
-
-/**
- * @}
- */
-
-#endif /* CRS */
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Private_Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extended peripheral:
+ * + Extended Peripheral Control functions
+ * + Extended Clock management functions
+ * + Extended Clock Recovery System Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ *in the root directory of this software component. If no LICENSE file comes
+ *with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+
+#define DIVIDER_P_UPDATE 0U
+#define DIVIDER_Q_UPDATE 1U
+#define DIVIDER_R_UPDATE 2U
+
+#define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LSCO_GPIO_PORT GPIOA
+#define LSCO_PIN GPIO_PIN_2
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control
+functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC
+Clocks frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is
+used to select the RTC clock source; in this case the Backup domain will be
+reset in order to modify the RTC Clock source, as consequence RTC registers
+(including the backup registers) are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initialize the RCC extended peripherals clocks according to the
+ * specified parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains a field PeriphClockSelection which can be a combination of
+ * the following values:
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for
+ * devices with UART4)
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for
+ * devices with UART5)
+ * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for
+ * devices with I2C4)
+ * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for
+ * devices with FDCAN)
+ * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for
+ * devices with USB)
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral
+ * clock (only for devices with ADC3, ADC4, ADC5)
+ * @arg @ref RCC_PERIPHCLK_QSPI QuadSPI peripheral clock (only for
+ * devices with QuadSPI)
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source: in this case the access to Backup domain is
+ * enabled.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(
+ RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
+ uint32_t tmpregister;
+ uint32_t tickstart;
+ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
+ HAL_StatusTypeDef status = HAL_OK; /* Final status */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*-------------------------- RTC clock source configuration
+ * ----------------------*/
+ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) ==
+ RCC_PERIPHCLK_RTC) {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while ((PWR->CR1 & PWR_CR1_DBP) == 0U) {
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
+ ret = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ if (ret == HAL_OK) {
+ /* Reset the Backup domain only if the RTC Clock source selection is
+ * modified from default */
+ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
+
+ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) &&
+ (tmpregister != PeriphClkInit->RTCClockSelection)) {
+ /* Store the content of BDCR register before the reset of Backup Domain
+ */
+ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset
+ */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpregister;
+ }
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain
+ * reset */
+ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
+ ret = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ if (ret == HAL_OK) {
+ /* Apply new RTC clock source selection */
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ } else {
+ /* set overall return value */
+ status = ret;
+ }
+ } else {
+ /* set overall return value */
+ status = ret;
+ }
+
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET) {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+
+ /*-------------------------- USART1 clock source configuration
+ * -------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) ==
+ RCC_PERIPHCLK_USART1) {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ }
+
+ /*-------------------------- USART2 clock source configuration
+ * -------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) ==
+ RCC_PERIPHCLK_USART2) {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+ /* Configure the USART2 clock source */
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ }
+
+#if defined(USART3)
+
+ /*-------------------------- USART3 clock source configuration
+ * -------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) ==
+ RCC_PERIPHCLK_USART3) {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+ /* Configure the USART3 clock source */
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ }
+
+#endif /* USART3 */
+
+#if defined(UART4)
+ /*-------------------------- UART4 clock source configuration
+ * --------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) ==
+ RCC_PERIPHCLK_UART4) {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+ /* Configure the UART4 clock source */
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+ }
+#endif /* UART4 */
+
+#if defined(UART5)
+
+ /*-------------------------- UART5 clock source configuration
+ * --------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) ==
+ RCC_PERIPHCLK_UART5) {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+ /* Configure the UART5 clock source */
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+ }
+
+#endif /* UART5 */
+
+ /*-------------------------- LPUART1 clock source configuration
+ * ------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) ==
+ RCC_PERIPHCLK_LPUART1) {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+
+ /* Configure the LPUAR1 clock source */
+ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+ }
+
+ /*-------------------------- I2C1 clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) ==
+ RCC_PERIPHCLK_I2C1) {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ }
+
+ /*-------------------------- I2C2 clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) ==
+ RCC_PERIPHCLK_I2C2) {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+ /* Configure the I2C2 clock source */
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ }
+#if defined(I2C3)
+
+ /*-------------------------- I2C3 clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) ==
+ RCC_PERIPHCLK_I2C3) {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+ /* Configure the I2C3 clock source */
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ }
+
+#endif /* I2C3 */
+#if defined(I2C4)
+
+ /*-------------------------- I2C4 clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) ==
+ RCC_PERIPHCLK_I2C4) {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+ /* Configure the I2C4 clock source */
+ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+ }
+
+#endif /* I2C4 */
+
+ /*-------------------------- LPTIM1 clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) ==
+ RCC_PERIPHCLK_LPTIM1) {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+ /* Configure the LPTIM1 clock source */
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ }
+
+#if defined(SAI1)
+ /*-------------------------- SAI1 clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) ==
+ RCC_PERIPHCLK_SAI1) {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+ /* Configure the SAI1 interface clock source */
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+
+ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) {
+ /* Enable PLL48M1CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ }
+ }
+
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
+ /*-------------------------- I2S clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) ==
+ RCC_PERIPHCLK_I2S) {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+ /* Configure the I2S interface clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+
+ if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) {
+ /* Enable PLL48M1CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ }
+ }
+
+#endif /* SPI_I2S_SUPPORT */
+
+#if defined(FDCAN1)
+ /*-------------------------- FDCAN clock source configuration
+ * ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) ==
+ RCC_PERIPHCLK_FDCAN) {
+ /* Check the parameters */
+ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
+
+ /* Configure the FDCAN interface clock source */
+ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+
+ if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) {
+ /* Enable PLL48M1CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ }
+ }
+#endif /* FDCAN1 */
+
+#if defined(USB)
+
+ /*-------------------------- USB clock source configuration
+ * ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) ==
+ (RCC_PERIPHCLK_USB)) {
+ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+
+ if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) {
+ /* Enable PLL48M1CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ }
+ }
+
+#endif /* USB */
+
+ /*-------------------------- RNG clock source configuration
+ * ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) ==
+ (RCC_PERIPHCLK_RNG)) {
+ assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
+ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+
+ if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) {
+ /* Enable PLL48M1CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ }
+ }
+
+ /*-------------------------- ADC12 clock source configuration
+ * ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) ==
+ RCC_PERIPHCLK_ADC12) {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
+
+ /* Configure the ADC12 interface clock source */
+ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
+
+ if (PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) {
+ /* Enable PLLADCCLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
+ }
+ }
+
+#if defined(ADC345_COMMON)
+ /*-------------------------- ADC345 clock source configuration
+ * ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) ==
+ RCC_PERIPHCLK_ADC345) {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
+
+ /* Configure the ADC345 interface clock source */
+ __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
+
+ if (PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL) {
+ /* Enable PLLADCCLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
+ }
+ }
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+ /*-------------------------- QuadSPIx clock source configuration
+ * ----------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) ==
+ RCC_PERIPHCLK_QSPI) {
+ /* Check the parameters */
+ assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
+
+ /* Configure the QuadSPI clock source */
+ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+
+ if (PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL) {
+ /* Enable PLL48M1CLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ }
+ }
+
+#endif /* QUADSPI */
+
+ return status;
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration
+ * registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals
+ * clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2,
+ * I2C3, I2C4, LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
+ /* Set all possible values for the extended clock type parameter------------*/
+
+#if defined(STM32G474xx) || defined(STM32G484xx)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG |
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 |
+ RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G414xx)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_UART4 |
+ RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2S |
+ RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC12 |
+ RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S |
+ RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | RCC_PERIPHCLK_QSPI |
+ RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | RCC_PERIPHCLK_QSPI |
+ RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G471xx)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 |
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G431xx) || defined(STM32G441xx)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 |
+ RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 |
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN |
+ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 |
+ RCC_PERIPHCLK_RTC;
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_UART4 |
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN |
+ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32GBK1CB)
+
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |
+ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 |
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG |
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC;
+
+#endif /* STM32G474xx || STM32G484xx */
+
+ /* Get the USART1 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+ /* Get the USART2 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+
+#if defined(USART3)
+ /* Get the USART3 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+#endif /* USART3 */
+
+#if defined(UART4)
+ /* Get the UART4 clock source ----------------------------------------------*/
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+#endif /* UART4 */
+
+#if defined(UART5)
+ /* Get the UART5 clock source ----------------------------------------------*/
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+#endif /* UART5 */
+
+ /* Get the LPUART1 clock source --------------------------------------------*/
+ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ /* Get the I2C1 clock source -----------------------------------------------*/
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Get the I2C2 clock source ----------------------------------------------*/
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+
+#if defined(I2C3)
+ /* Get the I2C3 clock source -----------------------------------------------*/
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+#endif /* I2C3 */
+
+#if defined(I2C4)
+ /* Get the I2C4 clock source -----------------------------------------------*/
+ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
+#endif /* I2C4 */
+
+ /* Get the LPTIM1 clock source ---------------------------------------------*/
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+#if defined(SAI1)
+ /* Get the SAI1 clock source -----------------------------------------------*/
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
+ /* Get the I2S clock source -----------------------------------------------*/
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+#endif /* SPI_I2S_SUPPORT */
+
+#if defined(FDCAN1)
+ /* Get the FDCAN clock source
+ * -----------------------------------------------*/
+ PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
+#endif /* FDCAN1 */
+
+#if defined(USB)
+ /* Get the USB clock source ------------------------------------------------*/
+ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
+#endif /* USB */
+
+ /* Get the RNG clock source ------------------------------------------------*/
+ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
+
+ /* Get the ADC12 clock source
+ * -----------------------------------------------*/
+ PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
+
+#if defined(ADC345_COMMON)
+ /* Get the ADC345 clock source
+ * ----------------------------------------------*/
+ PeriphClkInit->Adc345ClockSelection = __HAL_RCC_GET_ADC345_SOURCE();
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+ /* Get the QuadSPIclock source --------------------------------------------*/
+ PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
+#endif /* QUADSPI */
+
+ /* Get the RTC clock source ------------------------------------------------*/
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+}
+
+/**
+ * @brief Return the peripheral clock frequency for peripherals with clock
+ * source from PLL
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for
+ * devices with UART4)
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for
+ * devices with UART5)
+ * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for
+ * devices with I2C4)
+ * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S SPI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for
+ * devices with FDCAN)
+ * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for
+ * devices with USB)
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral
+ * clock (only for devices with ADC3, ADC4, ADC5)
+ * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock (only for
+ * devices with QSPI)
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @retval Frequency in Hz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) {
+ uint32_t frequency = 0U;
+ uint32_t srcclk;
+ uint32_t pllvco, plln, pllp;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ if (PeriphClk == RCC_PERIPHCLK_RTC) {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_RTCCLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) &&
+ (srcclk == RCC_RTCCLKSOURCE_LSI)) {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) &&
+ (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) {
+ frequency = HSE_VALUE / 32U;
+ }
+ /* Clock not enabled for RTC*/
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ } else {
+ /* Other external peripheral clock source than RTC */
+
+ /* Compute PLL clock input */
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) {
+ pllvco = HSI_VALUE;
+ } else {
+ pllvco = 0U;
+ }
+ } else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) {
+ pllvco = HSE_VALUE;
+ } else {
+ pllvco = 0U;
+ }
+ } else /* No source */
+ {
+ pllvco = 0U;
+ }
+
+ /* f(PLL Source) / PLLM */
+ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >>
+ RCC_PLLCFGR_PLLM_Pos) +
+ 1U));
+
+ switch (PeriphClk) {
+ case RCC_PERIPHCLK_USART1:
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2) {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ } else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_USART1CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_USART1CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+ case RCC_PERIPHCLK_USART2:
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_USART2CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_USART2CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#if defined(USART3)
+ case RCC_PERIPHCLK_USART3:
+ /* Get the current USART3 source */
+ srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+ if (srcclk == RCC_USART3CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_USART3CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_USART3CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART3 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+#endif /* USART3 */
+
+#if defined(UART4)
+ case RCC_PERIPHCLK_UART4:
+ /* Get the current UART4 source */
+ srcclk = __HAL_RCC_GET_UART4_SOURCE();
+
+ if (srcclk == RCC_UART4CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_UART4CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_UART4CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART4 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+#endif /* UART4 */
+
+#if defined(UART5)
+ case RCC_PERIPHCLK_UART5:
+ /* Get the current UART5 source */
+ srcclk = __HAL_RCC_GET_UART5_SOURCE();
+
+ if (srcclk == RCC_UART5CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_UART5CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_UART5CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART5 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+#endif /* UART5 */
+
+ case RCC_PERIPHCLK_LPUART1:
+ /* Get the current LPUART1 source */
+ srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_LPUART1CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_LPUART1CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPUART1 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C1:
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_I2C1CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C1 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C2:
+ /* Get the current I2C2 source */
+ srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+
+ if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_I2C2CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C2 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#if defined(I2C3)
+
+ case RCC_PERIPHCLK_I2C3:
+ /* Get the current I2C3 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ if (srcclk == RCC_I2C3CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_I2C3CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C3 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#endif /* I2C3 */
+
+#if defined(I2C4)
+
+ case RCC_PERIPHCLK_I2C4:
+ /* Get the current I2C4 source */
+ srcclk = __HAL_RCC_GET_I2C4_SOURCE();
+
+ if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_I2C4CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2C4 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#endif /* I2C4 */
+
+ case RCC_PERIPHCLK_LPTIM1:
+ /* Get the current LPTIM1 source */
+ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+ if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) &&
+ (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) {
+ frequency = LSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) &&
+ (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPTIM1 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#if defined(SAI1)
+
+ case RCC_PERIPHCLK_SAI1:
+ /* Get the current SAI1 source */
+ srcclk = __HAL_RCC_GET_SAI1_SOURCE();
+
+ if (srcclk == RCC_SAI1CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if (srcclk == RCC_SAI1CLKSOURCE_PLL) {
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) {
+ /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos;
+ frequency =
+ (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
+ RCC_PLLCFGR_PLLQ_Pos) +
+ 1U)
+ << 1U);
+ }
+ } else if (srcclk == RCC_SAI1CLKSOURCE_EXT) {
+ /* External clock used.*/
+ frequency = EXTERNAL_CLOCK_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_SAI1CLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for SAI1 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
+ case RCC_PERIPHCLK_I2S:
+ /* Get the current I2Sx source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+
+ if (srcclk == RCC_I2SCLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else if (srcclk == RCC_I2SCLKSOURCE_PLL) {
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) {
+ /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos;
+ frequency =
+ (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
+ RCC_PLLCFGR_PLLQ_Pos) +
+ 1U)
+ << 1U);
+ }
+ } else if (srcclk == RCC_I2SCLKSOURCE_EXT) {
+ /* External clock used.*/
+ frequency = EXTERNAL_CLOCK_VALUE;
+ } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) &&
+ (srcclk == RCC_I2SCLKSOURCE_HSI)) {
+ frequency = HSI_VALUE;
+ }
+ /* Clock not enabled for I2S */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+#endif /* SPI_I2S_SUPPORT */
+
+#if defined(FDCAN1)
+ case RCC_PERIPHCLK_FDCAN:
+ /* Get the current FDCANx source */
+ srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
+
+ if (srcclk == RCC_FDCANCLKSOURCE_PCLK1) {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ } else if (srcclk == RCC_FDCANCLKSOURCE_HSE) {
+ frequency = HSE_VALUE;
+ } else if (srcclk == RCC_FDCANCLKSOURCE_PLL) {
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) {
+ /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos;
+ frequency =
+ (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
+ RCC_PLLCFGR_PLLQ_Pos) +
+ 1U)
+ << 1U);
+ }
+ }
+ /* Clock not enabled for FDCAN */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+#endif /* FDCAN1 */
+
+#if defined(USB)
+
+ case RCC_PERIPHCLK_USB:
+ /* Get the current USB source */
+ srcclk = __HAL_RCC_GET_USB_SOURCE();
+
+ if (srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */
+ {
+ /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+ plln =
+ READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ frequency =
+ (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
+ RCC_PLLCFGR_PLLQ_Pos) +
+ 1U)
+ << 1U);
+ } else if ((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) &&
+ (srcclk == RCC_USBCLKSOURCE_HSI48)) /* HSI48 ? */
+ {
+ frequency = HSI48_VALUE;
+ } else /* No clock source */
+ {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#endif /* USB */
+
+ case RCC_PERIPHCLK_RNG:
+ /* Get the current RNG source */
+ srcclk = __HAL_RCC_GET_RNG_SOURCE();
+
+ if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */
+ {
+ /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+ plln =
+ READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ frequency =
+ (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
+ RCC_PLLCFGR_PLLQ_Pos) +
+ 1U)
+ << 1U);
+ } else if ((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) &&
+ (srcclk == RCC_RNGCLKSOURCE_HSI48)) /* HSI48 ? */
+ {
+ frequency = HSI48_VALUE;
+ } else /* No clock source */
+ {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+ case RCC_PERIPHCLK_ADC12:
+ /* Get the current ADC12 source */
+ srcclk = __HAL_RCC_GET_ADC12_SOURCE();
+
+ if (srcclk == RCC_ADC12CLKSOURCE_PLL) {
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) {
+ /* f(PLLP) = f(VCO input) * PLLN / PLLP */
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos;
+ pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >>
+ RCC_PLLCFGR_PLLPDIV_Pos;
+ if (pllp == 0U) {
+ if (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) {
+ pllp = 17U;
+ } else {
+ pllp = 7U;
+ }
+ }
+ frequency = (pllvco * plln) / pllp;
+ }
+ } else if (srcclk == RCC_ADC12CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for ADC12 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#if defined(ADC345_COMMON)
+ case RCC_PERIPHCLK_ADC345:
+ /* Get the current ADC345 source */
+ srcclk = __HAL_RCC_GET_ADC345_SOURCE();
+
+ if (srcclk == RCC_ADC345CLKSOURCE_PLL) {
+ if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) {
+ /* f(PLLP) = f(VCO input) * PLLN / PLLP */
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>
+ RCC_PLLCFGR_PLLN_Pos;
+ pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >>
+ RCC_PLLCFGR_PLLPDIV_Pos;
+ if (pllp == 0U) {
+ if (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) {
+ pllp = 17U;
+ } else {
+ pllp = 7U;
+ }
+ }
+ frequency = (pllvco * plln) / pllp;
+ }
+ } else if (srcclk == RCC_ADC345CLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for ADC345 */
+ else {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+ case RCC_PERIPHCLK_QSPI:
+ /* Get the current QSPI source */
+ srcclk = __HAL_RCC_GET_QSPI_SOURCE();
+
+ if (srcclk == RCC_QSPICLKSOURCE_PLL) /* PLL ? */
+ {
+ /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+ plln =
+ READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ frequency =
+ (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >>
+ RCC_PLLCFGR_PLLQ_Pos) +
+ 1U)
+ << 1U);
+ } else if (srcclk == RCC_QSPICLKSOURCE_HSI) {
+ frequency = HSI_VALUE;
+ } else if (srcclk == RCC_QSPICLKSOURCE_SYSCLK) {
+ frequency = HAL_RCC_GetSysClockFreq();
+ } else /* No clock source */
+ {
+ /* nothing to do: frequency already initialized to 0 */
+ }
+ break;
+
+#endif /* QUADSPI */
+
+ default:
+ break;
+ }
+ }
+
+ return (frequency);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management
+functions
+ * @brief Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended clock management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the
+ activation or deactivation of LSE CSS,
+ Low speed clock output and clock after wake-up from STOP mode.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the LSE Clock Security System.
+ * @note Prior to enable the LSE Clock Security System, LSE oscillator is to
+ * be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be
+ * selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); }
+
+/**
+ * @brief Disable the LSE Clock Security System.
+ * @note LSE Clock Security System can only be disabled after a LSE failure
+ * detection.
+ * @retval None
+ */
+void HAL_RCCEx_DisableLSECSS(void) {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+
+ /* Disable LSE CSS IT if any */
+ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+ * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI
+ * line.
+ * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS_IT(void) {
+ /* Enable LSE CSS */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+
+ /* Enable LSE CSS IT */
+ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+ /* Enable IT on EXTI Line 19 */
+ __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+ * @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_LSECSS_IRQHandler(void) {
+ /* Check RCC LSE CSSF flag */
+ if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) {
+ /* RCC LSE Clock Security System interrupt user callback */
+ HAL_RCCEx_LSECSS_Callback();
+
+ /* Clear RCC LSE CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+ }
+}
+
+/**
+ * @brief RCCEx LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_LSECSS_Callback(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
+ * @param LSCOSource specifies the Low Speed clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
+ * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) {
+ GPIO_InitTypeDef GPIO_InitStruct;
+ FlagStatus pwrclkchanged = RESET;
+ FlagStatus backupchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
+
+ /* LSCO Pin Clock Enable */
+ __LSCO_CLK_ENABLE();
+
+ /* Configure the LSCO pin in analog mode */
+ GPIO_InitStruct.Pin = LSCO_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
+
+ /* Update LSCOSEL clock source in Backup Domain control register */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
+ HAL_PWR_EnableBkUpAccess();
+ backupchanged = SET;
+ }
+
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN,
+ LSCOSource | RCC_BDCR_LSCOEN);
+
+ if (backupchanged == SET) {
+ HAL_PWR_DisableBkUpAccess();
+ }
+ if (pwrclkchanged == SET) {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+}
+
+/**
+ * @brief Disable the Low Speed clock output.
+ * @retval None
+ */
+void HAL_RCCEx_DisableLSCO(void) {
+ FlagStatus pwrclkchanged = RESET;
+ FlagStatus backupchanged = RESET;
+
+ /* Update LSCOEN bit in Backup Domain control register */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) {
+ /* Enable access to the backup domain */
+ HAL_PWR_EnableBkUpAccess();
+ backupchanged = SET;
+ }
+
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+
+ /* Restore previous configuration */
+ if (backupchanged == SET) {
+ /* Disable access to the backup domain */
+ HAL_PWR_DisableBkUpAccess();
+ }
+ if (pwrclkchanged == SET) {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+}
+
+/**
+ * @}
+ */
+
+#if defined(CRS)
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System
+Control functions
+ * @brief Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Clock Recovery System Control functions #####
+ ===============================================================================
+ [..]
+ For devices with Clock Recovery System feature (CRS), RCC Extension HAL
+driver can be used as follows:
+
+ (#) In System clock config, HSI48 needs to be enabled
+
+ (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+ (#) Call CRS functions as follows:
+ (##) Prepare synchronization configuration necessary for HSI48
+calibration
+ (+++) Default values can be set for frequency Error Measurement
+(reload and error limit) and also HSI48 oscillator smooth trimming.
+ (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used
+to calculate directly reload value with target and sychronization frequencies
+values
+ (##) Call function HAL_RCCEx_CRSConfig which
+ (+++) Resets CRS registers to their default values.
+ (+++) Configures CRS registers with synchronization configuration
+ (+++) Enables automatic calibration and frequency error counter
+feature Note: When using USB LPM (Link Power Management) and the device is in
+Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC
+signal will therefore be provided to the CRS to calibrate the HSI48 on the run.
+To guarantee the required clock precision after waking up from Sleep mode, the
+LSE or reference clock on the GPIOs should be used as SYNC signal.
+
+ (##) A polling function is provided to wait for complete
+synchronization
+ (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+ (+++) According to CRS status, user can decide to adjust again the
+calibration or continue application if synchronization is OK
+
+ (#) User can retrieve information related to synchronization in calling
+function HAL_RCCEx_CRSGetSynchronizationInfo()
+
+ (#) Regarding synchronization status and synchronization information, user
+can try a new calibration in changing synchronization configuration and call
+again HAL_RCCEx_CRSConfig. Note: When the SYNC event is detected during the
+downcounting phase (before reaching the zero value), it means that the actual
+frequency is lower than the target (and so, that the TRIM value should be
+ incremented), while when it is detected during the upcounting phase
+it means that the actual frequency is higher (and that the TRIM value should be
+decremented).
+
+ (#) In interrupt mode, user can resort to the available macros
+(__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler
+(CRS_IRQn/CRS_IRQHandler)
+ (++) Call function HAL_RCCEx_CRSConfig()
+ (++) Enable CRS_IRQn (thanks to NVIC functions)
+ (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+ (++) Implement CRS status management in the following user
+callbacks called from HAL_RCCEx_CRS_IRQHandler():
+ (+++) HAL_RCCEx_CRS_SyncOkCallback()
+ (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+ (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+ (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+ (#) To force a SYNC EVENT, user can use the function
+HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called
+before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start automatic synchronization for polling mode
+ * @param pInit Pointer on RCC_CRSInitTypeDef structure
+ * @retval None
+ */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) {
+ uint32_t value;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+ assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+ assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+ assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+ assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+ assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+ /* CONFIGURATION */
+
+ /* Before configuration, reset CRS registers to their default values*/
+ __HAL_RCC_CRS_FORCE_RESET();
+ __HAL_RCC_CRS_RELEASE_RESET();
+
+ /* Set the SYNCDIV[2:0] bits according to Prescaler value */
+ /* Set the SYNCSRC[1:0] bits according to Source value */
+ /* Set the SYNCSPOL bit according to Polarity value */
+ value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+ /* Set the RELOAD[15:0] bits according to ReloadValue value */
+ value |= pInit->ReloadValue;
+ /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+ value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+ WRITE_REG(CRS->CFGR, value);
+
+ /* Adjust HSI48 oscillator smooth trimming */
+ /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM,
+ (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+ /* START AUTOMATIC SYNCHRONIZATION*/
+
+ /* Enable Automatic trimming & Frequency error counter */
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+ * @brief Generate the software synchronization event
+ * @retval None
+ */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) {
+ SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+ * @brief Return synchronization info
+ * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+ * @retval None
+ */
+void HAL_RCCEx_CRSGetSynchronizationInfo(
+ RCC_CRSSynchroInfoTypeDef *pSynchroInfo) {
+ /* Check the parameter */
+ assert_param(pSynchroInfo != (void *)NULL);
+
+ /* Get the reload value */
+ pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+ /* Get HSI48 oscillator smooth trimming */
+ pSynchroInfo->HSI48CalibrationValue =
+ (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+ /* Get Frequency error capture */
+ pSynchroInfo->FreqErrorCapture =
+ (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+ /* Get Frequency error direction */
+ pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+ * @brief Wait for CRS Synchronization status.
+ * @param Timeout Duration of the timeout
+ * @note Timeout is based on the maximum time to receive a SYNC event based on
+ * synchronization frequency.
+ * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+ * @retval Combination of Synchronization status
+ * This parameter can be a combination of the following values:
+ * @arg @ref RCC_CRS_TIMEOUT
+ * @arg @ref RCC_CRS_SYNCOK
+ * @arg @ref RCC_CRS_SYNCWARN
+ * @arg @ref RCC_CRS_SYNCERR
+ * @arg @ref RCC_CRS_SYNCMISS
+ * @arg @ref RCC_CRS_TRIMOVF
+ */
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) {
+ uint32_t crsstatus = RCC_CRS_NONE;
+ uint32_t tickstart;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for CRS flag or timeout detection */
+ do {
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) {
+ crsstatus = RCC_CRS_TIMEOUT;
+ }
+ }
+ /* Check CRS SYNCOK flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) {
+ /* CRS SYNC event OK */
+ crsstatus |= RCC_CRS_SYNCOK;
+
+ /* Clear CRS SYNC event OK bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+ }
+
+ /* Check CRS SYNCWARN flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) {
+ /* CRS SYNC warning */
+ crsstatus |= RCC_CRS_SYNCWARN;
+
+ /* Clear CRS SYNCWARN bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+ }
+
+ /* Check CRS TRIM overflow flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) {
+ /* CRS SYNC Error */
+ crsstatus |= RCC_CRS_TRIMOVF;
+
+ /* Clear CRS Error bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+ }
+
+ /* Check CRS Error flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) {
+ /* CRS SYNC Error */
+ crsstatus |= RCC_CRS_SYNCERR;
+
+ /* Clear CRS Error bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+ }
+
+ /* Check CRS SYNC Missed flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) {
+ /* CRS SYNC Missed */
+ crsstatus |= RCC_CRS_SYNCMISS;
+
+ /* Clear CRS SYNC Missed bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+ }
+
+ /* Check CRS Expected SYNC flag */
+ if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) {
+ /* frequency error counter reached a zero value */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+ }
+ } while (RCC_CRS_NONE == crsstatus);
+
+ return crsstatus;
+}
+
+/**
+ * @brief Handle the Clock Recovery System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_CRS_IRQHandler(void) {
+ uint32_t crserror = RCC_CRS_NONE;
+ /* Get current IT flags and IT sources values */
+ uint32_t itflags = READ_REG(CRS->ISR);
+ uint32_t itsources = READ_REG(CRS->CR);
+
+ /* Check CRS SYNCOK flag */
+ if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) &&
+ ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) {
+ /* Clear CRS SYNC event OK flag */
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+ /* user callback */
+ HAL_RCCEx_CRS_SyncOkCallback();
+ }
+ /* Check CRS SYNCWARN flag */
+ else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) &&
+ ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) {
+ /* Clear CRS SYNCWARN flag */
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+ /* user callback */
+ HAL_RCCEx_CRS_SyncWarnCallback();
+ }
+ /* Check CRS Expected SYNC flag */
+ else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) &&
+ ((itsources & RCC_CRS_IT_ESYNC) != 0U)) {
+ /* frequency error counter reached a zero value */
+ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+ /* user callback */
+ HAL_RCCEx_CRS_ExpectedSyncCallback();
+ }
+ /* Check CRS Error flags */
+ else {
+ if (((itflags & RCC_CRS_FLAG_ERR) != 0U) &&
+ ((itsources & RCC_CRS_IT_ERR) != 0U)) {
+ if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) {
+ crserror |= RCC_CRS_SYNCERR;
+ }
+ if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) {
+ crserror |= RCC_CRS_SYNCMISS;
+ }
+ if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) {
+ crserror |= RCC_CRS_TRIMOVF;
+ }
+
+ /* Clear CRS Error flags */
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+ /* user error callback */
+ HAL_RCCEx_CRS_ErrorCallback(crserror);
+ }
+ }
+}
+
+/**
+ * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in
+ the user file
+ */
+}
+
+/**
+ * @brief RCCEx Clock Recovery System Error interrupt callback.
+ * @param Error Combination of Error status.
+ * This parameter can be a combination of the following values:
+ * @arg @ref RCC_CRS_SYNCERR
+ * @arg @ref RCC_CRS_SYNCMISS
+ * @arg @ref RCC_CRS_TRIMOVF
+ * @retval none
+ */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Error);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the
+ user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* CRS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c
index a005bf3..c2844d3 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c
@@ -1,4213 +1,4217 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_spi.c
- * @author MCD Application Team
- * @brief SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Serial Peripheral Interface (SPI)
- peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SPI HAL driver can be used as follows:
-
- (#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
-
- (#)Initialize the SPI low level resources by implementing the
- HAL_SPI_MspInit() API:
- (##) Enable the SPIx interface clock
- (##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
- (+++) Configure these SPI pins as alternate function push-pull
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SPIx interrupt priority
- (+++) Enable the NVIC SPI IRQ handle
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the
- transmit or receive Stream/Channel
- (+++) Enable the DMAx clock
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Stream/Channel
- (+++) Associate the initialized hdma_tx(or _rx) handle to the
- hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer
- complete interrupt on the DMA Tx or Rx Stream/Channel
-
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler,
- NSS management, Clock polarity and phase, FirstBit and CRC configuration in
- the hspi Init structure.
-
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK,
- CORTEX...etc) by calling the customized HAL_SPI_MspInit() API.
- [..]
- Circular mode restriction:
- (#) The DMA circular mode cannot be used when the SPI is configured in
- these modes:
- (##) Master 2Lines RxOnly
- (##) Master 1Line Rx
- (#) The CRC feature is not managed when the DMA circular mode is enabled
- (#) When the SPI DMA Pause/Stop features are used, we must use the
- following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI
- callbacks
- [..]
- Master Receive mode restriction:
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0,
- RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to
- ensure that the SPI does not initiate a new transfer the following procedure
- has to be respected:
- (##) HAL_SPI_DeInit()
- (##) HAL_SPI_Init()
- [..]
- Callback registration:
-
- (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
- allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_SPI_RegisterCallback() to register an interrupt
- callback.
-
- Function HAL_SPI_RegisterCallback() allows to register following
- callbacks:
- (++) TxCpltCallback : SPI Tx Completed callback
- (++) RxCpltCallback : SPI Rx Completed callback
- (++) TxRxCpltCallback : SPI TxRx Completed callback
- (++) TxHalfCpltCallback : SPI Tx Half Completed callback
- (++) RxHalfCpltCallback : SPI Rx Half Completed callback
- (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (++) ErrorCallback : SPI Error callback
- (++) AbortCpltCallback : SPI Abort callback
- (++) MspInitCallback : SPI Msp Init callback
- (++) MspDeInitCallback : SPI Msp DeInit callback
- This function takes as parameters the HAL peripheral handle, the
- Callback ID and a pointer to the user callback function.
-
-
- (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the
- default weak function. HAL_SPI_UnRegisterCallback takes as parameters the HAL
- peripheral handle, and the Callback ID. This function allows to reset
- following callbacks:
- (++) TxCpltCallback : SPI Tx Completed callback
- (++) RxCpltCallback : SPI Rx Completed callback
- (++) TxRxCpltCallback : SPI TxRx Completed callback
- (++) TxHalfCpltCallback : SPI Tx Half Completed callback
- (++) RxHalfCpltCallback : SPI Rx Half Completed callback
- (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (++) ErrorCallback : SPI Error callback
- (++) AbortCpltCallback : SPI Abort callback
- (++) MspInitCallback : SPI Msp Init callback
- (++) MspDeInitCallback : SPI Msp DeInit callback
-
- [..]
- By default, after the HAL_SPI_Init() and when the state is
- HAL_SPI_STATE_RESET all callbacks are set to the corresponding weak functions:
- examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_SPI_Init()/
- HAL_SPI_DeInit() only when these callbacks are null (not registered
- beforehand). If MspInit or MspDeInit are not null, the HAL_SPI_Init()/
- HAL_SPI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered
- beforehand) whatever the state.
-
- [..]
- Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state
- only. Exception done MspInit/MspDeInit functions that can be
- registered/unregistered in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the
- Init/DeInit. Then, the user first registers the MspInit/MspDeInit user
- callbacks using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or
- HAL_SPI_Init() function.
-
- [..]
- When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
-
- [..]
- Using the HAL it is not possible to reach all supported SPI frequency
- with the different SPI Modes, the following table resume the max SPI frequency
- reached with data size 8bits/16bits, according to frequency of the APBx
- Peripheral Clock (fPCLK) used by the SPI instance.
-
- @endverbatim
-
- Additional table :
-
- DataSize = SPI_DATASIZE_8BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly |
- 1Line | | Process | Transfer mode
- |---------------------|----------------------|----------------------| | | |
- Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA |
- NA | NA | | X
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA |
- NA | NA | | R
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
- NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 |
- Fpclk/8 | Fpclk/8 | |
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 |
- Fpclk/8 | Fpclk/4 | | X
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 |
- Fpclk/2 | Fpclk/16 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/8 | Fpclk/2 | NA | NA |
- Fpclk/8 | Fpclk/8 | |
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA |
- Fpclk/16 | Fpclk/8 | | X
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
- Fpclk/8 | Fpclk/16 |
- +----------------------------------------------------------------------------------------------+
-
- DataSize = SPI_DATASIZE_16BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly |
- 1Line | | Process | Transfer mode
- |---------------------|----------------------|----------------------| | | |
- Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA |
- NA | NA | | X
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA |
- NA | NA | | R
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
- NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 |
- Fpclk/8 | Fpclk/8 | |
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 |
- Fpclk/8 | Fpclk/4 | | X
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 |
- Fpclk/2 | Fpclk/16 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/8 | Fpclk/2 | NA | NA |
- Fpclk/8 | Fpclk/8 | |
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA |
- Fpclk/16 | Fpclk/8 | | X
- |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
- Fpclk/8 | Fpclk/16 |
- +----------------------------------------------------------------------------------------------+
- @note The max SPI frequency depend on SPI data size (4bits, 5bits,...,
- 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line
- TX/RX) and Process mode (Polling, IT, DMA).
- @note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(),
- HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and
- HAL_SPI_Receive_DMA()
- (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and
- HAL_SPI_Transmit_DMA()
-
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPI SPI
- * @brief SPI HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
- uint32_t Flag,
- FlagStatus State,
- uint32_t Timeout,
- uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
- uint32_t Fifo,
- uint32_t State,
- uint32_t Timeout,
- uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,
- uint32_t Timeout,
- uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi,
- uint32_t Timeout,
- uint32_t Tickstart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization
-functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPIx peripheral:
-
- (+) User must implement HAL_SPI_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPI_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Direction
- (++) Data Size
- (++) Clock Polarity and Phase
- (++) NSS Management
- (++) BaudRate Prescaler
- (++) FirstBit
- (++) TIMode
- (++) CRC Calculation
- (++) CRC Polynomial if CRC enabled
- (++) CRC Length, used only with Data8 and Data16
- (++) FIFO reception threshold
-
- (+) Call the function HAL_SPI_DeInit() to restore the default
-configuration of the selected SPIx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SPI according to the specified parameters
- * in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) {
- uint32_t frxth;
-
- /* Check the SPI handle allocation */
- if (hspi == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
- assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_NSS(hspi->Init.NSS));
- assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
- if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) {
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-
- if (hspi->Init.Mode == SPI_MODE_MASTER) {
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- } else {
- /* Baudrate prescaler not use in Motoraola Slave mode. force to default
- * value */
- hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
- }
- } else {
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-
- /* Force polarity and phase to TI protocaol requirements */
- hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
- hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
- }
-#if (USE_SPI_CRC != 0U)
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
- }
-#else
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
- if (hspi->State == HAL_SPI_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- hspi->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- /* Init the SPI Callback settings */
- hspi->TxCpltCallback =
- HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hspi->RxCpltCallback =
- HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
- hspi->TxRxCpltCallback =
- HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
- hspi->TxHalfCpltCallback =
- HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- hspi->RxHalfCpltCallback =
- HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- hspi->TxRxHalfCpltCallback =
- HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
- hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
- hspi->AbortCpltCallback =
- HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
-
- if (hspi->MspInitCallback == NULL) {
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
- }
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- hspi->MspInitCallback(hspi);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the selected SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Align by default the rs fifo threshold on the data size */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- frxth = SPI_RXFIFO_THRESHOLD_HF;
- } else {
- frxth = SPI_RXFIFO_THRESHOLD_QF;
- }
-
- /* CRC calculation is valid only for 16Bit and 8 Bit */
- if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) &&
- (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) {
- /* CRC must be disabled */
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
- }
-
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
- /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS
- management, Communication speed, First bit and CRC calculation state */
- WRITE_REG(
- hspi->Instance->CR1,
- ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
- (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
- (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
- (hspi->Init.CLKPhase & SPI_CR1_CPHA) | (hspi->Init.NSS & SPI_CR1_SSM) |
- (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
- (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
- (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
-#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCL Configuration -------------------*/
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Align the CRC Length on the data size */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) {
- /* CRC Length aligned on the data size : value set by default */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
- } else {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
- }
- }
-
- /* Configure : CRC Length */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo
- * threshold */
- WRITE_REG(hspi->Instance->CR2,
- (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
- (hspi->Init.TIMode & SPI_CR2_FRF) |
- (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
- (hspi->Init.DataSize & SPI_CR2_DS_Msk) | (frxth & SPI_CR2_FRXTH)));
-
-#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
- /* Configure : CRC Polynomial */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- WRITE_REG(hspi->Instance->CRCPR,
- (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
- }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is
- * reset) */
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initialize the SPI peripheral.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) {
- /* Check the SPI handle allocation */
- if (hspi == NULL) {
- return HAL_ERROR;
- }
-
- /* Check SPI Instance parameter */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the SPI Peripheral Clock */
- __HAL_SPI_DISABLE(hspi);
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- if (hspi->MspDeInitCallback == NULL) {
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- hspi->MspDeInitCallback(hspi);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_SPI_MspDeInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SPI MSP.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspInit should be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize the SPI MSP.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit should be implemented in the user file
- */
-}
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
- * @brief Register a User SPI Callback
- * To be used instead of the weak predefined callback
- * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI.
- * @param CallbackID ID of the callback to be registered
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi,
- HAL_SPI_CallbackIDTypeDef CallbackID,
- pSPI_CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- /* Update the error code */
- hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hspi);
-
- if (HAL_SPI_STATE_READY == hspi->State) {
- switch (CallbackID) {
- case HAL_SPI_TX_COMPLETE_CB_ID:
- hspi->TxCpltCallback = pCallback;
- break;
-
- case HAL_SPI_RX_COMPLETE_CB_ID:
- hspi->RxCpltCallback = pCallback;
- break;
-
- case HAL_SPI_TX_RX_COMPLETE_CB_ID:
- hspi->TxRxCpltCallback = pCallback;
- break;
-
- case HAL_SPI_TX_HALF_COMPLETE_CB_ID:
- hspi->TxHalfCpltCallback = pCallback;
- break;
-
- case HAL_SPI_RX_HALF_COMPLETE_CB_ID:
- hspi->RxHalfCpltCallback = pCallback;
- break;
-
- case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID:
- hspi->TxRxHalfCpltCallback = pCallback;
- break;
-
- case HAL_SPI_ERROR_CB_ID:
- hspi->ErrorCallback = pCallback;
- break;
-
- case HAL_SPI_ABORT_CB_ID:
- hspi->AbortCpltCallback = pCallback;
- break;
-
- case HAL_SPI_MSPINIT_CB_ID:
- hspi->MspInitCallback = pCallback;
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID:
- hspi->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (HAL_SPI_STATE_RESET == hspi->State) {
- switch (CallbackID) {
- case HAL_SPI_MSPINIT_CB_ID:
- hspi->MspInitCallback = pCallback;
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID:
- hspi->MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
- return status;
-}
-
-/**
- * @brief Unregister an SPI Callback
- * SPI callback is redirected to the weak predefined callback
- * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI.
- * @param CallbackID ID of the callback to be unregistered
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(
- SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- if (HAL_SPI_STATE_READY == hspi->State) {
- switch (CallbackID) {
- case HAL_SPI_TX_COMPLETE_CB_ID:
- hspi->TxCpltCallback =
- HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
- break;
-
- case HAL_SPI_RX_COMPLETE_CB_ID:
- hspi->RxCpltCallback =
- HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
- break;
-
- case HAL_SPI_TX_RX_COMPLETE_CB_ID:
- hspi->TxRxCpltCallback =
- HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
- break;
-
- case HAL_SPI_TX_HALF_COMPLETE_CB_ID:
- hspi->TxHalfCpltCallback =
- HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- break;
-
- case HAL_SPI_RX_HALF_COMPLETE_CB_ID:
- hspi->RxHalfCpltCallback =
- HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- break;
-
- case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID:
- hspi->TxRxHalfCpltCallback =
- HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
- break;
-
- case HAL_SPI_ERROR_CB_ID:
- hspi->ErrorCallback =
- HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_SPI_ABORT_CB_ID:
- hspi->AbortCpltCallback =
- HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- break;
-
- case HAL_SPI_MSPINIT_CB_ID:
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID:
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default:
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (HAL_SPI_STATE_RESET == hspi->State) {
- switch (CallbackID) {
- case HAL_SPI_MSPINIT_CB_ID:
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID:
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default:
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
- return status;
-}
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SPI
- data transfers.
-
- [..] The SPI supports master and slave mode :
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same
-function after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and
-HAL_SPI_TxRxCpltCallback() user callbacks will be executed respectively at the
-end of the transmit or Receive process The HAL_SPI_ErrorCallback()user callback
-will be executed when a communication error is detected
-
- (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking
-mode using either Interrupt or DMA) exist for 1Line (simplex) and 2Lines (full
-duplex) modes.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size, uint32_t Timeout) {
- uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
- uint16_t initial_TxXferCount;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
- initial_TxXferCount = Size;
-
- if (hspi->State != HAL_SPI_STATE_READY) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit data in 16 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- /* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0U) {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- } else {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) &&
- (Timeout != HAL_MAX_DELAY)) ||
- (Timeout == 0U)) {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- /* Transmit data in 8 Bit mode */
- else {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
- if (hspi->TxXferCount > 1U) {
- /* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- } else {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
- }
- }
- while (hspi->TxXferCount > 0U) {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) {
- if (hspi->TxXferCount > 1U) {
- /* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- } else {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
- }
- } else {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) &&
- (Timeout != HAL_MAX_DELAY)) ||
- (Timeout == 0U)) {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not
- * read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES) {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- errorcode = HAL_ERROR;
- }
-
-error:
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size, uint32_t Timeout) {
-#if (USE_SPI_CRC != 0U)
- __IO uint32_t tmpreg = 0U;
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
- (hspi->Init.Direction == SPI_DIRECTION_2LINES)) {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate
- * clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (hspi->State != HAL_SPI_STATE_READY) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- /* this is done to handle the CRCNEXT before the latest data */
- hspi->RxXferCount--;
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the Rx Fifo threshold */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- /* Set RX Fifo threshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- } else {
- /* Set RX Fifo threshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Configure communication direction: 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_RX(hspi);
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Receive data in 8 Bit mode */
- if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U) {
- /* Check the RXNE flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) {
- /* read the received data */
- (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- } else {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) &&
- (Timeout != HAL_MAX_DELAY)) ||
- (Timeout == 0U)) {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- } else {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U) {
- /* Check the RXNE flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- } else {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) &&
- (Timeout != HAL_MAX_DELAY)) ||
- (Timeout == 0U)) {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Handle the CRC Transmission */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* freeze the CRC before the latest data */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
- /* Read the latest data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
- tickstart) != HAL_OK) {
- /* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Receive last data in 16 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- }
- /* Receive last data in 8 Bit mode */
- else {
- (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
- }
-
- /* Wait the CRC data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
- tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Read CRC to Flush DR and RXNE flag */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) {
- /* Read 16bit CRC */
- tmpreg = READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- } else {
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
- /* Read 8bit CRC */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
-
- if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) &&
- (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) {
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
- tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
- }
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- errorcode = HAL_ERROR;
- }
-
-error:
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @param Size amount of data to be sent and received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi,
- uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size, uint32_t Timeout) {
- uint16_t initial_TxXferCount;
- uint16_t initial_RxXferCount;
- uint32_t tmp_mode;
- HAL_SPI_StateTypeDef tmp_state;
- uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
- __IO uint32_t tmpreg = 0U;
- uint32_t spi_cr1;
- uint32_t spi_cr2;
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-#endif /* USE_SPI_CRC */
-
- /* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Init temporary variables */
- tmp_state = hspi->State;
- tmp_mode = hspi->Init.Mode;
- initial_TxXferCount = Size;
- initial_RxXferCount = Size;
-#if (USE_SPI_CRC != 0U)
- spi_cr1 = READ_REG(hspi->Instance->CR1);
- spi_cr2 = READ_REG(hspi->Instance->CR2);
-#endif /* USE_SPI_CRC */
-
- if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) &&
- (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
- (tmp_state == HAL_SPI_STATE_BUSY_RX)))) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX) {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferCount = Size;
- hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferCount = Size;
- hspi->TxXferSize = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the Rx Fifo threshold */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) {
- /* Set fiforxthreshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- } else {
- /* Set fiforxthreshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit and Receive data in 16 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) {
- /* Check TXE flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) &&
- (hspi->TxXferCount > 0U) && (txallowed == 1U)) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->TxXferCount == 0U) &&
- (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
- /* Set NSS Soft to received correctly the CRC on slave mode with NSS
- * pulse activated */
- if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) &&
- (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
- }
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Check RXNE flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) &&
- (hspi->RxXferCount > 0U)) {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if (((HAL_GetTick() - tickstart) >= Timeout) &&
- (Timeout != HAL_MAX_DELAY)) {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- /* Transmit and Receive data in 8 Bit mode */
- else {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
- if (hspi->TxXferCount > 1U) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- } else {
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
- }
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) {
- /* Check TXE flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) &&
- (hspi->TxXferCount > 0U) && (txallowed == 1U)) {
- if (hspi->TxXferCount > 1U) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- } else {
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
- }
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->TxXferCount == 0U) &&
- (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
- /* Set NSS Soft to received correctly the CRC on slave mode with NSS
- * pulse activated */
- if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) &&
- (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
- }
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Wait until RXNE flag is reset */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) &&
- (hspi->RxXferCount > 0U)) {
- if (hspi->RxXferCount > 1U) {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2U;
- if (hspi->RxXferCount <= 1U) {
- /* Set RX Fifo threshold before to switch on 8 bit data size */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- } else {
- (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
- hspi->pRxBuffPtr++;
- hspi->RxXferCount--;
- }
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if ((((HAL_GetTick() - tickstart) >= Timeout) &&
- ((Timeout != HAL_MAX_DELAY))) ||
- (Timeout == 0U)) {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Read CRC from DR to close CRC calculation process */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Wait until TXE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
- tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- /* Read CRC */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) {
- /* Read 16bit CRC */
- tmpreg = READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- } else {
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
- /* Read 8bit CRC */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
-
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) {
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
- tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
- }
- }
- }
-
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- /* Clear CRC Flag */
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- errorcode = HAL_ERROR;
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) {
- errorcode = HAL_ERROR;
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
-error:
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size) {
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if ((pData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- if (hspi->State != HAL_SPI_STATE_READY) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->RxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- hspi->TxISR = SPI_TxISR_16BIT;
- } else {
- hspi->TxISR = SPI_TxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error:
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size) {
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
- (hspi->Init.Mode == SPI_MODE_MASTER)) {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate
- * clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->TxISR = NULL;
-
- /* Check the data size to adapt Rx threshold and the set the function for IT
- * treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- /* Set RX Fifo threshold according the reception data length: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_16BIT;
- } else {
- /* Set RX Fifo threshold according the reception data length: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- hspi->CRCSize = 1U;
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) &&
- (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) {
- hspi->CRCSize = 2U;
- }
- SPI_RESET_CRC(hspi);
- } else {
- hspi->CRCSize = 0U;
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with
- * Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @param Size amount of data to be sent and received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi,
- uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size) {
- uint32_t tmp_mode;
- HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- /* Init temporary variables */
- tmp_state = hspi->State;
- tmp_mode = hspi->Init.Mode;
-
- if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) &&
- (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
- (tmp_state == HAL_SPI_STATE_BUSY_RX)))) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX) {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- } else {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- hspi->CRCSize = 1U;
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) &&
- (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) {
- hspi->CRCSize = 2U;
- }
- SPI_RESET_CRC(hspi);
- } else {
- hspi->CRCSize = 0U;
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if packing mode is enabled and if there is more than 2 data to
- * receive */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) {
- /* Set RX Fifo threshold according the reception data length: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- } else {
- /* Set RX Fifo threshold according the reception data length: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size) {
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check tx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the SPI TxDMA Half transfer complete callback */
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- /* Packing mode is enabled only if the DMA setting is HALWORD */
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) &&
- (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) {
- /* Check the even/odd of the data size + crc if enabled */
- if ((hspi->TxXferCount & 0x1U) == 0U) {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1U);
- } else {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
- }
- }
-
- /* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr,
- (uint32_t)&hspi->Instance->DR,
- hspi->TxXferCount)) {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx
- * shall be defined.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
- uint16_t Size) {
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check rx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
- (hspi->Init.Mode == SPI_MODE_MASTER)) {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
-
- /* Check tx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Call transmit-receive function to send Dummy data on Tx line and generate
- * clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- /* Set RX Fifo threshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- } else {
- /* Set RX Fifo threshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) {
- /* Set RX Fifo threshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if ((hspi->RxXferCount & 0x1U) == 0x0U) {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1U;
- } else {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
- }
- }
- }
-
- /* Set the SPI RxDMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR,
- (uint32_t)hspi->pRxBuffPtr,
- hspi->RxXferCount)) {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi,
- uint8_t *pTxData,
- uint8_t *pRxData, uint16_t Size) {
- uint32_t tmp_mode;
- HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check rx & tx dma handles */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- /* Init temporary variables */
- tmp_state = hspi->State;
- tmp_mode = hspi->Init.Mode;
-
- if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) &&
- (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
- (tmp_state == HAL_SPI_STATE_BUSY_RX)))) {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX) {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Reset the threshold bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
-
- /* The packing mode management is enabled by the DMA settings according the
- * spi data size */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- /* Set fiforxthreshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- } else {
- /* Set RX Fifo threshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) {
- if ((hspi->TxXferSize & 0x1U) == 0x0U) {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = hspi->TxXferCount >> 1U;
- } else {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
- }
- }
-
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) {
- /* Set RX Fifo threshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if ((hspi->RxXferCount & 0x1U) == 0x0U) {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1U;
- } else {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
- }
- }
- }
-
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer
- * complete callback */
- if (hspi->State == HAL_SPI_STATE_BUSY_RX) {
- /* Set the SPI Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
- } else {
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
- }
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR,
- (uint32_t)hspi->pRxBuffPtr,
- hspi->RxXferCount)) {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Set the SPI Tx DMA transfer complete callback as NULL because the
- communication closing is performed in DMA reception complete callback */
- hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
- hspi->hdmatx->XferErrorCallback = NULL;
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr,
- (uint32_t)&hspi->Instance->DR,
- hspi->TxXferCount)) {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (blocking mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx
- * and Rx), started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
- * in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function,
- * Abort is considered as completed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) {
- HAL_StatusTypeDef errorcode;
- __IO uint32_t count;
- __IO uint32_t resetcount;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- count = resetcount;
-
- /* Clear ERRIE interrupt to avoid error interrupts generation during Abort
- * procedure */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame
- * error) interrupts */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) {
- hspi->TxISR = SPI_AbortTx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) {
- hspi->RxISR = SPI_AbortRx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- /* Disable the SPI DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) {
- /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no
- * callback) */
- if (hspi->hdmatx != NULL) {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort
- procedure */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
- HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- }
- }
-
- /* Disable the SPI DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) {
- /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no
- * callback) */
- if (hspi->hdmarx != NULL) {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort
- procedure */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
- }
- }
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- } else {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->state to ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (Interrupt mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx
- * and Rx), started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
- * transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort
- * procedure could be considered as completed only when user abort complete
- * callback is executed (not when exiting function).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) {
- HAL_StatusTypeDef errorcode;
- uint32_t abortcplt;
- __IO uint32_t count;
- __IO uint32_t resetcount;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- abortcplt = 1U;
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- count = resetcount;
-
- /* Clear ERRIE interrupt to avoid error interrupts generation during Abort
- * procedure */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts
- */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) {
- hspi->TxISR = SPI_AbortTx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) {
- hspi->RxISR = SPI_AbortRx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort
- complete callbacks should be initialised before any call to DMA Abort
- functions */
- /* DMA Tx Handle is valid */
- if (hspi->hdmatx != NULL) {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) {
- hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
- } else {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if (hspi->hdmarx != NULL) {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) {
- hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
- } else {
- hspi->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SPI DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) {
- /* Abort the SPI DMA Tx Stream/Channel */
- if (hspi->hdmatx != NULL) {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) {
- hspi->hdmatx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- } else {
- abortcplt = 0U;
- }
- }
- }
- /* Disable the SPI DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) {
- /* Abort the SPI DMA Rx Stream/Channel */
- if (hspi->hdmarx != NULL) {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) {
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- } else {
- abortcplt = 0U;
- }
- }
- }
-
- if (abortcplt == 1U) {
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- } else {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->AbortCpltCallback(hspi);
-#else
- HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-
- return errorcode;
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) {
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) {
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Enable the SPI DMA Tx & Rx requests */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) {
- HAL_StatusTypeDef errorcode = HAL_OK;
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or
- HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): when calling
- HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or
- HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
- */
-
- /* Abort the SPI DMA tx Stream/Channel */
- if (hspi->hdmatx != NULL) {
- if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
- /* Abort the SPI DMA rx Stream/Channel */
- if (hspi->hdmarx != NULL) {
- if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->State = HAL_SPI_STATE_READY;
- return errorcode;
-}
-
-/**
- * @brief Handle SPI interrupt request.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval None
- */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) {
- uint32_t itsource = hspi->Instance->CR2;
- uint32_t itflag = hspi->Instance->SR;
-
- /* SPI in mode Receiver ----------------------------------------------------*/
- if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
- (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) &&
- (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) {
- hspi->RxISR(hspi);
- return;
- }
-
- /* SPI in mode Transmitter -------------------------------------------------*/
- if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) &&
- (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) {
- hspi->TxISR(hspi);
- return;
- }
-
- /* SPI in Error Treatment --------------------------------------------------*/
- if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) ||
- (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) ||
- (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) &&
- (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) {
- /* SPI Overrun error interrupt occurred ----------------------------------*/
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) {
- if (hspi->State != HAL_SPI_STATE_BUSY_TX) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- } else {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- return;
- }
- }
-
- /* SPI Mode Fault error interrupt occurred -------------------------------*/
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- /* SPI Frame error interrupt occurred ------------------------------------*/
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- /* Disable all interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
- hspi->State = HAL_SPI_STATE_READY;
- /* Disable the SPI DMA requests if enabled */
- if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) ||
- (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) {
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
- /* Abort the SPI DMA Rx channel */
- if (hspi->hdmarx != NULL) {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort
- procedure */
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- }
- }
- /* Abort the SPI DMA Tx channel */
- if (hspi->hdmatx != NULL) {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort
- procedure */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- }
- }
- } else {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- }
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user
- file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user
- file
- */
-}
-
-/**
- * @brief Tx and Rx Half Transfer callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user
- file
- */
-}
-
-/**
- * @brief SPI error callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback should be implemented in the user file
- */
- /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI
- processes and user can use HAL_SPI_GetError() API to check the latest error
- occurred
- */
-}
-
-/**
- * @brief SPI Abort Complete callback.
- * @param hspi SPI handle.
- * @retval None
- */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors
-functions
- * @brief SPI control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SPI.
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of
-the SPI peripheral
- (+) HAL_SPI_GetError() check in run-time Errors occurring during
-communication
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SPI handle state.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI state
- */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) {
- /* Return SPI handle state */
- return hspi->State;
-}
-
-/**
- * @brief Return the SPI error code.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI error code in bitmap format
- */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) {
- /* Return SPI ErrorCode */
- return hspi->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SPI_Private_Functions
- * @brief Private functions
- * @{
- */
-
-/**
- * @brief DMA SPI transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- uint32_t tickstart;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) !=
- HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received data is
- * not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES) {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->TxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
- }
- /* Call user Tx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxCpltCallback(hspi);
-#else
- HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
- __IO uint32_t tmpreg = 0U;
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-#endif /* USE_SPI_CRC */
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Wait until RXNE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET,
- SPI_DEFAULT_TIMEOUT,
- tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
- /* Read 16bit CRC */
- tmpreg = READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- } else {
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
- /* Read 8bit CRC */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
-
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) {
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET,
- SPI_DEFAULT_TIMEOUT,
- tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
- }
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if we are in Master RX 2 line mode */
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
- (hspi->Init.Mode == SPI_MODE_MASTER)) {
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx
- * direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- } else {
- /* Normal case */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
- }
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
- }
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxCpltCallback(hspi);
-#else
- HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
- __IO uint32_t tmpreg = 0U;
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-#endif /* USE_SPI_CRC */
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) &&
- (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) {
- if (SPI_WaitFifoStateUntilTimeout(
- hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL,
- SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
- /* Read 8bit CRC */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
- } else {
- if (SPI_WaitFifoStateUntilTimeout(
- hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT,
- tickstart) != HAL_OK) {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC to Flush DR and RXNE flag */
- tmpreg = READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) !=
- HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Disable Rx/Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0U;
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
- }
- /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxRxCpltCallback(hspi);
-#else
- HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI half transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user Tx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxHalfCpltCallback(hspi);
-#else
- HAL_SPI_TxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI half receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user Rx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxHalfCpltCallback(hspi);
-#else
- HAL_SPI_RxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI half transmit receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user TxRx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxRxHalfCpltCallback(hspi);
-#else
- HAL_SPI_TxRxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI communication error callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Stop the disable DMA transfer on SPI side */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI communication abort callback, when initiated by HAL services
- * on Error (To be called at end of DMA Abort procedure following error
- * occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort
- * request).
- * @note When this callback is executed, User Abort complete call back is
- * called only if no Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
- HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmarx != NULL) {
- if (hspi->hdmarx->XferAbortCallback != NULL) {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call
- * user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check no error during Abort procedure */
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->AbortCpltCallback(hspi);
-#else
- HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort
- * request).
- * @note When this callback is executed, User Abort complete call back is
- * called only if no Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) {
- SPI_HandleTypeDef *hspi =
- (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)
- ->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmatx != NULL) {
- if (hspi->hdmatx->XferAbortCallback != NULL) {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call
- * user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check no error during Abort procedure */
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->AbortCpltCallback(hspi);
-#else
- HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
- /* Receive data in packing mode */
- if (hspi->RxXferCount > 1U) {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2U;
- if (hspi->RxXferCount == 1U) {
- /* Set RX Fifo threshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- }
- /* Receive data in 8 Bit mode */
- else {
- *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
- hspi->pRxBuffPtr++;
- hspi->RxXferCount--;
- }
-
- /* Check end of the reception */
- if (hspi->RxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_2linesRxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if (hspi->TxXferCount == 0U) {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) {
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
- /* Read 8bit CRC to flush Data Register */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
-
- hspi->CRCSize--;
-
- /* Check end of the reception */
- if (hspi->CRCSize == 0U) {
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if (hspi->TxXferCount == 0U) {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
- /* Transmit data in packing Bit mode */
- if (hspi->TxXferCount >= 2U) {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- }
- /* Transmit data in 8 Bit mode */
- else {
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
- }
-
- /* Check the end of the transmission */
- if (hspi->TxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Set CRC Next Bit to send CRC */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if (hspi->RxXferCount == 0U) {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-/**
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
- /* Receive data in 16 Bit mode */
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
- if (hspi->RxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- hspi->RxISR = SPI_2linesRxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if (hspi->TxXferCount == 0U) {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt
- * mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) {
- __IO uint32_t tmpreg = 0U;
-
- /* Read 16bit CRC to flush Data Register */
- tmpreg = READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- /* Enable CRC Transmission */
- if (hspi->TxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Set CRC Next Bit to send CRC */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if (hspi->RxXferCount == 0U) {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) {
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
- /* Read 8bit CRC to flush Data Register */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
-
- hspi->CRCSize--;
-
- if (hspi->CRCSize == 0U) {
- SPI_CloseRx_ISR(hspi);
- }
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
- *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
- hspi->pRxBuffPtr++;
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->RxXferCount == 1U) &&
- (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->RxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- hspi->RxISR = SPI_RxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) {
- __IO uint32_t tmpreg = 0U;
-
- /* Read 16bit CRC to flush Data Register */
- tmpreg = READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->RxXferCount == 1U) &&
- (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->RxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- hspi->RxISR = SPI_RxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
-
- if (hspi->TxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- if (hspi->TxXferCount == 0U) {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag SPI flag to check
- * @param State flag state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
- uint32_t Flag,
- FlagStatus State,
- uint32_t Timeout,
- uint32_t Tickstart) {
- __IO uint32_t count;
- uint32_t tmp_timeout;
- uint32_t tmp_tickstart;
-
- /* Adjust Timeout value in case of end of transfer */
- tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
- tmp_tickstart = HAL_GetTick();
-
- /* Calculate Timeout based on a software loop to avoid blocking issue if
- * Systick is disabled */
- count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
-
- while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) {
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) ||
- (tmp_timeout == 0U)) {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
- ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
- (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- /* If Systick is disabled or not incremented, deactivate timeout to go in
- * disable loop procedure */
- if (count == 0U) {
- tmp_timeout = 0U;
- }
- count--;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SPI FIFO Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Fifo Fifo to check
- * @param State Fifo state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
- uint32_t Fifo,
- uint32_t State,
- uint32_t Timeout,
- uint32_t Tickstart) {
- __IO uint32_t count;
- uint32_t tmp_timeout;
- uint32_t tmp_tickstart;
- __IO uint8_t *ptmpreg8;
- __IO uint8_t tmpreg8 = 0;
-
- /* Adjust Timeout value in case of end of transfer */
- tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
- tmp_tickstart = HAL_GetTick();
-
- /* Initialize the 8bit temporary pointer */
- ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
-
- /* Calculate Timeout based on a software loop to avoid blocking issue if
- * Systick is disabled */
- count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
-
- while ((hspi->Instance->SR & Fifo) != State) {
- if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) {
- /* Flush Data Register by a blank read */
- tmpreg8 = *ptmpreg8;
- /* To avoid GCC warning */
- UNUSED(tmpreg8);
- }
-
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) ||
- (tmp_timeout == 0U)) {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
- ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
- (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- /* If Systick is disabled or not incremented, deactivate timeout to go in
- * disable loop procedure */
- if (count == 0U) {
- tmp_timeout = 0U;
- }
- count--;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle the check of the RX transaction complete.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,
- uint32_t Timeout,
- uint32_t Tickstart) {
- if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
- ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
- (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout,
- Tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
- ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
- (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- Timeout, Tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi SPI handle
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi,
- uint32_t Timeout,
- uint32_t Tickstart) {
- /* Control if the TX fifo is empty */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY,
- Timeout, Tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout,
- Tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- /* Control if the RX fifo is empty */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- Timeout, Tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle the end of the RXTX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) {
- uint32_t tickstart;
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) {
- hspi->State = HAL_SPI_STATE_READY;
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- } else {
-#endif /* USE_SPI_CRC */
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) {
- if (hspi->State == HAL_SPI_STATE_BUSY_RX) {
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxCpltCallback(hspi);
-#else
- HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- } else {
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxRxCpltCallback(hspi);
-#else
- HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- } else {
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the RX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) {
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
- HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- } else {
-#endif /* USE_SPI_CRC */
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) {
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxCpltCallback(hspi);
-#else
- HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- } else {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the TX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) {
- uint32_t tickstart;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Disable TXE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not
- * read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES) {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- } else {
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxCpltCallback(hspi);
-#else
- HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief Handle abort a Rx transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) {
- __IO uint32_t count;
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Disable RXNEIE interrupt */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
-
- /* Check RXNEIE is disabled */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
- * @brief Handle abort a Tx or Rx/Tx transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) {
- __IO uint32_t count;
-
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Disable TXEIE interrupt */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
-
- /* Check TXEIE is disabled */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
-
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
- HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) {
- /* Disable RXNEIE interrupt */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
-
- /* Check RXNEIE is disabled */
- do {
- if (count == 0U) {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
- SPI_DEFAULT_TIMEOUT,
- HAL_GetTick()) != HAL_OK) {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- }
- hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_spi.c
+ * @author MCD Application Team
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI)
+ peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the
+ HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the
+ transmit or receive Stream/Channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream/Channel
+ (+++) Associate the initialized hdma_tx(or _rx) handle to the
+ hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx or Rx Stream/Channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler,
+ NSS management, Clock polarity and phase, FirstBit and CRC configuration in
+ the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK,
+ CORTEX...etc) by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in
+ these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the
+ following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI
+ callbacks
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0,
+ RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to
+ ensure that the SPI does not initiate a new transfer the following procedure
+ has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt
+ callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following
+ callbacks:
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the
+ Callback ID and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the
+ default weak function. HAL_SPI_UnRegisterCallback takes as parameters the HAL
+ peripheral handle, and the Callback ID. This function allows to reset
+ following callbacks:
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+
+ [..]
+ By default, after the HAL_SPI_Init() and when the state is
+ HAL_SPI_STATE_RESET all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/
+ HAL_SPI_DeInit() only when these callbacks are null (not registered
+ beforehand). If MspInit or MspDeInit are not null, the HAL_SPI_Init()/
+ HAL_SPI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered
+ beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state
+ only. Exception done MspInit/MspDeInit functions that can be
+ registered/unregistered in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the
+ Init/DeInit. Then, the user first registers the MspInit/MspDeInit user
+ callbacks using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or
+ HAL_SPI_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency
+ with the different SPI Modes, the following table resume the max SPI frequency
+ reached with data size 8bits/16bits, according to frequency of the APBx
+ Peripheral Clock (fPCLK) used by the SPI instance.
+
+ @endverbatim
+
+ Additional table :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly |
+ 1Line | | Process | Transfer mode
+ |---------------------|----------------------|----------------------| | | |
+ Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA |
+ NA | NA | | X
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA |
+ NA | NA | | R
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
+ NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 |
+ Fpclk/8 | Fpclk/8 | |
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 |
+ Fpclk/8 | Fpclk/4 | | X
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 |
+ Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA |
+ Fpclk/8 | Fpclk/8 | |
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA |
+ Fpclk/16 | Fpclk/8 | | X
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
+ Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly |
+ 1Line | | Process | Transfer mode
+ |---------------------|----------------------|----------------------| | | |
+ Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA |
+ NA | NA | | X
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA |
+ NA | NA | | R
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
+ NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 |
+ Fpclk/8 | Fpclk/8 | |
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 |
+ Fpclk/8 | Fpclk/4 | | X
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 |
+ Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA |
+ Fpclk/8 | Fpclk/8 | |
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA |
+ Fpclk/16 | Fpclk/8 | | X
+ |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA |
+ Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,...,
+ 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line
+ TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(),
+ HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and
+ HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and
+ HAL_SPI_Transmit_DMA()
+
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 100U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
+ uint32_t Flag,
+ FlagStatus State,
+ uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
+ uint32_t Fifo,
+ uint32_t State,
+ uint32_t Timeout,
+ uint32_t Tickstart);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,
+ uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi,
+ uint32_t Timeout,
+ uint32_t Tickstart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization
+functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default
+configuration of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) {
+ uint32_t frxth;
+
+ /* Check the SPI handle allocation */
+ if (hspi == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER) {
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ } else {
+ /* Baudrate prescaler not use in Motoraola Slave mode. force to default
+ * value */
+ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+ }
+ } else {
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+
+ /* Force polarity and phase to TI protocaol requirements */
+ hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
+ hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
+ }
+#if (USE_SPI_CRC != 0U)
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback =
+ HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback =
+ HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback =
+ HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback =
+ HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback =
+ HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback =
+ HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback =
+ HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL) {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Align by default the rs fifo threshold on the data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ frxth = SPI_RXFIFO_THRESHOLD_HF;
+ } else {
+ frxth = SPI_RXFIFO_THRESHOLD_QF;
+ }
+
+ /* CRC calculation is valid only for 16Bit and 8 Bit */
+ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) &&
+ (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) {
+ /* CRC must be disabled */
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ }
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS
+ management, Communication speed, First bit and CRC calculation state */
+ WRITE_REG(
+ hspi->Instance->CR1,
+ ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
+ (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
+ (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
+ (hspi->Init.CLKPhase & SPI_CR1_CPHA) | (hspi->Init.NSS & SPI_CR1_SSM) |
+ (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
+ (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
+ (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCL Configuration -------------------*/
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) {
+ /* CRC Length aligned on the data size : value set by default */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ } else {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo
+ * threshold */
+ WRITE_REG(hspi->Instance->CR2,
+ (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
+ (hspi->Init.TIMode & SPI_CR2_FRF) |
+ (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
+ (hspi->Init.DataSize & SPI_CR2_DS_Msk) | (frxth & SPI_CR2_FRXTH)));
+
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ WRITE_REG(hspi->Instance->CRCPR,
+ (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is
+ * reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initialize the SPI peripheral.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) {
+ /* Check the SPI handle allocation */
+ if (hspi == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ if (hspi->MspDeInitCallback == NULL) {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi,
+ HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State) {
+ switch (CallbackID) {
+ case HAL_SPI_TX_COMPLETE_CB_ID:
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID:
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID:
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID:
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID:
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID:
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID:
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID:
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID:
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID:
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (HAL_SPI_STATE_RESET == hspi->State) {
+ switch (CallbackID) {
+ case HAL_SPI_MSPINIT_CB_ID:
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID:
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(
+ SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State) {
+ switch (CallbackID) {
+ case HAL_SPI_TX_COMPLETE_CB_ID:
+ hspi->TxCpltCallback =
+ HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID:
+ hspi->RxCpltCallback =
+ HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID:
+ hspi->TxRxCpltCallback =
+ HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID:
+ hspi->TxHalfCpltCallback =
+ HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID:
+ hspi->RxHalfCpltCallback =
+ HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID:
+ hspi->TxRxHalfCpltCallback =
+ HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID:
+ hspi->ErrorCallback =
+ HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID:
+ hspi->AbortCpltCallback =
+ HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID:
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID:
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default:
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (HAL_SPI_STATE_RESET == hspi->State) {
+ switch (CallbackID) {
+ case HAL_SPI_MSPINIT_CB_ID:
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID:
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default:
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same
+function after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and
+HAL_SPI_TxRxCpltCallback() user callbacks will be executed respectively at the
+end of the transmit or Receive process The HAL_SPI_ErrorCallback()user callback
+will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking
+mode using either Interrupt or DMA) exist for 1Line (simplex) and 2Lines (full
+duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi,
+ const uint8_t *pData, uint16_t Size,
+ uint32_t Timeout) {
+ uint32_t tickstart;
+ uint16_t initial_TxXferCount;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ initial_TxXferCount = Size;
+
+ if (hspi->State != HAL_SPI_STATE_READY) {
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0U) {
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ } else {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) &&
+ (Timeout != HAL_MAX_DELAY)) ||
+ (Timeout == 0U)) {
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
+ if (hspi->TxXferCount > 1U) {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ } else {
+ *((__IO uint8_t *)&hspi->Instance->DR) =
+ *((const uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+ }
+ while (hspi->TxXferCount > 0U) {
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) {
+ if (hspi->TxXferCount > 1U) {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ } else {
+ *((__IO uint8_t *)&hspi->Instance->DR) =
+ *((const uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+ } else {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) &&
+ (Timeout != HAL_MAX_DELAY)) ||
+ (Timeout == 0U)) {
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not
+ * read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ return HAL_ERROR;
+ } else {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout) {
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart;
+
+ if (hspi->State != HAL_SPI_STATE_READY) {
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES)) {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate
+ * clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+ }
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx Fifo threshold */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ } else {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Receive data in 8 Bit mode */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U) {
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) {
+ /* read the received data */
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ } else {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) &&
+ (Timeout != HAL_MAX_DELAY)) ||
+ (Timeout == 0U)) {
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ } else {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U) {
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ } else {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) &&
+ (Timeout != HAL_MAX_DELAY)) ||
+ (Timeout == 0U)) {
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Handle the CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* freeze the CRC before the latest data */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+
+ /* Read the latest data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
+ tickstart) != HAL_OK) {
+ /* the latest data has not been received */
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+
+ /* Receive last data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else {
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait the CRC data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
+ tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+
+ /* Read CRC to Flush DR and RXNE flag */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) {
+ /* Read 16bit CRC */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ } else {
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) &&
+ (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
+ tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ return HAL_ERROR;
+ } else {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi,
+ const uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout) {
+ uint16_t initial_TxXferCount;
+ uint16_t initial_RxXferCount;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ uint32_t spi_cr1;
+ uint32_t spi_cr2;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+ initial_TxXferCount = Size;
+ initial_RxXferCount = Size;
+#if (USE_SPI_CRC != 0U)
+ spi_cr1 = READ_REG(hspi->Instance->CR1);
+ spi_cr2 = READ_REG(hspi->Instance->CR2);
+#endif /* USE_SPI_CRC */
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) &&
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX)))) {
+ return HAL_BUSY;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX) {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx Fifo threshold */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) {
+ /* Set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ } else {
+ /* Set fiforxthreshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) &&
+ (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS
+ * pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) &&
+ (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) {
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) &&
+ (hspi->TxXferCount > 0U) && (txallowed == 1U)) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) &&
+ (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS
+ * pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) &&
+ (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Check RXNE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) &&
+ (hspi->RxXferCount > 0U)) {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if (((HAL_GetTick() - tickstart) >= Timeout) &&
+ (Timeout != HAL_MAX_DELAY)) {
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) {
+ if (hspi->TxXferCount > 1U) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ } else {
+ *(__IO uint8_t *)&hspi->Instance->DR =
+ *((const uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) &&
+ (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS
+ * pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) &&
+ (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) {
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) &&
+ (hspi->TxXferCount > 0U) && (txallowed == 1U)) {
+ if (hspi->TxXferCount > 1U) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ } else {
+ *(__IO uint8_t *)&hspi->Instance->DR =
+ *((const uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) &&
+ (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS
+ * pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) &&
+ (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Wait until RXNE flag is reset */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) &&
+ (hspi->RxXferCount > 0U)) {
+ if (hspi->RxXferCount > 1U) {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount <= 1U) {
+ /* Set RX Fifo threshold before to switch on 8 bit data size */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ } else {
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr++;
+ hspi->RxXferCount--;
+ }
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if ((((HAL_GetTick() - tickstart) >= Timeout) &&
+ ((Timeout != HAL_MAX_DELAY))) ||
+ (Timeout == 0U)) {
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Read CRC from DR to close CRC calculation process */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Wait until TXE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
+ tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ /* Read CRC */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) {
+ /* Read 16bit CRC */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ } else {
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout,
+ tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
+ }
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ }
+ }
+
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ /* Clear CRC Flag */
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ return HAL_ERROR;
+ } else {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi,
+ const uint8_t *pData, uint16_t Size) {
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ if (hspi->State != HAL_SPI_STATE_READY) {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ } else {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData,
+ uint16_t Size) {
+ if (hspi->State != HAL_SPI_STATE_READY) {
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (hspi->Init.Mode == SPI_MODE_MASTER)) {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate
+ * clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
+
+ /* Check the data size to adapt Rx threshold and the set the function for IT
+ * treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ } else {
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) &&
+ (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) {
+ hspi->CRCSize = 2U;
+ }
+ SPI_RESET_CRC(hspi);
+ } else {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* Enable RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with
+ * Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi,
+ const uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size) {
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) &&
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX)))) {
+ return HAL_BUSY;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX) {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ } else {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) &&
+ (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) {
+ hspi->CRCSize = 2U;
+ }
+ SPI_RESET_CRC(hspi);
+ } else {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if packing mode is enabled and if there is more than 2 data to
+ * receive */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) {
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ } else {
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi,
+ const uint8_t *pData, uint16_t Size) {
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ if (hspi->State != HAL_SPI_STATE_READY) {
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ /* Packing mode is enabled only if the DMA setting is HALWORD */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) &&
+ (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) {
+ /* Check the even/odd of the data size + crc if enabled */
+ if ((hspi->TxXferCount & 0x1U) == 0U) {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U);
+ } else {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
+ }
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr,
+ (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount)) {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx
+ * shall be defined.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
+ uint16_t Size) {
+ /* Check rx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
+ if (hspi->State != HAL_SPI_STATE_READY) {
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (hspi->Init.Mode == SPI_MODE_MASTER)) {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate
+ * clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ } else {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U) {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ } else {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR,
+ (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount)) {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi,
+ const uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size) {
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+
+ /* Check rx & tx dma handles */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) &&
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX)))) {
+ return HAL_BUSY;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX) {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+ /* The packing mode management is enabled by the DMA settings according the
+ * spi data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ /* Set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ } else {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) {
+ if ((hspi->TxXferSize & 0x1U) == 0x0U) {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1U;
+ } else {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
+ }
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U) {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ } else {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer
+ * complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX) {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ } else {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR,
+ (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount)) {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
+ }
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the
+ communication closing is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr,
+ (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount)) {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx
+ * and Rx), started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
+ * in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function,
+ * Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) {
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort
+ * procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame
+ * error) interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no
+ * callback) */
+ if (hspi->hdmatx != NULL) {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort
+ procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
+ HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) {
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no
+ * callback) */
+ if (hspi->hdmarx != NULL) {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort
+ procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ } else {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx
+ * and Rx), started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
+ * transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort
+ * procedure could be considered as completed only when user abort complete
+ * callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) {
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort
+ * procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts
+ */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort
+ complete callbacks should be initialised before any call to DMA Abort
+ functions */
+ /* DMA Tx Handle is valid */
+ if (hspi->hdmatx != NULL) {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ } else {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hspi->hdmarx != NULL) {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ } else {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL) {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ } else {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) {
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL) {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ } else {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if (abortcplt == 1U) {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ } else {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ return errorcode;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) {
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) {
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) {
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or
+ HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): when calling
+ HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or
+ HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL) {
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL) {
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return errorcode;
+}
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) {
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) &&
+ (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) &&
+ (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) ||
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) ||
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) &&
+ (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) {
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) {
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ } else {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ return;
+ }
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) ||
+ (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL) {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort
+ procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL) {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort
+ procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ } else {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ }
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI
+ processes and user can use HAL_SPI_GetError() API to check the latest error
+ occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors
+functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of
+the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during
+communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) {
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) {
+ /* Return SPI ErrorCode */
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) !=
+ HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is
+ * not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+ /* Call user Tx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
+ HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Wait until RXNE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET,
+ SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
+ /* Read 16bit CRC */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ } else {
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET,
+ SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if we are in Master RX 2 line mode */
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (hspi->Init.Mode == SPI_MODE_MASTER)) {
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx
+ * direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ } else {
+ /* Normal case */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) &&
+ (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) {
+ if (SPI_WaitFifoStateUntilTimeout(
+ hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL,
+ SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ } else {
+ if (SPI_WaitFifoStateUntilTimeout(
+ hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK) {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) !=
+ HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Call user Tx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Call user Rx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Call user TxRx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services
+ * on Error (To be called at end of DMA Abort procedure following error
+ * occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort
+ * request).
+ * @note When this callback is executed, User Abort complete call back is
+ * called only if no Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
+ HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL) {
+ if (hspi->hdmarx->XferAbortCallback != NULL) {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call
+ * user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort
+ * request).
+ * @note When this callback is executed, User Abort complete call back is
+ * called only if no Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) {
+ SPI_HandleTypeDef *hspi =
+ (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL) {
+ if (hspi->hdmatx->XferAbortCallback != NULL) {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call
+ * user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
+ /* Receive data in packing mode */
+ if (hspi->RxXferCount > 1U) {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount == 1U) {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else {
+ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
+ hspi->RxXferCount--;
+ }
+
+ /* Check end of the reception */
+ if (hspi->RxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U) {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) {
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC to flush Data Register */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ hspi->CRCSize--;
+
+ /* Check end of the reception */
+ if (hspi->CRCSize == 0U) {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U) {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
+ /* Transmit data in packing Bit mode */
+ if (hspi->TxXferCount >= 2U) {
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ /* Transmit data in 8 Bit mode */
+ else {
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+
+ /* Check the end of the transmission */
+ if (hspi->TxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if (hspi->RxXferCount == 0U) {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
+ /* Receive data in 16 Bit mode */
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if (hspi->RxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if (hspi->TxXferCount == 0U) {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt
+ * mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) {
+ __IO uint32_t tmpreg = 0U;
+
+ /* Read 16bit CRC to flush Data Register */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if (hspi->TxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if (hspi->RxXferCount == 0U) {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) {
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC to flush Data Register */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ hspi->CRCSize--;
+
+ if (hspi->CRCSize == 0U) {
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
+ *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->RxXferCount == 1U) &&
+ (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) {
+ __IO uint32_t tmpreg = 0U;
+
+ /* Read 16bit CRC to flush Data Register */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->RxXferCount == 1U) &&
+ (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) {
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+
+ if (hspi->TxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) {
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if (hspi->TxXferCount == 0U) {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
+ uint32_t Flag,
+ FlagStatus State,
+ uint32_t Timeout,
+ uint32_t Tickstart) {
+ __IO uint32_t count;
+ uint32_t tmp_timeout;
+ uint32_t tmp_tickstart;
+
+ /* Adjust Timeout value in case of end of transfer */
+ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
+ tmp_tickstart = HAL_GetTick();
+
+ /* Calculate Timeout based on a software loop to avoid blocking issue if
+ * Systick is disabled */
+ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
+
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) {
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) ||
+ (tmp_timeout == 0U)) {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
+ ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ /* If Systick is disabled or not incremented, deactivate timeout to go in
+ * disable loop procedure */
+ if (count == 0U) {
+ tmp_timeout = 0U;
+ }
+ count--;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
+ uint32_t Fifo,
+ uint32_t State,
+ uint32_t Timeout,
+ uint32_t Tickstart) {
+ __IO uint32_t count;
+ uint32_t tmp_timeout;
+ uint32_t tmp_tickstart;
+ __IO const uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+
+ /* Adjust Timeout value in case of end of transfer */
+ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
+ tmp_tickstart = HAL_GetTick();
+
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+
+ /* Calculate Timeout based on a software loop to avoid blocking issue if
+ * Systick is disabled */
+ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
+
+ while ((hspi->Instance->SR & Fifo) != State) {
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) {
+ /* Flush Data Register by a blank read */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) ||
+ (tmp_timeout == 0U)) {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
+ ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ /* If Systick is disabled or not incremented, deactivate timeout to go in
+ * disable loop procedure */
+ if (count == 0U) {
+ tmp_timeout = 0U;
+ }
+ count--;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RX transaction complete.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,
+ uint32_t Timeout,
+ uint32_t Tickstart) {
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
+ ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout,
+ Tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) &&
+ ((hspi->Init.Direction == SPI_DIRECTION_1LINE) ||
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) {
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ Timeout, Tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi,
+ uint32_t Timeout,
+ uint32_t Tickstart) {
+ /* Control if the TX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY,
+ Timeout, Tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout,
+ Tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Control if the RX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ Timeout, Tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) {
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) {
+ hspi->State = HAL_SPI_STATE_READY;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ } else {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) {
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX) {
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ } else {
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ } else {
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the RX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
+ HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ } else {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) {
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ } else {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the TX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) {
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not
+ * read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ } else {
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
+ HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Handle abort a Rx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) {
+ __IO uint32_t count;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @brief Handle abort a Tx or Rx/Tx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) {
+ __IO uint32_t count;
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
+
+ /* Check TXEIE is disabled */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) !=
+ HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) {
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do {
+ if (count == 0U) {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY,
+ SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK) {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c
index dce9f5d..5e6fa69 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c
@@ -1,109 +1,109 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_spi_ex.c
- * @author MCD Application Team
- * @brief Extended SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * SPI peripheral extended functionalities :
- * + IO operation functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPIEx SPIEx
- * @brief SPI Extended HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
- * @{
- */
-#define SPI_FIFO_SIZE 4UL
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
- * @{
- */
-
-/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of extended functions to manage the SPI
- data transfers.
-
- (#) Rx data flush function:
- (++) HAL_SPIEx_FlushRxFifo()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Flush the RX fifo.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) {
- __IO uint32_t tmpreg;
- uint8_t count = 0U;
- while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) {
- count++;
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
- if (count == SPI_FIFO_SIZE) {
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+ * @{
+ */
+#define SPI_FIFO_SIZE 4UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) Rx data flush function:
+ (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) {
+ __IO uint32_t tmpreg;
+ uint8_t count = 0U;
+ while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+ if (count == SPI_FIFO_SIZE) {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c
index 90184da..01a804d 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c
@@ -1,7661 +1,7682 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_tim.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer (TIM) peripheral:
- * + TIM Time Base Initialization
- * + TIM Time Base Start
- * + TIM Time Base Start Interruption
- * + TIM Time Base Start DMA
- * + TIM Output Compare/PWM Initialization
- * + TIM Output Compare/PWM Channel Configuration
- * + TIM Output Compare/PWM Start
- * + TIM Output Compare/PWM Start Interruption
- * + TIM Output Compare/PWM Start DMA
- * + TIM Input Capture Initialization
- * + TIM Input Capture Channel Configuration
- * + TIM Input Capture Start
- * + TIM Input Capture Start Interruption
- * + TIM Input Capture Start DMA
- * + TIM One Pulse Initialization
- * + TIM One Pulse Channel Configuration
- * + TIM One Pulse Start
- * + TIM Encoder Interface Initialization
- * + TIM Encoder Interface Start
- * + TIM Encoder Interface Start Interruption
- * + TIM Encoder Interface Start DMA
- * + Commutation Event configuration with Interruption and DMA
- * + TIM OCRef clear configuration
- * + TIM External Clock configuration
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### TIMER Generic features #####
- ==============================================================================
- [..] The Timer features include:
- (#) 16-bit up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
- counter clock frequency either by any factor between 1 and 65536.
- (#) Up to 4 independent channels for:
- (++) Input Capture
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals
-and to interconnect several timers together.
- (#) Supports incremental encoder for positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following
-functions depending on the selected feature:
- (++) Time Base : HAL_TIM_Base_MspInit()
- (++) Input Capture : HAL_TIM_IC_MspInit()
- (++) Output Compare : HAL_TIM_OC_MspInit()
- (++) PWM generation : HAL_TIM_PWM_MspInit()
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following
-function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using
-HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is
-the internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done
-before any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- Initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally
-HAL_TIMEx_OC_ConfigPulseOnCompare: to use the Timer to generate an Output
-Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to
-generate a PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to
-measure an external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the
-Timer in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
- (#) Activate the TIM peripheral using one of the start functions depending
-from the feature used:
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(),
-HAL_TIM_Base_Start_IT()
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(),
-HAL_TIM_IC_Start_IT()
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(),
-HAL_TIM_OC_Start_IT()
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(),
-HAL_TIM_PWM_Start_IT()
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(),
-HAL_TIM_OnePulse_Start_IT()
- (++) Encoder mode output : HAL_TIM_Encoder_Start(),
-HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
- (#) The DMA Burst is managed with the two following functions:
- HAL_TIM_DMABurst_WriteStart()
- HAL_TIM_DMABurst_ReadStart()
-
- *** Callback registration ***
- =============================================
-
- [..]
- The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- [..]
- Use Function HAL_TIM_RegisterCallback() to register a callback.
- HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
- the Callback ID and a pointer to the user callback function.
-
- [..]
- Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
- weak function.
- HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
-
- [..]
- These functions allow to register/unregister following callbacks:
- (+) Base_MspInitCallback : TIM Base Msp Init Callback.
- (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
- (+) IC_MspInitCallback : TIM IC Msp Init Callback.
- (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
- (+) OC_MspInitCallback : TIM OC Msp Init Callback.
- (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
- (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
- (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
- (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
- (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
- (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
- (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
- (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
- (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
- (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
- (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete
-Callback.
- (+) TriggerCallback : TIM Trigger Callback.
- (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
- (+) IC_CaptureCallback : TIM Input Capture Callback.
- (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete
-Callback.
- (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed
-Callback.
- (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
- (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete
-Callback.
- (+) ErrorCallback : TIM Error Callback.
- (+) CommutationCallback : TIM Commutation Callback.
- (+) CommutationHalfCpltCallback : TIM Commutation half complete
-Callback.
- (+) BreakCallback : TIM Break Callback.
- (+) Break2Callback : TIM Break2 Callback.
- (+) EncoderIndexCallback : TIM Encoder Index Callback.
- (+) DirectionChangeCallback : TIM Direction Change Callback
- (+) IndexErrorCallback : TIM Index Error Callback.
- (+) TransitionErrorCallback : TIM Transition Error Callback
-
- [..]
-By default, after the Init and when the state is HAL_TIM_STATE_RESET
-all interrupt callbacks are set to the corresponding weak functions:
- examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
-
- [..]
- Exception done for MspInit and MspDeInit functions that are reset to the
-legacy weak functionalities in the Init / DeInit only when these callbacks are
-null (not registered beforehand). If not, MspInit or MspDeInit are not null, the
-Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered
-beforehand)
-
- [..]
- Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state
-only. Exception done MspInit / MspDeInit that can be registered / unregistered
- in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
- thus registered(user) MspInit / DeInit callbacks can be used during the Init
-/ DeInit. In that case first register the MspInit/MspDeInit user callbacks using
-HAL_TIM_RegisterCallback() before calling DeInit or Init function.
-
- [..]
- When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all
-callbacks are set to the corresponding weak functions.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIM TIM
- * @brief TIM HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup TIM_Private_Constants
- * @{
- */
-#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(
- TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- *
-@verbatim
- ==============================================================================
- ##### Time Base functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
- (+) De-initialize the TIM base.
- (+) Start the Time Base.
- (+) Stop the Time Base.
- (+) Start the Time Base and enable interrupt.
- (+) Stop the Time Base and disable interrupt.
- (+) Start the Time Base and enable DMA transfer.
- (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated
- * handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode. Ex: call @ref HAL_TIM_Base_DeInit() before
- * HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) {
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->Base_MspInitCallback == NULL) {
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Base peripheral
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->Base_MspDeInitCallback == NULL) {
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->Base_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Base MSP.
- * @param htim TIM Base handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Base MSP.
- * @param htim TIM Base handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Base generation.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Check the TIM state */
- if (htim->State != HAL_TIM_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Check the TIM state */
- if (htim->State != HAL_TIM_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in DMA mode.
- * @param htim TIM Base handle
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to
- * peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t *pData, uint16_t Length) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- if (htim->State == HAL_TIM_STATE_BUSY) {
- return HAL_BUSY;
- } else if (htim->State == HAL_TIM_STATE_READY) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- } else {
- return HAL_ERROR;
- }
-
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback =
- TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData,
- (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Update DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in DMA mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
- (+) De-initialize the TIM Output Compare.
- (+) Start the TIM Output Compare.
- (+) Stop the TIM Output Compare.
- (+) Start the TIM Output Compare and enable interrupt.
- (+) Stop the TIM Output Compare and disable interrupt.
- (+) Start the TIM Output Compare and enable DMA transfer.
- (+) Stop the TIM Output Compare and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated
- * handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode. Ex: call @ref HAL_TIM_OC_DeInit() before
- * HAL_TIM_OC_Init()
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) {
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->OC_MspInitCallback == NULL) {
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OC_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->OC_MspDeInitCallback == NULL) {
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->OC_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare MSP.
- * @param htim TIM Output Compare handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Output Compare MSP.
- * @param htim TIM Output Compare handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM
- * peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
- return HAL_BUSY;
- } else if (TIM_CHANNEL_STATE_GET(htim, Channel) ==
- HAL_TIM_CHANNEL_STATE_READY) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- *
-@verbatim
- ==============================================================================
- ##### TIM PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM PWM.
- (+) De-initialize the TIM PWM.
- (+) Start the TIM PWM.
- (+) Stop the TIM PWM.
- (+) Start the TIM PWM and enable interrupt.
- (+) Stop the TIM PWM and disable interrupt.
- (+) Start the TIM PWM and enable DMA transfer.
- (+) Stop the TIM PWM and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated
- * handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode. Ex: call @ref HAL_TIM_PWM_DeInit() before
- * HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) {
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->PWM_MspInitCallback == NULL) {
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->PWM_MspDeInitCallback == NULL) {
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->PWM_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the PWM signal generation.
- * @param htim TIM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM
- * peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
- return HAL_BUSY;
- } else if (TIM_CHANNEL_STATE_GET(htim, Channel) ==
- HAL_TIM_CHANNEL_STATE_READY) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Capture/Compare 3 request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Input Capture functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
- (+) De-initialize the TIM Input Capture.
- (+) Start the TIM Input Capture.
- (+) Stop the TIM Input Capture.
- (+) Start the TIM Input Capture and enable interrupt.
- (+) Stop the TIM Input Capture and disable interrupt.
- (+) Start the TIM Input Capture and enable DMA transfer.
- (+) Stop the TIM Input Capture and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Input Capture Time base according to the
- * specified parameters in the TIM_HandleTypeDef and initializes the associated
- * handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode. Ex: call @ref HAL_TIM_IC_DeInit() before
- * HAL_TIM_IC_Init()
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) {
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->IC_MspInitCallback == NULL) {
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->IC_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->IC_MspDeInitCallback == NULL) {
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->IC_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture MSP.
- * @param htim TIM Input Capture handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Input Capture MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_state =
- TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state =
- TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- HAL_TIM_ChannelStateTypeDef channel_state =
- TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state =
- TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to
- * memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- HAL_TIM_ChannelStateTypeDef channel_state =
- TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state =
- TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Set the TIM channel state */
- if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
- return HAL_BUSY;
- } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
- (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
- (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3],
- (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4],
- (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### TIM One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
- (+) De-initialize the TIM One Pulse.
- (+) Start the TIM One Pulse.
- (+) Stop the TIM One Pulse.
- (+) Start the TIM One Pulse and enable interrupt.
- (+) Stop the TIM One Pulse and disable interrupt.
- (+) Start the TIM One Pulse and enable DMA transfer.
- (+) Stop the TIM One Pulse and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated
- * handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode. Ex: call @ref HAL_TIM_OnePulse_DeInit()
- * before HAL_TIM_OnePulse_Init()
- * @note When the timer instance is initialized in One Pulse mode, timer
- * channels 1 and channel 2 are reserved and cannot be used for other
- * purpose.
- * @param htim TIM One Pulse handle
- * @param OnePulseMode Select the One pulse mode.
- * This parameter can be one of the following values:
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim,
- uint32_t OnePulseMode) {
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->OnePulse_MspInitCallback == NULL) {
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OnePulse_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OnePulse_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the One Pulse Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Reset the OPM Bit */
- htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- htim->Instance->CR1 |= OnePulseMode;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM One Pulse
- * @param htim TIM One Pulse handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->OnePulse_MspDeInitCallback == NULL) {
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->OnePulse_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_OnePulse_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse MSP.
- * @param htim TIM One Pulse handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM One Pulse MSP.
- * @param htim TIM One Pulse handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation.
- * @note Though OutputChannel parameter is deprecated and ignored by the
- * function it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are
- TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the
- TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input,
- the TIM_CHANNEL_2 will be used as output whatever the combination, the
- TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation.
- * @note Though OutputChannel parameter is deprecated and ignored by the
- * function it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1
- and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will
- be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will
- be used as output whatever the combination, the TIM_CHANNEL_1 and
- TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @note Though OutputChannel parameter is deprecated and ignored by the
- * function it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are
- TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the
- TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input,
- the TIM_CHANNEL_2 will be used as output whatever the combination, the
- TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @note Though OutputChannel parameter is deprecated and ignored by the
- * function it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1
- and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will
- be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will
- be used as output whatever the combination, the TIM_CHANNEL_1 and
- TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Encoder functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
- (+) De-initialize the TIM Encoder.
- (+) Start the TIM Encoder.
- (+) Stop the TIM Encoder.
- (+) Start the TIM Encoder and enable interrupt.
- (+) Stop the TIM Encoder and disable interrupt.
- (+) Start the TIM Encoder and enable DMA transfer.
- (+) Stop the TIM Encoder and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Encoder Interface and initialize the associated
- * handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or
- * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
- * readonly in center aligned mode. Ex: call @ref HAL_TIM_Encoder_DeInit()
- * before HAL_TIM_Encoder_Init()
- * @note Encoder mode and External clock mode 2 are not compatible and must
- * not be selected together Ex: A call for @ref HAL_TIM_Encoder_Init will erase
- * the settings of @ref HAL_TIM_ConfigClockSource using TIM_CLOCKSOURCE_ETRMODE2
- * and vice versa
- * @note When the timer instance is initialized in Encoder mode, timer
- * channels 1 and channel 2 are reserved and cannot be used for other
- * purpose.
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,
- TIM_Encoder_InitTypeDef *sConfig) {
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->Encoder_MspInitCallback == NULL) {
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters
- */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Encoder interface
- * @param htim TIM Encoder Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->Encoder_MspDeInitCallback == NULL) {
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->Encoder_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Encoder_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Encoder Interface MSP.
- * @param htim TIM Encoder Interface handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim TIM Encoder Interface handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1) {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else if (Channel == TIM_CHANNEL_2) {
- if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
-
- /* Enable the encoder interface channels */
- switch (Channel) {
- case TIM_CHANNEL_1: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
-
- case TIM_CHANNEL_2: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
-
- default: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are
- TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- switch (Channel) {
- case TIM_CHANNEL_1: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
-
- case TIM_CHANNEL_2: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
-
- default: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1) {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else if (Channel == TIM_CHANNEL_2) {
- if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
-
- /* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2 */
- switch (Channel) {
- case TIM_CHANNEL_1: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- default: {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are
- TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if (Channel == TIM_CHANNEL_1) {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- } else if (Channel == TIM_CHANNEL_2) {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- } else {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 and 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1 The destination Buffer address for IC1.
- * @param pData2 The destination Buffer address for IC2.
- * @param Length The length of data to be transferred from TIM peripheral to
- * memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length) {
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1) {
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
- return HAL_BUSY;
- } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) {
- if ((pData1 == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1,
- HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
- } else if (Channel == TIM_CHANNEL_2) {
- if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
- return HAL_BUSY;
- } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) {
- if ((pData2 == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2,
- HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
- } else {
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
- return HAL_BUSY;
- } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) {
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1,
- HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2,
- HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
- }
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
- (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
- (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- break;
- }
-
- default: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
- (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
- (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- break;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are
- TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if (Channel == TIM_CHANNEL_1) {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- } else if (Channel == TIM_CHANNEL_2) {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- } else {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 and 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief TIM IRQ handler management
- *
-@verbatim
- ==============================================================================
- ##### IRQ handler management #####
- ==============================================================================
- [..]
- This section provides Timer IRQ handler function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) {
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Encoder index event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->EncoderIndexCallback(htim);
-#else
- HAL_TIMEx_EncoderIndexCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Direction change event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->DirectionChangeCallback(htim);
-#else
- HAL_TIMEx_DirectionChangeCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Index error event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IndexErrorCallback(htim);
-#else
- HAL_TIMEx_IndexErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Transition error event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET) {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET) {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TransitionErrorCallback(htim);
-#else
- HAL_TIMEx_TransitionErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief TIM Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the
- * specified parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM Output Compare handle
- * @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_5: {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 5 in Output Compare */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_6: {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 6 in Output Compare */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Initializes the TIM Input Capture Channels according to the specified
- * parameters in the TIM_IC_InitTypeDef.
- * @param htim TIM IC handle
- * @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_IC_InitTypeDef *sConfig,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- if (Channel == TIM_CHANNEL_1) {
- /* TI1 Configuration */
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;
- } else if (Channel == TIM_CHANNEL_2) {
- /* TI2 Configuration */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
- } else if (Channel == TIM_CHANNEL_3) {
- /* TI3 Configuration */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC3PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;
- } else if (Channel == TIM_CHANNEL_4) {
- /* TI4 Configuration */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC4PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
- } else {
- status = HAL_ERROR;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM PWM handle
- * @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be configured
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- case TIM_CHANNEL_5: {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_6: {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 6 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Initializes the TIM One Pulse Channels according to the specified
- * parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim TIM One Pulse handle
- * @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM output channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM input Channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @note To output a waveform with a minimum delay user can enable the fast
- * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
- * output is forced in response to the edge detection on TIx input,
- * without taking in account the comparison.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(
- TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel) {
- HAL_StatusTypeDef status = HAL_OK;
- TIM_OC_InitTypeDef temp1;
-
- /* Check the parameters */
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
- if (OutputChannel != InputChannel) {
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Extract the Output compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
- switch (OutputChannel) {
- case TIM_CHANNEL_1: {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_OC2_SetConfig(htim->Instance, &temp1);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- switch (InputChannel) {
- case TIM_CHANNEL_1: {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- case TIM_CHANNEL_2: {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return status;
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM
- * peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the
- * Data write This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_DTR2
- * @arg TIM_DMABASE_ECR
- * @arg TIM_DMABASE_TISEL
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
- * @arg TIM_DMABASE_OR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and
- * TIM_DMABURSTLENGTH_26TRANSFER.
- * @note This function should be used only when BurstLength is equal to DMA
- * data transfer length.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength) {
- HAL_StatusTypeDef status;
-
- status = HAL_TIM_DMABurst_MultiWriteStart(
- htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
-
- return status;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer multiple Data from the memory to
- * the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the
- * Data write This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_DTR2
- * @arg TIM_DMABASE_ECR
- * @arg TIM_DMABASE_TISEL
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
- * @arg TIM_DMABASE_OR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and
- * TIM_DMABURSTLENGTH_26TRANSFER.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength,
- uint32_t DataLength) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) {
- return HAL_BUSY;
- } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) {
- if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
- return HAL_ERROR;
- } else {
- htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
- }
- } else {
- /* nothing to do */
- }
-
- switch (BurstRequestSrc) {
- case TIM_DMA_UPDATE: {
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback =
- TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback =
- TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR,
- DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC1: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR,
- DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC2: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR,
- DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC3: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR,
- DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC4: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR,
- DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_COM: {
- /* Set the DMA commutation callbacks */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =
- TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =
- TIMEx_DMACommutationHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(
- htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_TRIGGER: {
- /* Set the DMA trigger callbacks */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback =
- TIM_DMATriggerHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(
- htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM DMA Burst mode
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim,
- uint32_t BurstRequestSrc) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch (BurstRequestSrc) {
- case TIM_DMA_UPDATE: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
- break;
- }
- case TIM_DMA_CC1: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
- case TIM_DMA_CC2: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
- case TIM_DMA_CC3: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
- case TIM_DMA_CC4: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
- case TIM_DMA_COM: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- break;
- }
- case TIM_DMA_TRIGGER: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to
- * the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the
- * Data read This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_DTR2
- * @arg TIM_DMABASE_ECR
- * @arg TIM_DMABASE_TISEL
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
- * @arg TIM_DMABASE_OR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and
- * TIM_DMABURSTLENGTH_26TRANSFER.
- * @note This function should be used only when BurstLength is equal to DMA
- * data transfer length.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength) {
- HAL_StatusTypeDef status;
-
- status = HAL_TIM_DMABurst_MultiReadStart(
- htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
-
- return status;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to
- * the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the
- * Data read This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_DTR2
- * @arg TIM_DMABASE_ECR
- * @arg TIM_DMABASE_TISEL
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
- * @arg TIM_DMABASE_OR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and
- * TIM_DMABURSTLENGTH_26TRANSFER.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim,
- uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer,
- uint32_t BurstLength,
- uint32_t DataLength) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) {
- return HAL_BUSY;
- } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) {
- if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
- return HAL_ERROR;
- } else {
- htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
- }
- } else {
- /* nothing to do */
- }
- switch (BurstRequestSrc) {
- case TIM_DMA_UPDATE: {
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback =
- TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback =
- TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC1: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC2: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC3: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC4: {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_COM: {
- /* Set the DMA commutation callbacks */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =
- TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =
- TIMEx_DMACommutationHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_TRIGGER: {
- /* Set the DMA trigger callbacks */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback =
- TIM_DMATriggerHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER],
- (uint32_t)&htim->Instance->DMAR,
- (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stop the DMA burst reading
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim,
- uint32_t BurstRequestSrc) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch (BurstRequestSrc) {
- case TIM_DMA_UPDATE: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
- break;
- }
- case TIM_DMA_CC1: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
- case TIM_DMA_CC2: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
- case TIM_DMA_CC3: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
- case TIM_DMA_CC4: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
- case TIM_DMA_COM: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- break;
- }
- case TIM_DMA_TRIGGER: {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Generate a software event
- * @param htim TIM handle
- * @param EventSource specifies the event source.
- * This parameter can be one of the following values:
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
- * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source
- * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
- * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
- * @note Basic timers can only generate an update event.
- * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
- * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
- * only for timer instances supporting break input(s).
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim,
- uint32_t EventSource) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the event sources */
- htim->Instance->EGR = EventSource;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure
- * that contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5
- * @arg TIM_CHANNEL_6: TIM Channel 6
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(
- TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (sClearInputConfig->ClearInputSource) {
- case TIM_CLEARINPUTSOURCE_NONE: {
- /* Clear the OCREF clear selection bit and the the ETR Bits */
- if (IS_TIM_OCCS_INSTANCE(htim->Instance)) {
- CLEAR_BIT(htim->Instance->SMCR,
- (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE |
- TIM_SMCR_ETP));
-
- /* Clear TIMx_AF2_OCRSEL (reset value) */
- CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
- } else {
- CLEAR_BIT(htim->Instance->SMCR,
- (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
- }
- break;
- }
-
- case TIM_CLEARINPUTSOURCE_COMP1:
- case TIM_CLEARINPUTSOURCE_COMP2:
- case TIM_CLEARINPUTSOURCE_COMP3:
- case TIM_CLEARINPUTSOURCE_COMP4:
-#if defined(COMP5)
- case TIM_CLEARINPUTSOURCE_COMP5:
-#endif /* COMP5 */
-#if defined(COMP6)
- case TIM_CLEARINPUTSOURCE_COMP6:
-#endif /* COMP6 */
-#if defined(COMP7)
- case TIM_CLEARINPUTSOURCE_COMP7:
-#endif /* COMP7 */
- {
- if (IS_TIM_OCCS_INSTANCE(htim->Instance)) {
- /* Clear the OCREF clear selection bit */
- CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-
- /* Clear TIM1_AF2_OCRSEL (reset value) */
- MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL,
- sClearInputConfig->ClearInputSource);
- }
- break;
- }
-
- case TIM_CLEARINPUTSOURCE_ETR: {
- /* Check the parameters */
- assert_param(
- IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(
- IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(
- IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- /* When OCRef clear feature is used with ETR source, ETR prescaler must be
- * off */
- if (sClearInputConfig->ClearInputPrescaler !=
- TIM_CLEARINPUTPRESCALER_DIV1) {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
-
- if (IS_TIM_OCCS_INSTANCE(htim->Instance)) {
- /* Set the OCREF clear selection bit */
- SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-
- /* Clear TIMx_AF2_OCRSEL (reset value) */
- CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
- }
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- switch (Channel) {
- case TIM_CHANNEL_1: {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
- /* Enable the OCREF clear feature for Channel 1 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
- } else {
- /* Disable the OCREF clear feature for Channel 1 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
- }
- break;
- }
- case TIM_CHANNEL_2: {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
- /* Enable the OCREF clear feature for Channel 2 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- } else {
- /* Disable the OCREF clear feature for Channel 2 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- break;
- }
- case TIM_CHANNEL_3: {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
- /* Enable the OCREF clear feature for Channel 3 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- } else {
- /* Disable the OCREF clear feature for Channel 3 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- break;
- }
- case TIM_CHANNEL_4: {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
- /* Enable the OCREF clear feature for Channel 4 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- } else {
- /* Disable the OCREF clear feature for Channel 4 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- break;
- }
- case TIM_CHANNEL_5: {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
- /* Enable the OCREF clear feature for Channel 5 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- } else {
- /* Disable the OCREF clear feature for Channel 5 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- break;
- }
- case TIM_CHANNEL_6: {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
- /* Enable the OCREF clear feature for Channel 6 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- } else {
- /* Disable the OCREF clear feature for Channel 6 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- break;
- }
- default:
- break;
- }
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Configures the clock source to be used
- * @param htim TIM handle
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(
- TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- htim->Instance->SMCR = tmpsmcr;
-
- switch (sClockSourceConfig->ClockSource) {
- case TIM_CLOCKSOURCE_INTERNAL: {
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- break;
- }
-
- case TIM_CLOCKSOURCE_ETRMODE1: {
- /* Check whether or not the timer instance supports external trigger input
- * mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
-
- /* Select the External clock mode1 and the ETRF trigger */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- break;
- }
-
- case TIM_CLOCKSOURCE_ETRMODE2: {
- /* Check whether or not the timer instance supports external trigger input
- * mode 2 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Enable the External clock mode2 */
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- break;
- }
-
- case TIM_CLOCKSOURCE_TI1: {
- /* Check whether or not the timer instance supports external clock mode 1
- */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- break;
- }
-
- case TIM_CLOCKSOURCE_TI2: {
- /* Check whether or not the timer instance supports external clock mode 1
- * (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI2 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- break;
- }
-
- case TIM_CLOCKSOURCE_TI1ED: {
- /* Check whether or not the timer instance supports external clock mode 1
- */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- break;
- }
-
- case TIM_CLOCKSOURCE_ITR0:
- case TIM_CLOCKSOURCE_ITR1:
- case TIM_CLOCKSOURCE_ITR2:
- case TIM_CLOCKSOURCE_ITR3:
-#if defined(TIM5)
- case TIM_CLOCKSOURCE_ITR4:
-#endif /* TIM5 */
- case TIM_CLOCKSOURCE_ITR5:
- case TIM_CLOCKSOURCE_ITR6:
- case TIM_CLOCKSOURCE_ITR7:
- case TIM_CLOCKSOURCE_ITR8:
-#if defined(TIM20)
- case TIM_CLOCKSOURCE_ITR9:
-#endif /* TIM20 */
-#if defined(HRTIM1)
- case TIM_CLOCKSOURCE_ITR10:
-#endif /* HRTIM1 */
- case TIM_CLOCKSOURCE_ITR11: {
- /* Check whether or not the timer instance supports internal trigger input
- */
- assert_param(IS_TIM_CLOCKSOURCE_INSTANCE(
- (htim->Instance), sClockSourceConfig->ClockSource));
-
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input
- * or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim TIM handle.
- * @param TI1_Selection Indicate whether or not channel 1 is connected to the
- * output of a XOR gate.
- * This parameter can be one of the following values:
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1
- * input
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
- * pins are connected to the TI1 input (XOR combination)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim,
- uint32_t TI1_Selection) {
- uint32_t tmpcr2;
-
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Reset the TI1 selection */
- tmpcr2 &= ~TIM_CR2_TI1S;
-
- /* Set the TI1 selection */
- tmpcr2 |= TI1_Selection;
-
- /* Write to TIMxCR2 */
- htim->Instance->CR2 = tmpcr2;
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset +
- * Trigger, Gated + Reset).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(
- TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) {
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(
- IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- /* Disable Trigger Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset +
- * Trigger, Gated + Reset).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(
- TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) {
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(
- IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- /* Enable Trigger Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim TIM handle.
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) {
- uint32_t tmpreg = 0U;
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2: {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) TIM Period elapsed callback
- (+) TIM Output Compare callback
- (+) TIM Input capture callback
- (+) TIM Trigger callback
- (+) TIM Error callback
- (+) TIM Index callback
- (+) TIM Direction change callback
- (+) TIM Index error callback
- (+) TIM Transition error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PeriodElapsedCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Period elapsed half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in
- the user file
- */
-}
-
-/**
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Input Capture half complete callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief PWM Pulse finished half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented
- in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Timer error callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User TIM callback to be used instead of the weak
- * predefined callback
- * @param htim tim handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
- * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback
- * ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit
- * Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback
- * ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit
- * Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit
- * Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half
- * complete Callback ID
- * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback
- * ID
- * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete
- * Callback ID
- * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay
- * Elapsed Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished
- * Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished
- * half complete Callback ID
- * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete
- * Callback ID
- * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
- * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
- * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback
- * ID
- * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
- * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback
- * ID
- * @param pCallback pointer to the callback function
- * @retval status
- */
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim,
- HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(htim);
-
- if (htim->State == HAL_TIM_STATE_READY) {
- switch (CallbackID) {
- case HAL_TIM_BASE_MSPINIT_CB_ID:
- htim->Base_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID:
- htim->Base_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID:
- htim->IC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID:
- htim->IC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID:
- htim->OC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID:
- htim->OC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID:
- htim->PWM_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID:
- htim->PWM_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
- htim->OnePulse_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID:
- htim->Encoder_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
- htim->HallSensor_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_CB_ID:
- htim->PeriodElapsedCallback = pCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID:
- htim->PeriodElapsedHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_TRIGGER_CB_ID:
- htim->TriggerCallback = pCallback;
- break;
-
- case HAL_TIM_TRIGGER_HALF_CB_ID:
- htim->TriggerHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_CB_ID:
- htim->IC_CaptureCallback = pCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_HALF_CB_ID:
- htim->IC_CaptureHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID:
- htim->OC_DelayElapsedCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID:
- htim->PWM_PulseFinishedCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID:
- htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_ERROR_CB_ID:
- htim->ErrorCallback = pCallback;
- break;
-
- case HAL_TIM_COMMUTATION_CB_ID:
- htim->CommutationCallback = pCallback;
- break;
-
- case HAL_TIM_COMMUTATION_HALF_CB_ID:
- htim->CommutationHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_BREAK_CB_ID:
- htim->BreakCallback = pCallback;
- break;
-
- case HAL_TIM_BREAK2_CB_ID:
- htim->Break2Callback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_INDEX_CB_ID:
- htim->EncoderIndexCallback = pCallback;
- break;
-
- case HAL_TIM_DIRECTION_CHANGE_CB_ID:
- htim->DirectionChangeCallback = pCallback;
- break;
-
- case HAL_TIM_INDEX_ERROR_CB_ID:
- htim->IndexErrorCallback = pCallback;
- break;
-
- case HAL_TIM_TRANSITION_ERROR_CB_ID:
- htim->TransitionErrorCallback = pCallback;
- break;
-
- default:
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (htim->State == HAL_TIM_STATE_RESET) {
- switch (CallbackID) {
- case HAL_TIM_BASE_MSPINIT_CB_ID:
- htim->Base_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID:
- htim->Base_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID:
- htim->IC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID:
- htim->IC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID:
- htim->OC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID:
- htim->OC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID:
- htim->PWM_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID:
- htim->PWM_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
- htim->OnePulse_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID:
- htim->Encoder_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
- htim->HallSensor_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
-
- default:
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Unregister a TIM callback
- * TIM callback is redirected to the weak predefined callback
- * @param htim tim handle
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
- * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback
- * ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit
- * Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback
- * ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit
- * Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit
- * Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half
- * complete Callback ID
- * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback
- * ID
- * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete
- * Callback ID
- * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay
- * Elapsed Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished
- * Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished
- * half complete Callback ID
- * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete
- * Callback ID
- * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
- * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
- * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback
- * ID
- * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
- * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback
- * ID
- * @retval status
- */
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(
- TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(htim);
-
- if (htim->State == HAL_TIM_STATE_READY) {
- switch (CallbackID) {
- case HAL_TIM_BASE_MSPINIT_CB_ID:
- /* Legacy weak Base MspInit Callback */
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID:
- /* Legacy weak Base Msp DeInit Callback */
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID:
- /* Legacy weak IC Msp Init Callback */
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID:
- /* Legacy weak IC Msp DeInit Callback */
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID:
- /* Legacy weak OC Msp Init Callback */
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID:
- /* Legacy weak OC Msp DeInit Callback */
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID:
- /* Legacy weak PWM Msp Init Callback */
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID:
- /* Legacy weak PWM Msp DeInit Callback */
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
- /* Legacy weak One Pulse Msp Init Callback */
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
- /* Legacy weak One Pulse Msp DeInit Callback */
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID:
- /* Legacy weak Encoder Msp Init Callback */
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
- /* Legacy weak Encoder Msp DeInit Callback */
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
- /* Legacy weak Hall Sensor Msp Init Callback */
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
- /* Legacy weak Hall Sensor Msp DeInit Callback */
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_CB_ID:
- /* Legacy weak Period Elapsed Callback */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID:
- /* Legacy weak Period Elapsed half complete Callback */
- htim->PeriodElapsedHalfCpltCallback =
- HAL_TIM_PeriodElapsedHalfCpltCallback;
- break;
-
- case HAL_TIM_TRIGGER_CB_ID:
- /* Legacy weak Trigger Callback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback;
- break;
-
- case HAL_TIM_TRIGGER_HALF_CB_ID:
- /* Legacy weak Trigger half complete Callback */
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_CB_ID:
- /* Legacy weak IC Capture Callback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_HALF_CB_ID:
- /* Legacy weak IC Capture half complete Callback */
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
- break;
-
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID:
- /* Legacy weak OC Delay Elapsed Callback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID:
- /* Legacy weak PWM Pulse Finished Callback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID:
- /* Legacy weak PWM Pulse Finished half complete Callback */
- htim->PWM_PulseFinishedHalfCpltCallback =
- HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
- break;
-
- case HAL_TIM_ERROR_CB_ID:
- /* Legacy weak Error Callback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback;
- break;
-
- case HAL_TIM_COMMUTATION_CB_ID:
- /* Legacy weak Commutation Callback */
- htim->CommutationCallback = HAL_TIMEx_CommutCallback;
- break;
-
- case HAL_TIM_COMMUTATION_HALF_CB_ID:
- /* Legacy weak Commutation half complete Callback */
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
- break;
-
- case HAL_TIM_BREAK_CB_ID:
- /* Legacy weak Break Callback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback;
- break;
-
- case HAL_TIM_BREAK2_CB_ID:
- /* Legacy weak Break2 Callback */
- htim->Break2Callback = HAL_TIMEx_Break2Callback;
- break;
-
- case HAL_TIM_ENCODER_INDEX_CB_ID:
- /* Legacy weak Encoder Index Callback */
- htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
- break;
-
- case HAL_TIM_DIRECTION_CHANGE_CB_ID:
- /* Legacy weak Direction Change Callback */
- htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
- break;
-
- case HAL_TIM_INDEX_ERROR_CB_ID:
- /* Legacy weak Index Error Callback */
- htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
- break;
-
- case HAL_TIM_TRANSITION_ERROR_CB_ID:
- /* Legacy weak Transition Error Callback */
- htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
- break;
-
- default:
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else if (htim->State == HAL_TIM_STATE_RESET) {
- switch (CallbackID) {
- case HAL_TIM_BASE_MSPINIT_CB_ID:
- /* Legacy weak Base MspInit Callback */
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID:
- /* Legacy weak Base Msp DeInit Callback */
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID:
- /* Legacy weak IC Msp Init Callback */
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID:
- /* Legacy weak IC Msp DeInit Callback */
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID:
- /* Legacy weak OC Msp Init Callback */
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID:
- /* Legacy weak OC Msp DeInit Callback */
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID:
- /* Legacy weak PWM Msp Init Callback */
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID:
- /* Legacy weak PWM Msp DeInit Callback */
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
- /* Legacy weak One Pulse Msp Init Callback */
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
- /* Legacy weak One Pulse Msp DeInit Callback */
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID:
- /* Legacy weak Encoder Msp Init Callback */
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
- /* Legacy weak Encoder Msp DeInit Callback */
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
- /* Legacy weak Hall Sensor Msp Init Callback */
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
- /* Legacy weak Hall Sensor Msp DeInit Callback */
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- break;
-
- default:
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- } else {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return status;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief TIM Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base handle state.
- * @param htim TIM Base handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return the TIM OC handle state.
- * @param htim TIM Output Compare handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM handle state.
- * @param htim TIM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture handle state.
- * @param htim TIM IC handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode handle state.
- * @param htim TIM OPM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode handle state.
- * @param htim TIM Encoder Interface handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode handle state.
- * @param htim TIM handle
- * @retval Active channel
- */
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) {
- return htim->Channel;
-}
-
-/**
- * @brief Return actual state of the TIM channel.
- * @param htim TIM handle
- * @param Channel TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5
- * @arg TIM_CHANNEL_6: TIM Channel 6
- * @retval TIM Channel state
- */
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_TIM_ChannelStateTypeDef channel_state;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
- return channel_state;
-}
-
-/**
- * @brief Return actual state of a DMA burst operation.
- * @param htim TIM handle
- * @retval DMA burst state
- */
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
- return htim->DMABurstState;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMAError(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- } else {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
-#else
- HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Delay Pulse half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- } else {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedHalfCpltCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Capture half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- } else {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureHalfCpltCallback(htim);
-#else
- HAL_TIM_IC_CaptureHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Period Elapse half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedHalfCpltCallback(htim);
-#else
- HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Trigger half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerHalfCpltCallback(htim);
-#else
- HAL_TIM_TriggerHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) {
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period;
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief Timer Output Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config) {
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx)) {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) {
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx)) {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config) {
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx)) {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config) {
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC4NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 12U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC4NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx)) {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- /* Reset the Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4N;
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 5 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config) {
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx)) {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 6 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config) {
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx)) {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Slave Timer configuration function
- * @param htim TIM handle
- * @param sSlaveConfig Slave timer configuration
- * @retval None
- */
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(
- TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger) {
- case TIM_TS_ETRF: {
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_TI1F_ED: {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) ||
- (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) {
- return HAL_ERROR;
- }
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
- break;
- }
-
- case TIM_TS_TI1FP1: {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_TI2FP2: {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_ITR0:
- case TIM_TS_ITR1:
- case TIM_TS_ITR2:
- case TIM_TS_ITR3:
-#if defined(TIM5)
- case TIM_TS_ITR4:
-#endif /* TIM5 */
- case TIM_TS_ITR5:
- case TIM_TS_ITR6:
- case TIM_TS_ITR7:
- case TIM_TS_ITR8:
-#if defined(TIM20)
- case TIM_TS_ITR9:
-#endif /* TIM20 */
-#if defined(HRTIM1)
- case TIM_TS_ITR10:
-#endif /* HRTIM1 */
- case TIM_TS_ITR11: {
- /* Check the parameter */
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(
- (htim->Instance), sSlaveConfig->InputTrigger));
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be
- * connected to IC1.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be
- * connected to IC2.
- * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected
- * to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- } else {
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICFilter) {
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4U);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be
- * connected to IC2.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be
- * connected to IC1.
- * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected
- * to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICFilter) {
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12U);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be
- * connected to IC3.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be
- * connected to IC4.
- * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected
- * to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
- uint32_t tmpccmr2;
- uint32_t tmpccer;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC3S;
- tmpccmr2 |= TIM_ICSelection;
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be
- * connected to IC4.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be
- * connected to IC3.
- * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected
- * to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- * @retval None
- */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
- uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
- uint32_t tmpccmr2;
- uint32_t tmpccer;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
- * @param InputTriggerSource The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @arg TIM_TS_ITR4: Internal Trigger 4 (*)
- * @arg TIM_TS_ITR5: Internal Trigger 5
- * @arg TIM_TS_ITR6: Internal Trigger 6
- * @arg TIM_TS_ITR7: Internal Trigger 7
- * @arg TIM_TS_ITR8: Internal Trigger 8
- * @arg TIM_TS_ITR9: Internal Trigger 9 (*)
- * @arg TIM_TS_ITR10: Internal Trigger 10
- * @arg TIM_TS_ITR11: Internal Trigger 11
- *
- * (*) Value not defined in all devices.
- *
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) {
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge
- * active.
- * @param ExtTRGFilter External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) {
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler |
- (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ChannelState) {
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |=
- (uint32_t)(ChannelState
- << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief Reset interrupt callbacks to the legacy weak callbacks.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-void TIM_ResetCallback(TIM_HandleTypeDef *htim) {
- /* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
- htim->TriggerCallback = HAL_TIM_TriggerCallback;
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
- htim->PWM_PulseFinishedHalfCpltCallback =
- HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
- htim->ErrorCallback = HAL_TIM_ErrorCallback;
- htim->CommutationCallback = HAL_TIMEx_CommutCallback;
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
- htim->BreakCallback = HAL_TIMEx_BreakCallback;
- htim->Break2Callback = HAL_TIMEx_Break2Callback;
- htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
- htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
- htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
- htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_tim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals
+and to interconnect several timers together.
+ (#) Supports incremental encoder for positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following
+functions depending on the selected feature:
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following
+function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using
+HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is
+the internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done
+before any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally
+HAL_TIMEx_OC_ConfigPulseOnCompare: to use the Timer to generate an Output
+Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to
+generate a PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to
+measure an external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the
+Timer in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending
+from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(),
+HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(),
+HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(),
+HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(),
+HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(),
+HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(),
+HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_TIM_RegisterCallback() to register a callback.
+ HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ [..]
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete
+Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete
+Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed
+Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete
+Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete
+Callback.
+ (+) BreakCallback : TIM Break Callback.
+ (+) Break2Callback : TIM Break2 Callback.
+ (+) EncoderIndexCallback : TIM Encoder Index Callback.
+ (+) DirectionChangeCallback : TIM Direction Change Callback
+ (+) IndexErrorCallback : TIM Index Error Callback.
+ (+) TransitionErrorCallback : TIM Transition Error Callback
+
+ [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+ examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+ [..]
+ Exception done for MspInit and MspDeInit functions that are reset to the
+legacy weak functionalities in the Init / DeInit only when these callbacks are
+null (not registered beforehand). If not, MspInit or MspDeInit are not null, the
+Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered
+beforehand)
+
+ [..]
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state
+only. Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init
+/ DeInit. In that case first register the MspInit/MspDeInit user callbacks using
+HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ [..]
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all
+callbacks are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup TIM_Private_Constants
+ * @{
+ */
+#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(
+ TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and initialize the associated
+ * handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode. Ex: call @ref HAL_TIM_Base_DeInit() before
+ * HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) {
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Base_MspInitCallback == NULL) {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Base_MspDeInitCallback == NULL) {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to
+ * peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim,
+ const uint32_t *pData,
+ uint16_t Length) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ if (htim->State == HAL_TIM_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (htim->State == HAL_TIM_STATE_READY) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback =
+ TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData,
+ (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated
+ * handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode. Ex: call @ref HAL_TIM_OC_DeInit() before
+ * HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) {
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OC_MspInitCallback == NULL) {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OC_MspDeInitCallback == NULL) {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM
+ * peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, const uint32_t *pData,
+ uint16_t Length) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (TIM_CHANNEL_STATE_GET(htim, Channel) ==
+ HAL_TIM_CHANNEL_STATE_READY) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM PWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated
+ * handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode. Ex: call @ref HAL_TIM_PWM_DeInit() before
+ * HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) {
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->PWM_MspInitCallback == NULL) {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->PWM_MspDeInitCallback == NULL) {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM
+ * peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, const uint32_t *pData,
+ uint16_t Length) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (TIM_CHANNEL_STATE_GET(htim, Channel) ==
+ HAL_TIM_CHANNEL_STATE_READY) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the
+ * specified parameters in the TIM_HandleTypeDef and initializes the associated
+ * handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode. Ex: call @ref HAL_TIM_IC_DeInit() before
+ * HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) {
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->IC_MspInitCallback == NULL) {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->IC_MspDeInitCallback == NULL) {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM Input Capture handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state =
+ TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state =
+ TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ HAL_TIM_ChannelStateTypeDef channel_state =
+ TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state =
+ TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to
+ * memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, uint32_t *pData,
+ uint16_t Length) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ HAL_TIM_ChannelStateTypeDef channel_state =
+ TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state =
+ TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel state */
+ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
+ return HAL_BUSY;
+ } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
+ (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
+ (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3],
+ (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4],
+ (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated
+ * handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode. Ex: call @ref HAL_TIM_OnePulse_DeInit()
+ * before HAL_TIM_OnePulse_Init()
+ * @note When the timer instance is initialized in One Pulse mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
+ * @param htim TIM One Pulse handle
+ * @param OnePulseMode Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim,
+ uint32_t OnePulseMode) {
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OnePulse_MspInitCallback == NULL) {
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OnePulse_MspDeInitCallback == NULL) {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the
+ * function it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are
+ TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the
+ TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input,
+ the TIM_CHANNEL_2 will be used as output whatever the combination, the
+ TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the
+ * function it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1
+ and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will
+ be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will
+ be used as output whatever the combination, the TIM_CHANNEL_1 and
+ TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the
+ * function it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are
+ TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the
+ TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input,
+ the TIM_CHANNEL_2 will be used as output whatever the combination, the
+ TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the
+ * function it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1
+ and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will
+ be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will
+ be used as output whatever the combination, the TIM_CHANNEL_1 and
+ TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and initialize the associated
+ * handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or
+ * reverse) requires a timer reset to avoid unexpected direction due to DIR bit
+ * readonly in center aligned mode. Ex: call @ref HAL_TIM_Encoder_DeInit()
+ * before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must
+ * not be selected together Ex: A call for @ref HAL_TIM_Encoder_Init will erase
+ * the settings of @ref HAL_TIM_ConfigClockSource using TIM_CLOCKSOURCE_ETRMODE2
+ * and vice versa
+ * @note When the timer instance is initialized in Encoder mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,
+ const TIM_Encoder_InitTypeDef *sConfig) {
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Encoder_MspInitCallback == NULL) {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters
+ */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Encoder_MspDeInitCallback == NULL) {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1) {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else if (Channel == TIM_CHANNEL_2) {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
+ /* Enable the encoder interface channels */
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+
+ default: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are
+ TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+
+ default: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1) {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else if (Channel == TIM_CHANNEL_2) {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ default: {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are
+ TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1) {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ } else if (Channel == TIM_CHANNEL_2) {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ } else {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 The destination Buffer address for IC1.
+ * @param pData2 The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to
+ * memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length) {
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1) {
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
+ return HAL_BUSY;
+ } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) {
+ if ((pData1 == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1,
+ HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+ } else if (Channel == TIM_CHANNEL_2) {
+ if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
+ return HAL_BUSY;
+ } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) {
+ if ((pData2 == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2,
+ HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+ } else {
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
+ return HAL_BUSY;
+ } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) {
+ if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1,
+ HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2,
+ HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+ }
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
+ (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
+ (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ break;
+ }
+
+ default: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
+ (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
+ (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ break;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are
+ TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1) {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ } else if (Channel == TIM_CHANNEL_2) {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ } else {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief TIM IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) {
+ uint32_t itsource = htim->Instance->DIER;
+ uint32_t itflag = htim->Instance->SR;
+
+ /* Capture compare 1 event */
+ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) {
+ if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) {
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) {
+ if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) {
+ if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) {
+ if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) {
+ if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break input event */
+ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) ||
+ ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) {
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
+ HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break2 input event */
+ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) {
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->Break2Callback(htim);
+#else
+ HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Trigger detection event */
+ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) {
+ if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM commutation event */
+ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) {
+ if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Encoder index event */
+ if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) {
+ if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->EncoderIndexCallback(htim);
+#else
+ HAL_TIMEx_EncoderIndexCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Direction change event */
+ if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) {
+ if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->DirectionChangeCallback(htim);
+#else
+ HAL_TIMEx_DirectionChangeCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Index error event */
+ if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) {
+ if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IndexErrorCallback(htim);
+#else
+ HAL_TIMEx_IndexErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Transition error event */
+ if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) {
+ if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TransitionErrorCallback(htim);
+#else
+ HAL_TIMEx_TransitionErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the
+ * specified parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ const TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_5: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_6: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim TIM IC handle
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim,
+ const TIM_IC_InitTypeDef *sConfig,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ if (Channel == TIM_CHANNEL_1) {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ } else if (Channel == TIM_CHANNEL_2) {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+ } else if (Channel == TIM_CHANNEL_3) {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ } else if (Channel == TIM_CHANNEL_4) {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+ } else {
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ const TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_5: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_6: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 6 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim TIM One Pulse handle
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM output channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel TIM input Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(
+ TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if (OutputChannel != InputChannel) {
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Output compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel) {
+ case TIM_CHANNEL_1: {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ switch (InputChannel) {
+ case TIM_CHANNEL_1: {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM
+ * peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the
+ * Data write This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and
+ * TIM_DMABURSTLENGTH_26TRANSFER.
+ * @note This function should be used only when BurstLength is equal to DMA
+ * data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ const uint32_t *BurstBuffer,
+ uint32_t BurstLength) {
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiWriteStart(
+ htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to
+ * the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the
+ * Data write This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and
+ * TIM_DMABURSTLENGTH_26TRANSFER.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ const uint32_t *BurstBuffer,
+ uint32_t BurstLength,
+ uint32_t DataLength) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
+ return HAL_ERROR;
+ } else {
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+ }
+ } else {
+ /* nothing to do */
+ }
+
+ switch (BurstRequestSrc) {
+ case TIM_DMA_UPDATE: {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback =
+ TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback =
+ TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR,
+ DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC1: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR,
+ DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC2: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR,
+ DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC3: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR,
+ DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC4: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR,
+ DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_COM: {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =
+ TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =
+ TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(
+ htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_TRIGGER: {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback =
+ TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(
+ htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim,
+ uint32_t BurstRequestSrc) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc) {
+ case TIM_DMA_UPDATE: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to
+ * the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the
+ * Data read This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and
+ * TIM_DMABURSTLENGTH_26TRANSFER.
+ * @note This function should be used only when BurstLength is equal to DMA
+ * data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer,
+ uint32_t BurstLength) {
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiReadStart(
+ htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to
+ * the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the
+ * Data read This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_DTR2
+ * @arg TIM_DMABASE_ECR
+ * @arg TIM_DMABASE_TISEL
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and
+ * TIM_DMABURSTLENGTH_26TRANSFER.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim,
+ uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer,
+ uint32_t BurstLength,
+ uint32_t DataLength) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
+ return HAL_ERROR;
+ } else {
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+ }
+ } else {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc) {
+ case TIM_DMA_UPDATE: {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback =
+ TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback =
+ TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC1: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC2: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC3: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC4: {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_COM: {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =
+ TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =
+ TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_TRIGGER: {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback =
+ TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER],
+ (uint32_t)&htim->Instance->DMAR,
+ (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim,
+ uint32_t BurstRequestSrc) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc) {
+ case TIM_DMA_UPDATE: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER: {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim TIM handle
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+ * only for timer instances supporting break input(s).
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim,
+ uint32_t EventSource) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure
+ * that contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(
+ TIM_HandleTypeDef *htim,
+ const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource) {
+ case TIM_CLEARINPUTSOURCE_NONE: {
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ if (IS_TIM_OCCS_INSTANCE(htim->Instance)) {
+ CLEAR_BIT(htim->Instance->SMCR,
+ (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE |
+ TIM_SMCR_ETP));
+
+ /* Clear TIMx_AF2_OCRSEL (reset value) */
+ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+ } else {
+ CLEAR_BIT(htim->Instance->SMCR,
+ (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+ }
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_COMP1:
+ case TIM_CLEARINPUTSOURCE_COMP2:
+ case TIM_CLEARINPUTSOURCE_COMP3:
+ case TIM_CLEARINPUTSOURCE_COMP4:
+#if defined(COMP5)
+ case TIM_CLEARINPUTSOURCE_COMP5:
+#endif /* COMP5 */
+#if defined(COMP6)
+ case TIM_CLEARINPUTSOURCE_COMP6:
+#endif /* COMP6 */
+#if defined(COMP7)
+ case TIM_CLEARINPUTSOURCE_COMP7:
+#endif /* COMP7 */
+ {
+ if (IS_TIM_OCCS_INSTANCE(htim->Instance)) {
+ /* Clear the OCREF clear selection bit */
+ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+ }
+
+ /* Set the clear input source */
+ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL,
+ sClearInputConfig->ClearInputSource);
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_ETR: {
+ /* Check the parameters */
+ assert_param(
+ IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(
+ IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(
+ IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be
+ * off */
+ if (sClearInputConfig->ClearInputPrescaler !=
+ TIM_CLEARINPUTPRESCALER_DIV1) {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ if (IS_TIM_OCCS_INSTANCE(htim->Instance)) {
+ /* Set the OCREF clear selection bit */
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+
+ /* Clear TIMx_AF2_OCRSEL (reset value) */
+ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+ }
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ } else {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_2: {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ } else {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_3: {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ } else {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_4: {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ } else {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5: {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ } else {
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_6: {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ } else {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim TIM handle
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(
+ TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource) {
+ case TIM_CLOCKSOURCE_INTERNAL: {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE1: {
+ /* Check whether or not the timer instance supports external trigger input
+ * mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE2: {
+ /* Check whether or not the timer instance supports external trigger input
+ * mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1: {
+ /* Check whether or not the timer instance supports external clock mode 1
+ */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI2: {
+ /* Check whether or not the timer instance supports external clock mode 1
+ * (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1ED: {
+ /* Check whether or not the timer instance supports external clock mode 1
+ */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ITR0:
+ case TIM_CLOCKSOURCE_ITR1:
+ case TIM_CLOCKSOURCE_ITR2:
+ case TIM_CLOCKSOURCE_ITR3:
+#if defined(TIM5)
+ case TIM_CLOCKSOURCE_ITR4:
+#endif /* TIM5 */
+ case TIM_CLOCKSOURCE_ITR5:
+ case TIM_CLOCKSOURCE_ITR6:
+ case TIM_CLOCKSOURCE_ITR7:
+ case TIM_CLOCKSOURCE_ITR8:
+#if defined(TIM20)
+ case TIM_CLOCKSOURCE_ITR9:
+#endif /* TIM20 */
+#if defined(HRTIM1)
+ case TIM_CLOCKSOURCE_ITR10:
+#endif /* HRTIM1 */
+ case TIM_CLOCKSOURCE_ITR11: {
+ /* Check whether or not the timer instance supports internal trigger input
+ */
+ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE(
+ (htim->Instance), sClockSourceConfig->ClockSource));
+
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim TIM handle.
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1
+ * input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim,
+ uint32_t TI1_Selection) {
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset +
+ * Trigger, Gated + Reset).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(
+ TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(
+ IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset +
+ * Trigger, Gated + Reset).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(
+ TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(
+ IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ uint32_t tmpreg = 0U;
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
+ (+) TIM Index callback
+ (+) TIM Direction change callback
+ (+) TIM Index error callback
+ (+) TIM Transition error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in
+ the user file
+ */
+}
+
+/**
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented
+ in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Timer error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TIM callback to be used instead of the weak
+ * predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback
+ * ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit
+ * Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback
+ * ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit
+ * Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit
+ * Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half
+ * complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback
+ * ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete
+ * Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay
+ * Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished
+ * Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished
+ * half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete
+ * Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+ * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback
+ * ID
+ * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+ * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback
+ * ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim,
+ HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ return HAL_ERROR;
+ }
+
+ if (htim->State == HAL_TIM_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_TIM_BASE_MSPINIT_CB_ID:
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID:
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID:
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID:
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID:
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID:
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID:
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID:
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID:
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID:
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID:
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID:
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID:
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID:
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID:
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID:
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID:
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID:
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID:
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID:
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID:
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID:
+ htim->BreakCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID:
+ htim->Break2Callback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_INDEX_CB_ID:
+ htim->EncoderIndexCallback = pCallback;
+ break;
+
+ case HAL_TIM_DIRECTION_CHANGE_CB_ID:
+ htim->DirectionChangeCallback = pCallback;
+ break;
+
+ case HAL_TIM_INDEX_ERROR_CB_ID:
+ htim->IndexErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRANSITION_ERROR_CB_ID:
+ htim->TransitionErrorCallback = pCallback;
+ break;
+
+ default:
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (htim->State == HAL_TIM_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_TIM_BASE_MSPINIT_CB_ID:
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID:
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID:
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID:
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID:
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID:
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID:
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID:
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID:
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback
+ * ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit
+ * Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback
+ * ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit
+ * Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit
+ * Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half
+ * complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback
+ * ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete
+ * Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay
+ * Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished
+ * Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished
+ * half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete
+ * Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+ * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback
+ * ID
+ * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+ * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback
+ * ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(
+ TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (htim->State == HAL_TIM_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_TIM_BASE_MSPINIT_CB_ID:
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID:
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID:
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID:
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID:
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID:
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID:
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID:
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID:
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID:
+ /* Legacy weak Period Elapsed Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID:
+ /* Legacy weak Period Elapsed half complete Callback */
+ htim->PeriodElapsedHalfCpltCallback =
+ HAL_TIM_PeriodElapsedHalfCpltCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID:
+ /* Legacy weak Trigger Callback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID:
+ /* Legacy weak Trigger half complete Callback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID:
+ /* Legacy weak IC Capture Callback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID:
+ /* Legacy weak IC Capture half complete Callback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID:
+ /* Legacy weak OC Delay Elapsed Callback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID:
+ /* Legacy weak PWM Pulse Finished Callback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID:
+ /* Legacy weak PWM Pulse Finished half complete Callback */
+ htim->PWM_PulseFinishedHalfCpltCallback =
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID:
+ /* Legacy weak Error Callback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID:
+ /* Legacy weak Commutation Callback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID:
+ /* Legacy weak Commutation half complete Callback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID:
+ /* Legacy weak Break Callback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID:
+ /* Legacy weak Break2 Callback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
+ break;
+
+ case HAL_TIM_ENCODER_INDEX_CB_ID:
+ /* Legacy weak Encoder Index Callback */
+ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
+ break;
+
+ case HAL_TIM_DIRECTION_CHANGE_CB_ID:
+ /* Legacy weak Direction Change Callback */
+ htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
+ break;
+
+ case HAL_TIM_INDEX_ERROR_CB_ID:
+ /* Legacy weak Index Error Callback */
+ htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
+ break;
+
+ case HAL_TIM_TRANSITION_ERROR_CB_ID:
+ /* Legacy weak Transition Error Callback */
+ htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
+ break;
+
+ default:
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (htim->State == HAL_TIM_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_TIM_BASE_MSPINIT_CB_ID:
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID:
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID:
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID:
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID:
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID:
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID:
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID:
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID:
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ break;
+
+ default:
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base handle state.
+ * @param htim TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM handle state.
+ * @param htim TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture handle state.
+ * @param htim TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode handle state.
+ * @param htim TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM handle
+ * @retval Active channel
+ */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) {
+ return htim->Channel;
+}
+
+/**
+ * @brief Return actual state of the TIM channel.
+ * @param htim TIM handle
+ * @param Channel TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval TIM Channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(
+ const TIM_HandleTypeDef *htim, uint32_t Channel) {
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+ return channel_state;
+}
+
+/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(
+ const TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ } else {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ } else {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ } else {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_Base_InitTypeDef *Structure) {
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear
+ * the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
+}
+
+/**
+ * @brief Timer Output Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config) {
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx)) {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) {
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx)) {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config) {
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx)) {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config) {
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC4NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 12U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC4NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx)) {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Reset the Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4N;
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config) {
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx)) {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ const TIM_OC_InitTypeDef *OC_Config) {
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx)) {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
+ * @retval None
+ */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(
+ TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger) {
+ case TIM_TS_ETRF: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI1F_ED: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) ||
+ (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) {
+ return HAL_ERROR;
+ }
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+ break;
+ }
+
+ case TIM_TS_TI1FP1: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI2FP2: {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
+#if defined(TIM5)
+ case TIM_TS_ITR4:
+#endif /* TIM5 */
+ case TIM_TS_ITR5:
+ case TIM_TS_ITR6:
+ case TIM_TS_ITR7:
+ case TIM_TS_ITR8:
+#if defined(TIM20)
+ case TIM_TS_ITR9:
+#endif /* TIM20 */
+#if defined(HRTIM1)
+ case TIM_TS_ITR10:
+#endif /* HRTIM1 */
+ case TIM_TS_ITR11: {
+ /* Check the parameter */
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(
+ (htim->Instance), sSlaveConfig->InputTrigger));
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be
+ * connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be
+ * connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected
+ * to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Select the Input */
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ } else {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICFilter) {
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be
+ * connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be
+ * connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected
+ * to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICFilter) {
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be
+ * connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be
+ * connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected
+ * to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be
+ * connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be
+ * connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected
+ * to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
+ uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_ITR4: Internal Trigger 4 (*)
+ * @arg TIM_TS_ITR5: Internal Trigger 5
+ * @arg TIM_TS_ITR6: Internal Trigger 6
+ * @arg TIM_TS_ITR7: Internal Trigger 7
+ * @arg TIM_TS_ITR8: Internal Trigger 8
+ * @arg TIM_TS_ITR9: Internal Trigger 9 (*)
+ * @arg TIM_TS_ITR10: Internal Trigger 10
+ * @arg TIM_TS_ITR11: Internal Trigger 11
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ *
+ * (*) Value not defined in all devices.
+ *
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) {
+ uint32_t tmpsmcr;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge
+ * active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) {
+ uint32_t tmpsmcr;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler |
+ (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ChannelState) {
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |=
+ (uint32_t)(ChannelState
+ << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim) {
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ htim->PWM_PulseFinishedHalfCpltCallback =
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
+ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
+ htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
+ htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
+ htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c
index 066c469..1ed70ee 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c
@@ -1,3822 +1,3804 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_tim_ex.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer Extended peripheral:
- * + Time Hall Sensor Interface Initialization
- * + Time Hall Sensor Interface Start
- * + Time Complementary signal break and dead time configuration
- * + Time Master and Slave synchronization configuration
- * + Time Output Compare/PWM Channel Configuration (for channels 5
- and 6)
- * + Time OCRef clear configuration
- * + Timer remapping capabilities configuration
- * + Timer encoder index configuration
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### TIMER Extended features #####
- ==============================================================================
- [..]
- The Timer Extended features include:
- (#) Complementary outputs with programmable dead-time for :
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and
- to interconnect several timers together.
- (#) Break input to put the timer output signals in reset state or in a known
- state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
- (#) In case of Pulse on compare, configure pulse length and delay
- (#) Encoder index configuration
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following
- functions depending on the selected feature:
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following
- function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using
- HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is
- the internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done
- before any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to
- use the Timer Hall Sensor Interface and the commutation event with the
- corresponding Interrupt and DMA request if needed (Note that One Timer is used
- to interface with the Hall sensor Interface and another Timer should be used
- to use the commutation event).
- (#) In case of Pulse On Compare:
- (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width
- and prescaler
-
-
- (#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(),
- HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(),
- HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
- (++) Complementary One-pulse mode output :
- HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(),
- HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIMEx TIMEx
- * @brief TIM Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
- * @{
- */
-/* Timeout for break input rearm */
-#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ChannelNState);
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor
-functions
- * @brief Timer Hall Sensor functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Hall Sensor functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
- (+) De-initialize TIM HAL Sensor.
- (+) Start the Hall Sensor Interface.
- (+) Stop the Hall Sensor Interface.
- (+) Start the Hall Sensor Interface and enable interrupts.
- (+) Stop the Hall Sensor Interface and disable interrupts.
- (+) Start the Hall Sensor Interface and enable DMA transfers.
- (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Hall Sensor Interface and initialize the
- * associated handle.
- * @note When the timer instance is initialized in Hall Sensor Interface mode,
- * timer channels 1 and channel 2 are reserved and cannot be used for
- * other purpose.
- * @param htim TIM Hall Sensor Interface handle
- * @param sConfig TIM Hall Sensor configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(
- TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) {
- TIM_OC_InitTypeDef OC_Config;
-
- /* Check the TIM handle allocation */
- if (htim == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->HallSensor_MspInitCallback == NULL) {
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->HallSensor_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Configure the Channel 1 as Input Channel to interface with the three
- * Outputs of the Hall sensor */
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC,
- sConfig->IC1Filter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
- /* Enable the Hall sensor interface (XOR function of the three inputs) */
- htim->Instance->CR2 |= TIM_CR2_TI1S;
-
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection
- */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
- OC_Config.OCMode = TIM_OCMODE_PWM2;
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101 */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Hall Sensor interface
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->HallSensor_MspDeInitCallback == NULL) {
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->HallSensor_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIMEx_HallSensor_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Hall Sensor MSP.
- * @param htim TIM Hall Sensor Interface handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user
- file
- */
-}
-
-/**
- * @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim TIM Hall Sensor Interface handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) {
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are
- TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall sensor Interface.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are
- TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) {
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the capture compare Interrupts 1 event */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are
- TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are
- TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts event */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor Interface handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to
- * memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t *pData,
- uint16_t Length) {
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel state */
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
- (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
- return HAL_BUSY;
- } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
- (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are
- TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Set the DMA Input Capture 1 Callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the DMA channel for Capture 1*/
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
- (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
- Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the capture compare 1 Interrupt */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are
- TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 event */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary
-Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary Output Compare/PWM.
- (+) Stop the Complementary Output Compare/PWM.
- (+) Start the Complementary Output Compare/PWM and enable interrupts.
- (+) Stop the Complementary Output Compare/PWM and disable interrupts.
- (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
- (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM OC handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpccer;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE |
- TIM_CCER_CC4NE)) == (uint32_t)RESET) {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM
- * peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
- return HAL_BUSY;
- } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) ==
- HAL_TIM_CHANNEL_STATE_READY) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM
-functions
- * @brief Timer Complementary PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary PWM.
- (+) Stop the Complementary PWM.
- (+) Start the Complementary PWM and enable interrupts.
- (+) Stop the Complementary PWM and disable interrupts.
- (+) Start the Complementary PWM and enable DMA transfers.
- (+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically
- * done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpccer;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE |
- TIM_CCER_CC4NE)) == (uint32_t)RESET) {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode on the
- * complementary output
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM
- * peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel, uint32_t *pData,
- uint16_t Length) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
- return HAL_BUSY;
- } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) ==
- HAL_TIM_CHANNEL_STATE_READY) {
- if ((pData == NULL) && (Length > 0U)) {
- return HAL_ERROR;
- } else {
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- } else {
- return HAL_ERROR;
- }
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
- TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
- (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is
- * automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
- __HAL_TIM_ENABLE(htim);
- }
- } else {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
- * output
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel) {
- case TIM_CHANNEL_1: {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2: {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3: {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4: {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK) {
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One
-Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM One Pulse signal generation on the complementary
- * output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to enable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- uint32_t input_channel =
- (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the complementary One Pulse output channel and the Input Capture
- * channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
- * output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- uint32_t input_channel =
- (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the complementary One Pulse output channel and the Input Capture
- * channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to enable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- uint32_t input_channel =
- (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef channel_1_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state =
- TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
- TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
- (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- /* Enable the complementary One Pulse output channel and the Input Capture
- * channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim,
- uint32_t OutputChannel) {
- uint32_t input_channel =
- (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the complementary One Pulse output channel and the Input Capture
- * channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control
-functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor
-interface.
- (+) Configure Output channels for OC and PWM mode.
-
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master synchronization.
- (+) Configure timer remapping capabilities.
- (+) Select timer input source.
- (+) Enable or disable channel grouping.
- (+) Configure Pulse on compare.
- (+) Configure Encoder index.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the TIM commutation event sequence.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI
- * input of the Timer, the typical use of this feature is with the use of
- * another Timer(interface Timer) configured in Hall sensor interface, this
- * interface Timer will generate the commutation at its TRGO output (connected
- * to Timer used in this function) each time the TI1 of the Interface Timer
- * detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer
- * Interfacing with the Hall sensor This parameter can be one of the following
- * values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
- * @arg TIM_TS_ITR5: Internal trigger 5 selected
- * @arg TIM_TS_ITR6: Internal trigger 6 selected
- * @arg TIM_TS_ITR7: Internal trigger 7 selected
- * @arg TIM_TS_ITR8: Internal trigger 8 selected
- * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
- * @arg TIM_TS_ITR10: Internal trigger 10 selected
- * @arg TIM_TS_ITR11: Internal trigger 11 selected
- * @arg TIM_TS_NONE: No trigger is needed
- *
- * (*) Value not defined in all devices.
- *
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the
- * Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by
- * software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim,
- uint32_t InputTrigger,
- uint32_t CommutationSource) {
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(
- IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
-
- __HAL_LOCK(htim);
-
-#if defined(TIM5) && defined(TIM20)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
- (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
- (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
- (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
-#elif defined(TIM5)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
- (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
- (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
-#elif defined(TIM20)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
- (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
- (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
-#else
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
- (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
- (InputTrigger == TIM_TS_ITR11))
-#endif /* TIM5 && TIM20 */
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Disable Commutation Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
-
- /* Disable Commutation DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with interrupt.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI
- * input of the Timer, the typical use of this feature is with the use of
- * another Timer(interface Timer) configured in Hall sensor interface, this
- * interface Timer will generate the commutation at its TRGO output (connected
- * to Timer used in this function) each time the TI1 of the Interface Timer
- * detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer
- * Interfacing with the Hall sensor This parameter can be one of the following
- * values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
- * @arg TIM_TS_ITR5: Internal trigger 5 selected
- * @arg TIM_TS_ITR6: Internal trigger 6 selected
- * @arg TIM_TS_ITR7: Internal trigger 7 selected
- * @arg TIM_TS_ITR8: Internal trigger 8 selected
- * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
- * @arg TIM_TS_ITR10: Internal trigger 10 selected
- * @arg TIM_TS_ITR11: Internal trigger 11 selected
- * @arg TIM_TS_NONE: No trigger is needed
- *
- * (*) Value not defined in all devices.
- *
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the
- * Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by
- * software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim,
- uint32_t InputTrigger,
- uint32_t CommutationSource) {
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(
- IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
-
- __HAL_LOCK(htim);
-
-#if defined(TIM5) && defined(TIM20)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
- (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
- (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
- (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
-#elif defined(TIM5)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
- (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
- (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
-#elif defined(TIM20)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
- (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
- (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
-#else
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
- (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
- (InputTrigger == TIM_TS_ITR11))
-#endif /* TIM5 && TIM20 */
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Disable Commutation DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
-
- /* Enable the Commutation Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with DMA.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI
- * input of the Timer, the typical use of this feature is with the use of
- * another Timer(interface Timer) configured in Hall sensor interface, this
- * interface Timer will generate the commutation at its TRGO output (connected
- * to Timer used in this function) each time the TI1 of the Interface Timer
- * detect a commutation at its input TI1.
- * @note The user should configure the DMA in his own software, in This
- * function only the COMDE bit is set
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer
- * Interfacing with the Hall sensor This parameter can be one of the following
- * values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
- * @arg TIM_TS_ITR5: Internal trigger 5 selected
- * @arg TIM_TS_ITR6: Internal trigger 6 selected
- * @arg TIM_TS_ITR7: Internal trigger 7 selected
- * @arg TIM_TS_ITR8: Internal trigger 8 selected
- * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
- * @arg TIM_TS_ITR10: Internal trigger 10 selected
- * @arg TIM_TS_ITR11: Internal trigger 11 selected
- * @arg TIM_TS_NONE: No trigger is needed
- *
- * (*) Value not defined in all devices.
- *
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the
- * Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by
- * software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim,
- uint32_t InputTrigger,
- uint32_t CommutationSource) {
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(
- IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
-
- __HAL_LOCK(htim);
-
-#if defined(TIM5) && defined(TIM20)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
- (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
- (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
- (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
-#elif defined(TIM5)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
- (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
- (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
-#elif defined(TIM20)
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
- (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
- (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
-#else
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
- (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
- (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
- (InputTrigger == TIM_TS_ITR11))
-#endif /* TIM5 && TIM20 */
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation DMA Request */
- /* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =
- TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =
- TIMEx_DMACommutationHalfCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Disable Commutation Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
-
- /* Enable the Commutation DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in master mode.
- * @param htim TIM handle.
- * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(
- TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) {
- uint32_t tmpcr2;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* If the timer supports ADC synchronization through TRGO2, set the master
- * mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
-
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim TIM handle
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
- * structure that contains the BDTR Register configuration information for the
- * TIM peripheral.
- * @note Interrupts can be generated when an active level is detected on the
- * break input, the break 2 input or the system break input. Break
- * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT
- * macro.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(
- TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) {
- /* Keep this variable initialized to 0 as it is used to configure BDTR
- * register */
- uint32_t tmpbdtr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
- assert_param(
- IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF,
- (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
-
- /* Set BREAK AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
- }
-
- if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
- assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
-
- /* Set the BREAK2 input related BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F,
- (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
-
- /* Set BREAK2 AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
- }
- }
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the break input source.
- * @param htim TIM handle.
- * @param BreakInput Break input to configure
- * This parameter can be one of the following values:
- * @arg TIM_BREAKINPUT_BRK: Timer break input
- * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
- * @param sBreakInputConfig Break input source configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(
- TIM_HandleTypeDef *htim, uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmporx;
- uint32_t bkin_enable_mask;
- uint32_t bkin_polarity_mask;
- uint32_t bkin_enable_bitpos;
- uint32_t bkin_polarity_bitpos;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_BREAKINPUT(BreakInput));
- assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
- assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
- assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- switch (sBreakInputConfig->Source) {
- case TIM_BREAKINPUTSOURCE_BKIN: {
- bkin_enable_mask = TIM1_AF1_BKINE;
- bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
- bkin_polarity_mask = TIM1_AF1_BKINP;
- bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
- break;
- }
- case TIM_BREAKINPUTSOURCE_COMP1: {
- bkin_enable_mask = TIM1_AF1_BKCMP1E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
- bkin_polarity_mask = TIM1_AF1_BKCMP1P;
- bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
- break;
- }
- case TIM_BREAKINPUTSOURCE_COMP2: {
- bkin_enable_mask = TIM1_AF1_BKCMP2E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
- bkin_polarity_mask = TIM1_AF1_BKCMP2P;
- bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
- break;
- }
- case TIM_BREAKINPUTSOURCE_COMP3: {
- bkin_enable_mask = TIM1_AF1_BKCMP3E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
- bkin_polarity_mask = TIM1_AF1_BKCMP3P;
- bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
- break;
- }
- case TIM_BREAKINPUTSOURCE_COMP4: {
- bkin_enable_mask = TIM1_AF1_BKCMP4E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
- bkin_polarity_mask = TIM1_AF1_BKCMP4P;
- bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
- break;
- }
-#if defined(COMP5)
- case TIM_BREAKINPUTSOURCE_COMP5: {
- bkin_enable_mask = TIM1_AF1_BKCMP5E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
- /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its
- * default value 0 */
- bkin_polarity_mask = 0U;
- bkin_polarity_bitpos = 0U;
- break;
- }
-#endif /* COMP5 */
-#if defined(COMP6)
- case TIM_BREAKINPUTSOURCE_COMP6: {
- bkin_enable_mask = TIM1_AF1_BKCMP6E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
- /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its
- * default value 0 */
- bkin_polarity_mask = 0U;
- bkin_polarity_bitpos = 0U;
- break;
- }
-#endif /* COMP7 */
-#if defined(COMP7)
- case TIM_BREAKINPUTSOURCE_COMP7: {
- bkin_enable_mask = TIM1_AF1_BKCMP7E;
- bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
- /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its
- * default value 0 */
- bkin_polarity_mask = 0U;
- bkin_polarity_bitpos = 0U;
- break;
- }
-#endif /* COMP7 */
-
- default: {
- bkin_enable_mask = 0U;
- bkin_polarity_mask = 0U;
- bkin_enable_bitpos = 0U;
- bkin_polarity_bitpos = 0U;
- break;
- }
- }
-
- switch (BreakInput) {
- case TIM_BREAKINPUT_BRK: {
- /* Get the TIMx_AF1 register value */
- tmporx = htim->Instance->AF1;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |=
- (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- /* Set the break input polarity */
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) &
- bkin_polarity_mask;
-
- /* Set TIMx_AF1 */
- htim->Instance->AF1 = tmporx;
- break;
- }
- case TIM_BREAKINPUT_BRK2: {
- /* Get the TIMx_AF2 register value */
- tmporx = htim->Instance->AF2;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |=
- (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- /* Set the break input polarity */
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) &
- bkin_polarity_mask;
-
- /* Set TIMx_AF2 */
- htim->Instance->AF2 = tmporx;
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Configures the TIMx Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap specifies the TIM remapping source.
- * For TIM1, the parameter can take one of the following values:
- * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
- * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1
- * output
- * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2
- * output
- * @arg TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3
- * output
- * @arg TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4
- * output
- * @arg TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1
- * AWD1
- * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1
- * AWD2
- * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1
- * AWD3
- * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4
- * AWD1 (*)
- * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4
- * AWD2 (*)
- * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4
- * AWD3 (*)
- *
- * For TIM2, the parameter can take one of the following values:
- * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
- * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1
- * output
- * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2
- * output
- * @arg TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3
- * output
- * @arg TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4
- * output
- * @arg TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR
- * pin
- * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR
- * pin
- * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR
- * pin (*)
- * @arg TIM_TIM2_ETR_LSE
- *
- * For TIM3, the parameter can take one of the following values:
- * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
- * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1
- * output
- * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2
- * output
- * @arg TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3
- * output
- * @arg TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4
- * output
- * @arg TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR
- * pin
- * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR
- * pin
- * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2
- * AWD1
- * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2
- * AWD2
- * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2
- * AWD3
- *
- * For TIM4, the parameter can take one of the following values:
- * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
- * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1
- * output
- * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2
- * output
- * @arg TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3
- * output
- * @arg TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4
- * output
- * @arg TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR
- * pin
- * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR
- * pin (*)
- *
- * For TIM5, the parameter can take one of the following values: (**)
- * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*)
- * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1
- * output (*)
- * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2
- * output (*)
- * @arg TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3
- * output (*)
- * @arg TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4
- * output (*)
- * @arg TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR
- * pin (*)
- * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR
- * pin (*)
- *
- * For TIM8, the parameter can take one of the following values:
- * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
- * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1
- * output
- * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2
- * output
- * @arg TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3
- * output
- * @arg TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4
- * output
- * @arg TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2
- * AWD1
- * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2
- * AWD2
- * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2
- * AWD3
- * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3
- * AWD1 (*)
- * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3
- * AWD2 (*)
- * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3
- * AWD3 (*)
- *
- * For TIM20, the parameter can take one of the following values: (**)
- * @arg TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO
- * @arg TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1
- * output (*)
- * @arg TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2
- * output (*)
- * @arg TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3
- * output (*)
- * @arg TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4
- * output (*)
- * @arg TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5
- * output (*)
- * @arg TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6
- * output (*)
- * @arg TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7
- * output (*)
- * @arg TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3
- * AWD1 (*)
- * @arg TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3
- * AWD2 (*)
- * @arg TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3
- * AWD3 (*)
- * @arg TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5
- * AWD1 (*)
- * @arg TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5
- * AWD2 (*)
- * @arg TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5
- * AWD3 (*)
- *
- * (*) Value not defined in all devices. \n
- * (**) Register not available in all devices.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim,
- uint32_t Remap) {
- /* Check parameters */
- assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
- assert_param(IS_TIM_REMAP(Remap));
-
- __HAL_LOCK(htim);
-
- MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Select the timer input source
- * @param htim TIM handle.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TI1 input channel
- * @arg TIM_CHANNEL_2: TI2 input channel
- * @arg TIM_CHANNEL_3: TI3 input channel
- * @arg TIM_CHANNEL_4: TI4 input channel
- * @param TISelection specifies the timer input source
- * For TIM1 this parameter can be one of the following values:
- * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to
- GPIO
- * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to
- COMP1 output
- * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to
- COMP2 output
- * @arg TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to
- COMP3 output
- * @arg TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to
- COMP4 output
- *
- * For TIM2 this parameter can be one of the following values:
- * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to
- GPIO
- * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to
- COMP1 output
- * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to
- COMP2 output
- * @arg TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to
- COMP3 output
- * @arg TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to
- COMP4 output
- * @arg TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to
- COMP5 output (*)
- *
- * @arg TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to
- GPIO
- * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to
- COMP1 output
- * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to
- COMP2 output
- * @arg TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to
- COMP3 output
- * @arg TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to
- COMP4 output
- * @arg TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to
- COMP6 output (*)
- *
- * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to
- GPIO
- * @arg TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to
- COMP4 output
- *
- * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to
- GPIO
- * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to
- COMP1 output
- * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to
- COMP2 output
- *
- * For TIM3 this parameter can be one of the following values:
- * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to
- GPIO
- * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to
- COMP1 output
- * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to
- COMP2 output
- * @arg TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to
- COMP3 output
- * @arg TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to
- COMP4 output
- * @arg TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to
- COMP5 output (*)
- * @arg TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to
- COMP6 output (*)
- * @arg TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to
- COMP7 output (*)
- *
- * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to
- GPIO
- * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to
- COMP1 output
- * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to
- COMP2 output
- * @arg TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to
- COMP3 output
- * @arg TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to
- COMP4 output
- * @arg TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to
- COMP5 output (*)
- * @arg TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to
- COMP6 output (*)
- * @arg TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to
- COMP7 output (*)
- *
- * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to
- GPIO
- * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to
- COMP3 output
-
- * For TIM4 this parameter can be one of the following values:
- * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to
- GPIO
- * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to
- COMP1 output
- * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to
- COMP2 output
- * @arg TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to
- COMP3 output
- * @arg TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to
- COMP4 output
- * @arg TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to
- COMP5 output (*)
- * @arg TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to
- COMP6 output (*)
- * @arg TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to
- COMP7 output (*)
- *
- * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to
- GPIO
- * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to
- COMP1 output
- * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to
- COMP2 output
- * @arg TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to
- COMP3 output
- * @arg TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to
- COMP4 output
- * @arg TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to
- COMP5 output (*)
- * @arg TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to
- COMP6 output (*)
- * @arg TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to
- COMP7 output (*)
- *
- * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to
- GPIO
- * @arg TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to
- COMP5 output (*)
- *
- * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to
- GPIO
- * @arg TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to
- COMP6 output (*)
- *
- * For TIM5 this parameter can be one of the following values: (**)
- * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to
- GPIO
- * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to
- LSI clock (*)
- * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to
- LSE clock (*)
- * @arg TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to
- RTC Wakeup (*)
- * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to
- COMP1 output (*)
- * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to
- COMP2 output (*)
- * @arg TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to
- COMP3 output (*)
- * @arg TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to
- COMP4 output (*)
- * @arg TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to
- COMP5 output (*)
- * @arg TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to
- COMP6 output (*)
- * @arg TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to
- COMP7 output (*)
- *
- * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to
- GPIO
- * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to
- COMP1 output
- * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to
- COMP2 output
- * @arg TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to
- COMP3 output
- * @arg TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to
- COMP4 output
- * @arg TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to
- COMP5 output (*)
- * @arg TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to
- COMP6 output (*)
- * @arg TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to
- COMP7 output (*)
- *
- * For TIM8 this parameter can be one of the following values:
- * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to
- GPIO
- * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to
- COMP1 output
- * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to
- COMP2 output
- * @arg TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to
- COMP3 output
- * @arg TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to
- COMP4 output
- *
- * For TIM15 this parameter can be one of the following values:
- * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to
- GPIO
- * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to
- LSE clock
- * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to
- COMP1 output
- * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to
- COMP2 output
- * @arg TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to
- COMP5 output (*)
- * @arg TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to
- COMP7 output (*)
- *
- * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to
- GPIO
- * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to
- COMP2 output
- * @arg TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to
- COMP3 output
- * @arg TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to
- COMP6 output (*)
- * @arg TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to
- COMP7 output (*)
- *
- * For TIM16 this parameter can be one of the following values:
- * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to
- GPIO
- * @arg TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to
- COMP6 output (*)
- * @arg TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to
- MCO output
- * @arg TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to
- HSE div 32
- * @arg TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to
- RTC wakeup
- * @arg TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to
- LSE clock
- * @arg TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to
- LSI clock
- *
- * For TIM17 this parameter can be one of the following values:
- * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to
- GPIO
- * @arg TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to
- COMP5 output (*)
- * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to
- MCO output
- * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to
- HSE div 32
- * @arg TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to
- RTC wakeup
- * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to
- LSE clock
- * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to
- LSI clock
-
- * For TIM20 this parameter can be one of the following values: (**)
- * @arg TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to
- GPIO
- * @arg TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to
- COMP1 output (*)
- * @arg TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to
- COMP2 output (*)
- * @arg TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to
- COMP3 output (*)
- * @arg TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to
- COMP4 output (*)
- *
- * (*) Value not defined in all devices. \n
- * (**) Register not available in all devices.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim,
- uint32_t TISelection,
- uint32_t Channel) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_TISEL(TISelection));
-
- __HAL_LOCK(htim);
-
- switch (Channel) {
- case TIM_CHANNEL_1:
- MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
-
- /* If required, set OR bit to request HSE/32 clock */
- if (IS_TIM_HSE32_INSTANCE(htim->Instance)) {
- SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
- } else {
- CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
- }
- break;
- case TIM_CHANNEL_2:
- MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
- break;
- case TIM_CHANNEL_3:
- MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
- break;
- case TIM_CHANNEL_4:
- MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Group channel 5 and channel 1, 2 or 3
- * @param htim TIM handle.
- * @param Channels specifies the reference signal(s) the OC5REF is combined
- * with. This parameter can be any combination of the following values:
- * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and
- * OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and
- * OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
- * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and
- * OC5REF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim,
- uint32_t Channels) {
- /* Check parameters */
- assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_GROUPCH5(Channels));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Clear GC5Cx bit fields */
- htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
-
- /* Set GC5Cx bit fields */
- htim->Instance->CCR5 |= Channels;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disarm the designated break input (when it operates in bidirectional
- * mode).
- * @param htim TIM handle.
- * @param BreakInput Break input to disarm
- * This parameter can be one of the following values:
- * @arg TIM_BREAKINPUT_BRK: Timer break input
- * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
- * @note The break input can be disarmed only when it is configured in
- * bidirectional mode and when when MOE is reset.
- * @note Purpose is to be able to have the input voltage back to high-state,
- * whatever the time constant on the output .
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim,
- uint32_t BreakInput) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpbdtr;
-
- /* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
- assert_param(IS_TIM_BREAKINPUT(BreakInput));
-
- switch (BreakInput) {
- case TIM_BREAKINPUT_BRK: {
- /* Check initial conditions */
- tmpbdtr = READ_REG(htim->Instance->BDTR);
- if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
- (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) {
- /* Break input BRK is disarmed */
- SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
- }
- break;
- }
-
- case TIM_BREAKINPUT_BRK2: {
- /* Check initial conditions */
- tmpbdtr = READ_REG(htim->Instance->BDTR);
- if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
- (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) {
- /* Break input BRK is disarmed */
- SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
- }
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Arm the designated break input (when it operates in bidirectional
- * mode).
- * @param htim TIM handle.
- * @param BreakInput Break input to arm
- * This parameter can be one of the following values:
- * @arg TIM_BREAKINPUT_BRK: Timer break input
- * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
- * @note Arming is possible at anytime, even if fault is present.
- * @note Break input is automatically armed as soon as MOE bit is set.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim,
- uint32_t BreakInput) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
- assert_param(IS_TIM_BREAKINPUT(BreakInput));
-
- switch (BreakInput) {
- case TIM_BREAKINPUT_BRK: {
- /* Check initial conditions */
- if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) {
- /* Break input BRK is re-armed automatically by hardware. Poll to check
- * whether fault condition disappeared */
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
- while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) {
- if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption
- */
- if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- break;
- }
-
- case TIM_BREAKINPUT_BRK2: {
- /* Check initial conditions */
- if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) {
- /* Break input BRK2 is re-armed automatically by hardware. Poll to check
- * whether fault condition disappeared */
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
- while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) {
- if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) {
- /* New check to avoid false timeout detection in case of preemption
- */
- if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Enable dithering
- * @param htim TIM handle
- * @note Main usage is PWM mode
- * @note This function must be called when timer is stopped or disabled (CEN
- * =0)
- * @note If dithering is activated, pay attention to ARR, CCRx, CNT
- * interpretation:
- * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers
- * (or CNT[26:0] for 32b timers)
- * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the
- * dither part for 16b timers
- * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the
- * dither part for 16b timers
- * - ARR and CCRx values are limited to 0xFFEF in dithering mode for
- * 16b timers (corresponds to 4094 for the integer part and 15 for the dithered
- * part).
- * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER()
- * __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() can be used to
- * calculate period (ARR) and delay (CCRx) value.
- * @note Enabling dithering, modifies automatically values of registers
- * ARR/CCRx to keep the same integer part.
- * @note Enabling dithering, modifies automatically values of registers
- * ARR/CCRx to keep the same integer part. So it may be necessary to read ARR
- * value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
- * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field
- * htim->Init.Period .
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
- return HAL_OK;
-}
-
-/**
- * @brief Disable dithering
- * @param htim TIM handle
- * @note This function must be called when timer is stopped or disabled (CEN
- * =0)
- * @note If dithering is activated, pay attention to ARR, CCRx, CNT
- * interpretation:
- * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers
- * (or CNT[26:0] for 32b timers)
- * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the
- * dither part for 16b timers
- * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the
- * dither part for 16b timers
- * - ARR and CCRx values are limited to 0xFFEF in dithering mode
- * (corresponds to 4094 for the integer part and 15 for the dithered
- * part).
- * @note Disabling dithering, modifies automatically values of registers
- * ARR/CCRx to keep the same integer part. So it may be necessary to read ARR
- * value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
- * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field
- * htim->Init.Period .
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the pulse on compare pulse width and pulse prescaler
- * @param htim TIM Output Compare handle
- * @param PulseWidthPrescaler Pulse width prescaler
- * This parameter can be a number between Min_Data = 0x0 and Max_Data =
- * 0x7
- * @param PulseWidth Pulse width
- * This parameter can be a number between Min_Data = 0x00 and Max_Data =
- * 0xFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(
- TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
- uint32_t PulseWidth) {
- uint32_t tmpecr;
-
- /* Check the parameters */
- assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
- assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Get the TIMx ECR register value */
- tmpecr = htim->Instance->ECR;
- /* Reset the Pulse width prescaler and the Pulse width */
- tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
- /* Set the Pulse width prescaler and Pulse width*/
- tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
- tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
- /* Write to TIMx ECR */
- htim->Instance->ECR = tmpecr;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure preload source of Slave Mode Selection bitfield (SMS in
- * SMCR register)
- * @param htim TIM handle
- * @param Source Source of slave mode selection preload
- * This parameter can be one of the following values:
- * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as
- * source of Slave Mode Selection preload
- * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as
- * source of Slave Mode Selection preload
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim,
- uint32_t Source) {
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
-
- MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
- return HAL_OK;
-}
-
-/**
- * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR
- * register)
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-
- SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
- return HAL_OK;
-}
-
-/**
- * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR
- * register)
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-
- CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
- return HAL_OK;
-}
-
-/**
- * @brief Enable deadtime preload
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-
- SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
- return HAL_OK;
-}
-
-/**
- * @brief Disable deadtime preload
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-
- CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
- return HAL_OK;
-}
-
-/**
- * @brief Configure deadtime
- * @param htim TIM handle
- * @param Deadtime Deadtime value
- * @note This parameter can be a number between Min_Data = 0x00 and Max_Data =
- * 0xFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim,
- uint32_t Deadtime) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DEADTIME(Deadtime));
-
- MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
- return HAL_OK;
-}
-
-/**
- * @brief Configure asymmetrical deadtime
- * @param htim TIM handle
- * @param FallingDeadtime Falling edge deadtime value
- * @note This parameter can be a number between Min_Data = 0x00 and Max_Data =
- * 0xFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(
- TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DEADTIME(FallingDeadtime));
-
- MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
- return HAL_OK;
-}
-
-/**
- * @brief Enable asymmetrical deadtime
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(
- TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-
- SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
- return HAL_OK;
-}
-
-/**
- * @brief Disable asymmetrical deadtime
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(
- TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-
- CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
- return HAL_OK;
-}
-
-/**
- * @brief Configures the encoder index.
- * @note warning in case of encoder mode clock plus direction
- * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref
- * TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 Direction must be set to @ref
- * TIM_ENCODERINDEX_DIRECTION_UP_DOWN
- * @param htim TIM handle.
- * @param sEncoderIndexConfig Encoder index configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(
- TIM_HandleTypeDef *htim,
- TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
- assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
- assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
- assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
- assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
- assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Configures the TIMx External Trigger (ETR) which is used as Index input */
- TIM_ETR_SetConfig(htim->Instance, sEncoderIndexConfig->Prescaler,
- sEncoderIndexConfig->Polarity, sEncoderIndexConfig->Filter);
-
- /* Configures the encoder index */
- MODIFY_REG(htim->Instance->ECR,
- TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
- (sEncoderIndexConfig->Direction |
- ((sEncoderIndexConfig->FirstIndexEnable == ENABLE)
- ? (0x1U << TIM_ECR_FIDX_Pos)
- : 0U) |
- sEncoderIndexConfig->Position | TIM_ECR_IE));
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable encoder index
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
- return HAL_OK;
-}
-
-/**
- * @brief Disable encoder index
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
- return HAL_OK;
-}
-
-/**
- * @brief Enable encoder first index
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
- return HAL_OK;
-}
-
-/**
- * @brief Disable encoder first index
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) {
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Callbacks functions #####
- ==============================================================================
- [..]
- This section provides Extended TIM callback functions:
- (+) Timer Commutation callback
- (+) Timer Break callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
-/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Encoder index callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_EncoderIndexCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Direction change callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_DirectionChangeCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @brief Index error callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_IndexErrorCallback could be implemented in the user
- file
- */
-}
-
-/**
- * @brief Transition error callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_TransitionErrorCallback could be implemented in the
- user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State
-functions
- * @brief Extended Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Hall Sensor interface handle state.
- * @param htim TIM Hall Sensor handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) {
- return htim->State;
-}
-
-/**
- * @brief Return actual state of the TIM complementary channel.
- * @param htim TIM handle
- * @param ChannelN TIM Complementary channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @retval TIM Complementary channel state
- */
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,
- uint32_t ChannelN) {
- HAL_TIM_ChannelStateTypeDef channel_state;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
-
- channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
- return channel_state;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
- * @{
- */
-
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Commutation half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationHalfCpltCallback(htim);
-#else
- HAL_TIMEx_CommutHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback (complementary channel).
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL) {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- } else {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA error callback (complementary channel)
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) {
- TIM_HandleTypeDef *htim =
- (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- } else {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
-#else
- HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
- * @retval None
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
- uint32_t ChannelNState) {
- uint32_t tmp;
-
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |=
- (uint32_t)(ChannelNState
- << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal break and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Time Output Compare/PWM Channel Configuration (for channels 5
+ and 6)
+ * + Time OCRef clear configuration
+ * + Timer remapping capabilities configuration
+ * + Timer encoder index configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and
+ to interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known
+ state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+ (#) In case of Pulse on compare, configure pulse length and delay
+ (#) Encoder index configuration
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following
+ functions depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following
+ function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using
+ HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is
+ the internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done
+ before any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to
+ use the Timer Hall Sensor Interface and the commutation event with the
+ corresponding Interrupt and DMA request if needed (Note that One Timer is used
+ to interface with the Hall sensor Interface and another Timer should be used
+ to use the commutation event).
+ (#) In case of Pulse On Compare:
+ (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width
+ and prescaler
+
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(),
+ HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(),
+ HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output :
+ HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(),
+ HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+ * @{
+ */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor
+functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the
+ * associated handle.
+ * @note When the timer instance is initialized in Hall Sensor Interface mode,
+ * timer channels 1 and channel 2 are reserved and cannot be used for
+ * other purpose.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param sConfig TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(
+ TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) {
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->HallSensor_MspInitCallback == NULL) {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three
+ * Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC,
+ sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection
+ */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->HallSensor_MspDeInitCallback == NULL) {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) {
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are
+ TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the three possible channels that can be used are
+ TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) {
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are
+ TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are
+ TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to
+ * memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t *pData,
+ uint16_t Length) {
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel state */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
+ (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
+ return HAL_BUSY;
+ } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
+ (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are
+ TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the DMA channel for Capture 1*/
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1],
+ (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are
+ TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary
+Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM
+ * peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel,
+ const uint32_t *pData,
+ uint16_t Length) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) ==
+ HAL_TIM_CHANNEL_STATE_READY) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM
+functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically
+ * done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM
+ * peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel,
+ const uint32_t *pData,
+ uint16_t Length) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
+ return HAL_BUSY;
+ } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) ==
+ HAL_TIM_CHANNEL_STATE_READY) {
+ if ((pData == NULL) || (Length == 0U)) {
+ return HAL_ERROR;
+ } else {
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ } else {
+ return HAL_ERROR;
+ }
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback =
+ TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData,
+ (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is
+ * automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
+ __HAL_TIM_ENABLE(htim);
+ }
+ } else {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel) {
+ case TIM_CHANNEL_1: {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2: {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3: {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4: {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK) {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One
+Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complementary
+ * output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to enable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ uint32_t input_channel =
+ (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture
+ * channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ uint32_t input_channel =
+ (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output channel and the Input Capture
+ * channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to enable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ uint32_t input_channel =
+ (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state =
+ TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state =
+ TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
+ (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture
+ * channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim,
+ uint32_t OutputChannel) {
+ uint32_t input_channel =
+ (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output channel and the Input Capture
+ * channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control
+functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor
+interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Select timer input source.
+ (+) Enable or disable channel grouping.
+ (+) Configure Pulse on compare.
+ (+) Configure Encoder index.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI
+ * input of the Timer, the typical use of this feature is with the use of
+ * another Timer(interface Timer) configured in Hall sensor interface, this
+ * interface Timer will generate the commutation at its TRGO output (connected
+ * to Timer used in this function) each time the TI1 of the Interface Timer
+ * detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer
+ * Interfacing with the Hall sensor This parameter can be one of the following
+ * values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
+ * @arg TIM_TS_ITR5: Internal trigger 5 selected
+ * @arg TIM_TS_ITR6: Internal trigger 6 selected
+ * @arg TIM_TS_ITR7: Internal trigger 7 selected
+ * @arg TIM_TS_ITR8: Internal trigger 8 selected
+ * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
+ * @arg TIM_TS_ITR10: Internal trigger 10 selected
+ * @arg TIM_TS_ITR11: Internal trigger 11 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ *
+ * (*) Value not defined in all devices.
+ *
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the
+ * Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by
+ * software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim,
+ uint32_t InputTrigger,
+ uint32_t CommutationSource) {
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(
+ IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+ __HAL_LOCK(htim);
+
+#if defined(TIM5) && defined(TIM20)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
+ (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM5)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM20)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
+ (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
+ (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
+#else
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
+ (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
+ (InputTrigger == TIM_TS_ITR11))
+#endif /* TIM5 && TIM20 */
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI
+ * input of the Timer, the typical use of this feature is with the use of
+ * another Timer(interface Timer) configured in Hall sensor interface, this
+ * interface Timer will generate the commutation at its TRGO output (connected
+ * to Timer used in this function) each time the TI1 of the Interface Timer
+ * detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer
+ * Interfacing with the Hall sensor This parameter can be one of the following
+ * values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
+ * @arg TIM_TS_ITR5: Internal trigger 5 selected
+ * @arg TIM_TS_ITR6: Internal trigger 6 selected
+ * @arg TIM_TS_ITR7: Internal trigger 7 selected
+ * @arg TIM_TS_ITR8: Internal trigger 8 selected
+ * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
+ * @arg TIM_TS_ITR10: Internal trigger 10 selected
+ * @arg TIM_TS_ITR11: Internal trigger 11 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ *
+ * (*) Value not defined in all devices.
+ *
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the
+ * Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by
+ * software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim,
+ uint32_t InputTrigger,
+ uint32_t CommutationSource) {
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(
+ IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+ __HAL_LOCK(htim);
+
+#if defined(TIM5) && defined(TIM20)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
+ (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM5)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM20)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
+ (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
+ (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
+#else
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
+ (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
+ (InputTrigger == TIM_TS_ITR11))
+#endif /* TIM5 && TIM20 */
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI
+ * input of the Timer, the typical use of this feature is with the use of
+ * another Timer(interface Timer) configured in Hall sensor interface, this
+ * interface Timer will generate the commutation at its TRGO output (connected
+ * to Timer used in this function) each time the TI1 of the Interface Timer
+ * detect a commutation at its input TI1.
+ * @note The user should configure the DMA in his own software, in This
+ * function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer
+ * Interfacing with the Hall sensor This parameter can be one of the following
+ * values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
+ * @arg TIM_TS_ITR5: Internal trigger 5 selected
+ * @arg TIM_TS_ITR6: Internal trigger 6 selected
+ * @arg TIM_TS_ITR7: Internal trigger 7 selected
+ * @arg TIM_TS_ITR8: Internal trigger 8 selected
+ * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
+ * @arg TIM_TS_ITR10: Internal trigger 10 selected
+ * @arg TIM_TS_ITR11: Internal trigger 11 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ *
+ * (*) Value not defined in all devices.
+ *
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the
+ * Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by
+ * software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim,
+ uint32_t InputTrigger,
+ uint32_t CommutationSource) {
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(
+ IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+ __HAL_LOCK(htim);
+
+#if defined(TIM5) && defined(TIM20)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
+ (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM5)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
+ (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
+ (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM20)
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
+ (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
+ (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
+#else
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
+ (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
+ (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
+ (InputTrigger == TIM_TS_ITR11))
+#endif /* TIM5 && TIM20 */
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =
+ TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =
+ TIMEx_DMACommutationHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(
+ TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) {
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master
+ * mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
+ * structure that contains the BDTR Register configuration information for the
+ * TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT
+ * macro.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(
+ TIM_HandleTypeDef *htim,
+ const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) {
+ /* Keep this variable initialized to 0 as it is used to configure BDTR
+ * register */
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ assert_param(
+ IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF,
+ (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+ /* Set the BREAK2 input related BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F,
+ (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+ }
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the break input source.
+ * @param htim TIM handle.
+ * @param BreakInput Break input to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @param sBreakInputConfig Break input source configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(
+ TIM_HandleTypeDef *htim, uint32_t BreakInput,
+ const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmporx;
+ uint32_t bkin_enable_mask;
+ uint32_t bkin_polarity_mask;
+ uint32_t bkin_enable_bitpos;
+ uint32_t bkin_polarity_bitpos;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ switch (sBreakInputConfig->Source) {
+ case TIM_BREAKINPUTSOURCE_BKIN: {
+ bkin_enable_mask = TIM1_AF1_BKINE;
+ bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKINP;
+ bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+ break;
+ }
+ case TIM_BREAKINPUTSOURCE_COMP1: {
+ bkin_enable_mask = TIM1_AF1_BKCMP1E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+ break;
+ }
+#if defined(COMP2)
+ case TIM_BREAKINPUTSOURCE_COMP2: {
+ bkin_enable_mask = TIM1_AF1_BKCMP2E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+ break;
+ }
+#endif /* COMP2 */
+ case TIM_BREAKINPUTSOURCE_COMP3: {
+ bkin_enable_mask = TIM1_AF1_BKCMP3E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKCMP3P;
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
+ break;
+ }
+#if defined(COMP4)
+ case TIM_BREAKINPUTSOURCE_COMP4: {
+ bkin_enable_mask = TIM1_AF1_BKCMP4E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKCMP4P;
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
+ break;
+ }
+#endif /* COMP4 */
+#if defined(COMP5)
+ case TIM_BREAKINPUTSOURCE_COMP5: {
+ bkin_enable_mask = TIM1_AF1_BKCMP5E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
+ /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its
+ * default value 0 */
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+#endif /* COMP5 */
+#if defined(COMP6)
+ case TIM_BREAKINPUTSOURCE_COMP6: {
+ bkin_enable_mask = TIM1_AF1_BKCMP6E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
+ /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its
+ * default value 0 */
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+#endif /* COMP7 */
+#if defined(COMP7)
+ case TIM_BREAKINPUTSOURCE_COMP7: {
+ bkin_enable_mask = TIM1_AF1_BKCMP7E;
+ bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
+ /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its
+ * default value 0 */
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+#endif /* COMP7 */
+
+ default: {
+ bkin_enable_mask = 0U;
+ bkin_polarity_mask = 0U;
+ bkin_enable_bitpos = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+ }
+
+ switch (BreakInput) {
+ case TIM_BREAKINPUT_BRK: {
+ /* Get the TIMx_AF1 register value */
+ tmporx = htim->Instance->AF1;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |=
+ (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) &
+ bkin_polarity_mask;
+
+ /* Set TIMx_AF1 */
+ htim->Instance->AF1 = tmporx;
+ break;
+ }
+ case TIM_BREAKINPUT_BRK2: {
+ /* Get the TIMx_AF2 register value */
+ tmporx = htim->Instance->AF2;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |=
+ (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) &
+ bkin_polarity_mask;
+
+ /* Set TIMx_AF2 */
+ htim->Instance->AF2 = tmporx;
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Configures the TIMx Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ * For TIM1, the parameter can take one of the following values:
+ * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
+ * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1
+ * output
+ * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2
+ * output
+ * @arg TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3
+ * output
+ * @arg TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4
+ * output
+ * @arg TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1
+ * AWD1
+ * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1
+ * AWD2
+ * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1
+ * AWD3
+ * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4
+ * AWD1 (*)
+ * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4
+ * AWD2 (*)
+ * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4
+ * AWD3 (*)
+ *
+ * For TIM2, the parameter can take one of the following values:
+ * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
+ * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1
+ * output
+ * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2
+ * output
+ * @arg TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3
+ * output
+ * @arg TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4
+ * output
+ * @arg TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR
+ * pin
+ * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR
+ * pin
+ * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR
+ * pin (*)
+ * @arg TIM_TIM2_ETR_LSE
+ *
+ * For TIM3, the parameter can take one of the following values:
+ * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
+ * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1
+ * output
+ * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2
+ * output
+ * @arg TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3
+ * output
+ * @arg TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4
+ * output
+ * @arg TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR
+ * pin
+ * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR
+ * pin
+ * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2
+ * AWD1
+ * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2
+ * AWD2
+ * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2
+ * AWD3
+ *
+ * For TIM4, the parameter can take one of the following values:
+ * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
+ * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1
+ * output
+ * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2
+ * output
+ * @arg TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3
+ * output
+ * @arg TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4
+ * output
+ * @arg TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR
+ * pin
+ * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR
+ * pin (*)
+ *
+ * For TIM5, the parameter can take one of the following values: (**)
+ * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*)
+ * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1
+ * output (*)
+ * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2
+ * output (*)
+ * @arg TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3
+ * output (*)
+ * @arg TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4
+ * output (*)
+ * @arg TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR
+ * pin (*)
+ * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR
+ * pin (*)
+ *
+ * For TIM8, the parameter can take one of the following values:
+ * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
+ * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1
+ * output
+ * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2
+ * output
+ * @arg TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3
+ * output
+ * @arg TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4
+ * output
+ * @arg TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2
+ * AWD1
+ * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2
+ * AWD2
+ * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2
+ * AWD3
+ * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3
+ * AWD1 (*)
+ * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3
+ * AWD2 (*)
+ * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3
+ * AWD3 (*)
+ *
+ * For TIM20, the parameter can take one of the following values: (**)
+ * @arg TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO
+ * @arg TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1
+ * output (*)
+ * @arg TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2
+ * output (*)
+ * @arg TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3
+ * output (*)
+ * @arg TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4
+ * output (*)
+ * @arg TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5
+ * output (*)
+ * @arg TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6
+ * output (*)
+ * @arg TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7
+ * output (*)
+ * @arg TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3
+ * AWD1 (*)
+ * @arg TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3
+ * AWD2 (*)
+ * @arg TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3
+ * AWD3 (*)
+ * @arg TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5
+ * AWD1 (*)
+ * @arg TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5
+ * AWD2 (*)
+ * @arg TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5
+ * AWD3 (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim,
+ uint32_t Remap) {
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+ __HAL_LOCK(htim);
+
+ MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select the timer input source
+ * @param htim TIM handle.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TI1 input channel
+ * @arg TIM_CHANNEL_2: TI2 input channel
+ * @arg TIM_CHANNEL_3: TI3 input channel
+ * @arg TIM_CHANNEL_4: TI4 input channel
+ * @param TISelection specifies the timer input source
+ * For TIM1 this parameter can be one of the following values:
+ * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to
+ COMP1 output
+ * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to
+ COMP2 output
+ * @arg TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to
+ COMP3 output
+ * @arg TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to
+ COMP4 output
+ *
+ * For TIM2 this parameter can be one of the following values:
+ * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to
+ COMP1 output
+ * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to
+ COMP2 output
+ * @arg TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to
+ COMP3 output
+ * @arg TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to
+ COMP4 output
+ * @arg TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to
+ COMP5 output (*)
+ *
+ * @arg TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to
+ GPIO
+ * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to
+ COMP1 output
+ * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to
+ COMP2 output
+ * @arg TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to
+ COMP3 output
+ * @arg TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to
+ COMP4 output
+ * @arg TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to
+ COMP6 output (*)
+ *
+ * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to
+ GPIO
+ * @arg TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to
+ COMP4 output
+ *
+ * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to
+ GPIO
+ * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to
+ COMP1 output
+ * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to
+ COMP2 output
+ *
+ * For TIM3 this parameter can be one of the following values:
+ * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to
+ COMP1 output
+ * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to
+ COMP2 output
+ * @arg TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to
+ COMP3 output
+ * @arg TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to
+ COMP4 output
+ * @arg TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to
+ COMP7 output (*)
+ *
+ * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to
+ GPIO
+ * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to
+ COMP1 output
+ * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to
+ COMP2 output
+ * @arg TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to
+ COMP3 output
+ * @arg TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to
+ COMP4 output
+ * @arg TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to
+ COMP7 output (*)
+ *
+ * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to
+ GPIO
+ * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to
+ COMP3 output
+ *
+ * For TIM4 this parameter can be one of the following values:
+ * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to
+ COMP1 output
+ * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to
+ COMP2 output
+ * @arg TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to
+ COMP3 output
+ * @arg TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to
+ COMP4 output
+ * @arg TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to
+ COMP7 output (*)
+ *
+ * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to
+ GPIO
+ * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to
+ COMP1 output
+ * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to
+ COMP2 output
+ * @arg TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to
+ COMP3 output
+ * @arg TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to
+ COMP4 output
+ * @arg TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to
+ COMP7 output (*)
+ *
+ * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to
+ GPIO
+ * @arg TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to
+ COMP5 output (*)
+ *
+ * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to
+ GPIO
+ * @arg TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to
+ COMP6 output (*)
+ *
+ * For TIM5 this parameter can be one of the following values: (**)
+ * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to
+ LSI clock (*)
+ * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to
+ LSE clock (*)
+ * @arg TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to
+ RTC Wakeup (*)
+ * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to
+ COMP1 output (*)
+ * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to
+ COMP2 output (*)
+ * @arg TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to
+ COMP3 output (*)
+ * @arg TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to
+ COMP4 output (*)
+ * @arg TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to
+ COMP7 output (*)
+ *
+ * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to
+ GPIO
+ * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to
+ COMP1 output
+ * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to
+ COMP2 output
+ * @arg TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to
+ COMP3 output
+ * @arg TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to
+ COMP4 output
+ * @arg TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to
+ COMP7 output (*)
+ *
+ * For TIM8 this parameter can be one of the following values:
+ * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to
+ COMP1 output
+ * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to
+ COMP2 output
+ * @arg TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to
+ COMP3 output
+ * @arg TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to
+ COMP4 output
+ *
+ * For TIM15 this parameter can be one of the following values:
+ * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to
+ LSE clock
+ * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to
+ COMP1 output
+ * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to
+ COMP2 output
+ * @arg TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to
+ COMP7 output (*)
+ *
+ * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to
+ GPIO
+ * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to
+ COMP2 output
+ * @arg TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to
+ COMP3 output
+ * @arg TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to
+ COMP7 output (*)
+ *
+ * For TIM16 this parameter can be one of the following values:
+ * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to
+ COMP6 output (*)
+ * @arg TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to
+ MCO output
+ * @arg TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to
+ HSE div 32
+ * @arg TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to
+ RTC wakeup
+ * @arg TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to
+ LSE clock
+ * @arg TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to
+ LSI clock
+ *
+ * For TIM17 this parameter can be one of the following values:
+ * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to
+ COMP5 output (*)
+ * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to
+ MCO output
+ * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to
+ HSE div 32
+ * @arg TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to
+ RTC wakeup
+ * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to
+ LSE clock
+ * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to
+ LSI clock
+
+ * For TIM20 this parameter can be one of the following values: (**)
+ * @arg TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to
+ GPIO
+ * @arg TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to
+ COMP1 output (*)
+ * @arg TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to
+ COMP2 output (*)
+ * @arg TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to
+ COMP3 output (*)
+ * @arg TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to
+ COMP4 output (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim,
+ uint32_t TISelection,
+ uint32_t Channel) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_TISEL(TISelection));
+
+ __HAL_LOCK(htim);
+
+ switch (Channel) {
+ case TIM_CHANNEL_1:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+
+ /* If required, set OR bit to request HSE/32 clock */
+ if (IS_TIM_HSE32_INSTANCE(htim->Instance)) {
+ SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
+ } else {
+ CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
+ }
+ break;
+ case TIM_CHANNEL_2:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+ break;
+ case TIM_CHANNEL_3:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+ break;
+ case TIM_CHANNEL_4:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Group channel 5 and channel 1, 2 or 3
+ * @param htim TIM handle.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined
+ * with. This parameter can be any combination of the following values:
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and
+ * OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and
+ * OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and
+ * OC5REF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim,
+ uint32_t Channels) {
+ /* Check parameters */
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_GROUPCH5(Channels));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Clear GC5Cx bit fields */
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+ /* Set GC5Cx bit fields */
+ htim->Instance->CCR5 |= Channels;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disarm the designated break input (when it operates in bidirectional
+ * mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to disarm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim,
+ uint32_t BreakInput) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpbdtr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput) {
+ case TIM_BREAKINPUT_BRK: {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+ }
+ break;
+ }
+ case TIM_BREAKINPUT_BRK2: {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Arm the designated break input (when it operates in bidirectional
+ * mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to arm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note Arming is possible at anytime, even if fault is present.
+ * @note Break input is automatically armed as soon as MOE bit is set.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim,
+ uint32_t BreakInput) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput) {
+ case TIM_BREAKINPUT_BRK: {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) {
+ /* Break input BRK is re-armed automatically by hardware. Poll to check
+ * whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption
+ */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2: {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) {
+ /* Break input BRK2 is re-armed automatically by hardware. Poll to check
+ * whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) {
+ /* New check to avoid false timeout detection in case of preemption
+ */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable dithering
+ * @param htim TIM handle
+ * @note Main usage is PWM mode
+ * @note This function must be called when timer is stopped or disabled (CEN
+ * =0)
+ * @note If dithering is activated, pay attention to ARR, CCRx, CNT
+ * interpretation:
+ * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers
+ * (or CNT[26:0] for 32b timers)
+ * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the
+ * dither part for 16b timers
+ * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the
+ * dither part for 16b timers
+ * - ARR and CCRx values are limited to 0xFFEF in dithering mode for
+ * 16b timers (corresponds to 4094 for the integer part and 15 for the dithered
+ * part).
+ * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER()
+ * __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() can be used to
+ * calculate period (ARR) and delay (CCRx) value.
+ * @note Enabling dithering, modifies automatically values of registers
+ * ARR/CCRx to keep the same integer part.
+ * @note Enabling dithering, modifies automatically values of registers
+ * ARR/CCRx to keep the same integer part. So it may be necessary to read ARR
+ * value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+ * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field
+ * htim->Init.Period .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable dithering
+ * @param htim TIM handle
+ * @note This function must be called when timer is stopped or disabled (CEN
+ * =0)
+ * @note If dithering is activated, pay attention to ARR, CCRx, CNT
+ * interpretation:
+ * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers
+ * (or CNT[26:0] for 32b timers)
+ * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the
+ * dither part for 16b timers
+ * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the
+ * dither part for 16b timers
+ * - ARR and CCRx values are limited to 0xFFEF in dithering mode
+ * (corresponds to 4094 for the integer part and 15 for the dithered
+ * part).
+ * @note Disabling dithering, modifies automatically values of registers
+ * ARR/CCRx to keep the same integer part. So it may be necessary to read ARR
+ * value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+ * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field
+ * htim->Init.Period .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the pulse on compare pulse width and pulse prescaler
+ * @param htim TIM Output Compare handle
+ * @param PulseWidthPrescaler Pulse width prescaler
+ * This parameter can be a number between Min_Data = 0x0 and Max_Data =
+ * 0x7
+ * @param PulseWidth Pulse width
+ * This parameter can be a number between Min_Data = 0x00 and Max_Data =
+ * 0xFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(
+ TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
+ uint32_t PulseWidth) {
+ uint32_t tmpecr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
+ assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx ECR register value */
+ tmpecr = htim->Instance->ECR;
+ /* Reset the Pulse width prescaler and the Pulse width */
+ tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
+ /* Set the Pulse width prescaler and Pulse width*/
+ tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
+ tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+ /* Write to TIMx ECR */
+ htim->Instance->ECR = tmpecr;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure preload source of Slave Mode Selection bitfield (SMS in
+ * SMCR register)
+ * @param htim TIM handle
+ * @param Source Source of slave mode selection preload
+ * This parameter can be one of the following values:
+ * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as
+ * source of Slave Mode Selection preload
+ * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as
+ * source of Slave Mode Selection preload
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim,
+ uint32_t Source) {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
+
+ MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR
+ * register)
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR
+ * register)
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable deadtime preload
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable deadtime preload
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure deadtime
+ * @param htim TIM handle
+ * @param Deadtime Deadtime value
+ * @note This parameter can be a number between Min_Data = 0x00 and Max_Data =
+ * 0xFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim,
+ uint32_t Deadtime) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DEADTIME(Deadtime));
+
+ MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure asymmetrical deadtime
+ * @param htim TIM handle
+ * @param FallingDeadtime Falling edge deadtime value
+ * @note This parameter can be a number between Min_Data = 0x00 and Max_Data =
+ * 0xFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(
+ TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DEADTIME(FallingDeadtime));
+
+ MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable asymmetrical deadtime
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(
+ TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable asymmetrical deadtime
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(
+ TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the encoder index.
+ * @note warning in case of encoder mode clock plus direction
+ * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref
+ * TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 Direction must be set to @ref
+ * TIM_ENCODERINDEX_DIRECTION_UP_DOWN
+ * @param htim TIM handle.
+ * @param sEncoderIndexConfig Encoder index configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(
+ TIM_HandleTypeDef *htim,
+ TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
+ assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
+ assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
+ assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
+ assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
+ assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Configures the TIMx External Trigger (ETR) which is used as Index input */
+ TIM_ETR_SetConfig(htim->Instance, sEncoderIndexConfig->Prescaler,
+ sEncoderIndexConfig->Polarity, sEncoderIndexConfig->Filter);
+
+ /* Configures the encoder index */
+ MODIFY_REG(htim->Instance->ECR,
+ TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ (sEncoderIndexConfig->Direction |
+ ((sEncoderIndexConfig->FirstIndexEnable == ENABLE)
+ ? (0x1U << TIM_ECR_FIDX_Pos)
+ : 0U) |
+ sEncoderIndexConfig->Position | TIM_ECR_IE));
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable encoder index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable encoder index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable encoder first index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable encoder first index
+ * @param htim TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) {
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extended TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Commutation callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Commutation half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Break detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Encoder index callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_EncoderIndexCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Direction change callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_DirectionChangeCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Index error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_IndexErrorCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Transition error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_TransitionErrorCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State
+functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface handle state.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(
+ const TIM_HandleTypeDef *htim) {
+ return htim->State;
+}
+
+/**
+ * @brief Return actual state of the TIM complementary channel.
+ * @param htim TIM handle
+ * @param ChannelN TIM Complementary channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @retval TIM Complementary channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(
+ const TIM_HandleTypeDef *htim, uint32_t ChannelN) {
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+ channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+ return channel_state;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback (complementary channel).
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL) {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ } else {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback (complementary channel)
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) {
+ TIM_HandleTypeDef *htim =
+ (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ } else {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel,
+ uint32_t ChannelNState) {
+ uint32_t tmp;
+
+ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState
+ << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
index 4beab01..538c131 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
@@ -1,4440 +1,4513 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_uart.c
- * @author MCD Application Team
- * @brief UART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter
- Peripheral (UART).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- *
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The UART HAL driver can be used as follows:
-
- (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef
- huart).
- (#) Initialize the UART low level resources by implementing the
- HAL_UART_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) UART pins configuration:
- (+++) Enable the clock for the UART GPIOs.
- (+++) Configure these UART pins as alternate function pull-up.
- (++) NVIC configuration if you need to use interrupt process
- (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) UART interrupts handling:
- -@@- The specific UART interrupts (Transmission complete
- interrupt, RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
- are managed using the macros __HAL_UART_ENABLE_IT() and
- __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
- (++) DMA Configuration if you need to use DMA process
- (HAL_UART_Transmit_DMA() and HAL_UART_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required
- Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx
- handle.
- (+++) Configure the priority and enable the NVIC for the transfer
- complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value ,
- Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init
- structure.
-
- (#) If required, program UART advanced features (TX/RX pins swap, auto Baud
- rate detection,...) in the huart handle AdvancedInit structure.
-
- (#) For the UART asynchronous mode, initialize the UART registers by calling
- the HAL_UART_Init() API.
-
- (#) For the UART Half duplex mode, initialize the UART registers by calling
- the HAL_HalfDuplex_Init() API.
-
- (#) For the UART LIN (Local Interconnection Network) mode, initialize the
- UART registers by calling the HAL_LIN_Init() API.
-
- (#) For the UART Multiprocessor mode, initialize the UART registers
- by calling the HAL_MultiProcessor_Init() API.
-
- (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
- [..]
- (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(),
- HAL_MultiProcessor_Init(), also configure the low level Hardware GPIO, CLOCK,
- CORTEX...etc) by calling the customized HAL_UART_MspInit() API.
-
- ##### Callback registration #####
- ==================================
-
- [..]
- The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- [..]
- Use Function HAL_UART_RegisterCallback() to register a user callback.
- Function HAL_UART_RegisterCallback() allows to register following callbacks:
- (+) TxHalfCpltCallback : Tx Half Complete Callback.
- (+) TxCpltCallback : Tx Complete Callback.
- (+) RxHalfCpltCallback : Rx Half Complete Callback.
- (+) RxCpltCallback : Rx Complete Callback.
- (+) ErrorCallback : Error Callback.
- (+) AbortCpltCallback : Abort Complete Callback.
- (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
- (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
- (+) WakeupCallback : Wakeup Callback.
- (+) RxFifoFullCallback : Rx Fifo Full Callback.
- (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
- (+) MspInitCallback : UART MspInit.
- (+) MspDeInitCallback : UART MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
- [..]
- Use function HAL_UART_UnRegisterCallback() to reset a callback to the
- default weak (surcharged) function. HAL_UART_UnRegisterCallback() takes as
- parameters the HAL peripheral handle, and the Callback ID. This function allows
- to reset following callbacks:
- (+) TxHalfCpltCallback : Tx Half Complete Callback.
- (+) TxCpltCallback : Tx Complete Callback.
- (+) RxHalfCpltCallback : Rx Half Complete Callback.
- (+) RxCpltCallback : Rx Complete Callback.
- (+) ErrorCallback : Error Callback.
- (+) AbortCpltCallback : Abort Complete Callback.
- (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
- (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
- (+) WakeupCallback : Wakeup Callback.
- (+) RxFifoFullCallback : Rx Fifo Full Callback.
- (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
- (+) MspInitCallback : UART MspInit.
- (+) MspDeInitCallback : UART MspDeInit.
-
- [..]
- For specific callback RxEventCallback, use dedicated registration/reset
- functions: respectively HAL_UART_RegisterRxEventCallback() ,
- HAL_UART_UnRegisterRxEventCallback().
-
- [..]
- By default, after the HAL_UART_Init() and when the state is
- HAL_UART_STATE_RESET all callbacks are set to the corresponding weak
- (surcharged) functions: examples HAL_UART_TxCpltCallback(),
- HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit
- functions that are respectively reset to the legacy weak (surcharged) functions
- in the HAL_UART_Init() and HAL_UART_DeInit() only when these callbacks are null
- (not registered beforehand). If not, MspInit or MspDeInit are not null, the
- HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit
- callbacks (registered beforehand).
-
- [..]
- Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered
- (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that
- case first register the MspInit/MspDeInit user callbacks using
- HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() or HAL_UART_Init()
- function.
-
- [..]
- When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
-
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UART UART
- * @brief HAL UART module driver
- * @{
- */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
- * @{
- */
-#define USART_CR1_FIELDS \
- ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE | USART_CR1_OVER8 | \
- USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters \
- set by UART_SetConfig API */
-
-#define USART_CR3_FIELDS \
- ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | \
- USART_CR3_TXFTCFG | \
- USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters \
- set by UART_SetConfig API */
-
-#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
-#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
-
-#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
-#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
- * @{
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
-static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
-static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
-static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
-static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
-static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup UART_Private_variables
- * @{
- */
-const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U,
- 12U, 16U, 32U, 64U, 128U, 256U};
-/**
- * @}
- */
-
-/* Exported Constants --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and
-de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the
-USARTx or the UARTy in asynchronous mode.
- (+) For the asynchronous mode the parameters below can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data
-written in the data register is transmitted but is changed by the parity bit.
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- (++) One-Bit Sampling Method
- (+) For the asynchronous mode, the following advanced features can be
-configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) auto Baud rate detection
- [..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and
-HAL_MultiProcessor_Init()API follow respectively the UART asynchronous, UART
-Half duplex, UART LIN mode and UART multiprocessor mode configuration procedures
-(details for the procedures are available in reference manual).
-
-@endverbatim
-
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible UART formats are listed in the
- following table.
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Initialize the UART mode according to the specified
- * parameters in the UART_InitTypeDef and initialize the associated
- * handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) {
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
-
- if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) {
- /* Check the parameters */
- assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
- } else {
- /* Check the parameters */
- assert_param((IS_UART_INSTANCE(huart->Instance)) ||
- (IS_LPUART_INSTANCE(huart->Instance)));
- }
-
- if (huart->gState == HAL_UART_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- UART_InitCallbacksToDefault(huart);
-
- if (huart->MspInitCallback == NULL) {
- huart->MspInitCallback = HAL_UART_MspInit;
- }
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR) {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
- * to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Initialize the half-duplex mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) {
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
-
- /* Check UART instance */
- assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-
- if (huart->gState == HAL_UART_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- UART_InitCallbacksToDefault(huart);
-
- if (huart->MspInitCallback == NULL) {
- huart->MspInitCallback = HAL_UART_MspInit;
- }
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR) {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In half-duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
- * to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Initialize the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart UART handle.
- * @param BreakDetectLength Specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
- * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart,
- uint32_t BreakDetectLength) {
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the LIN UART instance */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
- /* Check the Break detection length parameter */
- assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
- /* LIN mode limited to 16-bit oversampling only */
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8) {
- return HAL_ERROR;
- }
- /* LIN mode limited to 8-bit data length */
- if (huart->Init.WordLength != UART_WORDLENGTH_8B) {
- return HAL_ERROR;
- }
-
- if (huart->gState == HAL_UART_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- UART_InitCallbacksToDefault(huart);
-
- if (huart->MspInitCallback == NULL) {
- huart->MspInitCallback = HAL_UART_MspInit;
- }
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR) {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In LIN mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
- CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
- /* Set the USART LIN Break detection length. */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
- * to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Initialize the multiprocessor mode according to the specified
- * parameters in the UART_InitTypeDef and initialize the associated
- * handle.
- * @param huart UART handle.
- * @param Address UART node address (4-, 6-, 7- or 8-bit long).
- * @param WakeUpMethod Specifies the UART wakeup method.
- * This parameter can be one of the following values:
- * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line
- * detection
- * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
- * @note If the user resorts to idle line detection wake up, the Address
- * parameter is useless and ignored by the initialization function.
- * @note If the user resorts to address mark wake up, the address length
- * detection is configured by default to 4 bits only. For the UART to be able to
- * manage 6-, 7- or 8-bit long addresses detection, the API
- * HAL_MultiProcessorEx_AddressLength_Set() must be called after
- * HAL_MultiProcessor_Init().
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart,
- uint8_t Address,
- uint32_t WakeUpMethod) {
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the wake up method parameter */
- assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
- if (huart->gState == HAL_UART_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- UART_InitCallbacksToDefault(huart);
-
- if (huart->MspInitCallback == NULL) {
- huart->MspInitCallback = HAL_UART_MspInit;
- }
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR) {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In multiprocessor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) {
- /* If address mark wake up method is chosen, set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD,
- ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
- }
-
- /* Set the wake up method by setting the WAKE bit in the CR1 register */
- MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
- * to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief DeInitialize the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) {
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param((IS_UART_INSTANCE(huart->Instance)) ||
- (IS_LPUART_INSTANCE(huart->Instance)));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- __HAL_UART_DISABLE(huart);
-
- huart->Instance->CR1 = 0x0U;
- huart->Instance->CR2 = 0x0U;
- huart->Instance->CR3 = 0x0U;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- if (huart->MspDeInitCallback == NULL) {
- huart->MspDeInitCallback = HAL_UART_MspDeInit;
- }
- /* DeInit the low level hardware */
- huart->MspDeInitCallback(huart);
-#else
- /* DeInit the low level hardware */
- HAL_UART_MspDeInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the UART MSP.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the UART MSP.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspDeInit can be implemented in the user file
- */
-}
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User UART Callback
- * To be used instead of the weak predefined callback
- * @param huart uart handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback
- * ID
- * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
- * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback
- * ID
- * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
- * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
- * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit
- * Complete Callback ID
- * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive
- * Complete Callback ID
- * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
- * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
- * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
- * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
- * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_RegisterCallback(
- UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
- pUART_CallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY) {
- switch (CallbackID) {
- case HAL_UART_TX_HALFCOMPLETE_CB_ID:
- huart->TxHalfCpltCallback = pCallback;
- break;
-
- case HAL_UART_TX_COMPLETE_CB_ID:
- huart->TxCpltCallback = pCallback;
- break;
-
- case HAL_UART_RX_HALFCOMPLETE_CB_ID:
- huart->RxHalfCpltCallback = pCallback;
- break;
-
- case HAL_UART_RX_COMPLETE_CB_ID:
- huart->RxCpltCallback = pCallback;
- break;
-
- case HAL_UART_ERROR_CB_ID:
- huart->ErrorCallback = pCallback;
- break;
-
- case HAL_UART_ABORT_COMPLETE_CB_ID:
- huart->AbortCpltCallback = pCallback;
- break;
-
- case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID:
- huart->AbortTransmitCpltCallback = pCallback;
- break;
-
- case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID:
- huart->AbortReceiveCpltCallback = pCallback;
- break;
-
- case HAL_UART_WAKEUP_CB_ID:
- huart->WakeupCallback = pCallback;
- break;
-
- case HAL_UART_RX_FIFO_FULL_CB_ID:
- huart->RxFifoFullCallback = pCallback;
- break;
-
- case HAL_UART_TX_FIFO_EMPTY_CB_ID:
- huart->TxFifoEmptyCallback = pCallback;
- break;
-
- case HAL_UART_MSPINIT_CB_ID:
- huart->MspInitCallback = pCallback;
- break;
-
- case HAL_UART_MSPDEINIT_CB_ID:
- huart->MspDeInitCallback = pCallback;
- break;
-
- default:
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- break;
- }
- } else if (huart->gState == HAL_UART_STATE_RESET) {
- switch (CallbackID) {
- case HAL_UART_MSPINIT_CB_ID:
- huart->MspInitCallback = pCallback;
- break;
-
- case HAL_UART_MSPDEINIT_CB_ID:
- huart->MspDeInitCallback = pCallback;
- break;
-
- default:
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- break;
- }
- } else {
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- }
-
- __HAL_UNLOCK(huart);
-
- return status;
-}
-
-/**
- * @brief Unregister an UART Callback
- * UART callaback is redirected to the weak predefined callback
- * @param huart uart handle
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback
- * ID
- * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
- * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback
- * ID
- * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
- * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
- * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit
- * Complete Callback ID
- * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive
- * Complete Callback ID
- * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
- * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
- * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
- * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
- * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(
- UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) {
- HAL_StatusTypeDef status = HAL_OK;
-
- __HAL_LOCK(huart);
-
- if (HAL_UART_STATE_READY == huart->gState) {
- switch (CallbackID) {
- case HAL_UART_TX_HALFCOMPLETE_CB_ID:
- huart->TxHalfCpltCallback =
- HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- break;
-
- case HAL_UART_TX_COMPLETE_CB_ID:
- huart->TxCpltCallback =
- HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
- break;
-
- case HAL_UART_RX_HALFCOMPLETE_CB_ID:
- huart->RxHalfCpltCallback =
- HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- break;
-
- case HAL_UART_RX_COMPLETE_CB_ID:
- huart->RxCpltCallback =
- HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
- break;
-
- case HAL_UART_ERROR_CB_ID:
- huart->ErrorCallback =
- HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_UART_ABORT_COMPLETE_CB_ID:
- huart->AbortCpltCallback =
- HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- break;
-
- case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID:
- huart->AbortTransmitCpltCallback =
- HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
- AbortTransmitCpltCallback */
- break;
-
- case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID:
- huart->AbortReceiveCpltCallback =
- HAL_UART_AbortReceiveCpltCallback; /* Legacy weak
- AbortReceiveCpltCallback */
- break;
-
- case HAL_UART_WAKEUP_CB_ID:
- huart->WakeupCallback =
- HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
- break;
-
- case HAL_UART_RX_FIFO_FULL_CB_ID:
- huart->RxFifoFullCallback =
- HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
- break;
-
- case HAL_UART_TX_FIFO_EMPTY_CB_ID:
- huart->TxFifoEmptyCallback =
- HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback
- */
- break;
-
- case HAL_UART_MSPINIT_CB_ID:
- huart->MspInitCallback =
- HAL_UART_MspInit; /* Legacy weak MspInitCallback */
- break;
-
- case HAL_UART_MSPDEINIT_CB_ID:
- huart->MspDeInitCallback =
- HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
- break;
-
- default:
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- break;
- }
- } else if (HAL_UART_STATE_RESET == huart->gState) {
- switch (CallbackID) {
- case HAL_UART_MSPINIT_CB_ID:
- huart->MspInitCallback = HAL_UART_MspInit;
- break;
-
- case HAL_UART_MSPDEINIT_CB_ID:
- huart->MspDeInitCallback = HAL_UART_MspDeInit;
- break;
-
- default:
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- break;
- }
- } else {
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- }
-
- __HAL_UNLOCK(huart);
-
- return status;
-}
-
-/**
- * @brief Register a User UART Rx Event Callback
- * To be used instead of the weak predefined callback
- * @param huart Uart handle
- * @param pCallback Pointer to the Rx Event Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(
- UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) {
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL) {
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY) {
- huart->RxEventCallback = pCallback;
- } else {
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(huart);
-
- return status;
-}
-
-/**
- * @brief UnRegister the UART Rx Event Callback
- * UART Rx Event Callback is redirected to the weak
- * HAL_UARTEx_RxEventCallback() predefined callback
- * @param huart Uart handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(
- UART_HandleTypeDef *huart) {
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY) {
- huart->RxEventCallback =
- HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
- } else {
- huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(huart);
- return status;
-}
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
- * @brief UART Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the UART
-asynchronous and Half duplex data transfers.
-
- (#) There are two mode of transfer:
- (+) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same
-function after finishing transfer.
- (+) Non-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user
-callbacks will be executed respectively at the end of the transmit or Receive
-process The HAL_UART_ErrorCallback()user callback will be executed when a
-communication error is detected
-
- (#) Blocking mode API's are :
- (+) HAL_UART_Transmit()
- (+) HAL_UART_Receive()
-
- (#) Non-Blocking mode API's with Interrupt are :
- (+) HAL_UART_Transmit_IT()
- (+) HAL_UART_Receive_IT()
- (+) HAL_UART_IRQHandler()
-
- (#) Non-Blocking mode API's with DMA are :
- (+) HAL_UART_Transmit_DMA()
- (+) HAL_UART_Receive_DMA()
- (+) HAL_UART_DMAPause()
- (+) HAL_UART_DMAResume()
- (+) HAL_UART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
- (+) HAL_UART_TxHalfCpltCallback()
- (+) HAL_UART_TxCpltCallback()
- (+) HAL_UART_RxHalfCpltCallback()
- (+) HAL_UART_RxCpltCallback()
- (+) HAL_UART_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_UART_Abort()
- (+) HAL_UART_AbortTransmit()
- (+) HAL_UART_AbortReceive()
- (+) HAL_UART_Abort_IT()
- (+) HAL_UART_AbortTransmit_IT()
- (+) HAL_UART_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of
-Abort Complete Callbacks are provided:
- (+) HAL_UART_AbortCpltCallback()
- (+) HAL_UART_AbortTransmitCpltCallback()
- (+) HAL_UART_AbortReceiveCpltCallback()
-
- (#) A Rx Event Reception Callback (Rx event notification) is available for
-Non_Blocking modes of enhanced reception services:
- (+) HAL_UARTEx_RxEventCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2
-categories. Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could
-go till end, but error severity is to be evaluated by user : this concerns Frame
-Error, Parity Error or Noise Error in Interrupt mode reception . Received
-character is then retrieved and stored in Rx buffer, Error code is set to allow
-user to identify error type, and HAL_UART_ErrorCallback() user callback is
-executed. Transfer is kept ongoing on UART side. If user wants to abort it,
-Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed
-properly and is aborted. This concerns Overrun Error In Interrupt mode reception
-and all errors in DMA mode. Error code is set to allow user to identify error
-type, and HAL_UART_ErrorCallback() user callback is executed.
-
- -@- In the Half duplex communication, it is forbidden to run the transmit
- and receive process in parallel, the UART state
-HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16.
- * In this case, Size must indicate the number of u16 provided through pData.
- * @note When FIFO mode is enabled, writing a data in the TDR register adds one
- * data to the TXFIFO. Write operations to the TDR register are performed
- * when TXFNF flag is set. From hardware perspective, TXFNF flag and
- * TXE are mapped on the same bit-field.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart,
- const uint8_t *pData, uint16_t Size,
- uint32_t Timeout) {
- const uint8_t *pdata8bits;
- const uint16_t *pdata16bits;
- uint32_t tickstart;
-
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a
- * uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- pdata8bits = NULL;
- pdata16bits = (const uint16_t *)pData;
- } else {
- pdata8bits = pData;
- pdata16bits = NULL;
- }
-
- __HAL_UNLOCK(huart);
-
- while (huart->TxXferCount > 0U) {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart,
- Timeout) != HAL_OK) {
- return HAL_TIMEOUT;
- }
- if (pdata8bits == NULL) {
- huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- pdata16bits++;
- } else {
- huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- pdata8bits++;
- }
- huart->TxXferCount--;
- }
-
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart,
- Timeout) != HAL_OK) {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
- * u16. In this case, Size must indicate the number of u16 available through
- * pData.
- * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
- * is not empty. Read operations from the RDR register are performed when
- * RXFNE flag is set. From hardware perspective, RXFNE flag and
- * RXNE are mapped on the same bit-field.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be received.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData,
- uint16_t Size, uint32_t Timeout) {
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint16_t uhMask;
- uint32_t tickstart;
-
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- uhMask = huart->Mask;
-
- /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a
- * uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- pdata8bits = NULL;
- pdata16bits = (uint16_t *)pData;
- } else {
- pdata8bits = pData;
- pdata16bits = NULL;
- }
-
- __HAL_UNLOCK(huart);
-
- /* as long as data have to be received */
- while (huart->RxXferCount > 0U) {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart,
- Timeout) != HAL_OK) {
- return HAL_TIMEOUT;
- }
- if (pdata8bits == NULL) {
- *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
- pdata16bits++;
- } else {
- *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- pdata8bits++;
- }
- huart->RxXferCount--;
- }
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16.
- * In this case, Size must indicate the number of u16 provided through pData.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart,
- const uint8_t *pData, uint16_t Size) {
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
- huart->TxISR = NULL;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Configure Tx interrupt processing */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- /* Set the Tx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- huart->TxISR = UART_TxISR_16BIT_FIFOEN;
- } else {
- huart->TxISR = UART_TxISR_8BIT_FIFOEN;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the TX FIFO threshold interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- } else {
- /* Set the Tx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- huart->TxISR = UART_TxISR_16BIT;
- } else {
- huart->TxISR = UART_TxISR_8BIT;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the Transmit Data Register Empty interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
- }
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
- * u16. In this case, Size must indicate the number of u16 available through
- * pData.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
- uint16_t Size) {
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- /* Set Reception type to Standard reception */
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- if (!(IS_LPUART_INSTANCE(huart->Instance))) {
- /* Check that USART RTOEN bit is set */
- if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
- /* Enable the UART Receiver Timeout Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
- }
- }
-
- return (UART_Start_Receive_IT(huart, pData, Size));
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16.
- * In this case, Size must indicate the number of u16 provided through pData.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart,
- const uint8_t *pData, uint16_t Size) {
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- if (huart->hdmatx != NULL) {
- /* Set the UART DMA transfer complete callback */
- huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmatx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the UART transmit DMA channel */
- if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr,
- (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- __HAL_UNLOCK(huart);
-
- /* Restore huart->gState to ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_ERROR;
- }
- }
- /* Clear the TC flag in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
-
- __HAL_UNLOCK(huart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
- * u16. In this case, Size must indicate the number of u16 available through
- * pData.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size) {
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- /* Set Reception type to Standard reception */
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- if (!(IS_LPUART_INSTANCE(huart->Instance))) {
- /* Check that USART RTOEN bit is set */
- if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
- /* Enable the UART Receiver Timeout Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
- }
- }
-
- return (UART_Start_Receive_DMA(huart, pData, Size));
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) {
- const HAL_UART_StateTypeDef gstate = huart->gState;
- const HAL_UART_StateTypeDef rxstate = huart->RxState;
-
- __HAL_LOCK(huart);
-
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
- (gstate == HAL_UART_STATE_BUSY_TX)) {
- /* Disable the UART DMA Tx request */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
- (rxstate == HAL_UART_STATE_BUSY_RX)) {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts
- */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) {
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_BUSY_TX) {
- /* Enable the UART DMA Tx request */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
- if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
- /* Clear the Overrun flag before resuming the Rx transfer */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
- /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts
- */
- if (huart->Init.Parity != UART_PARITY_NONE) {
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- }
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the UART DMA Rx request */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) {
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() /
- HAL_UART_RxCpltCallback() / HAL_UART_TxHalfCpltCallback /
- HAL_UART_RxHalfCpltCallback: indeed, when HAL_DMA_Abort() API is called,
- the DMA TX/RX Transfer or Half Transfer complete interrupt is generated if
- the DMA transfer interruption occurs at the middle or at the end of the
- stream and the corresponding call back is executed. */
-
- const HAL_UART_StateTypeDef gstate = huart->gState;
- const HAL_UART_StateTypeDef rxstate = huart->RxState;
-
- /* Stop UART DMA Tx request if ongoing */
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
- (gstate == HAL_UART_STATE_BUSY_TX)) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel */
- if (huart->hdmatx != NULL) {
- if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) {
- if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
- (rxstate == HAL_UART_STATE_BUSY_RX)) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL) {
- if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) {
- if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- UART_EndRxTransfer(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer
- * started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable UART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
- * in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function,
- * Abort is considered as completed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) {
- /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error,
- * overrun error) interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
- USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3,
- USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
-
- /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
- }
-
- /* Abort the UART DMA Tx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
- /* Disable the UART DMA Tx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback)
- */
- if (huart->hdmatx != NULL) {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) {
- if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Abort the UART DMA Rx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- /* Disable the UART DMA Rx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback)
- */
- if (huart->hdmarx != NULL) {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) {
- if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Flush the whole TX FIFO (if needed) */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
- }
-
- /* Discard the received data */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer
- * started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable UART Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
- * in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function,
- * Abort is considered as completed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) {
- /* Disable TCIE, TXEIE and TXFTIE interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Abort the UART DMA Tx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
- /* Disable the UART DMA Tx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback)
- */
- if (huart->hdmatx != NULL) {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) {
- if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Flush the whole TX FIFO (if needed) */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
- }
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer
- * started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable UART Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
- * in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function,
- * Abort is considered as completed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) {
- /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
-
- /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
- }
-
- /* Abort the UART DMA Rx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- /* Disable the UART DMA Rx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback)
- */
- if (huart->hdmarx != NULL) {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) {
- if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Discard the received data */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer
- * started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable UART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
- * transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort
- * procedure could be considered as completed only when user abort complete
- * callback is executed (not when exiting function).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) {
- uint32_t abortcplt = 1U;
-
- /* Disable interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
- USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
-
- /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
- }
-
- /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort
- complete callbacks should be initialised before any call to DMA Abort
- functions */
- /* DMA Tx Handle is valid */
- if (huart->hdmatx != NULL) {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
- huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
- } else {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if (huart->hdmarx != NULL) {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
- } else {
- huart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Abort the UART DMA Tx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
- /* Disable DMA Tx at UART level */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback)
- */
- if (huart->hdmatx != NULL) {
- /* UART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
- procedure */
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) {
- huart->hdmatx->XferAbortCallback = NULL;
- } else {
- abortcplt = 0U;
- }
- }
- }
-
- /* Abort the UART DMA Rx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- /* Disable the UART DMA Rx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback)
- */
- if (huart->hdmarx != NULL) {
- /* UART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
- procedure */
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) {
- huart->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- } else {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort
- * Complete callback */
- if (abortcplt == 1U) {
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- huart->TxISR = NULL;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Flush the whole TX FIFO (if needed) */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
- }
-
- /* Discard the received data */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort complete callback */
- huart->AbortCpltCallback(huart);
-#else
- /* Call legacy weak Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer
- * started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable UART Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
- * transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort
- * procedure could be considered as completed only when user abort complete
- * callback is executed (not when exiting function).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) {
- /* Disable interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Abort the UART DMA Tx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
- /* Disable the UART DMA Tx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback)
- */
- if (huart->hdmatx != NULL) {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
- procedure */
- huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) {
- /* Call Directly huart->hdmatx->XferAbortCallback function in case of
- * error */
- huart->hdmatx->XferAbortCallback(huart->hdmatx);
- }
- } else {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Clear TxISR function pointers */
- huart->TxISR = NULL;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort Transmit Complete Callback */
- huart->AbortTransmitCpltCallback(huart);
-#else
- /* Call legacy weak Abort Transmit Complete Callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- } else {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Clear TxISR function pointers */
- huart->TxISR = NULL;
-
- /* Flush the whole TX FIFO (if needed) */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
- }
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort Transmit Complete Callback */
- huart->AbortTransmitCpltCallback(huart);
-#else
- /* Call legacy weak Abort Transmit Complete Callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer
- * started in Interrupt or DMA mode. This procedure performs following
- * operations :
- * - Disable UART Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
- * transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort
- * procedure could be considered as completed only when user abort complete
- * callback is executed (not when exiting function).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) {
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
- * interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
- }
-
- /* Abort the UART DMA Rx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- /* Disable the UART DMA Rx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback)
- */
- if (huart->hdmarx != NULL) {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
- procedure */
- huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of
- * error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- } else {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear RxISR function pointer */
- huart->pRxBuffPtr = NULL;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Discard the received data */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort Receive Complete Callback */
- huart->AbortReceiveCpltCallback(huart);
-#else
- /* Call legacy weak Abort Receive Complete Callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- } else {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear RxISR function pointer */
- huart->pRxBuffPtr = NULL;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort Receive Complete Callback */
- huart->AbortReceiveCpltCallback(huart);
-#else
- /* Call legacy weak Abort Receive Complete Callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) {
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
-
- uint32_t errorflags;
- uint32_t errorcode;
-
- /* If no error occurs */
- errorflags =
- (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE |
- USART_ISR_NE | USART_ISR_RTOF));
- if (errorflags == 0U) {
- /* UART in mode Receiver
- * ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) &&
- (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
- ((cr3its & USART_CR3_RXFTIE) != 0U))) {
- if (huart->RxISR != NULL) {
- huart->RxISR(huart);
- }
- return;
- }
- }
-
- /* If some errors occur */
- if ((errorflags != 0U) &&
- ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) ||
- ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
- USART_CR1_RTOIE)) != 0U)))) {
- /* UART parity error interrupt occurred
- * -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) &&
- ((cr1its & USART_CR1_PEIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART frame error interrupt occurred
- * --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART noise error interrupt occurred
- * --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* UART Over-Run interrupt occurred
- * -----------------------------------------*/
- if (((isrflags & USART_ISR_ORE) != 0U) &&
- (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
- ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
-
- /* UART Receiver Timeout interrupt occurred
- * ---------------------------------*/
- if (((isrflags & USART_ISR_RTOF) != 0U) &&
- ((cr1its & USART_CR1_RTOIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
-
- huart->ErrorCode |= HAL_UART_ERROR_RTO;
- }
-
- /* Call UART Error Call back function if need be
- * ----------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE) {
- /* UART in mode Receiver
- * --------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) &&
- (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
- ((cr3its & USART_CR3_RXFTIE) != 0U))) {
- if (huart->RxISR != NULL) {
- huart->RxISR(huart);
- }
- }
-
- /* If Error is to be considered as blocking :
- - Receiver Timeout error in Reception
- - Overrun error in Reception
- - any error occurs in DMA mode reception
- */
- errorcode = huart->ErrorCode;
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
-
- /* Abort the UART DMA Rx channel if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- /* Disable the UART DMA Rx request if enabled */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL) {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort
- procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case
- * of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- } else {
- /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- } else {
- /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- } else {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : */
- if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) &&
- ((isrflags & USART_ISR_IDLE) != 0U) &&
- ((cr1its & USART_ISR_IDLE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-
- /* Check if DMA mode is enabled in UART */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
- /* DMA mode enabled */
- /* Check received length : If all expected data are received, do nothing,
- (DMA cplt callback will be called).
- Otherwise, if at least one data has already been received, IDLE event
- is to be notified to user */
- uint16_t nb_remaining_rx_data =
- (uint16_t)__HAL_DMA_GET_COUNTER(huart->hdmarx);
- if ((nb_remaining_rx_data > 0U) &&
- (nb_remaining_rx_data < huart->RxXferSize)) {
- /* Reception is not complete */
- huart->RxXferCount = nb_remaining_rx_data;
-
- /* In Normal mode, end DMA xfer and HAL UART Rx process*/
- if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) {
- /* Disable PE and ERR (Frame error, noise error, overrun error)
- * interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the
- DMAR bit in the UART CR3 register */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
- /* Last bytes received, so no need as the abort is immediate */
- (void)HAL_DMA_Abort(huart->hdmarx);
- }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart,
- (huart->RxXferSize - huart->RxXferCount));
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
- return;
- } else {
- /* DMA mode not enabled */
- /* Check received length : If all expected data are received, do nothing.
- Otherwise, if at least one data has already been received, IDLE event
- is to be notified to user */
- uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
- if ((huart->RxXferCount > 0U) && (nb_rx_data > 0U)) {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
-
- /* Disable the UART Error Interrupt:(Frame error, noise error, overrun
- * error) and RX FIFO Threshold interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
-
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxEventCallback(huart, nb_rx_data);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
- return;
- }
- }
-
- /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
- if (((isrflags & USART_ISR_WUF) != 0U) &&
- ((cr3its & USART_CR3_WUFIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
-
- /* UART Rx state is not reset as a reception process might be ongoing.
- If UART handle state fields need to be reset to READY, this could be done
- in Wakeup callback */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Wakeup Callback */
- huart->WakeupCallback(huart);
-#else
- /* Call legacy weak Wakeup Callback */
- HAL_UARTEx_WakeupCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- return;
- }
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) &&
- (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) ||
- ((cr3its & USART_CR3_TXFTIE) != 0U))) {
- if (huart->TxISR != NULL) {
- huart->TxISR(huart);
- }
- return;
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) {
- UART_EndTransmit_IT(huart);
- return;
- }
-
- /* UART TX Fifo Empty occurred
- * ----------------------------------------------*/
- if (((isrflags & USART_ISR_TXFE) != 0U) &&
- ((cr1its & USART_CR1_TXFEIE) != 0U)) {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Tx Fifo Empty Callback */
- huart->TxFifoEmptyCallback(huart);
-#else
- /* Call legacy weak Tx Fifo Empty Callback */
- HAL_UARTEx_TxFifoEmptyCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- return;
- }
-
- /* UART RX Fifo Full occurred ----------------------------------------------*/
- if (((isrflags & USART_ISR_RXFF) != 0U) &&
- ((cr1its & USART_CR1_RXFFIE) != 0U)) {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Rx Fifo Full Callback */
- huart->RxFifoFullCallback(huart);
-#else
- /* Call legacy weak Rx Fifo Full Callback */
- HAL_UARTEx_RxFifoFullCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART error callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortTransmitCpltCallback can be implemented in the
- user file.
- */
-}
-
-/**
- * @brief UART Abort Receive Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortReceiveCpltCallback can be implemented in the user
- file.
- */
-}
-
-/**
- * @brief Reception Event Callback (Rx event notification called after use of
- * advanced reception service).
- * @param huart UART handle
- * @param Size Number of data available in application reception buffer
- * (indicates a position in reception buffer until which, data are available)
- * @retval None
- */
-__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart,
- uint16_t Size) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- UNUSED(Size);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_RxEventCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @brief UART control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the UART.
- (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver
-timeout value on the fly
- (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout
-feature
- (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout
-feature
- (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
- (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
- (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
- (+) UART_SetConfig() API configures the UART peripheral
- (+) UART_AdvFeatureConfig() API optionally configures the UART advanced
-features
- (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after
-initialization
- (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables
-transmitter
- (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables
-receiver
- (+) HAL_LIN_SendBreak() API transmits the break characters
-@endverbatim
- * @{
- */
-
-/**
- * @brief Update on the fly the receiver timeout value in RTOR register.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART
- * module.
- * @param TimeoutValue receiver timeout value in number of baud blocks. The
- * timeout value must be less or equal to 0x0FFFFFFFF.
- * @retval None
- */
-void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart,
- uint32_t TimeoutValue) {
- if (!(IS_LPUART_INSTANCE(huart->Instance))) {
- assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
- MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
- }
-}
-
-/**
- * @brief Enable the UART receiver timeout feature.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART
- * module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) {
- if (!(IS_LPUART_INSTANCE(huart->Instance))) {
- if (huart->gState == HAL_UART_STATE_READY) {
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Set the USART RTOEN bit */
- SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the UART receiver timeout feature.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART
- * module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) {
- if (!(IS_LPUART_INSTANCE(huart->Instance))) {
- if (huart->gState == HAL_UART_STATE_READY) {
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear the USART RTOEN bit */
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
- } else {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable UART in mute mode (does not mean UART enters mute mode;
- * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be
- * called).
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) {
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Enable USART mute mode by setting the MME bit in the CR1 register */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Disable UART mute mode (does not mean the UART actually exits mute
- * mode as it may not have been in mute mode at this very moment).
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(
- UART_HandleTypeDef *huart) {
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable USART mute mode by clearing the MME bit in the CR1 register */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Enter UART mute mode (means UART actually enters mute mode).
- * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must
- * be called.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) {
- __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
-
-/**
- * @brief Enable the UART transmitter and disable the UART receiver.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) {
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear TE and RE bits */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
- /* Enable the USART's transmit interface by setting the TE bit in the USART
- * CR1 register */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
- huart->gState = HAL_UART_STATE_READY;
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the UART receiver and disable the UART transmitter.
- * @param huart UART handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) {
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear TE and RE bits */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
- /* Enable the USART's receive interface by setting the RE bit in the USART CR1
- * register */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
- huart->gState = HAL_UART_STATE_READY;
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Transmit break characters.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) {
- /* Check the parameters */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Send break characters */
- __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
-
- huart->gState = HAL_UART_STATE_READY;
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error
-functions
- * @brief UART Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Return the UART handle state.
- (+) Return the UART handle error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the UART handle state.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval HAL state
- */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) {
- uint32_t temp1;
- uint32_t temp2;
- temp1 = huart->gState;
- temp2 = huart->RxState;
-
- return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the UART handle error code.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval UART Error Code
- */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) {
- return huart->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup UART_Private_Functions UART Private Functions
- * @{
- */
-
-/**
- * @brief Initialize the callbacks to their default values.
- * @param huart UART handle.
- * @retval none
- */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) {
- /* Init the UART Callback settings */
- huart->TxHalfCpltCallback =
- HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- huart->TxCpltCallback =
- HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
- huart->RxHalfCpltCallback =
- HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- huart->RxCpltCallback =
- HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
- huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
- huart->AbortCpltCallback =
- HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- huart->AbortTransmitCpltCallback =
- HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
- AbortTransmitCpltCallback */
- huart->AbortReceiveCpltCallback =
- HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback
- */
- huart->WakeupCallback =
- HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
- huart->RxFifoFullCallback =
- HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
- huart->TxFifoEmptyCallback =
- HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
- huart->RxEventCallback =
- HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
-}
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) {
- uint32_t tmpreg;
- uint16_t brrtemp;
- UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv;
- HAL_StatusTypeDef ret = HAL_OK;
- uint32_t lpuart_ker_ck_pres;
- uint32_t pclk;
-
- /* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
- if (UART_INSTANCE_LOWPOWER(huart)) {
- assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
- } else {
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
- assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
- }
-
- assert_param(IS_UART_PARITY(huart->Init.Parity));
- assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
- assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity |
- huart->Init.Mode | huart->Init.OverSampling;
- MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART) */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
-
- if (!(UART_INSTANCE_LOWPOWER(huart))) {
- tmpreg |= huart->Init.OneBitSampling;
- }
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
-
- /*-------------------------- USART PRESC Configuration
- * -----------------------*/
- /* Configure
- * - UART Clock Prescaler : set PRESCALER according to
- * huart->Init.ClockPrescaler value */
- MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER,
- huart->Init.ClockPrescaler);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
-
- /* Check LPUART instance */
- if (UART_INSTANCE_LOWPOWER(huart)) {
- /* Retrieve frequency clock */
- switch (clocksource) {
- case UART_CLOCKSOURCE_PCLK1:
- pclk = HAL_RCC_GetPCLK1Freq();
- break;
- case UART_CLOCKSOURCE_HSI:
- pclk = (uint32_t)HSI_VALUE;
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- pclk = HAL_RCC_GetSysClockFreq();
- break;
- case UART_CLOCKSOURCE_LSE:
- pclk = (uint32_t)LSE_VALUE;
- break;
- default:
- pclk = 0U;
- ret = HAL_ERROR;
- break;
- }
-
- /* If proper clock source reported */
- if (pclk != 0U) {
- /* Compute clock after Prescaler */
- lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
-
- /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 *
- * baudrate] */
- if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
- (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) {
- ret = HAL_ERROR;
- } else {
- /* Check computed UsartDiv value is in allocated range
- (it is forbidden to write values lower than 0x300 in the LPUART_BRR
- register) */
- usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate,
- huart->Init.ClockPrescaler));
- if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) {
- huart->Instance->BRR = usartdiv;
- } else {
- ret = HAL_ERROR;
- }
- } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
- (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
- } /* if (pclk != 0) */
- }
- /* Check UART Over Sampling to set Baud Rate Register */
- else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) {
- switch (clocksource) {
- case UART_CLOCKSOURCE_PCLK1:
- pclk = HAL_RCC_GetPCLK1Freq();
- break;
- case UART_CLOCKSOURCE_PCLK2:
- pclk = HAL_RCC_GetPCLK2Freq();
- break;
- case UART_CLOCKSOURCE_HSI:
- pclk = (uint32_t)HSI_VALUE;
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- pclk = HAL_RCC_GetSysClockFreq();
- break;
- case UART_CLOCKSOURCE_LSE:
- pclk = (uint32_t)LSE_VALUE;
- break;
- default:
- pclk = 0U;
- ret = HAL_ERROR;
- break;
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if (pclk != 0U) {
- usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate,
- huart->Init.ClockPrescaler));
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) {
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
- } else {
- ret = HAL_ERROR;
- }
- }
- } else {
- switch (clocksource) {
- case UART_CLOCKSOURCE_PCLK1:
- pclk = HAL_RCC_GetPCLK1Freq();
- break;
- case UART_CLOCKSOURCE_PCLK2:
- pclk = HAL_RCC_GetPCLK2Freq();
- break;
- case UART_CLOCKSOURCE_HSI:
- pclk = (uint32_t)HSI_VALUE;
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- pclk = HAL_RCC_GetSysClockFreq();
- break;
- case UART_CLOCKSOURCE_LSE:
- pclk = (uint32_t)LSE_VALUE;
- break;
- default:
- pclk = 0U;
- ret = HAL_ERROR;
- break;
- }
-
- if (pclk != 0U) {
- /* USARTDIV must be greater than or equal to 0d16 */
- usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate,
- huart->Init.ClockPrescaler));
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) {
- huart->Instance->BRR = (uint16_t)usartdiv;
- } else {
- ret = HAL_ERROR;
- }
- }
- }
-
- /* Initialize the number of data to process during RX/TX ISR execution */
- huart->NbTxDataToProcess = 1;
- huart->NbRxDataToProcess = 1;
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- huart->TxISR = NULL;
-
- return ret;
-}
-
-/**
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) {
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_TXINVERT_INIT)) {
- assert_param(
- IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV,
- huart->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_RXINVERT_INIT)) {
- assert_param(
- IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV,
- huart->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_DATAINVERT_INIT)) {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV,
- huart->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_SWAP_INIT)) {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS,
- huart->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_DMADISABLEONERROR_INIT)) {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(
- huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE,
- huart->AdvancedInit.DMADisableonRxError);
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_AUTOBAUDRATE_INIT)) {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(
- huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN,
- huart->AdvancedInit.AutoBaudRateEnable);
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable ==
- UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(
- huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE,
- huart->AdvancedInit.AutoBaudRateMode);
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
- UART_ADVFEATURE_MSBFIRST_INIT)) {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST,
- huart->AdvancedInit.MSBFirst);
- }
-}
-
-/**
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) {
- uint32_t tickstart;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) {
- /* Wait until TEACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart,
- HAL_UART_TIMEOUT_VALUE) != HAL_OK) {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the Receiver is enabled */
- if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) {
- /* Wait until REACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart,
- HAL_UART_TIMEOUT_VALUE) != HAL_OK) {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles UART Communication Timeout. It waits
- * until a flag is no longer in the specified status.
- * @param huart UART handle.
- * @param Flag Specifies the UART flag to check
- * @param Status The actual Flag status (SET or RESET)
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
- uint32_t Flag, FlagStatus Status,
- uint32_t Tickstart,
- uint32_t Timeout) {
- /* Wait until flag is set */
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun
- error) interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
- USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
-
- if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) {
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) {
- /* Clear Receiver Timeout flag*/
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
-
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun
- error) interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
- USART_CR1_TXEIE_TXFNFIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- huart->ErrorCode = HAL_UART_ERROR_RTO;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Start Receive operation in interrupt mode.
- * @note This function could be called by all HAL UART API providing reception
- * in Interrupt mode.
- * @note When calling this function, parameters validity is considered as
- * already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as
- * Locked.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size) {
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
- huart->RxISR = NULL;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error)
- */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Configure Rx interrupt processing */
- if ((huart->FifoMode == UART_FIFOMODE_ENABLE) &&
- (Size >= huart->NbRxDataToProcess)) {
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- huart->RxISR = UART_RxISR_16BIT_FIFOEN;
- } else {
- huart->RxISR = UART_RxISR_8BIT_FIFOEN;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- if (huart->Init.Parity != UART_PARITY_NONE) {
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- }
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
- } else {
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- huart->RxISR = UART_RxISR_16BIT;
- } else {
- huart->RxISR = UART_RxISR_8BIT;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty
- * interrupt */
- if (huart->Init.Parity != UART_PARITY_NONE) {
- ATOMIC_SET_BIT(huart->Instance->CR1,
- USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
- } else {
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Start Receive operation in DMA mode.
- * @note This function could be called by all HAL UART API providing reception
- * in DMA mode.
- * @note When calling this function, parameters validity is considered as
- * already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as
- * Locked.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (u8 or u16 data elements).
- * @param Size Amount of data elements (u8 or u16) to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size) {
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- if (huart->hdmarx != NULL) {
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR,
- (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- __HAL_UNLOCK(huart);
-
- /* Restore huart->RxState to ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_ERROR;
- }
- }
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error Interrupt */
- if (huart->Init.Parity != UART_PARITY_NONE) {
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- }
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error)
- */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
-}
-
-/**
- * @brief End ongoing Tx transfer on UART peripheral (following error detection
- * or Transmit completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart) {
- /* Disable TXEIE, TCIE, TXFT interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-}
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection
- * or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart) {
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
- * interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* In case of reception waiting for IDLE event, disable also the IDLE IE
- * interrupt source */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Reset RxIsr function pointer */
- huart->RxISR = NULL;
-}
-
-/**
- * @brief DMA UART transmit process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- /* DMA Normal mode */
- if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) {
- huart->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the UART CR3 register */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the UART Transmit Complete Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- }
- /* DMA Circular mode */
- else {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief DMA UART transmit process half complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx Half complete callback*/
- huart->TxHalfCpltCallback(huart);
-#else
- /*Call legacy weak Tx Half complete callback*/
- HAL_UART_TxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA UART receive process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- /* DMA Normal mode */
- if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) {
- huart->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts
- */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR
- bit in the UART CR3 register */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- }
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : use Rx Event callback */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- } else {
- /* In other cases : use Rx Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief DMA UART receive process half complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : use Rx Event callback */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize / 2U);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- } else {
- /* In other cases : use Rx Half Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Half complete callback*/
- huart->RxHalfCpltCallback(huart);
-#else
- /*Call legacy weak Rx Half complete callback*/
- HAL_UART_RxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief DMA UART communication error callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAError(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- const HAL_UART_StateTypeDef gstate = huart->gState;
- const HAL_UART_StateTypeDef rxstate = huart->RxState;
-
- /* Stop UART DMA Tx request if ongoing */
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
- (gstate == HAL_UART_STATE_BUSY_TX)) {
- huart->TxXferCount = 0U;
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
- (rxstate == HAL_UART_STATE_BUSY_RX)) {
- huart->RxXferCount = 0U;
- UART_EndRxTransfer(huart);
- }
-
- huart->ErrorCode |= HAL_UART_ERROR_DMA;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA UART communication abort callback, when initiated by HAL services
- * on Error (To be called at end of DMA Abort procedure following error
- * occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort
- * request).
- * @note When this callback is executed, User Abort complete call back is
- * called only if no Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if (huart->hdmarx != NULL) {
- if (huart->hdmarx->XferAbortCallback != NULL) {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user
- * Abort Complete callback */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Flush the whole TX FIFO (if needed) */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
- }
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort complete callback */
- huart->AbortCpltCallback(huart);
-#else
- /* Call legacy weak Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort
- * request).
- * @note When this callback is executed, User Abort complete call back is
- * called only if no Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if (huart->hdmatx != NULL) {
- if (huart->hdmatx->XferAbortCallback != NULL) {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user
- * Abort Complete callback */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Discard the received data */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort complete callback */
- huart->AbortCpltCallback(huart);
-#else
- /* Call legacy weak Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user by a
- * call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback
- * is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-
- huart->TxXferCount = 0U;
-
- /* Flush the whole TX FIFO (if needed) */
- if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
- __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
- }
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort Transmit Complete Callback */
- huart->AbortTransmitCpltCallback(huart);
-#else
- /* Call legacy weak Abort Transmit Complete Callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user by a
- * call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback
- * is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) {
- UART_HandleTypeDef *huart =
- (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
- UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Discard the received data */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /* Call registered Abort Receive Complete Callback */
- huart->AbortReceiveCpltCallback(huart);
-#else
- /* Call legacy weak Abort Receive Complete Callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TX interrupt handler for 7 or 8 bits data word length .
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart UART handle.
- * @retval None
- */
-static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) {
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX) {
- if (huart->TxXferCount == 0U) {
- /* Disable the UART Transmit Data Register Empty Interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
-
- /* Enable the UART Transmit Complete Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- } else {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
- huart->pTxBuffPtr++;
- huart->TxXferCount--;
- }
- }
-}
-
-/**
- * @brief TX interrupt handler for 9 bits data word length.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart UART handle.
- * @retval None
- */
-static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) {
- const uint16_t *tmp;
-
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX) {
- if (huart->TxXferCount == 0U) {
- /* Disable the UART Transmit Data Register Empty Interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
-
- /* Enable the UART Transmit Complete Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- } else {
- tmp = (const uint16_t *)huart->pTxBuffPtr;
- huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
- huart->pTxBuffPtr += 2U;
- huart->TxXferCount--;
- }
- }
-}
-
-/**
- * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is
- * enabled.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart UART handle.
- * @retval None
- */
-static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) {
- uint16_t nb_tx_data;
-
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX) {
- for (nb_tx_data = huart->NbTxDataToProcess; nb_tx_data > 0U; nb_tx_data--) {
- if (huart->TxXferCount == 0U) {
- /* Disable the TX FIFO threshold interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Enable the UART Transmit Complete Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- break; /* force exit loop */
- } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
- huart->pTxBuffPtr++;
- huart->TxXferCount--;
- } else {
- /* Nothing to do */
- }
- }
- }
-}
-
-/**
- * @brief TX interrupt handler for 9 bits data word length and FIFO mode is
- * enabled.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart UART handle.
- * @retval None
- */
-static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) {
- const uint16_t *tmp;
- uint16_t nb_tx_data;
-
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX) {
- for (nb_tx_data = huart->NbTxDataToProcess; nb_tx_data > 0U; nb_tx_data--) {
- if (huart->TxXferCount == 0U) {
- /* Disable the TX FIFO threshold interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Enable the UART Transmit Complete Interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- break; /* force exit loop */
- } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) {
- tmp = (const uint16_t *)huart->pTxBuffPtr;
- huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
- huart->pTxBuffPtr += 2U;
- huart->TxXferCount--;
- } else {
- /* Nothing to do */
- }
- }
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) {
- /* Disable the UART Transmit Complete Interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Cleat TxISR function pointer */
- huart->TxISR = NULL;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief RX interrupt handler for 7 or 8 bits data word length .
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) {
- uint16_t uhMask = huart->Mask;
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
- uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- huart->pRxBuffPtr++;
- huart->RxXferCount--;
-
- if (huart->RxXferCount == 0U) {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
- * error) */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- /* Set reception type to Standard */
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Disable IDLE interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
- /* Clear IDLE Flag */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- } else {
- /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- }
- } else {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
-
-/**
- * @brief RX interrupt handler for 9 bits data word length .
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) {
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
- uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
- tmp = (uint16_t *)huart->pRxBuffPtr;
- *tmp = (uint16_t)(uhdata & uhMask);
- huart->pRxBuffPtr += 2U;
- huart->RxXferCount--;
-
- if (huart->RxXferCount == 0U) {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- ATOMIC_CLEAR_BIT(huart->Instance->CR1,
- (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
- * error) */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- /* Set reception type to Standard */
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Disable IDLE interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
- /* Clear IDLE Flag */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- } else {
- /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- }
- } else {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
-
-/**
- * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode
- * is enabled.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) {
- uint16_t uhMask = huart->Mask;
- uint16_t uhdata;
- uint16_t nb_rx_data;
- uint16_t rxdatacount;
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
- nb_rx_data = huart->NbRxDataToProcess;
- while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) {
- uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- huart->pRxBuffPtr++;
- huart->RxXferCount--;
- isrflags = READ_REG(huart->Instance->ISR);
-
- /* If some non blocking errors occurred */
- if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) {
- /* UART parity error interrupt occurred
- * -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) &&
- ((cr1its & USART_CR1_PEIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART frame error interrupt occurred
- * --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) &&
- ((cr3its & USART_CR3_EIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART noise error interrupt occurred
- * --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) &&
- ((cr3its & USART_CR3_EIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* Call UART Error Call back function if need be
- * ----------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE) {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
- }
-
- if (huart->RxXferCount == 0U) {
- /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
- error) and RX FIFO Threshold interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- /* Set reception type to Standard */
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Disable IDLE interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
- /* Clear IDLE Flag */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- } else {
- /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- }
- }
-
- /* When remaining number of bytes to receive is less than the RX FIFO
- threshold, next incoming frames are processed as if FIFO mode was
- disabled (i.e. one interrupt per received frame).
- */
- rxdatacount = huart->RxXferCount;
- if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) {
- /* Disable the UART RXFT interrupt*/
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
-
- /* Update the RxISR function pointer */
- huart->RxISR = UART_RxISR_8BIT;
-
- /* Enable the UART Data Register Not Empty interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
- }
- } else {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
-
-/**
- * @brief RX interrupt handler for 9 bits data word length and FIFO mode is
- * enabled.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) {
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- uint16_t uhdata;
- uint16_t nb_rx_data;
- uint16_t rxdatacount;
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
- nb_rx_data = huart->NbRxDataToProcess;
- while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) {
- uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
- tmp = (uint16_t *)huart->pRxBuffPtr;
- *tmp = (uint16_t)(uhdata & uhMask);
- huart->pRxBuffPtr += 2U;
- huart->RxXferCount--;
- isrflags = READ_REG(huart->Instance->ISR);
-
- /* If some non blocking errors occurred */
- if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) {
- /* UART parity error interrupt occurred
- * -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) &&
- ((cr1its & USART_CR1_PEIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART frame error interrupt occurred
- * --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) &&
- ((cr3its & USART_CR3_EIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART noise error interrupt occurred
- * --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) &&
- ((cr3its & USART_CR3_EIE) != 0U)) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* Call UART Error Call back function if need be
- * ----------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE) {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
- }
-
- if (huart->RxXferCount == 0U) {
- /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
- error) and RX FIFO Threshold interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR3,
- (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
-
- /* Check current reception Mode :
- If Reception till IDLE event has been selected : */
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- /* Set reception type to Standard */
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
- /* Disable IDLE interrupt */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
- /* Clear IDLE Flag */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize);
-#else
- /*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- } else {
- /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- }
- }
- }
-
- /* When remaining number of bytes to receive is less than the RX FIFO
- threshold, next incoming frames are processed as if FIFO mode was
- disabled (i.e. one interrupt per received frame).
- */
- rxdatacount = huart->RxXferCount;
- if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) {
- /* Disable the UART RXFT interrupt*/
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
-
- /* Update the RxISR function pointer */
- huart->RxISR = UART_RxISR_16BIT;
-
- /* Enable the UART Data Register Not Empty interrupt */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
- }
- } else {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter
+ Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef
+ huart).
+ (#) Initialize the UART low level resources by implementing the
+ HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process
+ (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete
+ interrupt, RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+ are managed using the macros __HAL_UART_ENABLE_IT() and
+ __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process
+ (HAL_UART_Transmit_DMA() and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required
+ Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx
+ handle.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value ,
+ Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init
+ structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud
+ rate detection,...) in the huart handle AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the
+ UART registers by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(),
+ HAL_MultiProcessor_Init(), also configure the low level Hardware GPIO, CLOCK,
+ CORTEX...etc) by calling the customized HAL_UART_MspInit() API.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_UART_RegisterCallback() to register a user callback.
+ Function HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_UART_UnRegisterCallback() to reset a callback to the
+ default weak function. HAL_UART_UnRegisterCallback() takes as parameters the
+ HAL peripheral handle, and the Callback ID. This function allows to reset
+ following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ For specific callback RxEventCallback, use dedicated registration/reset
+ functions: respectively HAL_UART_RegisterRxEventCallback() ,
+ HAL_UART_UnRegisterRxEventCallback().
+
+ [..]
+ By default, after the HAL_UART_Init() and when the state is
+ HAL_UART_STATE_RESET all callbacks are set to the corresponding weak functions:
+ examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak functions in the HAL_UART_Init()
+ and HAL_UART_DeInit() only when these callbacks are null (not registered
+ beforehand). If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and
+ HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered
+ beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered
+ (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that
+ case first register the MspInit/MspDeInit user callbacks using
+ HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() or HAL_UART_Init()
+ function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak callbacks are used.
+
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief HAL UART module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define USART_CR1_FIELDS \
+ ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8 | \
+ USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters \
+ set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS \
+ ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | \
+ USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters \
+ set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U,
+ 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and
+de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the
+USARTx or the UARTy in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data
+written in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be
+configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and
+HAL_MultiProcessor_Init()API follow respectively the UART asynchronous, UART
+Half duplex, UART LIN mode and UART multiprocessor mode configuration procedures
+(details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated
+ * handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) {
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ } else {
+ /* Check the parameters */
+ assert_param((IS_UART_INSTANCE(huart->Instance)) ||
+ (IS_LPUART_INSTANCE(huart->Instance)));
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL) {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are
+ * set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR) {
+ return HAL_ERROR;
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
+ * to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) {
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if (huart->gState == HAL_UART_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL) {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are
+ * set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR) {
+ return HAL_ERROR;
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
+ * to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param BreakDetectLength Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart,
+ uint32_t BreakDetectLength) {
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B) {
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL) {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are
+ * set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR) {
+ return HAL_ERROR;
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
+ * to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated
+ * handle.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod Specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line
+ * detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address
+ * parameter is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length
+ * detection is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart,
+ uint8_t Address,
+ uint32_t WakeUpMethod) {
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if (huart->gState == HAL_UART_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL) {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are
+ * set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR) {
+ return HAL_ERROR;
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD,
+ ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
+ * to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief DeInitialize the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) {
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param((IS_UART_INSTANCE(huart->Instance)) ||
+ (IS_LPUART_INSTANCE(huart->Instance)));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL) {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used to override the weak predefined callback
+ * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(),
+ * HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init() or
+ * HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register callbacks for
+ * HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback
+ * ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback
+ * ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit
+ * Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive
+ * Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(
+ UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_READY) {
+ switch (CallbackID) {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID:
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID:
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID:
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID:
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID:
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID:
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID:
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID:
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID:
+ huart->WakeupCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID:
+ huart->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID:
+ huart->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID:
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID:
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (huart->gState == HAL_UART_STATE_RESET) {
+ switch (CallbackID) {
+ case HAL_UART_MSPINIT_CB_ID:
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID:
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default:
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @note The HAL_UART_UnRegisterCallback() may be called before
+ * HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(),
+ * HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to
+ * un-register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback
+ * ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback
+ * ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit
+ * Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive
+ * Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(
+ UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_UART_STATE_READY == huart->gState) {
+ switch (CallbackID) {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID:
+ huart->TxHalfCpltCallback =
+ HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID:
+ huart->TxCpltCallback =
+ HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID:
+ huart->RxHalfCpltCallback =
+ HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID:
+ huart->RxCpltCallback =
+ HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID:
+ huart->ErrorCallback =
+ HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID:
+ huart->AbortCpltCallback =
+ HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID:
+ huart->AbortTransmitCpltCallback =
+ HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID:
+ huart->AbortReceiveCpltCallback =
+ HAL_UART_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID:
+ huart->WakeupCallback =
+ HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID:
+ huart->RxFifoFullCallback =
+ HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID:
+ huart->TxFifoEmptyCallback =
+ HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback
+ */
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID:
+ huart->MspInitCallback =
+ HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID:
+ huart->MspDeInitCallback =
+ HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default:
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ } else if (HAL_UART_STATE_RESET == huart->gState) {
+ switch (CallbackID) {
+ case HAL_UART_MSPINIT_CB_ID:
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID:
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default:
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ } else {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Register a User UART Rx Event Callback
+ * To be used instead of the weak predefined callback
+ * @param huart Uart handle
+ * @param pCallback Pointer to the Rx Event Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(
+ UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL) {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ huart->RxEventCallback = pCallback;
+ } else {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the UART Rx Event Callback
+ * UART Rx Event Callback is redirected to the weak
+ * HAL_UARTEx_RxEventCallback() predefined callback
+ * @param huart Uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(
+ UART_HandleTypeDef *huart) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ huart->RxEventCallback =
+ HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
+ } else {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the UART
+asynchronous and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same
+function after finishing transfer.
+ (+) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user
+callbacks will be executed respectively at the end of the transmit or Receive
+process The HAL_UART_ErrorCallback()user callback will be executed when a
+communication error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of
+Abort Complete Callbacks are provided:
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) A Rx Event Reception Callback (Rx event notification) is available for
+Non_Blocking modes of enhanced reception services:
+ (+) HAL_UARTEx_RxEventCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2
+categories. Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could
+go till end, but error severity is to be evaluated by user : this concerns Frame
+Error, Parity Error or Noise Error in Interrupt mode reception . Received
+character is then retrieved and stored in Rx buffer, Error code is set to allow
+user to identify error type, and HAL_UART_ErrorCallback() user callback is
+executed. Transfer is kept ongoing on UART side. If user wants to abort it,
+Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed
+properly and is aborted. This concerns Overrun Error In Interrupt mode reception
+and all errors in DMA mode. Error code is set to allow user to identify error
+type, and HAL_UART_ErrorCallback() user callback is executed.
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state
+HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16.
+ * In this case, Size must indicate the number of u16 provided through pData.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart,
+ const uint8_t *pData, uint16_t Size,
+ uint32_t Timeout) {
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a
+ * uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ pdata8bits = NULL;
+ pdata16bits = (const uint16_t *)pData;
+ } else {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (huart->TxXferCount > 0U) {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart,
+ Timeout) != HAL_OK) {
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL) {
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
+ } else {
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
+ }
+ huart->TxXferCount--;
+ }
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart,
+ Timeout) != HAL_OK) {
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
+ * u16. In this case, Size must indicate the number of u16 available through
+ * pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout) {
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a
+ * uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *)pData;
+ } else {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U) {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart,
+ Timeout) != HAL_OK) {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL) {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ } else {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ huart->RxXferCount--;
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16.
+ * In this case, Size must indicate the number of u16 provided through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart,
+ const uint8_t *pData, uint16_t Size) {
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ huart->TxISR = NULL;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Configure Tx interrupt processing */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+ } else {
+ huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+ }
+
+ /* Enable the TX FIFO threshold interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ } else {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ huart->TxISR = UART_TxISR_16BIT;
+ } else {
+ huart->TxISR = UART_TxISR_8BIT;
+ }
+
+ /* Enable the Transmit Data Register Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
+ * u16. In this case, Size must indicate the number of u16 available through
+ * pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
+ uint16_t Size) {
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ return (UART_Start_Receive_IT(huart, pData, Size));
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16.
+ * In this case, Size must indicate the number of u16 provided through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart,
+ const uint8_t *pData, uint16_t Size) {
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ if (huart->hdmatx != NULL) {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the UART transmit DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr,
+ (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
+ * u16. In this case, Size must indicate the number of u16 available through
+ * pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size) {
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ return (UART_Start_Receive_DMA(huart, pData, Size));
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) {
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX)) {
+ /* Disable the UART DMA Tx request */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX)) {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts
+ */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) {
+ if (huart->gState == HAL_UART_STATE_BUSY_TX) {
+ /* Enable the UART DMA Tx request */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts
+ */
+ if (huart->Init.Parity != UART_PARITY_NONE) {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART DMA Rx request */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) {
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() /
+ HAL_UART_RxCpltCallback() / HAL_UART_TxHalfCpltCallback /
+ HAL_UART_RxHalfCpltCallback: indeed, when HAL_DMA_Abort() API is called,
+ the DMA TX/RX Transfer or Half Transfer complete interrupt is generated if
+ the DMA transfer interruption occurs at the middle or at the end of the
+ stream and the corresponding call back is executed. */
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX)) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if (huart->hdmatx != NULL) {
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX)) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL) {
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer
+ * started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
+ * in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function,
+ * Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) {
+ /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error,
+ * overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3,
+ USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback)
+ */
+ if (huart->hdmatx != NULL) {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback)
+ */
+ if (huart->hdmarx != NULL) {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer
+ * started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
+ * in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function,
+ * Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) {
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback)
+ */
+ if (huart->hdmatx != NULL) {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer
+ * started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer
+ * in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function,
+ * Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) {
+ /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback)
+ */
+ if (huart->hdmarx != NULL) {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer
+ * started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
+ * transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort
+ * procedure could be considered as completed only when user abort complete
+ * callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) {
+ uint32_t abortcplt = 1U;
+
+ /* Disable interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort
+ complete callbacks should be initialised before any call to DMA Abort
+ functions */
+ /* DMA Tx Handle is valid */
+ if (huart->hdmatx != NULL) {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ } else {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (huart->hdmarx != NULL) {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ } else {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
+ /* Disable DMA Tx at UART level */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback)
+ */
+ if (huart->hdmatx != NULL) {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
+ procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) {
+ huart->hdmatx->XferAbortCallback = NULL;
+ } else {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback)
+ */
+ if (huart->hdmarx != NULL) {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
+ procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ } else {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort
+ * Complete callback */
+ if (abortcplt == 1U) {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer
+ * started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
+ * transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort
+ * procedure could be considered as completed only when user abort complete
+ * callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) {
+ /* Disable interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) {
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback)
+ */
+ if (huart->hdmatx != NULL) {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
+ procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of
+ * error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ } else {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ } else {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer
+ * started in Interrupt or DMA mode. This procedure performs following
+ * operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of
+ * transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort
+ * procedure could be considered as completed only when user abort complete
+ * callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) {
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+ * interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback)
+ */
+ if (huart->hdmarx != NULL) {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort
+ procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of
+ * error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ } else {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ } else {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) {
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags =
+ (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE |
+ USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U) {
+ /* UART in mode Receiver
+ * ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & USART_CR3_RXFTIE) != 0U))) {
+ if (huart->RxISR != NULL) {
+ huart->RxISR(huart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U) &&
+ ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) ||
+ ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_RTOIE)) != 0U)))) {
+ /* UART parity error interrupt occurred
+ * -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) &&
+ ((cr1its & USART_CR1_PEIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred
+ * --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred
+ * --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred
+ * -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* UART Receiver Timeout interrupt occurred
+ * ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) &&
+ ((cr1its & USART_CR1_RTOIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ }
+
+ /* Call UART Error Call back function if need be
+ * ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE) {
+ /* UART in mode Receiver
+ * --------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & USART_CR3_RXFTIE) != 0U))) {
+ if (huart->RxISR != NULL) {
+ huart->RxISR(huart);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = huart->ErrorCode;
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL) {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort
+ procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case
+ * of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ } else {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ } else {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ } else {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) &&
+ ((isrflags & USART_ISR_IDLE) != 0U) &&
+ ((cr1its & USART_ISR_IDLE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* Check if DMA mode is enabled in UART */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) {
+ /* DMA mode enabled */
+ /* Check received length : If all expected data are received, do nothing,
+ (DMA cplt callback will be called).
+ Otherwise, if at least one data has already been received, IDLE event
+ is to be notified to user */
+ uint16_t nb_remaining_rx_data =
+ (uint16_t)__HAL_DMA_GET_COUNTER(huart->hdmarx);
+ if ((nb_remaining_rx_data > 0U) &&
+ (nb_remaining_rx_data < huart->RxXferSize)) {
+ /* Reception is not complete */
+ huart->RxXferCount = nb_remaining_rx_data;
+
+ /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) {
+ /* Disable PE and ERR (Frame error, noise error, overrun error)
+ * interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the
+ DMAR bit in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Last bytes received, so no need as the abort is immediate */
+ (void)HAL_DMA_Abort(huart->hdmarx);
+ }
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback
+ execution; In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart,
+ (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ } else {
+ /* If DMA is in Circular mode, Idle event is to be reported to user
+ even if occurring after a Transfer Complete event from DMA */
+ if (nb_remaining_rx_data == huart->RxXferSize) {
+ if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) {
+ /* Initialize type of RxEvent that correspond to RxEvent callback
+ execution; In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ }
+ }
+ return;
+ } else {
+ /* DMA mode not enabled */
+ /* Check received length : If all expected data are received, do nothing.
+ Otherwise, if at least one data has already been received, IDLE event
+ is to be notified to user */
+ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ if ((huart->RxXferCount > 0U) && (nb_rx_data > 0U)) {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt:(Frame error, noise error, overrun
+ * error) and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback
+ execution; In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxEventCallback(huart, nb_rx_data);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ }
+
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+ if (((isrflags & USART_ISR_WUF) != 0U) &&
+ ((cr3its & USART_CR3_WUFIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+ /* UART Rx state is not reset as a reception process might be ongoing.
+ If UART handle state fields need to be reset to READY, this could be done
+ in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Wakeup Callback */
+ huart->WakeupCallback(huart);
+#else
+ /* Call legacy weak Wakeup Callback */
+ HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) &&
+ (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) ||
+ ((cr3its & USART_CR3_TXFTIE) != 0U))) {
+ if (huart->TxISR != NULL) {
+ huart->TxISR(huart);
+ }
+ return;
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
+
+ /* UART TX Fifo Empty occurred
+ * ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) &&
+ ((cr1its & USART_CR1_TXFEIE) != 0U)) {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ huart->TxFifoEmptyCallback(huart);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) &&
+ ((cr1its & USART_CR1_RXFFIE) != 0U)) {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ huart->RxFifoFullCallback(huart);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART error callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the
+ user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user
+ file.
+ */
+}
+
+/**
+ * @brief Reception Event Callback (Rx event notification called after use of
+ * advanced reception service).
+ * @param huart UART handle
+ * @param Size Number of data available in application reception buffer
+ * (indicates a position in reception buffer until which, data are available)
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart,
+ uint16_t Size) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ UNUSED(Size);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver
+timeout value on the fly
+ (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout
+feature
+ (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout
+feature
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced
+features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after
+initialization
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables
+transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables
+receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART
+ * module.
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The
+ * timeout value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart,
+ uint32_t TimeoutValue) {
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+ MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+ }
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART
+ * module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) {
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ if (huart->gState == HAL_UART_STATE_READY) {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART
+ * module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) {
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ if (huart->gState == HAL_UART_STATE_READY) {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+ } else {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be
+ * called).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) {
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute
+ * mode as it may not have been in mute mode at this very moment).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(
+ UART_HandleTypeDef *huart) {
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must
+ * be called.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) {
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) {
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's transmit interface by setting the TE bit in the USART
+ * CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) {
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1
+ * register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) {
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error
+functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) {
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART handle error code.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+ */
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) {
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) {
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback =
+ HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback =
+ HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback =
+ HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback =
+ HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback =
+ HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback =
+ HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback =
+ HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback
+ */
+ huart->WakeupCallback =
+ HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ huart->RxFifoFullCallback =
+ HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ huart->TxFifoEmptyCallback =
+ HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->RxEventCallback =
+ HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) {
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ UART_ClockSourceTypeDef clocksource;
+ uint32_t usartdiv;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t lpuart_ker_ck_pres;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ if (UART_INSTANCE_LOWPOWER(huart)) {
+ assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+ } else {
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ }
+
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity |
+ huart->Init.Mode | huart->Init.OverSampling;
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+ if (!(UART_INSTANCE_LOWPOWER(huart))) {
+ tmpreg |= huart->Init.OneBitSampling;
+ }
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART PRESC Configuration
+ * -----------------------*/
+ /* Configure
+ * - UART Clock Prescaler : set PRESCALER according to
+ * huart->Init.ClockPrescaler value */
+ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER,
+ huart->Init.ClockPrescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ /* Check LPUART instance */
+ if (UART_INSTANCE_LOWPOWER(huart)) {
+ /* Retrieve frequency clock */
+ switch (clocksource) {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ pclk = (uint32_t)HSI_VALUE;
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ pclk = (uint32_t)LSE_VALUE;
+ break;
+ default:
+ pclk = 0U;
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* If proper clock source reported */
+ if (pclk != 0U) {
+ /* Compute clock after Prescaler */
+ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+ /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 *
+ * baudrate] */
+ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+ (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) {
+ ret = HAL_ERROR;
+ } else {
+ /* Check computed UsartDiv value is in allocated range
+ (it is forbidden to write values lower than 0x300 in the LPUART_BRR
+ register) */
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate,
+ huart->Init.ClockPrescaler));
+ if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) {
+ huart->Instance->BRR = usartdiv;
+ } else {
+ ret = HAL_ERROR;
+ }
+ } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+ (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+ } /* if (pclk != 0) */
+ }
+ /* Check UART Over Sampling to set Baud Rate Register */
+ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) {
+ switch (clocksource) {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ pclk = (uint32_t)HSI_VALUE;
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ pclk = (uint32_t)LSE_VALUE;
+ break;
+ default:
+ pclk = 0U;
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if (pclk != 0U) {
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate,
+ huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ } else {
+ ret = HAL_ERROR;
+ }
+ }
+ } else {
+ switch (clocksource) {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ pclk = (uint32_t)HSI_VALUE;
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ pclk = (uint32_t)LSE_VALUE;
+ break;
+ default:
+ pclk = 0U;
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (pclk != 0U) {
+ /* USARTDIV must be greater than or equal to 0d16 */
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate,
+ huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) {
+ huart->Instance->BRR = (uint16_t)usartdiv;
+ } else {
+ ret = HAL_ERROR;
+ }
+ }
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ huart->NbTxDataToProcess = 1;
+ huart->NbRxDataToProcess = 1;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) {
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_SWAP_INIT)) {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_TXINVERT_INIT)) {
+ assert_param(
+ IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV,
+ huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_RXINVERT_INIT)) {
+ assert_param(
+ IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV,
+ huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_DATAINVERT_INIT)) {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV,
+ huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS,
+ huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT)) {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(
+ huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE,
+ huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT)) {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(
+ huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN,
+ huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable ==
+ UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(
+ huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE,
+ huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit,
+ UART_ADVFEATURE_MSBFIRST_INIT)) {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST,
+ huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) {
+ uint32_t tickstart;
+
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) {
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart,
+ HAL_UART_TIMEOUT_VALUE) != HAL_OK) {
+ /* Disable TXE interrupt for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) {
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart,
+ HAL_UART_TIMEOUT_VALUE) != HAL_OK) {
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles UART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status The actual Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
+ uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart,
+ uint32_t Timeout) {
+ /* Wait until flag is set */
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) {
+ return HAL_TIMEOUT;
+ }
+
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) &&
+ (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) {
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) {
+ /* Clear Receiver Timeout flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in interrupt mode.
+ * @note This function could be called by all HAL UART API providing reception
+ * in Interrupt mode.
+ * @note When calling this function, parameters validity is considered as
+ * already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as
+ * Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size) {
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) &&
+ (Size >= huart->NbRxDataToProcess)) {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ } else {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ if (huart->Init.Parity != UART_PARITY_NONE) {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ } else {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ huart->RxISR = UART_RxISR_16BIT;
+ } else {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty
+ * interrupt */
+ if (huart->Init.Parity != UART_PARITY_NONE) {
+ ATOMIC_SET_BIT(huart->Instance->CR1,
+ USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ } else {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in DMA mode.
+ * @note This function could be called by all HAL UART API providing reception
+ * in DMA mode.
+ * @note When calling this function, parameters validity is considered as
+ * already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as
+ * Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size) {
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL) {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR,
+ (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ /* Restore huart->RxState to ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the UART Parity Error Interrupt */
+ if (huart->Init.Parity != UART_PARITY_NONE) {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection
+ * or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart) {
+ /* Disable TXEIE, TCIE, TXFT interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection
+ * or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart) {
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+ * interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* In case of reception waiting for IDLE event, disable also the IDLE IE
+ * interrupt source */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
+}
+
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) {
+ huart->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx Half complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx Half complete callback*/
+ HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) {
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts
+ */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR
+ bit in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ }
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ } else {
+ /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Half Transfer */
+ huart->RxEventType = HAL_UART_RXEVENT_HT;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ } else {
+ /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX)) {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX)) {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services
+ * on Error (To be called at end of DMA Abort procedure following error
+ * occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ huart->RxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort
+ * request).
+ * @note When this callback is executed, User Abort complete call back is
+ * called only if no Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmarx != NULL) {
+ if (huart->hdmarx->XferAbortCallback != NULL) {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user
+ * Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort
+ * request).
+ * @note When this callback is executed, User Abort complete call back is
+ * called only if no Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmatx != NULL) {
+ if (huart->hdmatx->XferAbortCallback != NULL) {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user
+ * Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a
+ * call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback
+ * is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE) {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a
+ * call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback
+ * is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) {
+ UART_HandleTypeDef *huart =
+ (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF |
+ UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TX interrupt handler for 7 or 8 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) {
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX) {
+ if (huart->TxXferCount == 0U) {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ } else {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 9 bits data word length.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) {
+ const uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX) {
+ if (huart->TxXferCount == 0U) {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ } else {
+ tmp = (const uint16_t *)huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is
+ * enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) {
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX) {
+ for (nb_tx_data = huart->NbTxDataToProcess; nb_tx_data > 0U; nb_tx_data--) {
+ if (huart->TxXferCount == 0U) {
+ /* Disable the TX FIFO threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ } else {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 9 bits data word length and FIFO mode is
+ * enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) {
+ const uint16_t *tmp;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX) {
+ for (nb_tx_data = huart->NbTxDataToProcess; nb_tx_data > 0U; nb_tx_data--) {
+ if (huart->TxXferCount == 0U) {
+ /* Disable the TX FIFO threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) {
+ tmp = (const uint16_t *)huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ } else {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) {
+ /* Disable the UART Transmit Complete Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief RX interrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) {
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
+ uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U) {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
+ * error) */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ } else {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ } else {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 9 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) {
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
+ uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *)huart->pRxBuffPtr;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U) {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
+ * error) */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ } else {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ } else {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode
+ * is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) {
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) {
+ uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) {
+ /* UART parity error interrupt occurred
+ * -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) &&
+ ((cr1its & USART_CR1_PEIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred
+ * --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) &&
+ ((cr3its & USART_CR3_EIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred
+ * --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) &&
+ ((cr3its & USART_CR3_EIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be
+ * ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE) {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+
+ if (huart->RxXferCount == 0U) {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
+ error) and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ } else {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ break;
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) {
+ /* Disable the UART RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_8BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ } else {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 9 bits data word length and FIFO mode is
+ * enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) {
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX) {
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) {
+ uhdata = (uint16_t)READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *)huart->pRxBuffPtr;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) {
+ /* UART parity error interrupt occurred
+ * -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) &&
+ ((cr1its & USART_CR1_PEIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred
+ * --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) &&
+ ((cr3its & USART_CR3_EIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred
+ * --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) &&
+ ((cr3its & USART_CR3_EIE) != 0U)) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be
+ * ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE) {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+
+ if (huart->RxXferCount == 0U) {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun
+ error) and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3,
+ (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance))) {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ } else {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ break;
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) {
+ /* Disable the UART RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_16BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ } else {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
index 5d8f053..7fc6375 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
@@ -1,1001 +1,1035 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_hal_uart_ex.c
- * @author MCD Application Team
- * @brief Extended UART HAL module driver.
- * This file provides firmware functions to manage the following
- extended
- * functionalities of the Universal Asynchronous Receiver Transmitter
- Peripheral (UART).
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### UART peripheral extended features #####
- ==============================================================================
-
- (#) Declare a UART_HandleTypeDef handle structure.
-
- (#) For the UART RS485 Driver Enable mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
- (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
-
- -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
- starting RX/TX transfers. Also RX/TX FIFO thresholds must be
- configured prior starting RX/TX transfers.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UARTEx UARTEx
- * @brief UART Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
- * @{
- */
-/* UART RX FIFO depth */
-#define RX_FIFO_DEPTH 8U
-
-/* UART TX FIFO depth */
-#define TX_FIFO_DEPTH 8U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
- * @{
- */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart,
- UART_WakeUpTypeDef WakeUpSelection);
-static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
- * @{
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and
-de-initialization functions
- * @brief Extended Initialization and Configuration Functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the
-USARTx or the UARTy in asynchronous mode.
- (+) For the asynchronous mode the parameters below can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data
-written in the data register is transmitted but is changed by the parity bit.
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- (++) One-Bit Sampling Method
- (+) For the asynchronous mode, the following advanced features can be
-configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) auto Baud rate detection
- [..]
- The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
- procedures (details for the procedures are available in reference manual).
-
-@endverbatim
-
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible UART formats are listed in the
- following table.
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Initialize the RS485 Driver enable feature according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart UART handle.
- * @param Polarity Select the driver enable polarity.
- * This parameter can be one of the following values:
- * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
- * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
- * @param AssertionTime Driver Enable assertion time:
- * 5-bit value defining the time between the activation of the DE (Driver
- * Enable) signal and the beginning of the start bit. It is expressed in sample
- * time units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param DeassertionTime Driver Enable deassertion time:
- * 5-bit value defining the time between the end of the last stop bit, in
- * a transmitted message, and the de-activation of the DE (Driver Enable)
- * signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending
- * on the oversampling rate).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
- uint32_t AssertionTime,
- uint32_t DeassertionTime) {
- uint32_t temp;
-
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
- /* Check the Driver Enable UART instance */
- assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
- /* Check the Driver Enable polarity */
- assert_param(IS_UART_DE_POLARITY(Polarity));
-
- /* Check the Driver Enable assertion time */
- assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
- /* Check the Driver Enable deassertion time */
- assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
- if (huart->gState == HAL_UART_STATE_RESET) {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- UART_InitCallbacksToDefault(huart);
-
- if (huart->MspInitCallback == NULL) {
- huart->MspInitCallback = HAL_UART_MspInit;
- }
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR) {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
- UART_AdvFeatureConfig(huart);
- }
-
- /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
- /* Set the Driver Enable polarity */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
- /* Set the Driver Enable assertion and deassertion times */
- temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
- * to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @}
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
- * @brief Extended functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of Wakeup and FIFO mode related callback
-functions.
-
- (#) Wakeup from Stop mode Callback:
- (+) HAL_UARTEx_WakeupCallback()
-
- (#) TX/RX Fifos Callbacks:
- (+) HAL_UARTEx_RxFifoFullCallback()
- (+) HAL_UARTEx_TxFifoEmptyCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief UART wakeup from Stop mode callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_WakeupCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART RX Fifo full callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_RxFifoFullCallback can be implemented in the user
- file.
- */
-}
-
-/**
- * @brief UART TX Fifo empty callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user
- file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides the following functions:
- (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART
-node address detection length to more than 4 bits for multiprocessor address
-mark wake up.
- (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from
-stop mode trigger: address match, Start Bit detection or RXNE bit status.
- (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU
-from stop mode
- (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
- (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
- (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
- (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
- (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
-
- [..] This subsection also provides a set of additional functions providing
-enhanced reception services to user. (For example, these functions allow
-application to handle use cases where number of data to be received is unknown).
-
- (#) Compared to standard reception services which only consider number of
-received data elements as reception completion criteria, these functions also
-consider additional events as triggers for updating reception status to caller :
- (+) Detection of inactivity period (RX line has not been active for a
-given period).
- (++) RX inactivity detected by IDLE event, i.e. RX line has been in
-idle state (normally high state) for 1 frame time, after last received byte.
- (++) RX inactivity detected by RTO, i.e. line has been in idle state
- for a programmable time, after last received byte.
- (+) Detection that a specific character has been received.
-
- (#) There are two mode of transfer:
- (+) Blocking mode: The reception is performed in polling mode, until
-either expected number of data is received, or till IDLE event occurs. Reception
-is handled only during function execution. When function exits, no data
-reception could occur. HAL status and number of actually received data elements,
- are returned by function after finishing transfer.
- (+) Non-Blocking mode: The reception is performed using Interrupts or
-DMA. These API's return the HAL status. The end of the data processing will be
-indicated through the dedicated UART IRQ when using Interrupt mode or the DMA
-IRQ when using DMA mode. The HAL_UARTEx_RxEventCallback() user callback will be
-executed during Receive process The HAL_UART_ErrorCallback()user callback will
-be executed when a reception error is detected.
-
- (#) Blocking mode API:
- (+) HAL_UARTEx_ReceiveToIdle()
-
- (#) Non-Blocking mode API with Interrupt:
- (+) HAL_UARTEx_ReceiveToIdle_IT()
-
- (#) Non-Blocking mode API with DMA:
- (+) HAL_UARTEx_ReceiveToIdle_DMA()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief By default in multiprocessor mode, when the wake up method is set
- * to address mark, the UART handles only 4-bit long addresses detection;
- * this API allows to enable longer addresses detection (6-, 7- or 8-bit
- * long).
- * @note Addresses detection lengths are: 6-bit address detection in 7-bit data
- * mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in
- * 9-bit data mode.
- * @param huart UART handle.
- * @param AddressLength This parameter can be one of the following values:
- * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
- * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(
- UART_HandleTypeDef *huart, uint32_t AddressLength) {
- /* Check the UART handle allocation */
- if (huart == NULL) {
- return HAL_ERROR;
- }
-
- /* Check the address length parameter */
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Set Wakeup from Stop mode interrupt flag selection.
- * @note It is the application responsibility to enable the interrupt used as
- * usart_wkup interrupt source before entering low-power mode.
- * @param huart UART handle.
- * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit
- * status. This parameter can be one of the following values:
- * @arg @ref UART_WAKEUP_ON_ADDRESS
- * @arg @ref UART_WAKEUP_ON_STARTBIT
- * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(
- UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) {
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart;
-
- /* check the wake-up from stop mode UART instance */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
- /* check the wake-up selection parameter */
- assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the wake-up selection scheme */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
-
- if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) {
- UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
- }
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- /* Wait until REACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart,
- HAL_UART_TIMEOUT_VALUE) != HAL_OK) {
- status = HAL_TIMEOUT;
- } else {
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return status;
-}
-
-/**
- * @brief Enable UART Stop Mode.
- * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART
- * clock is HSI or LSE.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) {
- /* Process Locked */
- __HAL_LOCK(huart);
-
- /* Set UESM bit */
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable UART Stop Mode.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) {
- /* Process Locked */
- __HAL_LOCK(huart);
-
- /* Clear UESM bit */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the FIFO mode.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) {
- uint32_t tmpcr1;
-
- /* Check parameters */
- assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Save actual UART configuration */
- tmpcr1 = READ_REG(huart->Instance->CR1);
-
- /* Disable UART */
- __HAL_UART_DISABLE(huart);
-
- /* Enable FIFO mode */
- SET_BIT(tmpcr1, USART_CR1_FIFOEN);
- huart->FifoMode = UART_FIFOMODE_ENABLE;
-
- /* Restore UART configuration */
- WRITE_REG(huart->Instance->CR1, tmpcr1);
-
- /* Determine the number of data to process during RX/TX ISR execution */
- UARTEx_SetNbDataToProcess(huart);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the FIFO mode.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) {
- uint32_t tmpcr1;
-
- /* Check parameters */
- assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Save actual UART configuration */
- tmpcr1 = READ_REG(huart->Instance->CR1);
-
- /* Disable UART */
- __HAL_UART_DISABLE(huart);
-
- /* Enable FIFO mode */
- CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
- huart->FifoMode = UART_FIFOMODE_DISABLE;
-
- /* Restore UART configuration */
- WRITE_REG(huart->Instance->CR1, tmpcr1);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the TXFIFO threshold.
- * @param huart UART handle.
- * @param Threshold TX FIFO threshold value
- * This parameter can be one of the following values:
- * @arg @ref UART_TXFIFO_THRESHOLD_1_8
- * @arg @ref UART_TXFIFO_THRESHOLD_1_4
- * @arg @ref UART_TXFIFO_THRESHOLD_1_2
- * @arg @ref UART_TXFIFO_THRESHOLD_3_4
- * @arg @ref UART_TXFIFO_THRESHOLD_7_8
- * @arg @ref UART_TXFIFO_THRESHOLD_8_8
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart,
- uint32_t Threshold) {
- uint32_t tmpcr1;
-
- /* Check parameters */
- assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
- assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Save actual UART configuration */
- tmpcr1 = READ_REG(huart->Instance->CR1);
-
- /* Disable UART */
- __HAL_UART_DISABLE(huart);
-
- /* Update TX threshold configuration */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
-
- /* Determine the number of data to process during RX/TX ISR execution */
- UARTEx_SetNbDataToProcess(huart);
-
- /* Restore UART configuration */
- WRITE_REG(huart->Instance->CR1, tmpcr1);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the RXFIFO threshold.
- * @param huart UART handle.
- * @param Threshold RX FIFO threshold value
- * This parameter can be one of the following values:
- * @arg @ref UART_RXFIFO_THRESHOLD_1_8
- * @arg @ref UART_RXFIFO_THRESHOLD_1_4
- * @arg @ref UART_RXFIFO_THRESHOLD_1_2
- * @arg @ref UART_RXFIFO_THRESHOLD_3_4
- * @arg @ref UART_RXFIFO_THRESHOLD_7_8
- * @arg @ref UART_RXFIFO_THRESHOLD_8_8
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart,
- uint32_t Threshold) {
- uint32_t tmpcr1;
-
- /* Check the parameters */
- assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
- assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Save actual UART configuration */
- tmpcr1 = READ_REG(huart->Instance->CR1);
-
- /* Disable UART */
- __HAL_UART_DISABLE(huart);
-
- /* Update RX threshold configuration */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
-
- /* Determine the number of data to process during RX/TX ISR execution */
- UARTEx_SetNbDataToProcess(huart);
-
- /* Restore UART configuration */
- WRITE_REG(huart->Instance->CR1, tmpcr1);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode till either the expected
- * number of data is received or an IDLE event occurs.
- * @note HAL_OK is returned if reception is completed (expected number of data
- * has been received) or if reception is stopped after IDLE event (less than the
- * expected number of data has been received) In this case, RxLen output
- * parameter indicates number of data available in reception buffer.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
- * uint16_t. In this case, Size must indicate the number of uint16_t available
- * through pData.
- * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
- * is not empty. Read operations from the RDR register are performed when
- * RXFNE flag is set. From hardware perspective, RXFNE flag and
- * RXNE are mapped on the same bit-field.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
- * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
- * @param RxLen Number of data elements finally received
- * (could be lower than Size, in case reception ends on IDLE
- * event)
- * @param Timeout Timeout duration expressed in ms (covers the whole reception
- * sequence).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size,
- uint16_t *RxLen, uint32_t Timeout) {
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint16_t uhMask;
- uint32_t tickstart;
-
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- uhMask = huart->Mask;
-
- /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a
- * uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
- (huart->Init.Parity == UART_PARITY_NONE)) {
- pdata8bits = NULL;
- pdata16bits = (uint16_t *)pData;
- } else {
- pdata8bits = pData;
- pdata16bits = NULL;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Initialize output number of received elements */
- *RxLen = 0U;
-
- /* as long as data have to be received */
- while (huart->RxXferCount > 0U) {
- /* Check if IDLE flag is set */
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) {
- /* Clear IDLE flag in ISR */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-
- /* If Set, but no data ever received, clear flag without exiting loop */
- /* If Set, and data has already been received, this means Idle Event is
- * valid : End reception */
- if (*RxLen > 0U) {
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
- }
- }
-
- /* Check if RXNE flag is set */
- if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) {
- if (pdata8bits == NULL) {
- *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
- pdata16bits++;
- } else {
- *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- pdata8bits++;
- }
- /* Increment number of received elements */
- *RxLen += 1U;
- huart->RxXferCount--;
- }
-
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY) {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) {
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set number of received elements in output parameter : RxLen */
- *RxLen = huart->RxXferSize - huart->RxXferCount;
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode till either the expected
- * number of data is received or an IDLE event occurs.
- * @note Reception is initiated by this function call. Further progress of
- * reception is achieved thanks to UART interrupts raised by RXNE and IDLE
- * events. Callback is called at end of reception indicating number of received
- * data elements.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
- * uint16_t. In this case, Size must indicate the number of uint16_t available
- * through pData.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
- * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size) {
- HAL_StatusTypeDef status;
-
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- /* Set Reception type to reception till IDLE Event*/
- huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
- status = UART_Start_Receive_IT(huart, pData, Size);
-
- /* Check Rx process has been successfully started */
- if (status == HAL_OK) {
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- } else {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception
- abortion. (Overrun error for instance). In such case Reception Type
- has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
- }
-
- return status;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode till either the expected number
- * of data is received or an IDLE event occurs.
- * @note Reception is initiated by this function call. Further progress of
- * reception is achieved thanks to DMA services, transferring automatically
- * received data elements in user reception buffer and calling registered
- * callbacks at half/end of reception. UART IDLE events are also used to
- * consider reception phase as ended. In all cases, callback execution will
- * indicate number of received data elements.
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @note When UART parity is not enabled (PCE = 0), and Word Length is
- * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
- * uint16_t. In this case, Size must indicate the number of uint16_t available
- * through pData.
- * @param huart UART handle.
- * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
- * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart,
- uint8_t *pData, uint16_t Size) {
- HAL_StatusTypeDef status;
-
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY) {
- if ((pData == NULL) || (Size == 0U)) {
- return HAL_ERROR;
- }
-
- __HAL_LOCK(huart);
-
- /* Set Reception type to reception till IDLE Event*/
- huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
- status = UART_Start_Receive_DMA(huart, pData, Size);
-
- /* Check Rx process has been successfully started */
- if (status == HAL_OK) {
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- } else {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception
- abortion. (Overrun error for instance). In such case Reception Type
- has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
- }
-
- return status;
- } else {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup UARTEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Initialize the UART wake-up from stop mode parameters when triggered
- * by address detection.
- * @param huart UART handle.
- * @param WakeUpSelection UART wake up from stop mode parameters.
- * @retval None
- */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart,
- UART_WakeUpTypeDef WakeUpSelection) {
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
-
- /* Set the USART address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7,
- WakeUpSelection.AddressLength);
-
- /* Set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD,
- ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
-}
-
-/**
- * @brief Calculate the number of data to process in RX/TX ISR.
- * @note The RX FIFO depth and the TX FIFO depth is extracted from
- * the UART configuration registers.
- * @param huart UART handle.
- * @retval None
- */
-static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) {
- uint8_t rx_fifo_depth;
- uint8_t tx_fifo_depth;
- uint8_t rx_fifo_threshold;
- uint8_t tx_fifo_threshold;
- static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
-
- if (huart->FifoMode == UART_FIFOMODE_DISABLE) {
- huart->NbTxDataToProcess = 1U;
- huart->NbRxDataToProcess = 1U;
- } else {
- rx_fifo_depth = RX_FIFO_DEPTH;
- tx_fifo_depth = TX_FIFO_DEPTH;
- rx_fifo_threshold =
- (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >>
- USART_CR3_RXFTCFG_Pos);
- tx_fifo_threshold =
- (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >>
- USART_CR3_TXFTCFG_Pos);
- huart->NbTxDataToProcess =
- ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
- (uint16_t)denominator[tx_fifo_threshold];
- huart->NbRxDataToProcess =
- ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
- (uint16_t)denominator[rx_fifo_threshold];
- }
-}
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter
+ Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+ * @{
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart,
+ UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and
+de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the
+USARTx or the UARTy in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data
+written in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be
+configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param Polarity Select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver
+ * Enable) signal and the beginning of the start bit. It is expressed in sample
+ * time units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in
+ * a transmitted message, and the de-activation of the DE (Driver Enable)
+ * signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending
+ * on the oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
+ uint32_t AssertionTime,
+ uint32_t DeassertionTime) {
+ uint32_t temp;
+
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if (huart->gState == HAL_UART_STATE_RESET) {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL) {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are
+ * set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR) {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState
+ * to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of Wakeup and FIFO mode related callback
+functions.
+
+ (#) Wakeup from Stop mode Callback:
+ (+) HAL_UARTEx_WakeupCallback()
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_UARTEx_RxFifoFullCallback()
+ (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART RX Fifo full callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxFifoFullCallback can be implemented in the user
+ file.
+ */
+}
+
+/**
+ * @brief UART TX Fifo empty callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user
+ file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART
+node address detection length to more than 4 bits for multiprocessor address
+mark wake up.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from
+stop mode trigger: address match, Start Bit detection or RXNE bit status.
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU
+from stop mode
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+ (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+ [..] This subsection also provides a set of additional functions providing
+enhanced reception services to user. (For example, these functions allow
+application to handle use cases where number of data to be received is unknown).
+
+ (#) Compared to standard reception services which only consider number of
+received data elements as reception completion criteria, these functions also
+consider additional events as triggers for updating reception status to caller :
+ (+) Detection of inactivity period (RX line has not been active for a
+given period).
+ (++) RX inactivity detected by IDLE event, i.e. RX line has been in
+idle state (normally high state) for 1 frame time, after last received byte.
+ (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ for a programmable time, after last received byte.
+ (+) Detection that a specific character has been received.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The reception is performed in polling mode, until
+either expected number of data is received, or till IDLE event occurs. Reception
+is handled only during function execution. When function exits, no data
+reception could occur. HAL status and number of actually received data elements,
+ are returned by function after finishing transfer.
+ (+) Non-Blocking mode: The reception is performed using Interrupts or
+DMA. These API's return the HAL status. The end of the data processing will be
+indicated through the dedicated UART IRQ when using Interrupt mode or the DMA
+IRQ when using DMA mode. The HAL_UARTEx_RxEventCallback() user callback will be
+executed during Receive process The HAL_UART_ErrorCallback()user callback will
+be executed when a reception error is detected.
+
+ (#) Blocking mode API:
+ (+) HAL_UARTEx_ReceiveToIdle()
+
+ (#) Non-Blocking mode API with Interrupt:
+ (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+ (#) Non-Blocking mode API with DMA:
+ (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data
+ * mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in
+ * 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength This parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(
+ UART_HandleTypeDef *huart, uint32_t AddressLength) {
+ /* Check the UART handle allocation */
+ if (huart == NULL) {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @note It is the application responsibility to enable the interrupt used as
+ * usart_wkup interrupt source before entering low-power mode.
+ * @param huart UART handle.
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit
+ * status. This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(
+ UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) {
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) {
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart,
+ HAL_UART_TIMEOUT_VALUE) != HAL_OK) {
+ status = HAL_TIMEOUT;
+ } else {
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART
+ * clock is HSI or LSE.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Set UESM bit */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Clear UESM bit */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) {
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) {
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Disable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_TXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart,
+ uint32_t Threshold) {
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_RXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart,
+ uint32_t Threshold) {
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode till either the expected
+ * number of data is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data
+ * has been received) or if reception is stopped after IDLE event (less than the
+ * expected number of data has been received) In this case, RxLen output
+ * parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
+ * uint16_t. In this case, Size must indicate the number of uint16_t available
+ * through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @param RxLen Number of data elements finally received
+ * (could be lower than Size, in case reception ends on IDLE
+ * event)
+ * @param Timeout Timeout duration expressed in ms (covers the whole reception
+ * sequence).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size,
+ uint16_t *RxLen, uint32_t Timeout) {
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a
+ * uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) &&
+ (huart->Init.Parity == UART_PARITY_NONE)) {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *)pData;
+ } else {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ /* Initialize output number of received elements */
+ *RxLen = 0U;
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U) {
+ /* Check if IDLE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) {
+ /* Clear IDLE flag in ISR */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* If Set, but no data ever received, clear flag without exiting loop */
+ /* If Set, and data has already been received, this means Idle Event is
+ * valid : End reception */
+ if (*RxLen > 0U) {
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ }
+
+ /* Check if RXNE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) {
+ if (pdata8bits == NULL) {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ } else {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ /* Increment number of received elements */
+ *RxLen += 1U;
+ huart->RxXferCount--;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY) {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set number of received elements in output parameter : RxLen */
+ *RxLen = huart->RxXferSize - huart->RxXferCount;
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode till either the expected
+ * number of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of
+ * reception is achieved thanks to UART interrupts raised by RXNE and IDLE
+ * events. Callback is called at end of reception indicating number of received
+ * data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
+ * uint16_t. In this case, Size must indicate the number of uint16_t available
+ * through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size) {
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ (void)UART_Start_Receive_IT(huart, pData, Size);
+
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ } else {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to
+ HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+
+ return status;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode till either the expected number
+ * of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of
+ * reception is achieved thanks to DMA services, transferring automatically
+ * received data elements in user reception buffer and calling registered
+ * callbacks at half/end of reception. UART IDLE events are also used to
+ * consider reception phase as ended. In all cases, callback execution will
+ * indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is
+ * configured to 9 bits (M1-M0 = 01), the received data is handled as a set of
+ * uint16_t. In this case, Size must indicate the number of uint16_t available
+ * through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart,
+ uint8_t *pData, uint16_t Size) {
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY) {
+ if ((pData == NULL) || (Size == 0U)) {
+ return HAL_ERROR;
+ }
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ status = UART_Start_Receive_DMA(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK) {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ } else {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception
+ abortion. (Overrun error for instance). In such case Reception Type
+ has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ } else {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+ * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA()
+ * API are called, progress of reception process is provided to application
+ * through calls of Rx Event callback (either default one
+ * HAL_UARTEx_RxEventCallback() or user registered one). As several types
+ * of events could occur (IDLE event, Half Transfer, or Transfer Complete), this
+ * function allows to retrieve the Rx Event type that has lead to Rx Event
+ * callback execution.
+ * @note This function is expected to be called within the user implementation
+ * of Rx Event Callback, in order to provide the accurate value : In Interrupt
+ * Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected
+ * nb of data has been received)
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception
+ * has been completed (nb of received data is lower than expected one) In DMA
+ * Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected
+ * nb of data has been received)
+ * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been
+ * received
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception
+ * has been completed (nb of received data is lower than expected one). In DMA
+ * mode, RxEvent callback could be called several times; When DMA is configured
+ * in Normal Mode, HT event does not stop Reception process; When DMA is
+ * configured in Circular Mode, HT, TC or IDLE events don't stop Reception
+ * process;
+ * @param huart UART handle.
+ * @retval Rx Event Type (return vale will be a value of @ref
+ * UART_RxEvent_Type_Values)
+ */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(
+ const UART_HandleTypeDef *huart) {
+ /* Return Rx Event type value, as stored in UART handle */
+ return (huart->RxEventType);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered
+ * by address detection.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
+ * @retval None
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart,
+ UART_WakeUpTypeDef WakeUpSelection) {
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7,
+ WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD,
+ ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the UART configuration registers.
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) {
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (huart->FifoMode == UART_FIFOMODE_DISABLE) {
+ huart->NbTxDataToProcess = 1U;
+ huart->NbRxDataToProcess = 1U;
+ } else {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold =
+ (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >>
+ USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold =
+ (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >>
+ USART_CR3_TXFTCFG_Pos);
+ huart->NbTxDataToProcess =
+ ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ huart->NbRxDataToProcess =
+ ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
index 5361f6d..367dfa8 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
@@ -1,1253 +1,1247 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_adc.c
- * @author MCD Application Team
- * @brief ADC LL module driver
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_ll_adc.h"
-
-#include "stm32g4xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32G4xx_LL_Driver
- * @{
- */
-
-#if defined(ADC1) || defined(ADC2) || defined(ADC3) || defined(ADC4) || \
- defined(ADC5)
-
-/** @addtogroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup ADC_LL_Private_Constants
- * @{
- */
-
-/* Definitions of ADC hardware constraints delays */
-/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
-/* not timeout values: */
-/* Timeout values for ADC operations are dependent to device clock */
-/* configuration (system clock versus ADC clock), */
-/* and therefore must be defined in user application. */
-/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
-/* values definition. */
-/* Note: ADC timeout values are defined here in CPU cycles to be independent */
-/* of device clock setting. */
-/* In user application, ADC timeout values should be defined with */
-/* temporal values, in function of device clock settings. */
-/* Highest ratio CPU clock frequency vs ADC clock frequency: */
-/* - ADC clock from synchronous clock with AHB prescaler 512, */
-/* ADC prescaler 4. */
-/* Ratio max = 512 *4 = 2048 */
-/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
-/* Highest CPU clock PLL (PLLR). */
-/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
-/* = 3968 */
-/* Unit: CPU cycles. */
-#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
-#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
-#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES \
- (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup ADC_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* common to several ADC instances. */
-#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
- (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) || \
- ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) || \
- ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) || \
- ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256))
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC instance. */
-#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
- (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) || \
- ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) || \
- ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) || \
- ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B))
-
-#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
- (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) || \
- ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT))
-
-#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
- (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) || \
- ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT))
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group regular */
-#if defined(STM32G474xx) || defined(STM32G484xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
- ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
- ((__ADC_INSTANCE__) == ADC5)) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4))))
-#elif defined(STM32G473xx) || defined(STM32G483xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
- ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
- ((__ADC_INSTANCE__) == ADC5)) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2))))
-#elif defined(STM32G471xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
- (((__ADC_INSTANCE__) == ADC3) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
- (((__ADC_INSTANCE__) == ADC3) && \
- (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
- ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2))))
-#endif
-
-#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) || \
- ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
-
-#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
- (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) || \
- ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) || \
- ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
-
-#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
- (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) || \
- ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN))
-
-#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) || \
- ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
-
-#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) || \
- ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS))
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group injected */
-#if defined(STM32G474xx) || defined(STM32G484xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
- ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
- ((__ADC_INSTANCE__) == ADC5)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
-#elif defined(STM32G473xx) || defined(STM32G483xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
- ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
- ((__ADC_INSTANCE__) == ADC5)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
-#elif defined(STM32G471xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
- ((((__ADC_INSTANCE__) == ADC3)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
-#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
- ((((__ADC_INSTANCE__) == ADC3)) && \
- (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) || \
- ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
-#endif
-
-#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
- (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) || \
- ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) || \
- ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING))
-
-#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) || \
- ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) || \
- ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) || \
- ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) || \
- ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) || \
- ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK))
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* multimode. */
-#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
- (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) || \
- ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM))
-
-#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
- (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) || \
- ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) || \
- ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) || \
- ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) || \
- ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B))
-
-#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
- (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) || \
- ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES))
-
-#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
- (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) || \
- ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) || \
- ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE))
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of all ADC instances belonging to
- * the same ADC common instance to their default reset values.
- * @note This function is performing a hard reset, using high level
- * clock source RCC ADC reset.
- * Caution: On this STM32 series, if several ADC instances are available
- * on the selected device, RCC ADC reset will reset
- * all ADC instances belonging to the common ADC instance.
- * To de-initialize only 1 ADC instance, use
- * function @ref LL_ADC_DeInit().
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) {
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-
- if (ADCxy_COMMON == ADC12_COMMON) {
- /* Force reset of ADC clock (core clock) */
- LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
-
- /* Release reset of ADC clock (core clock) */
- LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
- }
-#if defined(ADC345_COMMON)
- else {
- /* Force reset of ADC clock (core clock) */
- LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
-
- /* Release reset of ADC clock (core clock) */
- LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
- }
-#endif
-
- return SUCCESS;
-}
-
-/**
- * @brief Initialize some features of ADC common parameters
- * (all ADC instances belonging to the same ADC common instance)
- * and multimode (for devices with several ADC instances available).
- * @note The setting of ADC common parameters is conditioned to
- * ADC instances state:
- * All ADC instances belonging to the same ADC common instance
- * must be disabled.
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro
- * @ref __LL_ADC_COMMON_INSTANCE() )
- * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef
- * structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are initialized
- * - ERROR: ADC common registers are not initialized
- */
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON,
- LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) {
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
- assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
- if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) {
- assert_param(
- IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
- assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(
- ADC_CommonInitStruct->MultiTwoSamplingDelay));
- }
-#endif /* ADC_MULTIMODE_SUPPORT */
-
- /* Note: Hardware constraint (refer to description of functions */
- /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 series, setting of these features is conditioned to */
- /* ADC state: */
- /* All ADC instances of the ADC common group must be disabled. */
- if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) {
- /* Configuration of ADC hierarchical scope: */
- /* - common to several ADC */
- /* (all ADC instances belonging to the same ADC common instance) */
- /* - Set ADC clock (conversion clock) */
- /* - multimode (if several ADC instances available on the */
- /* selected device) */
- /* - Set ADC multimode configuration */
- /* - Set ADC multimode DMA transfer */
- /* - Set ADC multimode: delay between 2 sampling phases */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) {
- MODIFY_REG(ADCxy_COMMON->CCR,
- ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA |
- ADC_CCR_DELAY,
- ADC_CommonInitStruct->CommonClock |
- ADC_CommonInitStruct->Multimode |
- ADC_CommonInitStruct->MultiDMATransfer |
- ADC_CommonInitStruct->MultiTwoSamplingDelay);
- } else {
- MODIFY_REG(ADCxy_COMMON->CCR,
- ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA |
- ADC_CCR_DELAY,
- ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT);
- }
-#else
- LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
-#endif
- } else {
- /* Initialization error: One or several ADC instances belonging to */
- /* the same ADC common instance are not disabled. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
- * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef
- * structure whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) {
- /* Set ADC_CommonInitStruct fields to default values */
- /* Set fields of ADC common */
- /* (all ADC instances belonging to the same ADC common instance) */
- ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Set fields of ADC multimode */
- ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
- ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
- ADC_CommonInitStruct->MultiTwoSamplingDelay =
- LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
-#endif /* ADC_MULTIMODE_SUPPORT */
-}
-
-/**
- * @brief De-initialize registers of the selected ADC instance
- * to their default reset values.
- * @note To reset all ADC instances quickly (perform a hard reset),
- * use function @ref LL_ADC_CommonDeInit().
- * @note If this functions returns error status, it means that ADC instance
- * is in an unknown state.
- * In this case, perform a hard reset using high level
- * clock source RCC ADC reset.
- * Caution: On this STM32 series, if several ADC instances are available
- * on the selected device, RCC ADC reset will reset
- * all ADC instances belonging to the common ADC instance.
- * Refer to function @ref LL_ADC_CommonDeInit().
- * @param ADCx ADC instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are de-initialized
- * - ERROR: ADC registers are not de-initialized
- */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) {
- ErrorStatus status = SUCCESS;
-
- __IO uint32_t timeout_cpu_cycles = 0UL;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- /* Disable ADC instance if not already disabled. */
- if (LL_ADC_IsEnabled(ADCx) == 1UL) {
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
- /* Stop potential ADC conversion on going on ADC group regular. */
- if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) {
- if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) {
- LL_ADC_REG_StopConversion(ADCx);
- }
- }
-
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
- /* Stop potential ADC conversion on going on ADC group injected. */
- if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) {
- if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) {
- LL_ADC_INJ_StopConversion(ADCx);
- }
- }
-
- /* Wait for ADC conversions are effectively stopped */
- timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
- while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) |
- LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) {
- timeout_cpu_cycles--;
- if (timeout_cpu_cycles == 0UL) {
- /* Time-out error */
- status = ERROR;
- break;
- }
- }
-
- /* Flush group injected contexts queue (register JSQR): */
- /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
- /* contexts queue is maintained with the last active context). */
- LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
-
- /* Disable the ADC instance */
- LL_ADC_Disable(ADCx);
-
- /* Wait for ADC instance is effectively disabled */
- timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
- while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) {
- timeout_cpu_cycles--;
- if (timeout_cpu_cycles == 0UL) {
- /* Time-out error */
- status = ERROR;
- break;
- }
- }
- }
-
- /* Check whether ADC state is compliant with expected state */
- if (READ_BIT(ADCx->CR, (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |
- ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) ==
- 0UL) {
- /* ========== Reset ADC registers ========== */
- /* Reset register IER */
- CLEAR_BIT(ADCx->IER, (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS |
- LL_ADC_IT_OVR | LL_ADC_IT_EOSMP | LL_ADC_IT_JEOC |
- LL_ADC_IT_JEOS | LL_ADC_IT_JQOVF | LL_ADC_IT_AWD1 |
- LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3));
-
- /* Reset register ISR */
- SET_BIT(ADCx->ISR,
- (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS |
- LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP | LL_ADC_FLAG_JEOC |
- LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_AWD1 |
- LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3));
-
- /* Reset register CR */
- /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
- /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
- /* access mode "read-set": no direct reset applicable. */
- /* - Reset Calibration mode to default setting (single ended). */
- /* - Disable ADC internal voltage regulator. */
- /* - Enable ADC deep power down. */
- /* Note: ADC internal voltage regulator disable and ADC deep power */
- /* down enable are conditioned to ADC state disabled: */
- /* already done above. */
- CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
- SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
-
- /* Reset register CFGR */
- MODIFY_REG(
- ADCx->CFGR,
- (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN |
- ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM |
- ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES |
- ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
- ADC_CFGR_JQDIS);
-
- /* Reset register CFGR2 */
- CLEAR_BIT(
- ADCx->CFGR2,
- (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_SWTRIG |
- ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG | ADC_CFGR2_GCOMP | ADC_CFGR2_OVSR |
- ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE));
-
- /* Reset register SMPR1 */
- CLEAR_BIT(ADCx->SMPR1, (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
- ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
- ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1));
-
- /* Reset register SMPR2 */
- CLEAR_BIT(ADCx->SMPR2,
- (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
- ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
- ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10));
-
- /* Reset register TR1 */
- MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1,
- ADC_TR1_HT1);
-
- /* Reset register TR2 */
- MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
-
- /* Reset register TR3 */
- MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
-
- /* Reset register SQR1 */
- CLEAR_BIT(ADCx->SQR1, (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
- ADC_SQR1_SQ1 | ADC_SQR1_L));
-
- /* Reset register SQR2 */
- CLEAR_BIT(ADCx->SQR2, (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
- ADC_SQR2_SQ6 | ADC_SQR2_SQ5));
-
- /* Reset register SQR3 */
- CLEAR_BIT(ADCx->SQR3, (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
- ADC_SQR3_SQ11 | ADC_SQR3_SQ10));
-
- /* Reset register SQR4 */
- CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
-
- /* Reset register JSQR */
- CLEAR_BIT(ADCx->JSQR,
- (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |
- ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1));
-
- /* Reset register DR */
- /* Note: bits in access mode read only, no direct reset applicable */
-
- /* Reset register OFR1 */
- CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH |
- ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN |
- ADC_OFR1_OFFSETPOS);
- /* Reset register OFR2 */
- CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH |
- ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN |
- ADC_OFR2_OFFSETPOS);
- /* Reset register OFR3 */
- CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH |
- ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN |
- ADC_OFR3_OFFSETPOS);
- /* Reset register OFR4 */
- CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH |
- ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN |
- ADC_OFR4_OFFSETPOS);
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* Note: bits in access mode read only, no direct reset applicable */
-
- /* Reset register AWD2CR */
- CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
-
- /* Reset register AWD3CR */
- CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
-
- /* Reset register DIFSEL */
- CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
-
- /* Reset register CALFACT */
- CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-
- /* Reset register GCOMP */
- CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
- } else {
- /* ADC instance is in an unknown state */
- /* Need to performing a hard reset of ADC instance, using high level */
- /* clock source RCC ADC reset. */
- /* Caution: On this STM32 series, if several ADC instances are available */
- /* on the selected device, RCC ADC reset will reset */
- /* all ADC instances belonging to the common ADC instance. */
- /* Caution: On this STM32 series, if several ADC instances are available */
- /* on the selected device, RCC ADC reset will reset */
- /* all ADC instances belonging to the common ADC instance. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, some other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) {
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
- assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
- assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if (LL_ADC_IsEnabled(ADCx) == 0UL) {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC instance */
- /* - Set ADC data resolution */
- /* - Set ADC conversion data alignment */
- /* - Set ADC low power mode */
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY,
- ADC_InitStruct->Resolution | ADC_InitStruct->DataAlignment |
- ADC_InitStruct->LowPowerMode);
-
- } else {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) {
- /* Set ADC_InitStruct fields to default values */
- /* Set fields of ADC instance */
- ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
- ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
- ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
-}
-
-/**
- * @brief Initialize some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx,
- LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) {
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
- assert_param(
- IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
- assert_param(
- IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
- if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) {
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(
- ADC_REG_InitStruct->SequencerDiscont));
-
- /* ADC group regular continuous mode and discontinuous mode */
- /* can not be enabled simultenaeously */
- assert_param(
- (ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) ||
- (ADC_REG_InitStruct->SequencerDiscont ==
- LL_ADC_REG_SEQ_DISCONT_DISABLE));
- }
- assert_param(
- IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
- assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
- assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if (LL_ADC_IsEnabled(ADCx) == 0UL) {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group regular */
- /* - Set ADC group regular trigger source */
- /* - Set ADC group regular sequencer length */
- /* - Set ADC group regular sequencer discontinuous mode */
- /* - Set ADC group regular continuous mode */
- /* - Set ADC group regular conversion data transfer: no transfer or */
- /* transfer by DMA, and DMA requests mode */
- /* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
- /* setting of trigger source to SW start. */
- if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) {
- MODIFY_REG(ADCx->CFGR,
- ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN |
- ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN |
- ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD,
- ADC_REG_InitStruct->TriggerSource |
- ADC_REG_InitStruct->SequencerDiscont |
- ADC_REG_InitStruct->ContinuousMode |
- ADC_REG_InitStruct->DMATransfer |
- ADC_REG_InitStruct->Overrun);
- } else {
- MODIFY_REG(
- ADCx->CFGR,
- ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN |
- ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN |
- ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD,
- ADC_REG_InitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE |
- ADC_REG_InitStruct->ContinuousMode |
- ADC_REG_InitStruct->DMATransfer | ADC_REG_InitStruct->Overrun);
- }
-
- /* Set ADC group regular sequencer length and scan direction */
- LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
- } else {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) {
- /* Set ADC_REG_InitStruct fields to default values */
- /* Set fields of ADC group regular */
- /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
- /* setting of trigger source to SW start. */
- ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
- ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
- ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
-}
-
-/**
- * @brief Initialize some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @note Caution if feature ADC group injected contexts queue is enabled
- * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
- * using successively several times this function will appear as
- * having no effect.
- * To set several features of ADC group injected, use
- * function @ref LL_ADC_INJ_ConfigQueueContext().
- * @param ADCx ADC instance
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx,
- LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) {
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
- assert_param(
- IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
- assert_param(
- IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
- if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) {
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(
- ADC_INJ_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if (LL_ADC_IsEnabled(ADCx) == 0UL) {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group injected */
- /* - Set ADC group injected trigger source */
- /* - Set ADC group injected sequencer length */
- /* - Set ADC group injected sequencer discontinuous mode */
- /* - Set ADC group injected conversion trigger: independent or */
- /* from ADC group regular */
- /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
- /* setting of trigger source to SW start. */
- if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) {
- MODIFY_REG(
- ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO,
- ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto);
- } else {
- MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO,
- LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto);
- }
-
- MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL,
- ADC_INJ_InitStruct->TriggerSource |
- ADC_INJ_InitStruct->SequencerLength);
- } else {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) {
- /* Set ADC_INJ_InitStruct fields to default values */
- /* Set fields of ADC group injected */
- ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
- ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
- ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_ll_adc.h"
+
+#include "stm32g4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G4xx_LL_Driver
+ * @{
+ */
+
+#if defined(ADC1) || defined(ADC2) || defined(ADC3) || defined(ADC4) || \
+ defined(ADC5)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+ * @{
+ */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values: */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
+/* values definition. */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent */
+/* of device clock setting. */
+/* In user application, ADC timeout values should be defined with */
+/* temporal values, in function of device clock settings. */
+/* Highest ratio CPU clock frequency vs ADC clock frequency: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* ADC prescaler 4. */
+/* Ratio max = 512 *4 = 2048 */
+/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
+/* Highest CPU clock PLL (PLLR). */
+/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
+/* = 3968 */
+/* Unit: CPU cycles. */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES \
+ (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) || \
+ ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256))
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B))
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) || \
+ ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT))
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) || \
+ ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT))
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
+ ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
+ ((__ADC_INSTANCE__) == ADC5)) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4))))
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
+ ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
+ ((__ADC_INSTANCE__) == ADC5)) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2))))
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
+ (((__ADC_INSTANCE__) == ADC3) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2))))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || \
+ defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))) || \
+ (((__ADC_INSTANCE__) == ADC3) && \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) || \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2))))
+#endif /* STM32G4xx */
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) || \
+ ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) || \
+ ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) || \
+ ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) || \
+ ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN))
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) || \
+ ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) || \
+ ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS))
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
+ ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
+ ((__ADC_INSTANCE__) == ADC5)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
+ ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || \
+ ((__ADC_INSTANCE__) == ADC5)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
+ ((((__ADC_INSTANCE__) == ADC3)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || \
+ defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) || \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))) || \
+ ((((__ADC_INSTANCE__) == ADC3)) && \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) || \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3))))
+#endif /* STM32G4xx */
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) || \
+ ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) || \
+ ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING))
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) || \
+ ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) || \
+ ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) || \
+ ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) || \
+ ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) || \
+ ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* multimode. */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) || \
+ ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM))
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
+ (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) || \
+ ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) || \
+ ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) || \
+ ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) || \
+ ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B))
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
+ (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) || \
+ ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES))
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
+ (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) || \
+ ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) || \
+ ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE))
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @note This function is performing a hard reset, using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 series, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * To de-initialize only 1 ADC instance, use
+ * function @ref LL_ADC_DeInit().
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) {
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ if (ADCxy_COMMON == ADC12_COMMON) {
+ /* Force reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
+ }
+#if defined(ADC345_COMMON)
+ else {
+ /* Force reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
+ }
+#endif /* ADC345_COMMON */
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro
+ * @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef
+ * structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(
+ ADC_Common_TypeDef *ADCxy_COMMON,
+ const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) {
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
+ if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) {
+ assert_param(
+ IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
+ assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(
+ pADC_CommonInitStruct->MultiTwoSamplingDelay));
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 series, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ /* - multimode (if several ADC instances available on the */
+ /* selected device) */
+ /* - Set ADC multimode configuration */
+ /* - Set ADC multimode DMA transfer */
+ /* - Set ADC multimode: delay between 2 sampling phases */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA |
+ ADC_CCR_DELAY,
+ pADC_CommonInitStruct->CommonClock |
+ pADC_CommonInitStruct->Multimode |
+ pADC_CommonInitStruct->MultiDMATransfer |
+ pADC_CommonInitStruct->MultiTwoSamplingDelay);
+ } else {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA |
+ ADC_CCR_DELAY,
+ pADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT);
+ }
+#else
+ LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
+#endif /* ADC_MULTIMODE_SUPPORT */
+ } else {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef
+ * structure whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) {
+ /* Set pADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Set fields of ADC multimode */
+ pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
+ pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+ pADC_CommonInitStruct->MultiTwoSamplingDelay =
+ LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @note If this functions returns error status, it means that ADC instance
+ * is in an unknown state.
+ * In this case, perform a hard reset using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 series, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * Refer to function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) {
+ ErrorStatus status = SUCCESS;
+
+ __IO uint32_t timeout_cpu_cycles = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 1UL) {
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) {
+ if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) {
+ LL_ADC_REG_StopConversion(ADCx);
+ }
+ }
+
+ /* Stop potential ADC conversion on going on ADC group injected. */
+ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) {
+ if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) {
+ LL_ADC_INJ_StopConversion(ADCx);
+ }
+ }
+
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) |
+ LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL) {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+
+ /* Flush group injected contexts queue (register JSQR): */
+ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
+ /* contexts queue is maintained with the last active context). */
+ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+
+ /* Wait for ADC instance is effectively disabled */
+ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+ while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL) {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ if (READ_BIT(ADCx->CR, (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |
+ ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) ==
+ 0UL) {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(ADCx->IER, (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS |
+ LL_ADC_IT_OVR | LL_ADC_IT_EOSMP | LL_ADC_IT_JEOC |
+ LL_ADC_IT_JEOS | LL_ADC_IT_JQOVF | LL_ADC_IT_AWD1 |
+ LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3));
+
+ /* Reset register ISR */
+ SET_BIT(ADCx->ISR,
+ (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS |
+ LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP | LL_ADC_FLAG_JEOC |
+ LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_AWD1 |
+ LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3));
+
+ /* Reset register CR */
+ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
+ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
+ /* access mode "read-set": no direct reset applicable. */
+ /* - Reset Calibration mode to default setting (single ended). */
+ /* - Disable ADC internal voltage regulator. */
+ /* - Enable ADC deep power down. */
+ /* Note: ADC internal voltage regulator disable and ADC deep power */
+ /* down enable are conditioned to ADC state disabled: */
+ /* already done above. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+ SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR */
+ MODIFY_REG(
+ ADCx->CFGR,
+ (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN |
+ ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM |
+ ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES |
+ ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
+ ADC_CFGR_JQDIS);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(
+ ADCx->CFGR2,
+ (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_SWTRIG |
+ ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG | ADC_CFGR2_GCOMP | ADC_CFGR2_OVSR |
+ ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE));
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1, (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1));
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10));
+
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1,
+ ADC_TR1_HT1);
+
+ /* Reset register TR2 */
+ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+
+ /* Reset register TR3 */
+ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1, (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L));
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2, (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5));
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(ADCx->SQR3, (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ ADC_SQR3_SQ11 | ADC_SQR3_SQ10));
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1));
+
+ /* Reset register DR */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH |
+ ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN |
+ ADC_OFR1_OFFSETPOS);
+ /* Reset register OFR2 */
+ CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH |
+ ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN |
+ ADC_OFR2_OFFSETPOS);
+ /* Reset register OFR3 */
+ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH |
+ ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN |
+ ADC_OFR3_OFFSETPOS);
+ /* Reset register OFR4 */
+ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH |
+ ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN |
+ ADC_OFR4_OFFSETPOS);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+ /* Reset register GCOMP */
+ CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
+ } else {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ /* Caution: On this STM32 series, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ /* Caution: On this STM32 series, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 series).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 series. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx,
+ const LL_ADC_InitTypeDef *pADC_InitStruct) {
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ /* - Set ADC low power mode */
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY,
+ pADC_InitStruct->Resolution | pADC_InitStruct->DataAlignment |
+ pADC_InitStruct->LowPowerMode);
+
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) {
+ /* Set pADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
+ pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+ pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 series. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx,
+ const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) {
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(
+ IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct->TriggerSource));
+ assert_param(
+ IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
+ if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(
+ pADC_RegInitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param(
+ (pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) ||
+ (pADC_RegInitStruct->SequencerDiscont ==
+ LL_ADC_REG_SEQ_DISCONT_DISABLE));
+ }
+ assert_param(
+ IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
+ assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN |
+ ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN |
+ ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD,
+ pADC_RegInitStruct->TriggerSource |
+ pADC_RegInitStruct->SequencerDiscont |
+ pADC_RegInitStruct->ContinuousMode |
+ pADC_RegInitStruct->DMATransfer |
+ pADC_RegInitStruct->Overrun);
+ } else {
+ MODIFY_REG(
+ ADCx->CFGR,
+ ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN |
+ ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN |
+ ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD,
+ pADC_RegInitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE |
+ pADC_RegInitStruct->ContinuousMode |
+ pADC_RegInitStruct->DMATransfer | pADC_RegInitStruct->Overrun);
+ }
+
+ /* Set ADC group regular sequencer length and scan direction */
+ LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) {
+ /* Set pADC_RegInitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+ pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 series. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution if feature ADC group injected contexts queue is enabled
+ * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+ * using successively several times this function will appear as
+ * having no effect.
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @param ADCx ADC instance
+ * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx,
+ const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) {
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(
+ IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource));
+ assert_param(
+ IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
+ if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(
+ pADC_InjInitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) {
+ MODIFY_REG(
+ ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO,
+ pADC_InjInitStruct->SequencerDiscont | pADC_InjInitStruct->TrigAuto);
+ } else {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE | pADC_InjInitStruct->TrigAuto);
+ }
+
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL,
+ pADC_InjInitStruct->TriggerSource |
+ pADC_InjInitStruct->SequencerLength);
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) {
+ /* Set pADC_InjInitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c
index 593a909..2dd5572 100644
--- a/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c
+++ b/frc971/imu_fdcan/Dual_IMU/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c
@@ -1,737 +1,809 @@
-/**
- ******************************************************************************
- * @file stm32g4xx_ll_usb.c
- * @author MCD Application Team
- * @brief USB Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
- (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
- (#) The upper HAL HCD/PCD driver will call the right routines for its
- internal processes.
-
- @endverbatim
-
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g4xx_hal.h"
-
-/** @addtogroup STM32G4xx_LL_USB_DRIVER
- * @{
- */
-
-#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
-#if defined(USB)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Initializes the USB Core
- * @param USBx USB Instance
- * @param cfg pointer to a USB_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(cfg);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is
- used only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EnableGlobalInt
- * Enables the controller's Global Int in the AHB Config reg
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) {
- uint32_t winterruptmask;
-
- /* Clear pending interrupts */
- USBx->ISTR = 0U;
-
- /* Set winterruptmask variable */
- winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM |
- USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM |
- USB_CNTR_RESETM | USB_CNTR_L1REQM;
-
- /* Set interrupt mask */
- USBx->CNTR = (uint16_t)winterruptmask;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DisableGlobalInt
- * Disable the controller's Global Int in the AHB Config reg
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) {
- uint32_t winterruptmask;
-
- /* Set winterruptmask variable */
- winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM |
- USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM |
- USB_CNTR_RESETM | USB_CNTR_L1REQM;
-
- /* Clear interrupt mask */
- USBx->CNTR &= (uint16_t)(~winterruptmask);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetCurrentMode Set functional mode
- * @param USBx Selected device
- * @param mode current core mode
- * This parameter can be one of the these values:
- * @arg USB_DEVICE_MODE Peripheral mode
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(mode);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is
- used only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevInit Initializes the USB controller registers
- * for device mode
- * @param USBx Selected device
- * @param cfg pointer to a USB_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(cfg);
-
- /* Init Device */
- /* CNTR_FRES = 1 */
- USBx->CNTR = (uint16_t)USB_CNTR_FRES;
-
- /* CNTR_FRES = 0 */
- USBx->CNTR = 0U;
-
- /* Clear pending interrupts */
- USBx->ISTR = 0U;
-
- /*Set Btable Address*/
- USBx->BTABLE = BTABLE_ADDRESS;
-
- return HAL_OK;
-}
-
-#if defined(HAL_PCD_MODULE_ENABLED)
-/**
- * @brief Activate and configure an endpoint
- * @param USBx Selected device
- * @param ep pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
- HAL_StatusTypeDef ret = HAL_OK;
- uint16_t wEpRegVal;
-
- wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
-
- /* initialize Endpoint */
- switch (ep->type) {
- case EP_TYPE_CTRL:
- wEpRegVal |= USB_EP_CONTROL;
- break;
-
- case EP_TYPE_BULK:
- wEpRegVal |= USB_EP_BULK;
- break;
-
- case EP_TYPE_INTR:
- wEpRegVal |= USB_EP_INTERRUPT;
- break;
-
- case EP_TYPE_ISOC:
- wEpRegVal |= USB_EP_ISOCHRONOUS;
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
-
- PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
-
- if (ep->doublebuffer == 0U) {
- if (ep->is_in != 0U) {
- /*Set the endpoint Transmit buffer address */
- PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- if (ep->type != EP_TYPE_ISOC) {
- /* Configure NAK status for the Endpoint */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
- } else {
- /* Configure TX Endpoint to disabled state */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- }
- } else {
- /* Set the endpoint Receive buffer address */
- PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
-
- /* Set the endpoint Receive buffer counter */
- PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- }
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- /* Double Buffer */
- else {
- if (ep->type == EP_TYPE_BULK) {
- /* Set bulk endpoint as double buffered */
- PCD_SET_BULK_EP_DBUF(USBx, ep->num);
- } else {
- /* Set the ISOC endpoint in double buffer mode */
- PCD_CLEAR_EP_KIND(USBx, ep->num);
- }
-
- /* Set buffer address for double buffered mode */
- PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
-
- if (ep->is_in == 0U) {
- /* Clear the data toggle bits for the endpoint IN/OUT */
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- } else {
- /* Clear the data toggle bits for the endpoint IN/OUT */
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- if (ep->type != EP_TYPE_ISOC) {
- /* Configure NAK status for the Endpoint */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
- } else {
- /* Configure TX Endpoint to disabled state */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- }
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- }
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- return ret;
-}
-
-/**
- * @brief De-activate and de-initialize an endpoint
- * @param USBx Selected device
- * @param ep pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
- if (ep->doublebuffer == 0U) {
- if (ep->is_in != 0U) {
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- /* Configure DISABLE status for the Endpoint */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- }
-
- else {
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
- /* Configure DISABLE status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- }
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- /* Double Buffer */
- else {
- if (ep->is_in == 0U) {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(USBx, ep->num);
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- } else {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
- PCD_RX_DTOG(USBx, ep->num);
-
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- }
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPStartXfer setup and starts a transfer over an EP
- * @param USBx Selected device
- * @param ep pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
- uint32_t len;
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- uint16_t pmabuffer;
- uint16_t wEPVal;
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- /* IN endpoint */
- if (ep->is_in == 1U) {
- /*Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket) {
- len = ep->maxpacket;
- } else {
- len = ep->xfer_len;
- }
-
- /* configure and validate Tx endpoint */
- if (ep->doublebuffer == 0U) {
- USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
- PCD_SET_EP_TX_CNT(USBx, ep->num, len);
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- else {
- /* double buffer bulk management */
- if (ep->type == EP_TYPE_BULK) {
- if (ep->xfer_len_db > ep->maxpacket) {
- /* enable double buffer */
- PCD_SET_BULK_EP_DBUF(USBx, ep->num);
-
- /* each Time to write in PMA xfer_len_db will */
- ep->xfer_len_db -= len;
-
- /* Fill the two first buffer in the Buffer0 & Buffer1 */
- if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) {
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr1;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- ep->xfer_buff += len;
-
- if (ep->xfer_len_db > ep->maxpacket) {
- ep->xfer_len_db -= len;
- } else {
- len = ep->xfer_len_db;
- ep->xfer_len_db = 0U;
- }
-
- /* Set the Double buffer counter for pmabuffer0 */
- PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr0;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- } else {
- /* Set the Double buffer counter for pmabuffer0 */
- PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr0;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- ep->xfer_buff += len;
-
- if (ep->xfer_len_db > ep->maxpacket) {
- ep->xfer_len_db -= len;
- } else {
- len = ep->xfer_len_db;
- ep->xfer_len_db = 0U;
- }
-
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr1;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- }
- }
- /* auto Switch to single buffer mode when transfer <Mps no need to
- manage in double buffer */
- else {
- len = ep->xfer_len_db;
-
- /* disable double buffer mode for Bulk endpoint */
- PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
-
- /* Set Tx count with nbre of byte to be transmitted */
- PCD_SET_EP_TX_CNT(USBx, ep->num, len);
- pmabuffer = ep->pmaaddr0;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- }
- } else /* manage isochronous double buffer IN mode */
- {
- /* each Time to write in PMA xfer_len_db will */
- ep->xfer_len_db -= len;
-
- /* Fill the data buffer */
- if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) {
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr1;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- } else {
- /* Set the Double buffer counter for pmabuffer0 */
- PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr0;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- }
- }
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
- } else /* OUT endpoint */
- {
- if (ep->doublebuffer == 0U) {
- /* Multi packet transfer */
- if (ep->xfer_len > ep->maxpacket) {
- len = ep->maxpacket;
- ep->xfer_len -= len;
- } else {
- len = ep->xfer_len;
- ep->xfer_len = 0U;
- }
- /* configure and validate Rx endpoint */
- PCD_SET_EP_RX_CNT(USBx, ep->num, len);
- }
-#if (USE_USB_DOUBLE_BUFFER == 1U)
- else {
- /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
- /* Set the Double buffer counter */
- if (ep->type == EP_TYPE_BULK) {
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
-
- /* Coming from ISR */
- if (ep->xfer_count != 0U) {
- /* update last value to check if there is blocking state */
- wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
-
- /*Blocking State */
- if ((((wEPVal & USB_EP_DTOG_RX) != 0U) &&
- ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
- (((wEPVal & USB_EP_DTOG_RX) == 0U) &&
- ((wEPVal & USB_EP_DTOG_TX) == 0U))) {
- PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
- }
- }
- }
- /* iso out double */
- else if (ep->type == EP_TYPE_ISOC) {
- /* Multi packet transfer */
- if (ep->xfer_len > ep->maxpacket) {
- len = ep->maxpacket;
- ep->xfer_len -= len;
- } else {
- len = ep->xfer_len;
- ep->xfer_len = 0U;
- }
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
- } else {
- return HAL_ERROR;
- }
- }
-#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPSetStall set a stall condition over an EP
- * @param USBx Selected device
- * @param ep pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
- if (ep->is_in != 0U) {
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
- } else {
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPClearStall Clear a stall condition over an EP
- * @param USBx Selected device
- * @param ep pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
- if (ep->doublebuffer == 0U) {
- if (ep->is_in != 0U) {
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- if (ep->type != EP_TYPE_ISOC) {
- /* Configure NAK status for the Endpoint */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
- }
- } else {
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- }
- }
-
- return HAL_OK;
-}
-#endif /* defined (HAL_PCD_MODULE_ENABLED) */
-
-/**
- * @brief USB_StopDevice Stop the usb device mode
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) {
- /* disable all interrupts and force USB reset */
- USBx->CNTR = (uint16_t)USB_CNTR_FRES;
-
- /* clear interrupt status register */
- USBx->ISTR = 0U;
-
- /* switch-off device */
- USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetDevAddress Stop the usb device mode
- * @param USBx Selected device
- * @param address new device address to be assigned
- * This parameter can be a value from 0 to 255
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) {
- if (address == 0U) {
- /* set device address and enable function */
- USBx->DADDR = (uint16_t)USB_DADDR_EF;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevConnect Connect the USB device by enabling the
- * pull-up/pull-down
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) {
- /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
- USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevDisconnect Disconnect the USB device by disabling the
- * pull-up/pull-down
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) {
- /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP
- * line */
- USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadInterrupts return the global USB interrupt status
- * @param USBx Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) {
- uint32_t tmpreg;
-
- tmpreg = USBx->ISTR;
- return tmpreg;
-}
-
-/**
- * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) {
- USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
- * @param USBx Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) {
- USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
-
- return HAL_OK;
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx USB peripheral instance register address.
- * @param pbUsrBuf pointer to user memory area.
- * @param wPMABufAddr address into PMA.
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr,
- uint16_t wNBytes) {
- uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
- uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i;
- uint32_t temp1;
- uint32_t temp2;
- __IO uint16_t *pdwVal;
- uint8_t *pBuf = pbUsrBuf;
-
- pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U +
- ((uint32_t)wPMABufAddr * PMA_ACCESS));
-
- for (i = n; i != 0U; i--) {
- temp1 = *pBuf;
- pBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
- *pdwVal = (uint16_t)temp2;
- pdwVal++;
-
-#if PMA_ACCESS > 1U
- pdwVal++;
-#endif /* PMA_ACCESS */
-
- pBuf++;
- }
-}
-
-/**
- * @brief Copy data from packet memory area (PMA) to user memory buffer
- * @param USBx USB peripheral instance register address.
- * @param pbUsrBuf pointer to user memory area.
- * @param wPMABufAddr address into PMA.
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr,
- uint16_t wNBytes) {
- uint32_t n = (uint32_t)wNBytes >> 1;
- uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i;
- uint32_t temp;
- __IO uint16_t *pdwVal;
- uint8_t *pBuf = pbUsrBuf;
-
- pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U +
- ((uint32_t)wPMABufAddr * PMA_ACCESS));
-
- for (i = n; i != 0U; i--) {
- temp = *(__IO uint16_t *)pdwVal;
- pdwVal++;
- *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
- pBuf++;
- *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
- pBuf++;
-
-#if PMA_ACCESS > 1U
- pdwVal++;
-#endif /* PMA_ACCESS */
- }
-
- if ((wNBytes % 2U) != 0U) {
- temp = *pdwVal;
- *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB) */
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) \
- */
-
-/**
- * @}
- */
+/**
+ ******************************************************************************
+ * @file stm32g4xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its
+ internal processes.
+
+ @endverbatim
+
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_LL_USB_DRIVER
+ * @{
+ */
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+#if defined(USB)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief Initializes the USB Core
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(cfg);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is
+ used only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EnableGlobalInt
+ * Enables the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) {
+ uint32_t winterruptmask;
+
+ /* Clear pending interrupts */
+ USBx->ISTR = 0U;
+
+ /* Set winterruptmask variable */
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM |
+ USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+ /* Set interrupt mask */
+ USBx->CNTR = (uint16_t)winterruptmask;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DisableGlobalInt
+ * Disable the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) {
+ uint32_t winterruptmask;
+
+ /* Set winterruptmask variable */
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM |
+ USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+ /* Clear interrupt mask */
+ USBx->CNTR &= (uint16_t)(~winterruptmask);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetCurrentMode Set functional mode
+ * @param USBx Selected device
+ * @param mode current core mode
+ * This parameter can be one of the these values:
+ * @arg USB_DEVICE_MODE Peripheral mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(mode);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is
+ used only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevInit Initializes the USB controller registers
+ * for device mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(cfg);
+
+ /* Init Device */
+ /* CNTR_FRES = 1 */
+ USBx->CNTR = (uint16_t)USB_CNTR_FRES;
+
+ /* CNTR_FRES = 0 */
+ USBx->CNTR = 0U;
+
+ /* Clear pending interrupts */
+ USBx->ISTR = 0U;
+
+ /*Set Btable Address*/
+ USBx->BTABLE = BTABLE_ADDRESS;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx : Selected device
+ * @param num : FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is
+ used only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx) {
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is
+ used only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+#if defined(HAL_PCD_MODULE_ENABLED)
+/**
+ * @brief Activate and configure an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t wEpRegVal;
+
+ wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
+
+ /* initialize Endpoint */
+ switch (ep->type) {
+ case EP_TYPE_CTRL:
+ wEpRegVal |= USB_EP_CONTROL;
+ break;
+
+ case EP_TYPE_BULK:
+ wEpRegVal |= USB_EP_BULK;
+ break;
+
+ case EP_TYPE_INTR:
+ wEpRegVal |= USB_EP_INTERRUPT;
+ break;
+
+ case EP_TYPE_ISOC:
+ wEpRegVal |= USB_EP_ISOCHRONOUS;
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
+
+ PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
+
+ if (ep->doublebuffer == 0U) {
+ if (ep->is_in != 0U) {
+ /*Set the endpoint Transmit buffer address */
+ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC) {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ } else {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ } else {
+ /* Set the endpoint Receive buffer address */
+ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+
+ /* Set the endpoint Receive buffer counter */
+ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ if (ep->num == 0U) {
+ /* Configure VALID status for EP0 */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ } else {
+ /* Configure NAK status for OUT Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
+ else {
+ if (ep->type == EP_TYPE_BULK) {
+ /* Set bulk endpoint as double buffered */
+ PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+ } else {
+ /* Set the ISOC endpoint in double buffer mode */
+ PCD_CLEAR_EP_KIND(USBx, ep->num);
+ }
+
+ /* Set buffer address for double buffered mode */
+ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
+
+ if (ep->is_in == 0U) {
+ /* Clear the data toggle bits for the endpoint IN/OUT */
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Set endpoint RX count */
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+
+ /* Set endpoint RX to valid state */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ } else {
+ /* Clear the data toggle bits for the endpoint IN/OUT */
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC) {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ } else {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ return ret;
+}
+
+/**
+ * @brief De-activate and de-initialize an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
+ if (ep->doublebuffer == 0U) {
+ if (ep->is_in != 0U) {
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Configure DISABLE status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+
+ else {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure DISABLE status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
+ else {
+ if (ep->is_in == 0U) {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(USBx, ep->num);
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ } else {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ PCD_RX_DTOG(USBx, ep->num);
+
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPStartXfer setup and starts a transfer over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
+ uint32_t len;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ uint16_t pmabuffer;
+ uint16_t wEPVal;
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ /* IN endpoint */
+ if (ep->is_in == 1U) {
+ /* Multi packet transfer */
+ if (ep->xfer_len > ep->maxpacket) {
+ len = ep->maxpacket;
+ } else {
+ len = ep->xfer_len;
+ }
+
+ /* configure and validate Tx endpoint */
+ if (ep->doublebuffer == 0U) {
+ USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else {
+ /* double buffer bulk management */
+ if (ep->type == EP_TYPE_BULK) {
+ if (ep->xfer_len_db > ep->maxpacket) {
+ /* enable double buffer */
+ PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the two first buffer in the Buffer0 & Buffer1 */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket) {
+ ep->xfer_len_db -= len;
+ } else {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ } else {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket) {
+ ep->xfer_len_db -= len;
+ } else {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
+ /* auto Switch to single buffer mode when transfer <Mps no need to
+ manage in double buffer */
+ else {
+ len = ep->xfer_len_db;
+
+ /* disable double buffer mode for Bulk endpoint */
+ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
+
+ /* Set Tx count with nbre of byte to be transmitted */
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ } else /* Manage isochronous double buffer IN mode */
+ {
+ /* Each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the data buffer */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ } else {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+ } else /* OUT endpoint */
+ {
+ if (ep->doublebuffer == 0U) {
+ if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) {
+ /* This is a status out stage set the OUT_STATUS */
+ PCD_SET_OUT_STATUS(USBx, ep->num);
+ } else {
+ PCD_CLEAR_OUT_STATUS(USBx, ep->num);
+ }
+
+ /* Multi packet transfer */
+ if (ep->xfer_len > ep->maxpacket) {
+ ep->xfer_len -= ep->maxpacket;
+ } else {
+ ep->xfer_len = 0U;
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else {
+ /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
+ /* Set the Double buffer counter */
+ if (ep->type == EP_TYPE_BULK) {
+ /* Coming from ISR */
+ if (ep->xfer_count != 0U) {
+ /* Update last value to check if there is blocking state */
+ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
+
+ /* Blocking State */
+ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) &&
+ ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
+ (((wEPVal & USB_EP_DTOG_RX) == 0U) &&
+ ((wEPVal & USB_EP_DTOG_TX) == 0U))) {
+ PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
+ }
+ }
+ }
+ /* iso out double */
+ else if (ep->type == EP_TYPE_ISOC) {
+ /* Only single packet transfer supported in FS */
+ ep->xfer_len = 0U;
+ } else {
+ return HAL_ERROR;
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPSetStall set a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
+ if (ep->is_in != 0U) {
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
+ } else {
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPClearStall Clear a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
+ if (ep->is_in != 0U) {
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC) {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ } else {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure VALID status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPStoptXfer Stop transfer on an EP
+ * @param USBx usb device instance
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) {
+ /* IN endpoint */
+ if (ep->is_in == 1U) {
+ if (ep->doublebuffer == 0U) {
+ if (ep->type != EP_TYPE_ISOC) {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ } else {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ }
+ } else /* OUT endpoint */
+ {
+ if (ep->doublebuffer == 0U) {
+ if (ep->type != EP_TYPE_ISOC) {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ } else {
+ /* Configure RX Endpoint to disabled state */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
+
+/**
+ * @brief USB_StopDevice Stop the usb device mode
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) {
+ /* disable all interrupts and force USB reset */
+ USBx->CNTR = (uint16_t)USB_CNTR_FRES;
+
+ /* clear interrupt status register */
+ USBx->ISTR = 0U;
+
+ /* switch-off device */
+ USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevAddress Stop the usb device mode
+ * @param USBx Selected device
+ * @param address new device address to be assigned
+ * This parameter can be a value from 0 to 255
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) {
+ if (address == 0U) {
+ /* set device address and enable function */
+ USBx->DADDR = (uint16_t)USB_DADDR_EF;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevConnect Connect the USB device by enabling the
+ * pull-up/pull-down
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) {
+ /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
+ USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevDisconnect Disconnect the USB device by disabling the
+ * pull-up/pull-down
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) {
+ /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP
+ * line */
+ USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadInterrupts return the global USB interrupt status
+ * @param USBx Selected device
+ * @retval USB Global Interrupt status
+ */
+uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) {
+ uint32_t tmpreg;
+
+ tmpreg = USBx->ISTR;
+ return tmpreg;
+}
+
+/**
+ * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) {
+ USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) {
+ USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx USB peripheral instance register address.
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ * @retval None
+ */
+void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes) {
+ uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
+ uint32_t BaseAddr = (uint32_t)USBx;
+ uint32_t count;
+ uint16_t WrVal;
+ __IO uint16_t *pdwVal;
+ uint8_t *pBuf = pbUsrBuf;
+
+ pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U +
+ ((uint32_t)wPMABufAddr * PMA_ACCESS));
+
+ for (count = n; count != 0U; count--) {
+ WrVal = pBuf[0];
+ WrVal |= (uint16_t)pBuf[1] << 8;
+ *pdwVal = (WrVal & 0xFFFFU);
+ pdwVal++;
+
+#if PMA_ACCESS > 1U
+ pdwVal++;
+#endif /* PMA_ACCESS */
+
+ pBuf++;
+ pBuf++;
+ }
+}
+
+/**
+ * @brief Copy data from packet memory area (PMA) to user memory buffer
+ * @param USBx USB peripheral instance register address.
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ * @retval None
+ */
+void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes) {
+ uint32_t n = (uint32_t)wNBytes >> 1;
+ uint32_t BaseAddr = (uint32_t)USBx;
+ uint32_t count;
+ uint32_t RdVal;
+ __IO uint16_t *pdwVal;
+ uint8_t *pBuf = pbUsrBuf;
+
+ pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U +
+ ((uint32_t)wPMABufAddr * PMA_ACCESS));
+
+ for (count = n; count != 0U; count--) {
+ RdVal = *(__IO uint16_t *)pdwVal;
+ pdwVal++;
+ *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
+ pBuf++;
+ *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
+ pBuf++;
+
+#if PMA_ACCESS > 1U
+ pdwVal++;
+#endif /* PMA_ACCESS */
+ }
+
+ if ((wNBytes % 2U) != 0U) {
+ RdVal = *pdwVal;
+ *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) \
+ */
+
+/**
+ * @}
+ */
diff --git a/frc971/imu_fdcan/Dual_IMU/Dual_IMU Debug.cfg b/frc971/imu_fdcan/Dual_IMU/Dual_IMU Debug.cfg
new file mode 100644
index 0000000..be74783
--- /dev/null
+++ b/frc971/imu_fdcan/Dual_IMU/Dual_IMU Debug.cfg
@@ -0,0 +1,44 @@
+# This is an genericBoard board with a single STM32G473RETx chip
+#
+# Generated by STM32CubeIDE
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
+
+source [find interface/stlink-dap.cfg]
+
+
+set WORKAREASIZE 0x8000
+
+transport select "dapdirect_swd"
+
+set CHIPNAME STM32G473RETx
+set BOARDNAME genericBoard
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 8000
+
+# Reset configuration
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate connect_assert_srst
+set CONNECT_UNDER_RESET 1
+set CORE_RESET 0
+
+# ACCESS PORT NUMBER
+set AP_NUM 0
+# GDB PORT
+set GDB_PORT 3333
+
+
+
+
+
+# BCTM CPU variables
+
+source [find target/stm32g4x.cfg]
+
diff --git a/frc971/imu_fdcan/Dual_IMU/Dual_IMU.ioc b/frc971/imu_fdcan/Dual_IMU/Dual_IMU.ioc
index ffc0648..b61a5fd 100644
--- a/frc971/imu_fdcan/Dual_IMU/Dual_IMU.ioc
+++ b/frc971/imu_fdcan/Dual_IMU/Dual_IMU.ioc
@@ -23,23 +23,27 @@
FDCAN2.NominalTimeSeg2=3
File.Version=6
GPIO.groupedBy=Group By Peripherals
+IWDG.IPParameters=Prescaler,Reload
+IWDG.Prescaler=IWDG_PRESCALER_16
+IWDG.Reload=200
KeepUserPlacement=false
Mcu.CPN=STM32G473RET6
Mcu.Family=STM32G4
Mcu.IP0=ADC5
Mcu.IP1=FDCAN2
-Mcu.IP10=TIM3
-Mcu.IP11=USART1
-Mcu.IP12=USB
-Mcu.IP2=NVIC
-Mcu.IP3=RCC
-Mcu.IP4=SPI1
-Mcu.IP5=SPI2
-Mcu.IP6=SPI3
-Mcu.IP7=SYS
-Mcu.IP8=TIM1
-Mcu.IP9=TIM2
-Mcu.IPNb=13
+Mcu.IP10=TIM2
+Mcu.IP11=TIM3
+Mcu.IP12=USART1
+Mcu.IP13=USB
+Mcu.IP2=IWDG
+Mcu.IP3=NVIC
+Mcu.IP4=RCC
+Mcu.IP5=SPI1
+Mcu.IP6=SPI2
+Mcu.IP7=SPI3
+Mcu.IP8=SYS
+Mcu.IP9=TIM1
+Mcu.IPNb=14
Mcu.Name=STM32G473R(B-C-E)Tx
Mcu.Package=LQFP64
Mcu.Pin0=PC13
@@ -89,21 +93,22 @@
Mcu.Pin49=PB7
Mcu.Pin5=PC0
Mcu.Pin50=PB9
-Mcu.Pin51=VP_SYS_VS_Systick
-Mcu.Pin52=VP_SYS_VS_DBSignals
-Mcu.Pin53=VP_TIM1_VS_ClockSourceINT
-Mcu.Pin54=VP_TIM2_VS_ClockSourceINT
-Mcu.Pin55=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin51=VP_IWDG_VS_IWDG
+Mcu.Pin52=VP_SYS_VS_Systick
+Mcu.Pin53=VP_SYS_VS_DBSignals
+Mcu.Pin54=VP_TIM1_VS_ClockSourceINT
+Mcu.Pin55=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin56=VP_TIM3_VS_ClockSourceINT
Mcu.Pin6=PC1
Mcu.Pin7=PC2
Mcu.Pin8=PC3
Mcu.Pin9=PA0
-Mcu.PinsNb=56
+Mcu.PinsNb=57
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32G473RETx
-MxCube.Version=6.10.0
-MxDb.Version=DB.6.0.100
+MxCube.Version=6.12.1
+MxDb.Version=DB.6.0.121
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
@@ -317,12 +322,12 @@
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32G473RETx
-ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1
+ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.6.1
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=false
+ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
@@ -338,7 +343,7 @@
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FDCAN2_Init-FDCAN2-false-HAL-true,4-MX_ADC5_Init-ADC5-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_SPI3_Init-SPI3-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true,10-MX_USB_PCD_Init-USB-false-HAL-true,11-MX_TIM2_Init-TIM2-false-HAL-true,12-MX_TIM1_Init-TIM1-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FDCAN2_Init-FDCAN2-false-HAL-true,4-MX_ADC5_Init-ADC5-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_SPI3_Init-SPI3-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true,10-MX_USB_PCD_Init-USB-false-HAL-true,11-MX_TIM2_Init-TIM2-false-HAL-true,12-MX_TIM1_Init-TIM1-false-HAL-true,13-MX_IWDG_Init-IWDG-false-HAL-true
RCC.ADC12Freq_Value=168000000
RCC.ADC345Freq_Value=168000000
RCC.AHBFreq_Value=168000000
@@ -438,6 +443,8 @@
USART1.VirtualMode-Asynchronous=VM_ASYNC
USB.IPParameters=Sof_enable
USB.Sof_enable=DISABLE
+VP_IWDG_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
VP_SYS_VS_Systick.Mode=SysTick