fixed a couple of trace ends that didn't quite match up
diff --git a/bbb_cape/schematic/cape.pcb b/bbb_cape/schematic/cape.pcb
index 9d4a84f..c70b378 100644
--- a/bbb_cape/schematic/cape.pcb
+++ b/bbb_cape/schematic/cape.pcb
@@ -6,7 +6,7 @@
PCB["971 BBB Cape" 500000 400000]
Grid[500.0 441 0 1]
-Cursor[325941 272000 0.000000]
+Cursor[259941 98500 0.000000]
PolyArea[3100.006200]
Thermal[0.500000]
DRC[800 1000 800 10 1000 500]
@@ -3506,7 +3506,7 @@
Line[270351 102067 269653 101369 800 1600 "clearline"]
Line[270351 139907 270351 103976 800 1600 "clearline"]
Line[272319 139907 272319 104406 800 1600 "clearline"]
- Line[272319 104092 272319 102328 800 1600 "clearline"]
+ Line[272319 104406 272319 102328 800 1600 "clearline"]
Line[272319 102328 273229 101418 800 1600 "clearline"]
Line[278225 139907 278225 120398 800 1600 "clearline"]
Line[253106 114250 237756 114250 800 1600 "clearline"]
@@ -3979,7 +3979,7 @@
Line[266978 130582 266978 113347 800 1600 "clearline"]
Line[266978 113347 262278 113347 800 1600 "clearline"]
Line[262278 113347 258841 109910 800 1600 "clearline"]
- Line[258841 109910 258841 98067 800 1600 "clearline"]
+ Line[258841 109910 258841 97900 800 1600 "clearline"]
Line[245312 50107 230441 64978 800 1600 "clearline"]
Line[230441 64978 230441 107000 800 1600 "clearline"]
Line[245312 57107 240441 61978 800 1600 "clearline"]