- Teensy 3.5 has a MK64FX512VMD12 (Freescale Kinetis K64 sub-family)
- It's a Cortex-M4F, which means it has an FPU and DSP instructions.
- 512 KB of flash
- 256 KB SRAM (64 KB SRAM_L, 192 KB SRAM_U)
- Up to 120 MHz
- datasheet
- errata
- TODO(Brian): Are all of our parts this revision?
- K64 reference manual
- schematic.
- actual docs on the bit-banding
- ARM Cortex-M Programming Guide to Memory Barrier Instructions
- Cortex-M4 instruction timings
- Optimizing Performance on Kinetis K-series MCUs
- motor
- 2 pole pairs per revolution
- RM08, 5v, 2048 edges per revolution, single ended incremental, with index pulse
- fet12v2 has a MK22FN1M0AVLK12
- It's a Cortex-M4F, which means it has an FPU and DSP instructions.
- 1 MB of flash
- 128 KB SRAM (64 KB SRAM_L, 64 KB SRAM_U)
- Alternative part is MK22FX512AVLK12 with 512 KB of flash
- datasheet
- reference manual
- fet12v2accessory has a MK22FN1M0AVLH12
- It's a Cortex-M4F, which means it has an FPU and DSP instructions.
- 1 MB of flash
- 128 KB SRAM (64 KB SRAM_L, 64 KB SRAM_U)
- Alternative part is MK22FX512AVLH12 with 512 KB of flash
- datasheet
- reference manual
- ARMv7-M Architecture Reference Manual
- TODO(Brian): Turn the cache on. Writethrough caching for the flash would be useful. https://www.nxp.com/docs/en/application-note/AN4745.pdf "Cache initialization" has steps.
Clocking
- Running the core clock at its maximum of 120 MHz
- Bus clocks (both of them) are their maximum of 60 MHz
Timing (what triggers what)
Coordinating the timing of everything is pretty important. The general idea is to keep everything in sync based on the FTM module(s) which drive the motor outputs. They trigger the ADCs too.
FTM0 and FTM3 are synced using the global time base when driving two motors for the pistol grip controller.
The timing is divided into "cycles". Each cycle is a fixed length of time. The start of the cycle is when the FTM module(s) have a count of 0.
See //motors/peripheral:adc_dma.cc for details on how hardware-triggered ADC sampling works.