flipped the symbol for the status LEDs
diff --git a/bbb_cape/schematic/cape.pcb b/bbb_cape/schematic/cape.pcb
index 16258ad..c9667a5 100644
--- a/bbb_cape/schematic/cape.pcb
+++ b/bbb_cape/schematic/cape.pcb
@@ -6,7 +6,7 @@
PCB["971 BBB Cape" 500000 400000]
Grid[500.0 441 0 0]
-Cursor[315941 174500 0.000000]
+Cursor[267441 75500 0.000000]
PolyArea[3100.006200]
Thermal[0.500000]
DRC[800 1000 800 10 1000 500]
@@ -6240,12 +6240,6 @@
)
Layer(7 "silk")
(
- Line[251441 71500 248941 69000 600 1200 "clearline"]
- Line[251441 71500 248941 74000 600 1200 "clearline"]
- Line[248941 74000 248941 69000 600 1200 "clearline"]
- Line[251441 71500 257441 71500 600 1200 "clearline"]
- Line[251441 68000 251441 75000 600 1200 "clearline"]
- Line[248941 71500 242441 71500 600 1200 "clearline"]
Line[406441 305000 403941 307500 600 1200 "clearline"]
Line[406441 305000 408941 307500 600 1200 "clearline"]
Line[403941 307500 408941 307500 600 1200 "clearline"]
@@ -6264,6 +6258,12 @@
Line[87941 193000 87941 199000 600 1200 "clearline"]
Line[84441 193000 91441 193000 600 1200 "clearline"]
Line[87941 190500 87941 187500 600 1200 "clearline"]
+ Line[247941 72000 250441 74500 600 1200 "clearline"]
+ Line[247941 72000 250441 69500 600 1200 "clearline"]
+ Line[250441 69500 250441 74500 600 1200 "clearline"]
+ Line[241941 72000 247941 72000 600 1200 "clearline"]
+ Line[247941 68500 247941 75500 600 1200 "clearline"]
+ Line[250441 72000 256941 72000 600 1200 "clearline"]
Text[384000 226503 1 105 "7 5 4 3 1 0" "clearline"]
Text[308438 170515 0 100 "- DIO CLK RST" "clearline"]
Text[308438 178515 0 100 "SWD connector" "clearline"]